WO2019009873A1 - Formation de motifs de damasquinage pour la fabrication de transistors à couches minces - Google Patents

Formation de motifs de damasquinage pour la fabrication de transistors à couches minces Download PDF

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Publication number
WO2019009873A1
WO2019009873A1 PCT/US2017/040552 US2017040552W WO2019009873A1 WO 2019009873 A1 WO2019009873 A1 WO 2019009873A1 US 2017040552 W US2017040552 W US 2017040552W WO 2019009873 A1 WO2019009873 A1 WO 2019009873A1
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Prior art keywords
tft
semiconductor layer
layer
tft semiconductor
trench
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PCT/US2017/040552
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English (en)
Inventor
Kevin Lin
Van Le
Jack Kavalieros
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Intel Corporation
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Priority to PCT/US2017/040552 priority Critical patent/WO2019009873A1/fr
Publication of WO2019009873A1 publication Critical patent/WO2019009873A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate

Definitions

  • Embodiments of the invention are in the field of semiconductor processing and, in particular, thin-film transistors and methods of forming such devices with damascene patterning processes.
  • thin- film transistors are fabricated by blanket depositing a layer of the thin- film transistor material. Thereafter, a photoresist layer is deposited over the thin-film transistor material layer and patterned. The pattern in the photoresist layer is then transferred to the thin- film transistor material layer using wet and/or dry etching processes in order to define the thin- film transistor.
  • thin- film transistors require precise fabrication conditions in order to produce efficient and high performance devices.
  • One particular fabrication condition that needs to be closely monitored is the temperature of the processing operations that are used to fabricate the thin- film transistor. For example, at elevated temperatures the elements of the thin-film transistor diffuse and disassociate with other materials. This alters the chemical composition of the thin- film transistor, and alters the performance of the thin- film transistor.
  • the thin-film transistor may be oxidized during etching and cleaning processes. Accordingly, the etchants used to pattern the semiconductor material for the thin film transistor are limited.
  • etching processes used to pattern the interlayer dielectrics surrounding the thin-film transistor may inadvertently attack the film and result in undercutting. Accordingly, restrictions on dry and/or wet etches used to form the thin-film transistor and restrictions on the materials used for the surrounding dielectric materials limit the performance of the thin-film transistor.
  • FIG. 1A is a cross-sectional illustration of an interlayer dielectric (ILD) in which a thin- film transistor (TFT) may be formed, according to an embodiment of the invention.
  • ILD interlayer dielectric
  • TFT thin- film transistor
  • Figure IB is a cross-sectional illustration of the device after the ILD that has been patterned to form a trench in which the TFT semiconductor layer may be deposited, according to an embodiment of the invention.
  • Figure 1C is a cross-sectional illustration of the device after the TFT semiconductor layer has been blanket deposited, according to an embodiment of the invention.
  • Figure ID is a cross-sectional illustration of the device after a capping layer is deposited over the TFT semiconductor layer, according to an embodiment of the invention.
  • Figure IE is a cross-sectional illustration of the device after a polishing operation is implemented to planarize the material layers, according to an embodiment of the invention.
  • Figure 2A is a cross-sectional illustration of a device after a source and drain contact have been fabricated in a first ILD, according to an embodiment of the invention.
  • Figure 2B is a cross-sectional illustration of the device after a second ILD has been deposited over the first ILD, according to an embodiment of the invention.
  • Figure 2C is a cross-sectional illustration of the device after the second ILD has been patterned to form a trench in which the TFT semiconductor layer may be deposited, according to an embodiment of the invention.
  • Figure 2D is a cross-sectional illustration of the device after the TFT semiconductor layer and the gate dielectric layer have been deposited, according to an embodiment of the invention.
  • Figure 2E is a cross-sectional illustration of the device after a capping layer has been deposited over the gate dielectric layer, according to an embodiment of the invention.
  • Figure 2F is a cross-sectional illustration of the device after the material layers are planarized with a polishing operation, according to an embodiment of the invention.
  • Figure 2G is a cross-sectional illustration of the device after a third ILD is deposited over the second ILD, according to an embodiment of the invention.
  • Figure 2H is a cross-sectional illustration of the device after a gate trench is patterned through the third ILD and the capping layer, according to an embodiment of the invention.
  • Figure 21 is a cross-sectional illustration of the device after the gate electrode is formed in the gate trench, according to an embodiment of the invention.
  • Figure 3A is a cross-sectional illustration of a first ILD with a gate electrode, according to an embodiment of the invention.
  • Figure 3B is a cross-sectional illustration of the device after a second ILD has been formed over the first ILD, according to an embodiment of the invention.
  • Figure 3C is a cross-sectional illustration of the device after a trench has been formed into the second ILD, according to an embodiment of the invention.
  • Figure 3D is a cross-sectional illustration of the device after a gate dielectric layer and a TFT semiconductor layer have been deposited in the trench, according to an embodiment of the invention.
  • Figure 3E is a cross-sectional illustration of the device after a capping layer has been deposited over the TFT layer, according to an embodiment of the invention.
  • Figure 3F is a cross-sectional illustration of the device after the layers have been planarized with a polishing operation, according to an embodiment of the invention.
  • Figure 3G is a cross-sectional illustration of the device after source and drain openings are formed through the capping layer, according to an embodiment of the invention.
  • Figure 3H is a cross-sectional illustration of the device after the source and drain are formed in the source and drain openings, according to an embodiment of the invention.
  • FIG. 4 is a cross-sectional illustration of a TFT that includes source, gate, and drain electrodes below the TFT, according to an embodiment of the invention.
  • FIG. 5 is a cross-sectional illustration of a TFT that includes source, gate, and drain electrodes above the TFT, according to an embodiment of the invention.
  • Figure 6 is an interposer implementing one or more embodiments of the invention.
  • Figure 7 is a computing device built in accordance with an embodiment of the invention.
  • TFTs thin-film transistors
  • various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
  • TFTs are currently fabricated with subtractive patterning processes, such as wet and/or dry etching processes.
  • these operations limit the materials that may be used to form the TFT due to concerns such as diffusion of the TFT materials during high temperature operations and other negative etching effects (e.g., undercutting, oxidation, or the like).
  • embodiments of the invention include TFTs that are fabricate with damascene processing operations.
  • the use of a damascene processing operations allows for the dimensions of the TFT to be defined prior to the deposition of the TFT material.
  • damascene processes used to from the TFT semiconductor material and capping layer allow for increased flexibility in material choice for the interlayer dielectric (ILD). Accordingly, negative etching interactions and diffusion are not present in embodiments of the invention because all etching happens before the TFT semiconductor material is formed.
  • ILD interlayer dielectric
  • FIGS 1A-1E a series of cross-sectional illustrations are shown that illustrate a generic process for forming the semiconductor layer of a TFT with a damascene process, according to an embodiment of the invention.
  • the source, gate, and drain contacts are omitted for clarity, and in order to not obscure embodiments of the invention.
  • embodiments that illustrate how the source, gate, and drain are fabricated in conjunction with the semiconductor layer are provided in greater detail below.
  • the ILD 110 may be a first layer of ILD formed on a support substrate (not shown), or it may be any subsequent ILD in a stack- up of multiple ILDs.
  • the ILD 110 may have a thickness Ti that is greater than a thickness of a subsequently formed TFT semiconductor layer.
  • the ILD 110 may have a thickness Ti that is greater than approximately 5 nm.
  • the ILD 110 may have a thickness Ti that is greater than approximately 50 nm.
  • the ILD 110 may have a thickness Ti that is greater than approximately 100 nm.
  • the ILD 110 may be any suitable low-k dielectric material.
  • low-k dielectric materials may include, but are not limited to, silicon dioxide (S1O 2 ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or
  • polytetrafluoroethylene fluorosilicate glass (FSG)
  • organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the ILD material may include pores or air gaps to further reduce their dielectric constant.
  • the trench 112 may be patterned with any suitable etching process.
  • the trench 112 may be patterned with typical wet and/or dry etching processes.
  • sidewalls 113 of the trench are illustrated as being slightly off axis from 90°.
  • the angle of the sidewalls with respect to the surface of the ILD 110 may be any angle, and is primarily determined by the etching processes that are used to form the trench 112.
  • the dimensions of the trench may be chosen in order to define a TFT that has a desired performance.
  • the trench 112 may have an opening with a length L that is substantially similar to the desired length of the subsequently formed TFT.
  • the length L may be between approximately 20 nm and approximately 200 nm. However, it is to be appreciated that the length L may also be less than 20 nm or greater than 200 nm according to different embodiments of the invention.
  • the depth D of the trench 112 may be chosen so that it is greater than the desired thickness of the subsequently deposited TFT semiconductor layer.
  • the depth D of the trench 112 may be between approximately 10 nm and approximately 100 nm. However, it is to be appreciated that the depth D may also be less than 10 nm or greater than 100 nm according to different embodiments of the invention.
  • the TFT semiconductor material may be any suitable
  • the TFT is a semiconductor material used for thin film transistors.
  • the TFT is a semiconductor material used for thin film transistors.
  • the TFT is a semiconductor material used for thin film transistors.
  • the semiconductor layer 120 may be one or more of InGaZnO, alpha-Ge, alpha-Si, ZnO, and polymer/organic semiconductors.
  • the TFT semiconductor layer 120 is deposited to a thickness T2 that is desired for the thickness of the TFT film in the final TFT device.
  • the thickness T2 may be between approximately 5 nm and
  • the thickness T2 may also be less than 5 nm or greater than 50 nm according to different embodiments of the invention.
  • the thickness of the TFT semiconductor layer 120 may be precisely controlled by using deposition process such as atomic layer deposition (ALD). Such deposition processes may be considered conformal deposition processes. As such, embodiments may include extensions 122 of the TFT semiconductor layer 120 that extend up along the wall 113 of the trench 112. In an embodiment, at least a portion of the extensions 122 may remain in the final TFT device, as will be shown below.
  • ALD atomic layer deposition
  • FIG. 1 a cross-sectional illustration of the device after a capping layer 130 is formed over the TFT semiconductor layer 120 is shown, according to an
  • the capping layer 130 may be any suitable non- conductive material that can be used to fill the remaining portions of the trench 112 in order to hermetically seal the TFT semiconductor layer 120 formed in the trench 112.
  • the capping layer 130 may be a dielectric material, such as SiN.
  • the SiN capping layer may be doped with any suitable dopants, such as carbon, oxygen, or the like.
  • the capping layer may be deposited with any suitable deposition processes, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or the like.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • the polishing process may recess the portions of the capping layer 130 and the TFT semiconductor layer 120 that are formed above the trench 112.
  • a portion of the ILD 110 may also be recessed.
  • a top surface of the capping layer 133 may be substantially coplanar with a top surface of the ILD 110.
  • the polishing process may be a chemical mechanical polishing (CMP) process. It is to be appreciated that substantially no oxidation of the TFT semiconductor layer 120 occurs during the polishing process since the capping layer protects the TFT semiconductor layer 120 during the polishing operation. Accordingly, the resulting device includes a TFT semiconductor layer 120 that is formed with the proper dimensions without suffering from oxidation, diffusion, or other etching effects such as those described above.
  • CMP chemical mechanical polishing
  • FIG. 2A-2I a series of cross-sectional illustrations are shown that illustrate a generic process for forming a TFT where the semiconductor layer of a TFT is formed with a damascene process, according to an embodiment of the invention.
  • the source and drain electrodes are formed below the TFT semiconductor layer, and the gate electrode is formed above the TFT semiconductor layer.
  • the first ILD 210 may be a first layer of ILD formed on a support substrate (not shown), or it may be any subsequent ILD in a stack-up of multiple ILDs.
  • the source electrode 241 and the drain electrode 242 may be formed with any suitable processes known in the art.
  • the source electrode 241 and the drain electrode 242 may be formed with subtractive processes or damascene processes.
  • the source electrode 241 and the drain electrode 242 may be conductive materials, such as copper.
  • the second ILD 214 may have a thickness Ti that is greater than a thickness of a subsequently formed TFT semiconductor layer.
  • the second ILD 214 may have a thickness Ti that is greater than approximately 5 nm.
  • the second ILD 214 may have a thickness Ti that is greater than approximately 50 nm.
  • the second ILD 214 may have a thickness Ti that is greater than approximately 100 nm.
  • the second ILD 214 may be any suitable dielectric material.
  • the trench 212 may be patterned with any suitable etching process.
  • the trench 212 may be patterned with typical wet and/or dry etching processes.
  • sidewalls 213 of the trench are illustrated as being slightly off axis from 90°.
  • the angle of the sidewalls with respect to the surface of the second ILD 214 may be any angle, and is primarily determined by the etching processes that are used to form the trench 212.
  • the dimensions of the trench may be chosen in order to define a TFT that has a desired performance.
  • the trench 212 may have an opening with a length L that is substantially similar to the desired length of the subsequently formed TFT.
  • the length L may be between approximately 20 nm and approximately 200 nm. However, it is to be appreciated that the length L may also be less than 20 nm or greater than 200 nm according to different embodiments of the invention.
  • the trench 214 may be formed entirely through the second ILD 214 in order to expose the source electrode 241 and the drain electrode 242.
  • the TFT semiconductor layer may be deposited in the trench 212 such that it is in direct contact with the source electrode 241 and the drain electrode 242.
  • the TFT semiconductor material may be any suitable semiconductor material used for thin film transistors.
  • the semiconductor layer 220 may be one or more of InGaZnO, alpha-Ge, alpha-Si, ZnO, and polymer/organic semiconductors.
  • the TFT semiconductor layer 220 is deposited to a thickness T2 that is desired for the thickness of the TFT film in the final TFT device.
  • the thickness T2 may be between approximately 5 nm and
  • the thickness T2 may also be less than 5 nm or greater than 50 nm according to different embodiments of the invention.
  • the thickness of the TFT semiconductor layer 220 may be precisely controlled by using deposition process such as ALD. Such deposition processes may be considered conformal deposition processes. As such, embodiments may include extensions 222 of the TFT semiconductor layer 220 that extend up along the wall 213 of the trench 212. In an embodiment, at least a portion of the extensions 222 may remain in the final TFT device, as will be shown below.
  • the gate dielectric layer 250 may be any suitable high-K dielectric material.
  • the gate dielectric layer 250 may include one layer or a stack of layers.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • the gate dielectric layer 250 may be blanket deposited over the TFT
  • the gate dielectric layer may be deposited with CVD, PECVD, or the like.
  • the capping layer 230 may be any suitable non-conductive material that can be used to fill the remaining portions of the trench 212 in order to hermetically seal the TFT semiconductor layer 220 formed in the trench 212.
  • the capping layer 130 may be a dielectric material, such as SiN.
  • the SiN capping layer may be doped with any suitable dopants, such as carbon, oxygen, or the like.
  • the capping layer may be deposited with any suitable deposition processes, such as CVD, PECVD, or the like.
  • the polishing process may recess the portions of the capping layer 230, the gate dielectric layer 250, and the TFT semiconductor layer 220 that are formed above the trench 212.
  • a portion of the second ILD 214 may also be recessed.
  • a top surface of the capping layer 233 may be substantially coplanar with a top surface of the second ILD 214.
  • the polishing process may be a CMP process. It is to be appreciated that substantially no oxidation of the TFT semiconductor layer 220 occurs during the polishing process since the capping layer 230 and the gate dielectric 250 protects the TFT semiconductor layer 120 during the polishing operation. Accordingly, the resulting device includes a TFT semiconductor layer 220 that is formed with the proper dimensions without suffering from oxidation, diffusion, or other etching effects such as those described above.
  • the third dielectric layer 216 may be any suitable dielectric material.
  • the selection of the dielectric material is not limited by processing conditions that may negatively affect the TFT semiconductor layer 220.
  • the gate trench 272 is formed through the third dielectric layer 216 and the capping layer 230 is shown, according to an embodiment of the invention.
  • the gate trench 272 may be formed with any patterning process, such as wet and/or dry etching.
  • the gate trench 272 exposes the gate dielectric layer 250.
  • the presence of the gate dielectric layer 250 provides protection to the TFT semiconductor layer 220 from the etching process.
  • the gate electrode 270 may be any suitable conductive material.
  • the gate electrode 270 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.
  • metals that may be used for the gate electrode 270 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • the gate electrode may be deposited with any suitable deposition process, such as CVD, PECVD, sputtering, or the like.
  • the gate electrode 272 may also be formed with a replacement metal gate process, as is known in the art. In such an embodiment, the gate trench 272 may be filled with a polysilicon material that is subsequently removed and replaced with one or more conductive metals.
  • FIG. 3A-3H a series of cross-sectional illustrations are shown that illustrate a process for forming a TFT where the semiconductor layer of a TFT is formed with a damascene process, according to an embodiment of the invention.
  • the source and drain electrodes are formed above the TFT semiconductor layer, and the gate electrode is formed below the TFT semiconductor layer.
  • the first ILD 310 may be a first layer of ILD formed on a support substrate (not shown), or it may be any subsequent ILD in a stack-up of multiple ILDs.
  • the gate electrode 370 may be formed with any suitable processes known in the art.
  • the gate electrode 370 may be formed with subtractive processes or damascene processes.
  • the gate electrode 370 may be conductive materials, such as those described above.
  • the second ILD 314 may have a thickness Ti that is greater than a thickness of a subsequently formed TFT semiconductor layer.
  • the second ILD 314 may have a thickness Ti that is greater than approximately 5 nm.
  • the second ILD 314 may have a thickness Ti that is greater than approximately 50 nm.
  • the second ILD 314 may have a thickness Ti that is greater than approximately 100 nm.
  • the second ILD 314 may be any suitable dielectric material.
  • the trench 312 may be patterned with any suitable etching process.
  • the trench 312 may be patterned with typical wet and/or dry etching processes.
  • sidewalls 313 of the trench are illustrated as being slightly off axis from 90°.
  • the angle of the sidewalls with respect to the surface of the second ILD 314 may be any angle, and is primarily determined by the etching processes that are used to form the trench 312.
  • the dimensions of the trench may be chosen in order to define a TFT that has a desired performance.
  • the trench 312 may have an opening with a length L that is substantially similar to the desired length of the subsequently formed TFT.
  • the length L may be between approximately 20 nm and approximately 200 nm. However, it is to be appreciated that the length L may also be less than 20 nm or greater than 200 nm according to different embodiments of the invention.
  • the trench 314 may be formed entirely through the second ILD 314 in order to expose the gate electrode 370.
  • the gate dielectric layer 350 may be deposited first so that it is formed over a top surface of the gate electrode 350.
  • the gate dielectric layer 350 may be any suitable high-K dielectric material, such as those described above.
  • the gate dielectric layer 350 may be blanket deposited over the TFT semiconductor layer.
  • the gate dielectric layer may be deposited with CVD, PECVD, or the like.
  • the TFT semiconductor layer may be deposited in the trench 312 such that it is formed over the top surface of the gate dielectric layer 350.
  • the TFT semiconductor material may be any suitable semiconductor material used for thin film transistors.
  • the TFT semiconductor layer 320 may be one or more of InGaZnO, alpha-Ge, alpha-Si, ZnO, and polymer/organic semiconductors.
  • the TFT semiconductor layer 320 is deposited to a thickness T2 that is desired for the thickness of the TFT film in the final TFT device.
  • the thickness T2 may be between approximately 5 nm and approximately 50 nm. However, it is to be appreciated that the thickness T2 may also be less than 5 nm or greater than 50 nm according to different embodiments of the invention.
  • the thickness of the TFT semiconductor layer 320 may be precisely controlled by using deposition process such as atomic layer deposition (ALD). Such deposition processes may be considered conformal deposition processes.
  • embodiments may include extensions 322 of the TFT semiconductor layer 320 that extend up along the wall 313 of the trench 312. In an embodiment, at least a portion of the extensions 322 may remain in the final TFT device, as will be shown below.
  • the capping layer 330 may be any suitable non-conductive material that can be used to fill the remaining portions of the trench 312 in order to hermetically seal the TFT semiconductor layer 320 formed in the trench 312.
  • the capping layer 330 may be a dielectric material, such as SiN.
  • the SiN capping layer may be doped with any suitable dopants, such as carbon, oxygen, or the like.
  • the capping layer may be deposited with any suitable deposition processes, such as CVD, PECVD, or the like.
  • the polishing process may recess the portions of the capping layer 330, the gate dielectric layer 350, and the TFT semiconductor layer 320 that are formed above the trench 312.
  • a portion of the second ILD 314 may also be recessed.
  • a top surface of the capping layer 333 may be substantially coplanar with a top surface of the second ILD 314.
  • the polishing process may be a CMP process. It is to be appreciated that substantially no oxidation of the TFT semiconductor layer 320 occurs during the polishing process since the capping layer 330 protects the TFT semiconductor layer 320 during the polishing operation. Accordingly, the resulting device includes a TFT semiconductor layer 320 that is formed with the proper dimensions without suffering from oxidation, diffusion, or other etching effects such as those described above.
  • the source and drain trenches 344,345 may be formed with any patterning process, such as wet and/or dry etching.
  • the source and drain trenches 344,345 expose TFT semiconductor layer 320.
  • the source electrode 341 and the drain electrode 342 may be any suitable conductive material.
  • the gate electrode may be copper.
  • the gate electrode may be deposited with any suitable deposition process, such as CVD, PECVD, sputtering, or the like.
  • TFT devices are just exemplary illustrations, and the use of damascene patterning to form the TFT semiconductor layer may be used to form many TFT devices with various configurations.
  • the TFT devices in Figures 21 and 3H include source/drain electrodes that are formed on opposite surfaces of the TFT semiconductor layer than the gate electrode.
  • embodiments may also include TFT devices where the source, drain, and gate electrodes are formed over the same surface of the TFT semiconductor layer.
  • the TFT device includes a TFT semiconductor layer 420 formed with a damascene process. Particularly, the indication that the TFT
  • the semiconductor layer 420 is formed with a damascene process is the presence of extensions 422 along the edge of the TFT semiconductor layer 420.
  • the source electrode 441 and the drain electrode 442 are in direct contact with a bottom surface of the TFT semiconductor layer 420, and the gate electrode 470 is separated from the bottom surface of the TFT semiconductor layer 520 by the gate dielectric 450.
  • the processing, and materials for forming the TFT device in Figure 4 may be substantially similar to those described above, as those skilled in the art will recognize.
  • the TFT device includes a TFT semiconductor layer 520 formed with a damascene process.
  • the indication that the TFT semiconductor layer 520 is formed with a damascene process is the presence of extensions 522 along the edge of the TFT semiconductor layer 520.
  • the source electrode 541 and the drain electrode 542 are in direct contact with a top surface of the TFT semiconductor layer 520, and the gate electrode 570 is separated from the bottom surface of the TFT semiconductor layer 520 by the gate dielectric 550.
  • the processing, and materials for forming the TFT device in Figure 5 may be substantially similar to those described above, as those skilled in the art will recognize.
  • FIG. 6 illustrates an interposer 600 that includes one or more embodiments of the invention.
  • the interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604.
  • the first substrate 602 may be, for instance, an integrated circuit die.
  • the second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604.
  • BGA ball grid array
  • the first and second substrates 602/604 are attached to opposing sides of the interposer 600.
  • the first and second substrates 602/604 are attached to the same side of the interposer 600.
  • three or more substrates are interconnected by way of the interposer 600.
  • the interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 608 and vias 610, including but not limited to through- silicon vias (TSVs) 612.
  • the interposer 600 may further include embedded devices 614, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600.
  • RF radio-frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.
  • FIG. 7 illustrates a computing device 700 in accordance with one embodiment of the invention.
  • the computing device 700 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard.
  • SoC system-on-a-chip
  • the components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one communication chip 708. In some
  • the communication chip 708 is fabricated as part of the integrated circuit die 702.
  • the integrated circuit die 702 may include a CPU 704 as well as on-die memory 706, often used as cache memory, that can be provided by technologies such as embedded DRAM
  • eDRAM spin- transfer torque memory
  • STTM spin- transfer torque memory
  • Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 710 (e.g., DRAM), non-volatile memory 712 (e.g., ROM or flash memory), a graphics processing unit 714 (GPU), a digital signal processor 716, a crypto processor 742 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 720, an antenna 722, a display or a touchscreen display 724, a touchscreen controller 726, a battery 728 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 728, a compass 730, a motion coprocessor or sensors 732 (that may include an accelerometer, a gyroscope, and a compass), a speaker 734, a camera 736, user input devices 738 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage
  • the communications chip 708 enables wireless communications for the transfer of data to and from the computing device 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 708.
  • a first communication chip 708 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes one or more devices, such as TFT devices formed with damascene processing operations, that are formed in accordance with embodiments of the invention.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 708 may also include one or more devices, such as TFT devices formed with damascene processing operations, that are formed in accordance with embodiments of the invention.
  • another component housed within the computing device 700 may contain one or more devices, such as TFT devices formed with damascene processing operations, that are formed in accordance with implementations of the invention.
  • the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • Example 1 a thin-film transistor (TFT) device, comprising: an interlayer dielectric (ILD) layer, wherein a trench is formed into the ILD layer; a TFT semiconductor layer formed in the trench, wherein extensions of the TFT semiconductor layer extend up sidewalls of the trench; a capping layer formed over a top surface of the TFT semiconductor layer; a source electrode and a drain electrode, wherein the source electrode and the drain electrode contact a surface of the TFT semiconductor layer; and a gate electrode separated from a surface of the TFT
  • ILD interlayer dielectric
  • Example 2 the TFT device of Example 1, wherein a top surface of the capping layer is substantially coplanar with a to surface of the ILD layer.
  • Example 3 the TFT device of Example 1 or Example 2, wherein the gate electrode is separated from a top surface of the TFT semiconductor layer by the gate dielectric layer.
  • Example 4 the TFT device of Example 1, Example 2, or Example 3, wherein the source electrode and the drain electrode contact a bottom surface of the TFT semiconductor layer.
  • Example 5 the TFT device of Example 1, Example 2, Example 3, or Example 4, wherein the source electrode and the drain electrode contact the top surface of the TFT semiconductor layer.
  • Example 6 the TFT device of Example 1, Example 2, Example 3, Example 4, or
  • Example 5 wherein the gate electrode is separated from a bottom surface of the TFT semiconductor layer by the gate dielectric layer.
  • Example 7 the TFT device of Example 1, Example 2, Example 3, Example 4, Example 5, or Example 6, wherein the source electrode and the drain electrode contact a top surface of the TFT semiconductor layer.
  • Example 8 the TFT device of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, or Example 7, wherein the source electrode and the drain electrode contact the bottom surface of the TFT semiconductor layer.
  • Example 9 the TFT device of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, or Example 8, wherein the gate dielectric layer is formed over a top surface of the TFT semiconductor layer, and wherein the cap layer is formed over a top surface of the TFT semiconductor layer.
  • Example 10 the TFT device of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, or Example 9, wherein the gate dielectric layer is formed over the surface of the trench, and wherein the TFT semiconductor layer is formed over a top surface of the top surface of the gate dielectric layer.
  • Example 11 the TFT device of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, or Example 10, wherein sidewalls of the trench are not oriented 90° with respect to a top surface of the ILD layer.
  • Example 12 the TFT device of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, or Example 11, wherein the TFT semiconductor layer is one or more of InGaZnO, alpha-Ge, alpha-Si, ZnO, or polymer/organic semiconductors.
  • Example 13 a method of forming a thin- film transistor (TFT) device, comprising:
  • an interlayer dielectric (ILD) layer forming an interlayer dielectric (ILD) layer; forming a trench into the ILD layer; depositing a TFT semiconductor material over the ILD layer with a conformal deposition process; depositing a capping material over a top surface of the TFT semiconductor material; and planarizing the device such that a top surface of the capping material is substantially coplanar with a top surface of the ILD layer.
  • ILD interlayer dielectric
  • Example 14 the method of Example 13, wherein the TFT semiconductor layer includes extensions formed along sidewalls of the trench in the ILD layer.
  • Example 15 the method of Example 13 or Example 14, further comprising: forming a source electrode and a drain electrode, wherein the source electrode and drain electrode contact a surface of the TFT semiconductor layer.
  • Example 16 the method of Example 13, Example 14, or Example 15, wherein forming the trench in the ILD layer exposes the surface of the source electrode and drain electrode.
  • Example 17 the method of Example 13, Example 14, Example 15, or Example 16, further comprising: forming a gate dielectric layer; and forming a gate electrode, wherein the gate electrode is separated from the TFT semiconductor layer by the gate dielectric layer.
  • Example 18 the method of Example 13, Example 14, Example 15, Example 16, or Example 17 wherein the gate dielectric layer is formed over a top surface of the TFT
  • Example 19 the method of Example 13, Example 14, Example 15, Example 16, Example 17, or Example 18, wherein the gate dielectric layer is formed below a bottom surface of the TFT semiconductor layer.
  • Example 20 the method of Example 13, Example 14, Example 15, Example 16, Example 17, Example 18, or Example 19, wherein the gate electrode is formed with a damascene process.
  • Example 21 the method of Example 13, Example 14, Example 15, Example 16, Example 17, Example 18, Example 19, or Example 20, wherein the gate electrode is formed with a replacement metal gate process.
  • Example 22 the method of Example 13, Example 14, Example 15, Example 16, Example 17, Example 18, Example 19, Example 20, or Example 21, wherein the TFT semiconductor layer in the trench is completely covered by the capping layer prior to the device being planarized.
  • Example 23 a thin- film transistor (TFT) device, comprising: an interlay er dielectric (ILD) layer, wherein a trench is formed into the ILD layer; a TFT semiconductor layer formed in the trench, wherein extensions of the TFT semiconductor layer extend up sidewalls of the trench; a capping layer formed over a top surface of the TFT semiconductor layer, wherein a top surface of the capping layer is substantially coplanar with a to surface of the ILD layer; a source electrode and a drain electrode, wherein the source electrode and the drain electrode contact a surface of the TFT semiconductor layer; and a gate electrode separated from a surface of the TFT semiconductor layer by a gate dielectric layer, wherein the gate electrode is formed over a surface of the TFT semiconductor layer that is opposite to the surface which the source electrode and the drain
  • Example 24 the TFT device of Example 23, wherein the source electrode and the drain electrode contact a bottom surface of the TFT semiconductor layer.
  • Example 25 the TFT device of Example 23 or Example 24, wherein the source electrode and the drain electrode contact a top surface of the TFT semiconductor layer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Thin Film Transistor (AREA)

Abstract

Des modes de réalisation de la présente invention comprennent des transistors à couches minces et des procédés de formation de tels dispositifs avec des procédés de damasquinage. Dans un mode de réalisation, le dispositif de transistor à couches minces (TFT) comprend une couche diélectrique intercouche (ILD), une tranchée étant formée dans la couche ILD. Dans un mode de réalisation, une couche semi-conductrice TFT est formée dans la tranchée, des extensions de la couche semi-conductrice TFT s'étendant jusqu'à des parois latérales de la tranchée. Dans un mode de réalisation, une couche de transition est formée sur une surface supérieure de la couche semi-conductrice TFT. Des modes de réalisation supplémentaires peuvent comprendre une électrode de source et une électrode de drain, l'électrode de source et l'électrode de drain étant en contact avec une surface de la couche semi-conductrice TFT, et une électrode de grille séparée d'une surface de la couche semi-conductrice TFT par une couche diélectrique de grille.
PCT/US2017/040552 2017-07-01 2017-07-01 Formation de motifs de damasquinage pour la fabrication de transistors à couches minces WO2019009873A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107662A (en) * 1997-08-14 2000-08-22 Lg Semicon Co., Ltd. Thin film transistor and method for fabricating the same
JP3273989B2 (ja) * 1993-02-19 2002-04-15 新日本製鐵株式会社 Ｍｉｓトランジスタの製造方法
JP2008060524A (ja) * 2006-08-31 2008-03-13 Sharp Corp 自己整合型の低不純物濃度ドレインを備えたリセスゲート薄膜トランジスタ、および当該トランジスタの形成方法
US20090258462A1 (en) * 2004-09-29 2009-10-15 Konevecki Michael W Method for forming doped polysilicon via connecting polysilicon layers
JP2013131766A (ja) * 2006-03-29 2013-07-04 Plastic Logic Ltd 自己整合電極を有するデバイスの作製方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3273989B2 (ja) * 1993-02-19 2002-04-15 新日本製鐵株式会社 Ｍｉｓトランジスタの製造方法
US6107662A (en) * 1997-08-14 2000-08-22 Lg Semicon Co., Ltd. Thin film transistor and method for fabricating the same
US20090258462A1 (en) * 2004-09-29 2009-10-15 Konevecki Michael W Method for forming doped polysilicon via connecting polysilicon layers
JP2013131766A (ja) * 2006-03-29 2013-07-04 Plastic Logic Ltd 自己整合電極を有するデバイスの作製方法
JP2008060524A (ja) * 2006-08-31 2008-03-13 Sharp Corp 自己整合型の低不純物濃度ドレインを備えたリセスゲート薄膜トランジスタ、および当該トランジスタの形成方法

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