WO2019007207A1

WO2019007207A1 - Semi-conductor apparatus and impedance regulation method therefor

Info

Publication number: WO2019007207A1
Application number: PCT/CN2018/091817
Authority: WO
Inventors: 徐宝岗; 董博宇; 文莉辉; 耿玉洁; 郭冰亮; 王军
Original assignee: 北京北方华创微电子装备有限公司
Priority date: 2017-07-04
Filing date: 2018-06-19
Publication date: 2019-01-10
Also published as: CN107227446A; TW201907510A; TWI697975B

Abstract

Disclosed are a semi-conductor apparatus and an impedance regulation method therefor. The semi-conductor apparatus comprises a chamber (100), a base (110) for bearing a substrate (200) being arranged in the chamber (100); and an impedance regulating circuit (190) electrically connected to the base (110) and a grounding terminal (300) respectively, and used for regulating the impedance between the base (110) and the grounding terminal (300). Thus, the semi-conductor apparatus can regulate the size of the bias voltage on the base (110), so that the cost of the semi-conductor apparatus can be reduced, and continuous regulation of the bias voltage on the base (110) can also be realized.

Description

Semiconductor device and impedance adjustment method thereof

Technical field

The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor device and an impedance adjustment method of the semiconductor device.

Background technique

In semiconductor fabrication processes, semiconductor devices are a commonly used tool for forming various semiconductor film layers and conductor film layers. For example, in the fabrication process of a light emitting diode (LED), a semiconductor device can be used to form a sapphire substrate and an n-type gallium nitride (n-GaN) aluminum nitride (ALN) film, thereby improving the power of the LED. Performance, including brightness, electrostatic discharge performance, etc.

In a typical semiconductor device, a sputtering power source is introduced into a process gas through an electrode and is coupled into a process gas, thereby exciting a gas into a plasma, and performing film deposition under the action of electrons and ions in the plasma.

Summary of the invention

Embodiments of the present disclosure provide a semiconductor device and an impedance adjustment method of the semiconductor device. The semiconductor device includes:

a chamber in which a susceptor for carrying a substrate is disposed;

An impedance adjustment circuit is electrically connected to the base and the ground respectively for adjusting an impedance between the base and the ground.

In some examples, the plurality of chambers are provided, and at least one of the chambers is provided with the impedance adjustment circuit.

In some examples, the impedance adjustment circuit includes:

a first adjusting circuit for reducing an impedance between the base and the ground;

a second adjusting circuit for increasing an impedance between the base and the ground;

And a selection switch for selectively electrically conducting at least one of the first conditioning circuit and the second conditioning circuit with the pedestal.

In some examples, the first conditioning circuit includes a variable capacitance line that includes a variable capacitance.

In some examples, the second conditioning circuit includes a variable resistance line, and/or a variable inductance line, wherein the variable resistance line includes a variable resistance; the variable inductance line includes a variable electrical sense.

In some examples, the second conditioning circuit includes a variable resistance line and a variable inductance line, and the variable capacitance line, the variable resistance line, and the variable inductance line are connected in parallel with each other; the selection switch includes a setting a first switch on the variable capacitance line, a second switch disposed on the variable resistance line, and a third switch disposed on the variable inductance line.

In some examples, the second adjustment circuit includes a variable resistance line and a variable inductance line, the variable resistance line and the variable inductance line are connected in series with each other, and are connected in parallel with the variable capacitance line; The selection switch includes a first switch disposed on the variable capacitance line, and a second switch disposed on the variable resistance line or the variable inductance line.

In some examples, the semiconductor device further includes a first node electrically coupled to the pedestal, and a second node that is grounded; the impedance adjustment circuit is electrically coupled to the first node and the second node, respectively.

In some examples, the second node is directly grounded.

In some examples, the capacitance of the variable capacitor is in the range of 50 pF to 1 μF.

In some examples, the variable resistance has a resistance value in the range of 100 Ω to 100 K Ω.

In some examples, the variable inductance has an inductance value in the range of 100 μH to 2000 μH.

In some examples, the chamber further includes:

a cavity, the pedestal is located inside the cavity, and the impedance adjusting circuit is located outside the cavity.

At least one embodiment of the present disclosure also provides an impedance adjustment method for a semiconductor device according to any of the above, comprising:

The impedance of the impedance adjustment circuit is adjusted to adjust the impedance between the base and the ground.

In some examples, the plurality of chambers are plural, at least one of the chambers is provided with the impedance adjustment circuit; and the impedance adjustment method comprises:

The impedance of the plurality of chambers is maintained to be uniform by adjusting the impedance of the impedance adjusting circuit corresponding to at least one of the chambers.

Beneficial effects:

Embodiments of the present disclosure provide an impedance adjustment method of a semiconductor device and a semiconductor device, which can adjust a magnitude of a bias voltage on a pedestal by adjusting an impedance between a pedestal and a ground via an impedance adjustment circuit, which is related to the prior art. By adjusting the output power of the bias power supply to adjust the bias voltage on the pedestal, the cost of the semiconductor device can be reduced, and continuous adjustment of the bias voltage on the pedestal can be achieved.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present disclosure, and are not to limit the disclosure. .

1 is a schematic structural view of a chamber in a semiconductor device;

2 is a schematic structural view of a chamber in another semiconductor device;

3a is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure;

3b is a schematic structural view of a single chamber in a semiconductor device according to a first embodiment of the present disclosure;

3c is a schematic diagram of an impedance adjustment circuit in a semiconductor device according to a first embodiment of the present disclosure;

3d is a schematic diagram of an impedance adjustment circuit in a semiconductor device according to a second embodiment of the present disclosure;

3e is a schematic diagram of an impedance adjustment circuit in a semiconductor device according to a third embodiment of the present disclosure;

4 is an equivalent circuit diagram of a chamber in a semiconductor device according to a third embodiment of the present disclosure;

5 is a schematic diagram of an impedance adjustment circuit in another semiconductor device according to a third embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a variable capacitor according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a variable resistor according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a variable inductor according to an embodiment of the present disclosure.

Detailed ways

The technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It is apparent that the described embodiments are part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present disclosure without departing from the scope of the invention are within the scope of the disclosure.

Unless otherwise defined, technical terms or scientific terms used in the present disclosure are intended to be understood in the ordinary meaning of the ordinary skill of the art. The words "first," "second," and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The word "comprising" or "comprises" or the like means that the element or item preceding the word is intended to be in the

1 is a schematic view showing the structure of a chamber in a semiconductor device. As shown in FIG. 1, the chamber in the semiconductor device includes a susceptor 10, a cavity 20, an electrode 30, a sputtering power source 40, and a target 50. The susceptor 10 is disposed in the cavity 20 for carrying the substrate 200 to be deposited. The electrode 30 is disposed in the cavity 20 and above the susceptor 10, and the sputtering power source 40 is electrically connected to the electrode 30. When the sputtering power source 40 is turned on, an electric field is formed between the electrode 30 and the susceptor 10, and the electric field can excite a process gas (for example, argon gas) in the cavity 20 to form a plasma, and electrons and ions in the plasma Next, film deposition on the substrate 200 is completed. For example, in the case of a sputter-coated semiconductor device, a cation (for example, argon ion) in a plasma bombards the target 50 under the action of an electric field, and the material of the target 50 is sputtered and deposited on the substrate 200. . As shown in FIG. 1, in the semiconductor device, the cavity 20 has an opening 21, and the semiconductor device further includes an exhaust valve 60, a vacuum line 70, and a vacuum pump 80; the exhaust valve 60 is disposed on the opening 21 of the cavity 20. The vacuum pump 80 is connected to the suction valve 60 through the vacuum line 70.

However, since the mass of electrons in the plasma is much smaller than the mass of the ions, and the charges of the electrons and ions are the same, under the same electric field, the electrons move faster than the speed of the ions, resulting in electrons attached to the susceptor. The number is greater than the number of ions; at the same time, due to the impedance between the pedestal and the ground, this causes the charge accumulated on the pedestal to not immediately disappear, thereby causing the pedestal to form a negative bias to ground. For the physical vapor deposition process, the magnitude of the bias on the pedestal has two effects: on the one hand, the kinetic energy of the ions that impact the target, and on the other hand, the kinetic energy of the ions that strike the substrate. The bias voltage on the susceptor can affect the properties of the deposited film on the substrate by the effects of the above two aspects, including film uniformity, stress, crystal quality and the like. Therefore, it is practical to obtain a good deposition effect by adjusting the magnitude of the bias of the susceptor by using an appropriate method and apparatus. Generally, in the physical vapor deposition process, the magnitude of the bias of the susceptor is determined by various factors, such as the type of process gas, the gas pressure, the output power of the sputtering power source, and the like. However, for a particular physical vapor deposition process, the above conditions are typically fixed, so additional bias adjustment means are needed to adjust the bias of the pedestal.

As shown in FIG. 1, the semiconductor device further includes a DC blocking capacitor 91, a matching device 92, and a bias power source 93. The bias power supply 93 is electrically coupled to the susceptor 10 via a matcher 92 and a DC blocking capacitor 91. The bias power supply 93 is typically a radio frequency power source for loading RF power to the susceptor 10 via the matcher 92 for use on the susceptor 10. A bias is generated. For example, the DC blocking capacitor 91 can be a capacitor having a capacitance value in the range of 100 pF to 200 pF; the bias power source 93 can be a radio frequency power source having a frequency ranging from 1 MHz to 25 MHz. The matcher 92 matches the load impedance with the output impedance of the bias power supply 93 to ensure that the power output by the bias power supply 93 is applied to the plasma inside the cavity 20 to the greatest extent. It should be noted that the above load includes a matching device, a DC blocking capacitor, and a plasma in the cavity.

The magnitude of the bias on the susceptor 10 can be adjusted by varying the output power of the bias power supply 93. However, adjusting the magnitude of the bias voltage on the susceptor 10 by adding a device such as the bias power supply 93 and the matcher 92 increases the cost of the semiconductor device. In addition, the above-described bias range which can be adjusted by increasing the magnitude of the bias voltage on the susceptor 10 by means of a device such as the bias power supply 93 and the matcher 92 is limited.

2 is a schematic view showing the structure of a chamber in another semiconductor device. As shown in FIG. 2, unlike the semiconductor device shown in FIG. 1, the semiconductor device is provided with an isolation layer 94 between the susceptor 10 and the electrode 30 in the cavity 20, and a radio frequency power source 95 and a DC blocking capacitor 91 are disposed. The RF power source 95 is electrically connected to the susceptor 10 through a DC blocking capacitor 91. By adjusting various parameters of the isolation layer 94, such as the radial thickness of the isolation layer 94, the inner peripheral wall area of the isolation layer 94, the spacing between the isolation layer 94 and the inner walls of the cavity, and the dielectric material employed by the isolation layer 94. The electric constant or the like can change the size of the coupling capacitance between the susceptor 10 and the electrode 30, thereby achieving adjustment of the magnitude of the bias of the susceptor 10. However, in one aspect, the semiconductor device described above requires first opening the cavity and then adjusting various parameters of the isolation layer 94 to adjust the magnitude of the bias of the susceptor 10, thereby causing the risk of contamination of the cavity and also increasing the bias voltage. The time of adjustment reduces efficiency. On the other hand, in practice, since the radial thickness of the isolation layer 94, the inner peripheral wall area of the isolation layer 94, and the dielectric constant of the dielectric material used for the isolation layer 94 cannot be continuously adjusted, the base cannot be realized. The continuous adjustment of the bias of the seat 10, and in order to be able to meet the need for bias adjustment of the pedestal, requires the production of a large number of different isolation layers, resulting in higher cost of implementing this approach.

In order to solve at least one of the above problems, an embodiment of the present disclosure provides a semiconductor device including: a chamber and an impedance adjustment circuit, wherein a susceptor for carrying a substrate is disposed in the chamber; and the impedance adjustment circuit respectively The pedestal is electrically connected to the ground for adjusting the impedance between the pedestal and the ground.

By adjusting the impedance between the pedestal and the ground by means of the impedance adjusting circuit, the magnitude of the bias on the pedestal can be adjusted, which is adjusted in the prior art by changing the output power of the bias power supply. In comparison, the cost of the semiconductor device can be reduced while continuous adjustment of the bias voltage on the pedestal can be achieved.

Hereinafter, a semiconductor device and an impedance adjustment method of the semiconductor device provided by the embodiments of the present disclosure will be described with reference to the accompanying drawings.

First embodiment

This embodiment provides a semiconductor device. FIG. 3a is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure. As shown in FIG. 3a, the semiconductor device includes a plurality of chambers 100. At least one of the chambers 100 is provided with the above-described impedance adjusting circuit. Six chambers are shown in Fig. 3a, but this is not particularly limited according to an embodiment of the present disclosure.

By adjusting the impedance between the pedestal and the ground of the corresponding chamber by means of the impedance adjusting circuit, the impedance of the plurality of chambers can be kept uniform while the performance of the film deposited on the substrate is satisfied, thereby improving The film deposition quality of the semiconductor device. At the same time, continuous adjustment of the bias on the base can be achieved. In addition, the semiconductor device has a simple structure and a low cost, which is advantageous for promotion.

It should be noted that, in the embodiment, the semiconductor device includes a plurality of chambers 100. However, the present invention is not limited thereto, and in practical applications, the semiconductor device may further include only one chamber.

FIG. 3b is a schematic structural diagram of a single chamber in a semiconductor device according to a first embodiment of the present disclosure. As shown in FIG. 3b, at least one of the chambers 100 includes a susceptor 110 that can carry a substrate 200, and an impedance adjustment circuit 190 that can adjust between the pedestal 110 of the chamber 100 and the ground terminal 300. The impedance is such that the properties of the film deposited on the substrate meet the requirements while maintaining the impedance of the plurality of chambers 100 consistent.

When the film layer in the semiconductor device is fabricated by using the semiconductor device provided in the embodiment, the impedance of the plurality of chambers can be kept consistent by the impedance adjusting circuit, so that the bias of the susceptor in the plurality of chambers can be maintained. Consistently, the uniformity and repeatability of the film layer of the semiconductor device can be improved, thereby improving the quality of the semiconductor device. On the other hand, the semiconductor device has a simple structure and a low cost, which is advantageous for promotion.

For example, as shown in FIG. 3a, the semiconductor device further includes a transfer chamber 900 in communication with the transfer chamber 900 and disposed about the transfer chamber 900.

For example, as shown in FIG. 3a, the semiconductor device further includes

load lock chambers

700 and 800 in communication with the transfer chamber 900 to effect transfer of the substrate between the transfer chamber and the front end environment.

The specific implementation of the impedance adjustment circuit will be described in detail below by taking a single chamber as an example. Specifically, FIG. 3c is a schematic diagram of an impedance adjustment circuit in a semiconductor device according to a first embodiment of the present disclosure. Referring to FIG. 3c, the impedance adjustment circuit includes: a first adjustment circuit 310, a second adjustment circuit 320, and a selection switch, wherein the first adjustment circuit 310 is configured to reduce the impedance between the base and the ground; the second adjustment circuit 320 For improving the impedance between the pedestal and the ground; the selection switch is for selectively electrically conducting at least one of the first conditioning circuit 310 and the second conditioning circuit 320 to the pedestal.

By changing the impedance between the pedestal and the ground, the charge-to-ground release channel characteristics accumulated on the pedestal can be changed, thereby changing the amount of charge accumulation on the pedestal, thereby achieving the purpose of adjusting the bias voltage on the pedestal. The first adjustment circuit 310 has a gain effect on the bias of the pedestal, that is, when the selection switch electrically conducts the first adjustment circuit 310 to the pedestal, the bias of the susceptor can be increased. Conversely, the second adjustment circuit 320 has a debuffing effect on the bias of the pedestal, that is, when the selection switch electrically conducts the first adjustment circuit 310 to the pedestal, the bias of the susceptor can be reduced. Since the bias of the susceptor can affect the properties of the deposited film on the substrate, including film uniformity, stress, crystal quality, etc., the bias of the susceptor can be adjusted by the impedance adjusting circuit to improve the film deposition quality of the semiconductor device. Moreover, when a plurality of semiconductor devices provided in the present embodiment are used to fabricate a film layer in a semiconductor device, the magnitude of the bias voltage of the pedestals of different semiconductor devices can be kept uniform by the impedance adjusting circuit, thereby improving the film of the semiconductor device. The consistency and repeatability of the layer, which in turn improves the quality of the semiconductor device. On the other hand, the impedance adjusting circuit does not need to be disposed in the cavity of the semiconductor device, and the cavity can be adjusted without using the impedance adjusting circuit to adjust the bias of the pedestal, thereby ensuring a good impedance adjustment effect. Improve impedance adjustment efficiency. In addition, the semiconductor device has a simple structure and a low cost, which is advantageous for promotion.

It should be noted that the above-mentioned increase or decrease of the bias voltage of the pedestal means that the amplitude of the bias voltage of the pedestal is increased or decreased. For example, when the bias of the susceptor is a negative bias, for example -30V, the bias of the susceptor described above can be increased from -30V to -60V, and the bias of the pedestal is reduced. The bias of the pedestal can be changed from -30V to -10V.

In the present embodiment, as shown in FIG. 3c, the first adjustment circuit 310 includes a variable capacitance line 191 including a variable capacitance 1910. Optionally, the capacitance of the variable capacitor 1910 can be in the range of 50 pF to 1 μF.

When the selection switch connects the variable capacitance line 191 to the pedestal, the variable capacitance line 191 can reduce the impedance between the pedestal and the ground, thereby increasing the bias on the pedestal. Moreover, by adjusting the size of the variable capacitor 1910 to access the circuit, the amount of decrease in impedance can be adjusted, which enables continuous adjustment of the impedance, so that continuous adjustment of the bias voltage on the pedestal can be achieved.

In the present embodiment, the second adjustment circuit 320 includes a variable resistance line 192 including a variable resistor 1920. Optionally, the resistance of the variable resistor 1920 is in a range of 100 Ω to 100 K Ω. For example, the resistance value of the variable resistor 1920 can be further selected in the range of 200 Ω to 100 K Ω.

When the selector switch connects the variable resistance line 192 to the pedestal, the variable resistance line 192 can increase the impedance between the pedestal and the ground, thereby reducing the bias on the pedestal. Moreover, by adjusting the size of the variable resistor 1920 to access the circuit, the amount of increase in impedance can be adjusted, which enables continuous adjustment of the impedance, so that continuous adjustment of the bias voltage on the pedestal can be achieved.

In the present embodiment, the variable capacitance line 191 and the variable resistance line 192 are connected in parallel with each other. When the selection switch connects the variable capacitance line 191 and the variable resistance line 192 to the pedestal at the same time, the parallel circuit can improve the pedestal and the pedestal. The impedance between the grounds, which reduces the bias on the pedestal. Further, the access of the variable capacitance line 191 can suppress the occurrence of a transient spike in the waveform shape of the bias voltage on the susceptor, so that the waveform shape can be made smoother.

In the present embodiment, the selection switch includes a first switch 1961 disposed on the variable capacitance line 191, and a second switch 1962 disposed on the variable resistance line 192. The variable capacitance line 191 and/or the variable resistance line 192 can be connected to the pedestal by selectively turning on the first switch 1961 and/or the second switch 1962.

In this embodiment, the semiconductor device further includes a first node 194 electrically connected to the pedestal, and a second node 195 electrically connected to the ground, the impedance adjusting circuit being electrically connected to the first node 194 and the second node 195, respectively. . Specifically, in the present embodiment, both ends of the variable capacitance line 191 and the variable resistance line 192 are respectively connected to the first node 194 and the second node 195.

Optionally, the foregoing second node 195 can be directly grounded. Here, the second node 195 "directly grounded" means that the second node 195 can be directly electrically connected to the ground through a wire or the like without further interposing other devices or power lamps.

The semiconductor device provided by the embodiment does not need to provide an additional radio frequency power supply, so that the cost of the semiconductor device can be reduced.

Second embodiment

The semiconductor device provided in this embodiment is the same as the semiconductor device provided in the first embodiment described above except that the impedance adjustment circuit is different. The differences between the impedance adjustment circuits are described in detail below.

FIG. 3 is a schematic diagram of an impedance adjustment circuit in a semiconductor device according to a second embodiment of the present disclosure. Referring to FIG. 3d, in the present embodiment, as in the first embodiment described above, the first adjustment circuit 310 also includes a variable capacitance line 191.

In the present embodiment, the second regulation circuit 320 includes a variable inductance line 193 that includes a variable inductance 1930. Optionally, the inductance of the variable inductor 1930 is in the range of 100 μH to 2000 μH.

When the selector switch connects the variable inductance line 193 to the pedestal, the variable inductance line 193 can increase the impedance between the pedestal and the ground, thereby reducing the bias on the pedestal. Moreover, by adjusting the size of the variable inductance 1930 to access the circuit, the amount of increase in impedance can be adjusted, which enables continuous adjustment of the impedance, so that continuous adjustment of the bias voltage on the pedestal can be achieved.

In the present embodiment, when the selection switch connects the variable capacitance line 191 and the variable inductance line 193 to the pedestal at the same time, the variable capacitance line 191 and the variable inductance line 193 are connected in parallel with each other, and the parallel circuit can improve the base. The impedance between the base and the ground reduces the bias on the pedestal. At the same time, since the inductance has a large influence on the waveform shape of the bias on the pedestal, by adjusting the variable inductance, the waveform shape can be avoided. A spike that makes the shape of the waveform smoother.

In the present embodiment, the selection switch includes a first switch 1961 disposed on the variable capacitance line 191, and a third switch 1963 disposed on the variable inductance line 193. The variable capacitance line 191 and/or the variable inductance line 193 can be connected to the pedestal by selectively turning on the first switch 1961 and/or the third switch 1963.

Third embodiment

The semiconductor device provided in this embodiment is the same as the semiconductor device provided in the first and second embodiments described above except that the impedance adjustment circuit is different. The differences between the impedance adjustment circuits are described in detail below.

Specifically, FIG. 3e is a schematic diagram of an impedance adjustment circuit in a semiconductor device according to a third embodiment of the present disclosure. Referring to FIG. 3e, in the present embodiment, as in the first embodiment described above, the first adjustment circuit 310 also includes a variable capacitance line 191.

In the present embodiment, the second regulating circuit 320 includes a variable resistance line 192 and a variable inductance line 193, and the variable resistance line 192, the variable inductance line 193, and the variable capacitance line 191 are connected in parallel with each other.

When the selection switch connects the variable capacitance line 191 to the pedestal, the variable capacitance line 191 can lower the impedance between the pedestal and the ground, thereby increasing the bias on the pedestal.

When the selection switch connects the variable resistance line 192 or the variable inductance line 193 to the pedestal, the variable resistance line 192 or the variable inductance line 193 can improve the impedance between the pedestal and the ground, thereby lowering the pedestal The bias on the upper.

When the selection switch connects the variable capacitance line 191 and the variable resistance line 192 to the pedestal at the same time, the parallel circuit can improve the impedance between the pedestal and the ground, thereby reducing the bias on the pedestal; Access to the resistive line 192 can increase the degree of continuity of the bias adjustment.

When the selection switch connects the variable capacitance line 191 and the variable inductance line 193 to the pedestal at the same time, the parallel circuit can improve the impedance between the pedestal and the ground, thereby reducing the bias on the pedestal; The access of the variable inductance line 193 can also avoid transient spikes in the waveform shape of the bias voltage on the pedestal, so that the waveform shape can be made smoother.

In the present embodiment, the selection switch includes a first switch 1961 disposed on the variable capacitance line 191, a second switch 1962 disposed on the variable resistance line 192, and a third disposed on the variable inductance line 193. Switch 1963.

It should be noted that in the present embodiment, the variable resistance line 192 and the variable inductance line 193 are connected in parallel with each other. Of course, the present disclosure includes but is not limited thereto. In practical applications, the variable resistance line 192 and the variable inductance line 193 may also be connected in series with each other, and the series circuit and the variable capacitance line 191 are connected in parallel with each other. In this case, the selection switch may include a first switch disposed on the variable capacitance line, and a second switch disposed on the variable resistance line or the variable inductance line.

In summary, the impedance adjustment circuit in the semiconductor device can select a variable capacitance line, a variable resistance line, and a variable inductance line to be accessed according to different needs.

It should be noted that, in each of the above embodiments, as shown in FIG. 3b, the semiconductor device further includes a cavity 120, the pedestal 110 is located inside the cavity 120, and the impedance adjusting circuit 190 is located outside the cavity 120. Thus, on the one hand, when the bias on the susceptor is adjusted, it is not necessary to open the cavity 120 and the bias adjustment is performed in the state in which the cavity 120 is opened, so that the cavity 120 can be prevented from being contaminated; It is necessary to open the cavity 120 to perform the bias adjustment, which can save the time required to open the cavity 120 and then return to the process conditions for vapor deposition, and if the bias on the pedestal cannot be adjusted to meet the process requirements, it needs to be repeated. The time taken to open the cavity for bias adjustment can greatly improve the efficiency of the bias adjustment.

In addition, the semiconductor device further includes an electrode 130 located in the cavity 120 and disposed opposite the susceptor 110, and the electrode 130 is electrically connected to the sputtering power source 140. When the sputtering power source 140 is energized, an electric field is formed between the electrode 130 and the susceptor 110, so that the process gas (for example, argon gas) in the cavity 120 can be excited into a plasma under the action of electrons and ions in the plasma. The film deposition on the substrate 200 is completed.

For example, in the case of a sputter-coated semiconductor device, a cation (for example, argon ion) in a plasma bombards the target 150 under the action of an electric field, and the material of the target 150 is sputtered and deposited on the substrate 200. .

In addition, in the semiconductor device, the cavity 120 has an opening 121, the semiconductor device further includes an exhaust valve 160, a vacuum line 170, and a vacuum pump 180; the exhaust valve 160 is disposed on the opening 121 of the cavity 120, and the vacuum pump 180 passes The vacuum line 170 is connected to the suction valve 160. It should be noted that, in addition to the sputter-coated semiconductor device, the semiconductor device provided by the embodiments of the present disclosure may also be other types of physical deposition devices, such as ion-coated semiconductor devices.

For example, the sputter power source can be a pulsed DC power source with a frequency in the range of 5 kHz to 1 MHz.

Taking the third embodiment as an example, FIG. 4 is an equivalent circuit diagram of a chamber in a semiconductor device according to a third embodiment of the present disclosure. Referring to FIG. 4, during the vapor deposition process, the plasma 125 in the cavity can be equivalent to the inductor 127 and the resistor 129 in parallel. A sheath capacitance 131 exists between the plasma 125 and the electrode (target); the first node 194 of the impedance adjustment circuit is coupled to the pedestal, and the second node 195 of the impedance adjustment circuit is coupled to ground.

The structure of the impedance adjusting circuit is as shown in FIG. 3e, and the variable capacitor 1910, the variable resistor 1920 and the variable inductor 1930 thereon are capable of changing the characteristics of the charge-to-ground release channel accumulated on the susceptor, thereby changing the pedestal. The amount of charge accumulated, thereby adjusting the bias on the pedestal. Specifically, the variable capacitor 1910, the variable resistor 1920, and/or the variable inductor 1930 can be connected to the pedestal by selectively turning on the first switch 1961, the second switch 1962, and/or the third switch 1963. The size of the connected capacitance value is adjusted by directly adjusting the variable capacitor 1910, the magnitude of the resistance value of the access is adjusted by directly adjusting the variable resistor 1920, and the inductance value of the access is adjusted by directly adjusting the variable inductor 1930. The size of the pedestal is precisely adjusted.

For example, as shown in FIGS. 3c-3e, in the variable capacitance line 191, the first switch 1961 is located between the variable capacitor 1910 and the first node 194; in the variable resistance line 192, the second switch 1962 is located The variable resistor 1920 is coupled to the first node 194; in the variable inductor line 193, the third switch 1963 is located between the variable inductor 1930 and the first node 194. Of course, embodiments of the present disclosure include but are not limited thereto.

FIG. 5 is a schematic diagram of an impedance adjustment circuit in another semiconductor device according to a third embodiment of the present disclosure. As shown in FIG. 5, in the variable capacitance line 191, the first switch 1961 is located between the variable capacitor 1910 and the second node 195. That is, the positions of the first switch 1961 and the variable capacitor 1910 in the variable capacitance line 191 can be interchanged. It should be noted that the impedance adjustment circuit in FIG. 5 is described by taking the structure in FIG. 3 e as an example. Of course, the embodiments of the present disclosure include but are not limited thereto, and the impedance adjustment circuit in FIG. 5 may also adopt FIG. 3 c or FIG. 3 d . The structure shown.

Similarly, in the variable resistance circuit, the second switch may also be located between the variable resistor and the second node; in the variable inductance circuit, the second switch may also be located between the variable inductor and the second node The embodiments of the present disclosure are not described herein again.

It should be noted that, in each of the above embodiments, the variable capacitance of the variable capacitance line 191 may be a variable capacitor, and the capacitance is changed by changing the relative effective area or the inter-chip distance between the pole pieces of the variable capacitor. However, the present invention is not limited thereto, and in practical applications, a variable capacitor of the following structure may also be employed.

Specifically, FIG. 6 is a schematic diagram of a variable capacitor according to an embodiment of the present disclosure. As shown in FIG. 6, the variable capacitor 1910 may include a plurality of branches connected in parallel with each other, each branch being provided with at least one sub-capacitor 1911, and a first selection switch 1912. Thus, the total capacitance value of the variable capacitor can be adjusted by closing or opening one or more of the plurality of first selection switches 1912. It should be noted that the variable capacitor can also adopt other structures as long as the capacitance value can be adjusted.

For example, the sub-capacitor can be at least one of a capacitance-capable adjustable capacitance and a capacitance-value fixed capacitance, so that the capacitance value of the adjustable capacitance can be adjusted or continuously adjustable.

Similar to the variable capacitor described above, FIG. 7 is a schematic diagram of a variable resistor according to an embodiment of the present disclosure. As shown in FIG. 7, the variable resistor 1920 may include a plurality of branches connected in parallel with each other, each of which is provided with at least one sub-resistor 1921 and a second selection switch 1922. Thus, the total resistance value of the variable resistor can be adjusted by closing or opening one or more of the plurality of second selection switches 1922. It should be noted that the variable resistor can also adopt other structures as long as the resistance value can be adjusted.

For example, the sub-resistor may be at least one of a resistance value adjustable resistance and a resistance value fixed resistance, so that the resistance value of the adjustable resistance is adjustable or continuously adjustable.

Similarly, FIG. 8 is a schematic diagram of a variable inductor according to an embodiment of the present disclosure. As shown in FIG. 8, the variable inductor 1930 may include a plurality of branches connected in parallel with each other, each branch being provided with at least one sub-inductor 1931, and a third selection switch 1932. Thus, the inductance value of the variable inductance can be adjusted by closing or opening one or more of the plurality of third selection switches 1932. It should be noted that the variable inductor can also adopt other structures as long as the inductance value can be adjusted.

For example, the sub-inductor can be at least one of an inductor with a variable inductance and a fixed inductor with an inductance value, so that the inductance of the adjustable inductor can be adjusted or continuously adjustable.

As another technical solution, an embodiment of the present invention further provides an impedance adjustment method for a semiconductor device, including:

Adjust the impedance of the impedance adjustment circuit to adjust the impedance between the base and ground.

Optionally, when there are a plurality of chambers, at least one of the chambers is provided with an impedance adjustment circuit. In this case, the impedances of the plurality of chambers can be made uniform by adjusting the impedance of the impedance adjusting circuit corresponding to at least one of the chambers.

Thus, on the one hand, the impedances of the plurality of chambers can be kept uniform by the impedance adjusting circuit, so that the magnitudes of the biases of the susceptors in the plurality of chambers can be kept uniform, thereby improving the film layer of the semiconductor device. Consistency and repeatability, which in turn improves the quality of the semiconductor device. On the other hand, the impedance adjusting circuit does not need to be disposed in the cavity of the semiconductor device, and the cavity is not required to be opened when the bias adjustment circuit is used to adjust the bias of the pedestal, thereby presupposing a good bias adjustment effect. Improve the bias adjustment efficiency. In addition, the semiconductor device has a simple structure and a low cost, which is advantageous for promotion.

The impedance adjustment method of the semiconductor device provided by an example of the embodiment includes steps S201-S203.

Step S201: Disconnect the impedance adjusting circuit and measure the magnitude of the bias of the pedestal.

It should be noted that the above-mentioned disconnection impedance adjustment circuit refers to the impedance adjustment circuit being disconnected from the pedestal. For example, the impedance adjustment circuit shown in FIG. 3 e is taken as an example, and the first switch 1961 in the impedance adjustment circuit can be disconnected. The second switch 1962 and the third switch 1963 are used to open the impedance adjustment circuit. It should be noted that the embodiment of the present disclosure includes but is not limited to, and a main switch may be disposed between the first node 194 and the pedestal, and the disconnection impedance adjustment circuit is implemented by disconnecting the main switch.

In addition, the magnitude of the bias of the pedestal refers to the voltage of the pedestal to the ground.

For example, the ped

Step S202: Comparing the magnitude relationship between the bias voltage of the pedestal and the reference bias voltage.

For example, the bias on the susceptor can be selected as the reference bias when the experiment is performed on the reference semiconductor device to select a good process result (good film performance).

Step S203: If the bias of the pedestal is less than the reference bias, close the first switch and turn off the second switch and the third switch, and adjust the size of the variable capacitor to reduce the difference between the bias voltage of the pedestal and the reference bias And if the bias of the pedestal is greater than the reference bias, closing at least one of the second switch and the third switch and opening the first switch, and adjusting at least one of the closed second switch and the third switch The variable resistor and/or variable inductor is sized to reduce the difference between the bias voltage of the pedestal and the reference bias voltage.

It should be noted that, the closing the first switch and disconnecting the second switch and the third switch means: if the impedance adjusting circuit includes one of the second switch and the third switch, disconnecting the impedance adjusting circuit includes And the second switch or the third switch, if the impedance adjusting circuit includes the second switch and the third switch at the same time, disconnecting the second switch and the third switch included in the impedance adjusting circuit. The at least one of closing the second switch and the third switch refers to: closing the second switch or the third switch included in the impedance adjusting circuit if the impedance adjusting circuit includes one of the second switch and the third switch, If the impedance adjustment circuit includes both the second switch and the third switch, the second switch and/or the third switch included in the impedance adjustment circuit are closed.

In the impedance adjustment method of the semiconductor device provided in the embodiment, the charge pair accumulated on the susceptor can be changed by adjusting at least one of the variable resistance and the variable inductance in the impedance adjustment circuit and the variable capacitance The release channel characteristics of the ground change the amount of charge buildup on the pedestal, thereby adjusting the bias of the pedestal. The variable capacitance in the impedance adjusting circuit has a gain effect on the bias of the pedestal, that is, closing the first switch to access the variable capacitor can increase the bias of the pedestal; the variable resistor in the impedance adjusting circuit And the variable inductance has a debuffing effect on the bias of the pedestal, that is, closing the second switch to access the variable resistor can reduce the bias of the pedestal, and closing the third switch to connect the variable inductor It can function to reduce the bias of the susceptor.

Since the bias of the susceptor can affect the properties of the deposited film on the substrate, including film uniformity, stress, crystal quality, etc., the bias of the susceptor can be adjusted by the impedance adjusting circuit, thereby improving the film deposition quality of the semiconductor device. . Moreover, the impedance adjustment method can be provided by the embodiment to keep the magnitudes of the bias voltages of the pedestals of different semiconductor devices consistent, thereby improving the uniformity and repeatability of the film layers in the semiconductor device fabricated by the semiconductor device, thereby improving The quality of the semiconductor device. On the other hand, when the bias adjustment method is used to adjust the bias of the susceptor, it is not necessary to open the cavity, so that the bias adjustment efficiency can be improved while ensuring a better bias adjustment effect.

For example, in the semiconductor device provided in the example of the embodiment, when the bias voltage of the susceptor is less than the reference bias voltage, the first switch is closed and the second switch and the third switch are turned off, and the size of the variable capacitor is adjusted to reduce the base. When the difference between the bias voltage of the seat and the reference bias is closed, if the first switch is closed and the second switch and the third switch are opened to access the variable capacitor, the bias of the base is still less than the reference bias, which can be increased by The capacitance of the variable capacitor increases the bias of the pedestal. If the first switch is closed and the second switch and the third switch are opened to access the variable capacitor, the bias of the pedestal is still greater than the reference bias. The bias of the pedestal is reduced by reducing the capacitance of the variable capacitor.

For example, in the semiconductor device provided in the example of the embodiment, the initial value of the variable capacitor can be set to be an intermediate value of the capacitance value adjustment range of the variable capacitor, thereby facilitating increasing or decreasing the capacitance value of the variable capacitor. For example, when the capacitance value of the variable capacitor is adjusted from 50pF to 1μF, the initial value of the variable capacitor can be set to 5000pF.

For example, in the semiconductor device provided in the example of the embodiment, if the bias of the susceptor is greater than the reference bias, the at least one of the second switch and the third switch is closed and the first switch is turned off, and the closed switch is adjusted. When the size of the variable resistor and/or the variable inductor corresponding to at least one of the second switch and the third switch is to reduce the difference between the bias voltage of the base and the reference bias, the following three cases are included:

(1) closing the second switch and opening the third switch and the first switch to access the variable resistor. At this time, if the second switch is closed and the third switch and the first switch are opened to access the variable resistor, If the bias voltage of the pedestal is still higher than the reference bias voltage, the bias voltage of the susceptor can be reduced by increasing the resistance value of the variable resistor, and if the second switch is closed and the third switch and the first switch are opened, the access can be After the resistance is changed, the bias voltage of the susceptor is less than the reference bias voltage, and the bias voltage of the susceptor can be increased by reducing the resistance value of the variable resistor;

(2) closing the third switch and disconnecting the second switch and the first switch to access the variable inductor. At this time, if the third switch is closed and the second switch and the first switch are opened to access the variable inductor After the bias of the pedestal is still higher than the reference bias, the bias of the pedestal can be reduced by increasing the inductance of the variable inductor. If the third switch is closed and the second switch and the first switch are opened, After the variable inductor is connected, the bias of the pedestal is less than the reference bias, and the bias of the pedestal can be increased by reducing the inductance of the variable inductor;

(3) closing the third switch and the second switch and opening the first switch to access the variable resistor and the variable inductor. At this time, the variable resistor and the variable inductor are connected in parallel, and if the third switch and the second are closed After switching and disconnecting the first switch to connect the variable resistor and the variable inductor, the bias of the pedestal is still higher than the reference bias, and the resistance of the variable resistor can be increased and the inductance of the variable inductor can be increased. The value is used to reduce the bias of the pedestal. If the third switch and the second switch are closed and the first switch is opened to access the variable resistor and the variable inductor, the bias of the pedestal is less than the reference bias voltage. The bias of the pedestal is increased by reducing the resistance value of the variable resistor and decreasing the inductance value of the variable inductance.

For example, in the semiconductor device provided in the example of the embodiment, the initial value of the variable resistor can be set to be an intermediate value of the resistance value adjustment range of the variable resistor, thereby facilitating to increase or decrease the resistance value of the variable resistor. For example, when the resistance value of the variable resistor is adjusted from 100Ω to 100KΩ, the initial value of the variable resistor can be set to 50KΩ. Similarly, setting the initial value of the variable inductance is the middle value of the inductance adjustment range of the variable inductor, thereby facilitating increasing or decreasing the inductance value of the variable inductor. For example, when the inductance value of the variable inductor is adjusted from 100μH to 2000μH, the initial value of the variable inductor can be set to 1000μH.

For example, the impedance adjustment method of the semiconductor device provided by the example of the embodiment further includes:

Measuring a transient spike of a waveform shape of the bias of the pedestal with the bias of the pedestal being greater than the reference bias;

Compare the magnitude of the instantaneous spike to the reference spike; and if the transient spike is greater than the reference spike, close the first switch and adjust the size of the variable capacitor to suppress transient spikes.

Thereby, when the instantaneous peak of the waveform shape of the bias of the susceptor is high, the instantaneous spike can be suppressed by the impedance adjustment method provided by the present embodiment.

For example, in the impedance adjustment method of the semiconductor device provided in the example of the embodiment, the peak value of the reference peak is greater than or equal to 120% of the stable value of the bias voltage of the susceptor.

For example, in the impedance adjustment method of the semiconductor device provided by the example of the embodiment, when the impedance adjustment method provided by the embodiment is used to suppress the transient spike, since the variable capacitor connected has a gain effect on the bias of the pedestal, The bias of the pedestal is increased; therefore, the initial value of the variable capacitor can be the minimum value of the variable capacitor, thereby reducing the influence of the variable capacitance on the magnitude of the bias of the susceptor.

Measuring the magnitude of the bias of the pedestal again;

Comparing the magnitude of the bias of the pedestal with the reference bias; and adjusting the size of the variable resistor and/or the variable inductor corresponding to at least one of the closed second switch and the third switch to reduce the bias of the pedestal The difference from the reference bias.

Therefore, when the impedance adjustment method provided by the embodiment is used to suppress the instantaneous peak, when the variable capacitance is inserted to suppress the instantaneous peak, if the magnitude of the bias of the susceptor changes, the pedestal can be performed by the above process. The magnitude of the bias voltage is adjusted again so that the difference between the magnitude of the bias of the pedestal and the magnitude of the reference bias is within the tolerance range.

There are a few points to note:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may be referred to the general design.

(2) The features of the same embodiment and different embodiments of the present disclosure may be combined with each other without conflict.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

A semiconductor device comprising:

a chamber in which a susceptor for carrying a substrate is disposed;

An impedance adjustment circuit is electrically connected to the base and the ground, respectively, for adjusting an impedance between the base and the ground.
The semiconductor device according to claim 1, wherein said plurality of chambers are provided, and at least one of said chambers is provided with said impedance adjusting circuit.
The semiconductor device according to claim 1 or 2, wherein said impedance adjustment circuit comprises:

a first adjusting circuit for reducing an impedance between the base and the ground;

a second adjusting circuit for increasing an impedance between the base and the ground;

And a selection switch for selectively electrically conducting at least one of the first conditioning circuit and the second conditioning circuit with the pedestal.
The semiconductor device according to claim 3, wherein said first adjustment circuit comprises a variable capacitance line, said variable capacitance line comprising a variable capacitance.
The semiconductor device according to claim 4, wherein said second regulating circuit comprises a variable resistance line, and/or a variable inductance line, wherein said variable resistance line comprises a variable resistor; said variable The inductor circuit includes a variable inductor.
The semiconductor device according to claim 5, wherein said second regulating circuit comprises a variable resistance line and a variable inductance line, and said variable capacitance line, variable resistance line and variable inductance line are connected in parallel with each other The selection switch includes a first switch disposed on the variable capacitance line, a second switch disposed on the variable resistance line, and a third switch disposed on the variable inductance line.
The semiconductor device according to claim 5, wherein said second regulating circuit comprises a variable resistance line and a variable inductance line, said variable resistance line and said variable inductance line being connected in series with each other The variable capacitance lines are connected in parallel with each other; the selection switch includes a first switch disposed on the variable capacitance line, and a second switch disposed on the variable resistance line or the variable inductance line.
The semiconductor device according to claim 1, wherein said semiconductor device further comprises a first node electrically connected to said pedestal, and a second node grounded; said impedance adjusting circuit respectively associated with said first node The second node is electrically connected.
The semiconductor device of claim 8 wherein said second node is directly grounded.
The semiconductor device according to claim 4, wherein said variable capacitance has a capacitance value in a range of 50 pF to 1 μF.
The semiconductor device according to claim 5, wherein said variable resistor has a resistance value in a range of 100 Ω to 100 k Ω.
The semiconductor device according to claim 5, wherein the variable inductance has an inductance value in a range of 100 μH to 2000 μH.
The semiconductor device of claim 1 wherein said chamber further comprises:

a cavity, the pedestal is located inside the cavity, and the impedance adjusting circuit is located outside the cavity.
A method of adjusting impedance of a semiconductor device according to claim 1, comprising:

The impedance of the impedance adjustment circuit is adjusted to adjust the impedance between the base and the ground.
The impedance adjusting method of a semiconductor device according to claim 14, wherein said plurality of chambers are provided, and at least one of said chambers is provided with said impedance adjusting circuit; said impedance adjusting method comprising:

The impedance of the plurality of chambers is maintained to be uniform by adjusting the impedance of the impedance adjusting circuit corresponding to at least one of the chambers.