WO2019005128A1

WO2019005128A1 - Magnetic tunneling junction device with nano-contact to free magnet

Info

Publication number: WO2019005128A1
Application number: PCT/US2017/040405
Authority: WO
Inventors: Charles C. Kuo; Sarah ATANASOV; Mark L. Doczy; Kaan OGUZ; Kevin P. O'brien
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

MTJ material stacks including one or more nano-contact, MTJ devices employing such stacks, and computing platforms employing such MTJ devices. Nano-contacts having lateral dimensions smaller than the lateral dimensions of a free magnet layer may convey a high current density into the free magnetic layer at their point(s) of contact during device operation. With such an architecture lower write currents and/or reduced switching times may be achieved for an MTJ device having a given free magnet area (footprint). A nano- contact may be fabricated with a spacer-based multi-patterning technique.

Description

Magnetic Tunneling Junction Device

With Nano-contact to Free Magnet

Non-volatile memory device performance and density can be improved by reducing memory cell dimensions while maintaining the ability to retain state. Magnetoresistive random-access memory (MRAM) holds the promise of significantly higher density than other technologies such as flash memory.

Some magnetic memory cell architectures utilize a phenomenon known as the tunneling magnetoresi stance (TMR) effect. For a structure including two ferromagnetic layers separated by a thin insulating barrier layer, it is more likely that electrons will tunnel through the barrier layer when magnetizations of the two magnetic layers are in a parallel orientation than if they are not (non-parallel or antiparallel orientation). As such, a magnetic tunneling junction (MTJ), typically comprising a fixed magnetic layer and a free magnetic layer separated by a barrier layer, can be switched between two states of electrical resistance, one state having a low resistance (impedance) and one state with a high resistance (impedance). The greater the differential in resistance, the higher the TMR ratio: (RAP-R_P)/R_P* 100 % where R_P and RAP are resistances for parallel and antiparallel alignment of the magnetizations, respectively. The higher the TMR ratio, the more readily a bit can be reliably stored in association with the MTJ resistive state. The TMR ratio of a given MTJ is therefore an important performance metric of an MTJ-based device.

In one MRAM technology referred to as spin transfer torque memory (STTM), current-induced magnetization switching may be used to set the bit states. Polarization states of one ferromagnetic layer can be switched relative to a fixed polarization of the second ferromagnetic layer via the spin transfer torque phenomenon, enabling states of the MTJ to be set by application of current. Angular momentum (spin) of the electrons may be polarized through one or more structures and techniques (e.g., direct current, spin-hall effect, etc.). These spin-polarized electrons can transfer their spin angular momentum to the

magnetization of the free layer and cause it to precess. As such, the magnetization of the free magnetic layer can be switched by a pulse of current (e.g., in about 1 -10 nanoseconds) exceeding a certain critical value, while magnetization of the fixed magnetic layer remains unchanged as long as the current pulse is below some higher threshold associated with the fixed layer architecture. BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:

FIG. 1 A is an isometric illustration of material layers of an MTJ device with a nano- contact, in accordance with some embodiments; FIG. IB is a cross-sectional view through two adjacent MTJ devices with nano- contacts, in accordance with some embodiments;

FIG. 2 is a cross-sectional view through two adjacent MTJ devices with nano- contacts, in accordance with some embodiments;

FIG. 3A, 3B and 3C are top-down plan views of MTJ devices with nano-contacts, in accordance with some embodiments;

FIG. 4 is a flow diagram illustrating methods of fabricating the MTJ devices illustrated in FIG. 1-3, in accordance with some embodiments;

FIG. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H and 51 are cross-sectional views through two adjacent MTJ devices evolving as operations of the methods illustrated in FIG. 4 are performed, in accordance with some embodiments;

FIG. 6 is a schematic of an MTJ-based memory cell, which includes a perpendicular spin transfer torque element, in accordance with some embodiments;

FIG. 7 is a cross-sectional view of an MTJ-based memory cell, according to some embodiments of the disclosure. FIG. 8 is a schematic illustrating a mobile computing platform and a data server machine employing an MTJ memory device, in accordance with embodiments; and FIG. 9 is a functional block diagram illustrating an electronic computing device, in accordance with some embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material or material "on" a second material or material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

In MTJ devices, magnetization of the free magnetic layer can be switched by a pulse of current exceeding a certain critical value. The critical current value may be dependent on current density within the free layer. For low-power memory operation, low write currents are advantageous. However, reducing the footprint of a free layer within an MTJ device for the sake of reduced write currents at a given current density has the concomitant effect of reducing device stability. The inventors have found that a reduction in the area of an electrode interfacing with a free magnet of the MTJ device can enable a reduction in write current of the device and/or enable an increase in the switching current density within the free magnet. MTJ material stacks including one or more nano-contact, MTJ devices employing such stacks, and computing platforms employing such MTJ devices are described herein. During device operation, nano-contacts having lateral dimensions smaller than the lateral dimensions of a free magnet layer may convey a high current density into the free magnetic layer at their point(s) of contact. With such an architecture, lower write currents and/or reduced switching times may be achieved for an MTJ device having a given free magnet area (footprint). Exemplary MTJ devices having one or more of the features described herein may be employed in devices, such as, but not limited to, embedded memory, embedded non-volatile memory (eNVM), magnetic random access memory (MRAM), and non-embedded or stand-alone memories.

FIG. 1 A illustrates an MTJ material stack 101 for an MTJ device 100, in accordance with some embodiments. In the illustrated example, MTJ device 100 is a columnar or pillar structure with material stack 101 having dot-like layers with layer thickness in a direction (e.g., z-axis) perpendicular to a plane of the device footprint (e.g., x-y axis). MTJ device 100 includes a first electrode 107 (e.g., bottom contact) and a second electrode 180 (e.g., top contact) with material stack 101 between electrodes 107 and 180. Electrode 107 interfaces MTJ device 100 to interconnect metallization 105 present in an underlying layer of an integrated circuit. Electrode 180 interfaces MTJ device 100 to interconnect metallization (not depicted) in an overlying layer of an integrated circuit. MTJ devices 100 may be embedded, or monolithically integrated with, an IC, sharing with the IC any substrate (not depicted) known to be suitable for an IC.

MTJ device 100 includes a free magnet and a fixed magnet separated by an intervening barrier layer that may filter electrons based on their Fermi wavevector. The terms "free magnet" and "fixed magnet" are employed herein to emphasize that each "magnet" may be a composite structure including a plurality of material layers that together comprise a functional component of MTJ device 100. In FIG. 1A, ellipses are drawn between illustrated material layers to further emphasize that MTJ device 100 may have any number of layers even if not specifically illustrated in FIG. 1A.

In the illustrated embodiment, the free magnet includes a free magnet layer 140 over electrode 107. Free magnet layer 140 comprises a ferromagnetic material. As employed herein, the term "ferromagnetic" refers to the magnetic mechanism of the material and such a material need not be an iron alloy, although it may be. As described further below, a free magnet may also include material layers other than free magnet layer 140. A fixed magnet includes a fixed magnet layer 120 that is separated from free magnet layer 140 by at least a barrier layer 130. Fixed magnet layer 120 comprises a ferromagnetic material. As described further below, a fixed magnet may also include material layers other than fixed magnet layer 120.

In some embodiments, MTJ material stack 101 is a perpendicular system. In FIG. 1 A, arrows in magnet layers 120 and 140 show the magnetic easy axis as in the z-direction out of the x-y plane of material layers in MTJ material stack 101. This perpendicular magnetic anisotropy (PMA) may advantageously reduce the switching current between "high" and "low" resistance states and may improve the scalability of MTJ material stack 101. The fixed magnet may comprise any material or stack of materials suitable for maintaining a fixed magnetization direction while the free magnet is magnetically softer (i.e. magnetization can more easily rotate to parallel and antiparallel state with respect to the fixed magnet). Ferromagnetic layers of the fixed and/or free magnets may, for example, comprise ferromagnetic metal alloys doped with one or more non-ferromagnetic

constituents. The ferromagnetic metal alloy may include one or more ferromagnetic constituent while the non-ferromagnetic constituents may, for example, impart an amorphous phase to the alloy, at least in the layer's "as-deposited" state. While in the amorphous phase, PMA may be effectively absent from the alloy until long range order is imparted during a thermal anneal process at which point crystallization within ferromagnetic layers may become nearly lattice matched to the barrier layer crystal structure. In some embodiments, ferromagnetic layers of the fixed and/or free magnets comprise one or more of cobalt (Co), iron (Fe), or nickel (Ni). In some embodiments, ferromagnetic layers of the fixed and/or free magnets comprise a Heusler alloy. Two examples of non-ferromagnetic dopants are boron or carbon, but many other elements may have a similar functional effect. In some exemplary embodiments, fixed magnet layer 120 comprises a CoFeB alloy. In some specific examples, Fe content within the CoFeB is at least 50 at. %. Exemplary embodiments include 20-30 at. % B with one specific alloy being Co2oFe6oB2o. This iron- rich alloy has been found to achieve perpendicular magnetic anisotropy. Other embodiments with equal parts cobalt and iron are also possible (e.g., Co4oFe4oB2o), as are more iron-rich alloys.

Fixed magnet layer 120 advantageously has crystallinity associated with the desired PMA. In some exemplary embodiments, fixed magnet layer 120 has body-centered cubic (BCC) crystal structure, which is advantageous for achieving perpendicular magnetic anisotropy in certain metal alloys comprising one or more of iron, cobalt, and nickel. Fixed magnet layer 120 may further have (001) out-of-plane texture, where texture refers to the distribution of crystallographic orientations within in fixed magnet layer 120. The inventors have found those with iron crystallize with BCC, (001) out-of-plane texture. Fixed magnet layer 120 may have a thickness between approximately 1.0 nm and 2.0 nm, for example. In some exemplary embodiments, free magnet layer 140 also has BCC crystal structure. Free magnet layer 140 may advantageously have (001) out-of-plane texture. Free magnet layer 140 may have a thickness between approximately 1.0 nm and 2.0 nm, for example. The composition of free magnet layer 140 may be the same as that of fixed magnet layer 120 with differences in thickness or the addition of other layers within the fixed or free magnet accounting for greater magnetic softness in the free magnet. In some exemplary embodiments, free magnet layer 140 is also a CoFeB alloy. In some specific examples, Fe content within the CoFeB is at least 50 at. %. Exemplary embodiments include 20-30 at. % B with one specific alloy being Co2oFe6oB2o. Other embodiments with equal parts cobalt and iron are also possible (e.g., Co4oFe4oB2o), as are more iron-rich alloys. Free magnet layer 140 may be one of a stack of material layers (not depicted) making up the free magnet structure. A free magnet stack may, for example, include multiple ferromagnetic material layers with a coupling layer (not depicted) separating adjacent ferromagnetic layers. The alloy compositions for any of these layers may be any of those described above for free magnet layer 140. The coupling layer may comprise one or more of W, Mo, Ta, Nb, V, Hf and Cr, for example.

Barrier layer 130 may be any material or stack of materials suitable for allowing current of a majority spin to pass through the layer, while impeding current of a minority spin (i.e., a spin filter), impacting the tunneling magneto-resistance associated with MTJ material stack 101. Barrier layer 130 may further provide a crystallization template (e.g., BCC with (001) out-of-plane texture) for epitaxy (e.g., solid phase) of the free and/or fixed magnets within MTJ material layer stack 101. In some embodiments, barrier layer 130 is a tunneling dielectric material comprising one or more metal and oxygen (e.g., a metal oxide). In some exemplary embodiments, barrier layer 130 is magnesium oxide (MgO). Between fixed magnet layer 120, and electrode 180 is a cap layer 170. In some embodiments, cap layer 170 comprises a metal oxide (e.g., MgO, VO, WO, TaO, HfO, MoO). Such a capping layer may be absent for some MTJ device implementations, such as a spin-hall effect (SHE) device.

The material layers within an MTJ material stack may vary considerably without deviating from the scope of the present disclosure. For example, , a cap layer 170 is between fixed magnet layer 120 and electrode 180. Cap layer 170 may comprise a metal oxide (e.g., MgO, VO, WO, TaO, HfO, MoO). Such a capping layer may be absent for some MTJ device implementations, such as a spin-hall effect (SHE) device. In further reference to FIG. 1A, one or more intermediate material layers may be disposed between fixed magnet layer 120 and electrode 180. In the illustrated embodiment, for example, MTJ material stack 101 includes an anti -ferromagnetic layer or a synthetic antiferromagnetic (SAF) structure 110. Such layer(s) may be useful for countering a fringing magnetic field associated with fixed magnet layer 120. Exemplary anti-ferromagnetic layers include, but are not limited to, iridium manganese (IrMn) or platinum manganese (PtMn). Exemplary SAF structures include, but are not limited to Co/Pt bilayers, Co/Pd bilayers, CoFe/Pt bilayers, or CoFe/Pd bilayers. In some exemplary embodiments, SAF structure 110 includes a first plurality of bilayers forming a superlattice of ferromagnetic material (e.g., Co, CoFe, Ni) and a nonmagnetic material (e.g., Pd, Pt, Ru). SAF structure 110 may include n bi-layers (e.g., n [Co/Pt] bilayers, or n [CoFe/Pd] bilayers, etc.) that are separated from a p bilayers (e.g., p [Co/Pt]) by an intervening non-magnetic spacer. The spacer may provide antiferromagnetic coupling between the bi-layers. The spacer may be a Ruthenium (Ru) layer less than 1 nm thick, for example. Other layers within SAF structure 110 may have thicknesses ranging from 0.1-0.4 nm, for example. SAF structures and/or anti-ferromagnetic layers may be considered part of a multi-layered fixed magnet. As further shown in FIG. 1 A, electrode 107 makes a nano-contact to free magnet layer 140. In the illustrated embodiment, electrode 107 is in direct contact with both a surface of free magnet layer 140 and a surface of interconnect metallization 105. Although illustrated as an annular structure, electrode 107 may have any architecture such that the nano-contact made to free magnet layer 140 has at least one lateral dimension that is significantly smaller than that of free magnet layer 140. As used herein "significantly" is more than incidental or inherent manufacturing variation (e.g., more than 15%).

In some embodiments, an electrode making a nano-contact to a free magnet layer has an architecture indicative of a self-aligned spacer mask patterning technique. As shown in FIG. 1A, free magnet layer 140 has a first minimum dimension, referred to herein as critical dimension CDMTJ, in the plane of the layer (i.e., lateral width). CDMTJ may be associated with a minimum lithographically definable feature dimension of a given patterning technology, for example. Electrode 107, at least at the contact point with free magnet layer 140, has a lateral width of a second minimum dimension, referred to herein as critical dimension CDNC. CDNC is measured parallel to the plane of free magnet layer 140. CDNC associated with electrode 107 is significantly smaller than CDMTJ associated with free magnet layer 140. In some embodiments, CDNC is no more than half CDMTJ. In some advantageous embodiments, CDNC is between 10% and 25% of CDMTJ. Although MTJ device dimensions can be expected to scale over time, in some exemplary embodiments where CDMTJ is in the range of 20-30 nm, CDNC is in the range of 1-10 nm.

Electrode 107 may further have a lateral nano-contact length of any size, which may be significantly larger than CDNC, and may be equal to, or larger than, CDMTJ. Electrode 107 makes contact to free magnet layer 140 over a nano-contact area that is a function of the lateral width and the lateral length of intersection between free magnet layer 140 and electrode 107. In the illustrated embodiment, electrode 107 has a substantially annular architecture with nano-contact area being approximately n(R²-r²), where R²-r² (i.e., distance between edges) is approximately equal to CDNC. In some exemplary embodiments R is approximately equal to half of CDMTJ. A dielectric material 108 occupies the space within the inner electrode edge having radius r. Radius r may be approximately a quarter of CDMTJ, or less. In some other embodiments R is approximately equal to half of the lateral CD of interconnect metallization 105, which may be larger, substantially equal to, or smaller than CDMTJ. In FIG. 1A, arrows passing through electrode 107 and into free magnet layer 140 represent a write current pulse (I write) delivered by interconnect metallization 105. In FIG. 1, interconnect metallization 105 is rectangular indicating it has been patterned separately from MTJ device 100. Because of the small cross-sectional area (e.g., x-y plane in FIG. 1), current density through the nano-contact of electrode 107 is significantly higher than would be expected for a disk-shaped electrode of CDMTJ, or for an electrode having the CD of interconnect metallization 105. The higher current density within electrode 107 is conveyed into free magnet layer 140 such that, at least at the contact point, current density with free magnet layer 140 is high until spreading into the larger cross-sectional area associated with the CDMTJ. The inventors have found that inducing one or more such locale of high current density within a free magnet layer can advantageously reduce the switching current associated with the free magnet layer. A high current density across the entirety of free magnet layer 140 may not be necessary to set the state of MTJ device 100. The introduction of a nano-contact in accordance with embodiments herein therefore provides a means of constricting current to induce a high current density locale within a free magnet layer of some larger minimum CDMTJ, which can be dimensioned for robust manufacture and high MTJ stability, for example, while remaining operable at low write currents.

A nano-contact may be of any composition that offers suitable conductivity and contact resistance between the free magnet layer and underlying interconnect. In some embodiments, electrode 107 is a metal or metal alloy. In some such embodiments, electrode 107 includes one or more constituents (e.g., metals or non-metal dopants) absent from interconnect metallization 105 and absent from free magnet layer 140. Electrode 107 may also include one or more constituents (e.g., metals or non-metal dopants) present within free magnet layer 140 and/or within interconnect metallization 105. In some advantageous embodiments, electrode 107 includes tantalum (Ta), tungsten (W), or ruthenium (Ru).

Direct contact (e.g., a metallurgical junction) between electrode 107 and free magnet layer 140 ensures a high current density locale within free magnet layer 140 can be developed (e.g., during a write operation). The advantages of a nano-contact may be compromised if any materials introduced between free magnet layer 140 and electrode 107 spread current over greater area than that of the nano-contact. For example, the practice of using a seed layer (not depicted) between free magnet layer 140 and electrode 107, could allow significant lateral current conduction under free magnet layer 140 if such a seed layer is merely inserted under free magnet layer 140 and allowed to have the minimum MTJ dimension CDMTJ. Notably however, dielectric material 108, being amorphous, may reduce the need for a seed layer as templating should not occur within much of the footprint of free magnet layer 140. Hence, the difference in dimensions of electrode 107 and free magnet layer 140 may also enable their direct contact, potentially offering the further advantage of a simpler, lower resistance, MTJ material stack 101.

Completing the discussion of FIG. 1A, the composition of electrode 180 may be any suitable metal or metal alloy. Electrode 180 may include, for example, tantalum (Ta), tungsten (W), or ruthenium (Ru). As also shown in FIG. 1A, electrode 180 has an area associated with the minimum MTJ device dimension CDMTJ as current constriction at fixed magnet end of MTJ device 100 may not offer the same advantages as for electrode 107.

FIG. IB is a cross-sectional view parallel to the x-axis in FIG. 1A and through two adj acent MTJ devices 100 having nano-contacts, in accordance with some embodiments. As shown in FIG. IB, MTJ devices 100 have a lateral dimension CDMTJ and a nominal MTJ device pitch PMTJ. Electrode 107 makes a nano-contact to free layer 140 that is proportional to CDNC, and is surrounded by dielectric material 108. Dielectric material 108 may have any composition known to be suitable as an interlay er dielectric, such as, but not limited to, silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), carbon-doped oxide (SiOC(H)), HSQ, MSQ, or porous dielectric. In the illustrated embodiment, adjacent electrodes 107 of one MTJ device have a pitch Pi that is less than pitch PMTJ. Within the cross-section illustrated in FIG. IB, pitch Pi may be approximately half of pitch PMTJ. Pitch Pi may be approximately half of pitch P2 of interconnect metallization 105. Electrode 107 has a vertical (e.g., z-dimension) nano-contact height HNC. While nano-contact height HNC may vary, in some embodiments it is at least equal to CDNC. For example, where CDNC is 1 - l Onm, HNC is also 1-1 Onm. In some embodiments, nano-contact height HNC is larger than CDNC.

In some embodiments, an MTJ device includes an electrode having more than one nano-contact to a free magnet layer. Depending on the dimensions of the free magnet layer and nano-contact, more than one high current density locale may be generated by coupling the free magnet layer through multiple nano-contacts. For example, the electrode 107 shown in FIG. 2 may be bifurcated within the y-axis of the device layer plane, for example where the y-dimensions of electrode 107 exceed CDMTJ and the etching process employed for patterning MTJ devices 200 etches through any exposed portions of electrode 107. Such in- plane cuts through electrode 107 are further described below.

FIG. 2 is a cross-sectional view through two adjacent MTJ devices 200 with nano- contacts, in accordance with some alternative embodiments having a substantially linear electrode 107. Reference number labels from FIG. 1A are retained in FIG. 2 for material layers that share any of the properties described in the context of FIG. 1A. Rather than the annular architecture illustrated above in FIG. 1A and I B, in MTJ devices 200 electrode 107 is a line of nano-dimensioned metallization extending between interconnect metallization 105 and free magnet layer 140. Electrode 107 again has the lateral dimension CDNC, which may be of a sub-lithographic feature size. The spacing between adjacent electrodes 107, each associated with a different MTJ device, is associated with a nominal critical dimension CD2. In the illustrated embodiment, critical dimension CD2 is at least equal to CDMTJ. In the illustrated embodiment, adjacent electrodes 107 of two adjacent MTJ devices have a pitch P3 that approximately equal to pitch PMTJ. Pitch P3 may also be approximately equal to pitch P2 of interconnect metallization 105.

As further shown in FIG. IB and FIG. 2, interconnect metallization 105 is embedded in a dielectric material 205, which may have any composition known to be suitable as an ILD, such as, but not limited to those described for dielectric material 108. In the example shown, there is a material interface between dielectric material 108 and dielectric material 205. Such an interface may be present even where dielectric material 205 has the same composition as dielectric material 108. Dielectric material (ILD) 220 surrounds MJT material layers 140, 130, 120, as well as electrode 180. Dielectric material 220 may have any composition known to be suitable as an interlay er dielectric, such as, but not limited to those described for dielectric material 108. In the example shown, there is a material interface between dielectric material 108 and dielectric material 220. Such an interface may be present even where dielectric material 220 has the same composition as dielectric material 108. In the illustrated embodiment, the interface between dielectric material 108 and dielectric material 220 is substantially planar with the material interface between free magnet layer 140 and electrode 107. Such planarity is indicative of electrodes 107 having been planarized concurrently with dielectric 108.

In some embodiments, an electrode making a nano-contact with a free magnet layer has crystallinity and/or texture indicative of being formed over a surface that is parallel to a plane of a free magnet layer. Hence, the electrode may display attributes consistent with being formed directly on a surface of an underlying interconnect metallization. For example, crystallinity and/or texture of the electrode may be indicative of being an anisotropic deposition process that deposited the electrode material in a direction substantially normal to a plane of a free magnet layer. As further illustrated in the expanded view of FIG. 2, electrode 107 has crystalline grains 250 with a directionality (i.e., anisotropic grain orientation) indicative of growth that is in the z-dimension. In some embodiments, crystalline grains 250 have <100> texture that is parallel to that of free magnet layer 140, at least over a portion of height HNC. Hence, where free magnet layer 140 has <100> out-of- plane texture, grains 250 may also have <100> out-of-plane texture. For metals with a columnar grain structure similar to that shown in FIG. 2, such an orientation of crystalline grains 250 is indicative of a growth axis extending from an interface of interconnect metallization 105, which is typical of a metal layer being blanket deposited over interconnect metallization 105. In some embodiments, one or more edge of a free magnet layer is aligned with an edge of a nano-contact. Such edge alignment may be indicative of a patterning process employed for the free magnet layer further serving as a second patterning of an underlying electrode. FIG. 3A, 3B and 3C are top-down plan views of MTJ devices 300 with nano- contacts, in accordance with some embodiments. In FIG. 3 A, electrode 107 has a substantially linear architecture, such that the nano-contact area is approximately equal to

CDNC multiplied with the length of intersection between free magnet layer 140 and electrode 107. With CDNC defined with a first (multi-)patterning process, dashed lines 305 represent locations of cuts through electrode 107 separating an electrode into separate nano-contacts od adjacent MTJ devices 300. In this example, after an initial patterning the y-dimension of electrode 107 exceeds CDMTJ. Subsequently, the etching process employed for patterning MTJ devices 200 (e.g., free magnet layer 140) may also etch through any portions of electrode 107 unprotected by an MTJ material stack (e.g., free magnet layer 140).

FIG. 3B illustrates another alternative embodiment where a polygon defined by a length of a nano-dimensioned electrode 107 overlaps a plurality of MTJ devices. As shown, electrode 107 comprises an annulus with R-r (i.e., inner and outer edge) being equal to CDNC, but both R and r are sufficiently large to overlap a set of four neighboring MTJ devices 300. Dashed lines 305 and 310 represent locations of secondary patterning cuts made through electrode 107 bifurcating the annular structure into arc quadrant segments, each of which provides a nano-contact to free magnet layer 140. Cuts through electrode 107 may again be the result of a second patterning performed after defining the annular electrode structure. For example, a second patterning process defining the free magnet layer 140 may additionally define cuts through electrode 107 along the line of intersection between free magnet layer 140 and electrode 107 such that ends of each arc quadrant are aligned with an edge of free magnet layer 140.

FIG. 3C illustrates another alternative embodiment where multiple edges of polygon perimeter defined by a length of a nano-dimensioned electrode 107 overlaps MTJ devices 300. In this example, bifurcation of electrode 107 along the lines 305 result in two separate metal features making separate nano-contacts to free magnet layer 140. Each of the first and second metal features have a lateral width of CDNC.

MTJ material stacks in accordance with the architectures above may be fabricated by a variety of methods applying a variety of techniques and processing chamber

configurations. FIG. 4 is a flow diagram illustrating methods 401 for fabricating the MTJ devices illustrated in FIG. 1-3, in accordance with some embodiments. Methods 401 leverage a self-aligned double (spacer) patterning technique to form an electrode of sufficiently small lateral dimension to make a nano-contact with a free magnet layer that is subsequently formed over the electrode. Methods 401 begin with receiving a substrate with one or more conductive interconnect structures. Any substrate known to be suitable for microelectronic fabrication may be received, such as, but not limited to crystalline silicon substrates. Transistors (e.g., silicon-channeled FETs) and/or one or more levels of interconnect metallization may be present on the substrate as received at operation 410, for example. At operation 420, the electrode metal layer is deposited over the interconnect metallization, making contact with the exposed surface of the underlying interconnect. Any deposition process known to be suitable for the chosen electrode metal may be enlisted at operation 420. At operation 430, a sacrificial layer is deposited over the electrode metal layer and patterned into sacrificial structures. Any material that can be etched and subsequently removed selectively to the underlying metal layer may be deposited by any suitable technique. In some embodiments, a dielectric material, such as but not limited to SiO, SiN, SiON, or SiOC(H), or amorphous carbon, is deposited. Such materials may be deposited by plasma enhanced chemical vapor deposition (PECVD), for example. Such films may be patterned into sacrificial features (e.g., trenches or pillars) according to any photolithographic mask patterning and film etch processes known to be suitable for the material layer composition. At operation 440, a spacer mask is formed along sidewalls of the sacrificial features.

Any film deposition and spacer etch back processing known to be suitable for forming a self-aligned sidewall spacer may be employed at operation 440. For example, a dielectric material, such as but not limited to SiO, SiN, SiON, or SiOC(H), or amorphous carbon, is deposited. In some advantageous embodiments, the dielectric material is deposited with a substantially conformal deposition process that deposits material on a sidewall of a sacrificial feature to nearly the same thickness as on a top surface of the sacrificial feature. Such materials may be deposited, for example, by plasma enhanced chemical vapor deposition (PECVD). The deposited film is then anisotropically etched, for example with an anisotropic dry (plasma) etch, forming a spacer aligned with sidewalls of the sacrificial feature. This sidewall spacer has a lateral dimension dependent on a thickness of the material layer, and does not rely on lithographic techniques to define its lateral critical dimension. As such, the sidewall spacer retained along a sidewall of the sacrificial feature may have nanometer critical dimensions that are sub-lithographic (i.e., below the resolution or capability of a given lithography technique). The sacrificial features are then removed selectively relative to the sidewall spacer.

At operation 450, the exposed portion of the electrode metal layer is then etched while a portion of the electrode metal layer is masked by the sidewall spacer. Any etch process known to be suitable for the chosen electrode metal composition may be employed. In some advantageous embodiments, the metal layer is etched with an anisotropic dry (plasma) etch process. An isotropic etch may also be employed to further reduce the lateral nano-contact dimensions, if desired. Anisotropic and isotropic etch techniques may also be combined, for example isotropically etching a metal feature first patterned with anisotropic etching. Following the electrode metal etch, any remaining sidewall spacer may be removed selectively relative to the electrode metal. Methods 401 continue at operation 460 where a dielectric is deposited over the patterned electrode, and planarized to expose the nano-contact surface. Any deposition and/or planarization process known may be enlisted at operation 460. In some embodiments, operation 460 includes a flowable dielectric deposition and/or a chemical-mechanical planarization (CMP) process. At operation 460 a free magnet layer is deposited over the nano-contact and surrounding dielectric material. Additional layers of the MTJ device are then formed over the free magnet layer at operation 470 according to any suitable techniques. The MTJ material layers are patterned according to any known techniques to form separate MTJ devices, each having a free magnet layer coupled to an underlying interconnect through a nano-contact. Various thermal processes (e.g., thermal anneals), and additional ILD deposition and/or interconnect metallization processes may be performed to complete an IC including the MTJ devices at operation 480. FIG. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H and 51 are cross-sectional views through two adjacent MTJ devices evolving as operations of the methods 401 are performed, in accordance with some embodiments. FIG. 5 A illustrates a substrate 501 that might be received as a starting material. Substrate 501 may be any known to be suitable for microelectronic fabrication, such as, but not limited to substrates including one or more layers of crystalline silicon. Substrate 501 may further include transistors (e.g., silicon- channeled FETs) and/or one or more levels of interconnect metallization. In the example shown in FIG. 5A, substrate 501 includes dielectric material (ILD) 205, a top surface of which is substantially planarized a top surface of interconnect metallization 105.

As shown in FIG. 5B, electrode metal layer 505 has been blanket deposited over interconnect metallization 105 and ILD 205. Sacrificial material layer 515 has been blanket deposited over electrode metal layer 505. Any deposition processes known to be suitable for these material layers may be employed, such as, but not limited to, physical vapor deposition (PVD), ionized metal plasma (IMP), CVD, PECVD, atomic layer deposition (ALD), flowable CVD (FCVD), or spin-on deposition. As shown in FIG. 5C, sacrificial layer 515 is patterned into sacrificial feature 516.

Any patterning technique suitable for the selected sacrificial material, and dimensions of sacrificial feature 516, may be practiced. Depending on mask polarity, sacrificial feature 516 or trench 510 may comprise the majority of the area. In the illustrated embodiment, a lithographic patterning process may be performed to pattern a mask, and trench 510 is then etched into a region of sacrificial layer 515 that is unprotected by the mask. Sacrificial layer 515 may be etched with any etch process, such as, but not limited to a plasma (dry) etch. Trench 510 extends through the thickness of sacrificial layer 515 to expose a portion of metal layer 505. As shown in FIG. 5C, trench 510 has at least one sidewall aligned over interconnect metallization 105. Although each trench 510 is aligned over separate interconnect metallization 105, in alternative embodiments a single trench may be aligned over two, or more, adjacent interconnect metallizations. For example, a single trench may be centered between a set of four nearest neighboring interconnect metallizations.

As shown in FIG. 5D, a mask layer 520 is formed over a sidewall of sacrificial feature 516 and over the feature sidewalls (i.e., lining a sidewall of trench 510). Any technique known for lining a trench may be practiced to form mask layer 520. Mask layer 520 may be of any composition known to be suitable as an etch mask for electrode metal layer 505 and also suitable for forming a sidewall spacer along the sidewall of trench 510. Any deposition technique known to be suitable for the chosen material may be enlisted. In some embodiments where mask layer 520 includes at least one SiO, SiN, SiON, or amorphous carbon, a CVD, PECVD, or ALD process is employed to deposit a 1-20 nm thick layer of material. More or less material may be deposited, depending on conformality of the deposition technique, to have a thickness over the trench sidewall (as a measured in a direction normal from the trench sidewall) that is 1-10 nm, for example.

As shown in FIG. 5E, mask layer 520 is then anisotropically etched back to form a sidewall spacer 525 along the trench/sacrificial feature sidewall. The etch back may be without a mask (i.e., a blanket etch) or it may be masked if mask layer 520 is also employed for defining interconnect routing (not depicted). As a result of the topography associated with the trench/sacrificial feature sidewall, a self-aligned spacer mask is retained adjacent to the sidewall. The lateral CD of sidewall spacer 525 is some function of the thickness mask layer 520 was deposited and the extent of chemical (isotropic) etch associated with the etch back process. In some embodiments, the etch back of mask layer 520 forms a sidewall spacer with a lateral CD of 1-lOnm. Following sidewalls of the sacrificial feature, sidewall spacer 525 can be expected to demark an enclosed perimeter of a polygon. In some embodiments, a second patterning process (not depicted) is performed to cut such polygons into two or more isolated or discontinuous segments. For example, where single trench is centered between two or more neighboring interconnect metallizations, a "spacer-cut" patterning process is employed to separate the sidewall spacer into separate segments with one segment over each of the interconnect metallizations. In some other embodiments where the polygon has lateral dimensions approximately equal to those of the MTJ device and/or will overlap only one MTJ device, no secondary spacer-cut patterning may be needed.

As shown in FIG. 5G, metal layer 505 may then be etched while masked by sidewall spacer 525. The lateral CD of electrode 107 is some function of the lateral CD of sidewall spacer 525 and the extent of chemical (isotropic) etch associated with the metal etch process. In some further embodiments, electrode 107 may be deliberately etched isotropically or partially oxidized to further reduce the lateral CD of electrode 107 relative to sidewall spacer 525. For embodiments where the spacer mask was not cut by a second patterning, the metal can be expected to demark an enclosed perimeter of a polygon. In some embodiments, that polygon overlaps only one MTJ device, for example forming an annulus aligned over an interconnect metallization 105.

As shown in FIG. 51, dielectric 108 is deposited around electrodes 107 with any suitable dielectric deposition process. Dielectric 108 may be then planarized, for example with any suitable CMP process, to expose a nano-contact surface of electrodes 107 and substantially planarize a top surface of dielectric 108. Layers of an MTJ material stack are then deposited over dielectric 108, and over the nano-contact surface of electrodes 107. In the illustrated example, free magnet layer 140 is deposited directly on dielectric 108, and on the nano-contact surface of electrodes 107. Barrier layer 130 is deposited over free magnet layer 140. Fixed magnet layer 120 is deposited over barrier layer 130, and electrode 180 is deposited over fixed magnet layer 120. Any deposition techniques may be employed to deposit the MTJ layers as embodiments herein are not limited in this respect.

As shown in FIG. 51, the MTJ material stack is patterned into separate MTJ devices 200, for example with any lithographic masking process and anisotropic etch process compatible with the various layers of the MTJ material stack. The MTJ device patterning etch exposes dielectric 108, forming MTJ devices with a lateral dimension of some nominal CD that is significantly larger than that of electrode 107. In some embodiments, the MTJ device patterning is further employed to etch through any electrode metal unprotected by an overlying layer of the MTJ material stack (e.g., free magnet layer 140). ILD 220 is then deposited over MTJ devices 200 and planarized with a top surface of electrode 180 in preparation for subsequent interconnect metallization that may be fabricated according to any known techniques. Where a portion of electrode metal was etched during the MTJ device patterning, ILD 220 can be expected to backfill any resulting recesses (e.g., between dielectric 108 and an edge of electrode 107 that is aligned to an edge of free magnet layer 140).

In some embodiments, the MTJ devices having one or more of the features or attributes described above function essentially as a resistor, where the resistance of an electrical path through the MTJ may exist in two resistive states, either "high" or "low," depending on the direction or orientation of magnetization in the free magnetic layer(s) and in the fixed magnetic layer(s). In the case that the spin direction is down (minority) in the free magnetic layer(s), a high resistive state exists and the directions of magnetization in the coupled free magnet and the fixed magnet are substantially opposed or anti-parallel with one another. In the case that the spin direction is up (majority) in a ferromagnetic material layer of the coupled free magnet, a low resistive state exists, and the directions of magnetization in the ferromagnetic layers of the coupled free magnet and the fixed magnet are substantially aligned or parallel with one another. The terms "low" and "high" with regard to the resistive state of the MTJ device and are relative to one another. In other words, the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa. Thus, with a detectible difference in resistance, the low and high resistive states can represent different bits of information (i.e. a "0" or a "1").

The direction of magnetization in the ferromagnetic layer(s) may be switched through a process called spin transfer torque ("STT") using a spin-polarized current. An electrical current is generally non-polarized (e.g. consisting of about 50% spin-up and about 50% spin-down electrons). A spin-polarized current is one with a greater number of electrons of either spin-up or spin-down. The spin-polarized current may be generated by passing a current through the fixed magnetic layer. The electrons of the spin polarized current from the fixed magnet may tunnel through the barrier layer and transfer spin angular momentum to a ferromagnetic layer of the free magnet, wherein the ferromagnetic layer will orient its magnetic direction from anti-parallel to that of the fixed magnet, or parallel.

The spin-hall effect may also be employed to generate spin-polarized current through a particular electrode material that is in contact with a free magnet. For such embodiments, the ferromagnetic material layer(s) of a free magnet may be oriented without applying current through the fixed magnet and other material layers of the MTJ device. In either implementation, the free magnetic layer may be returned to its original orientation by reversing the current. Thus, an MTJ device may store a single bit of information ("0" or "1") by its state of magnetization. The information stored in the MTJ device is sensed by driving a current through the MTJ material stack. The magnetic layer(s) of the free magnet do not require power to retain their magnetic orientations. As such, the state of the MTJ device may be preserved when power to the device is removed. Therefore, a spin transfer torque memory bit cell including the MTJ material stacks described herein are considered nonvolatile.

FIG. 6 is a schematic of an MTJ memory bit cell 601, which includes a spin transfer torque element 610, in accordance with some embodiments. The spin transfer torque element 610 includes a free magnet including at least one fixed magnet layer 120 and one free magnet layer 140. Element 610 further includes electrode 107 making a nano-contact to the free magnet layer 140. Barrier layer 130 is located between the free magnet and the fixed magnet. Electrode 180 is proximate to the fixed magnet. Electrode 180 is electrically coupled to a first metal interconnect 692 (e.g., bit line). Electrode 107 is electrically connected to a second metal interconnect 691 (e.g., source line) through a selector. In the exemplary embodiment, the selector is transistor 615 that is further connected to a third metal interconnect 693 (e.g., word line) in any manner conventional in the art. Altematively, for example in a cross-point architecture, transistor 615 may replaced with a two-terminal selector. In SHE implementations electrode 180 may also be coupled to a fourth metal interconnect 694 (e.g., maintained at a reference potential relative to first metal interconnect 692).

The spin transfer torque memory bit cell 601 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as understood by those skilled in the art of solid state non-volatile memory devices. A plurality of the spin transfer torque memory bit cells 601 may be operably connected to one another to form a memory array (not shown), and the memory array can be incorporated into a non-volatile memory device following any known techniques and architectures.

In some embodiments, transistors are formed in the front end of the line (FEOL) while an MTJ device is formed within the back end of the line (BEOL). Fig. 7 illustrates a cross-section 700 of a die layout including MTJ device 100 located in metal 3 and metal 2 layer regions, according to some embodiments of the disclosure. Elements in FIG. 7 having the same reference numbers (or names) as the elements of any other figures or description provided herein can comprise materials, operate, or function substantially as described elsewhere herein.

Cross-section 700 illustrates an active region having a transistor MN comprising diffusion region 701, a gate terminal 702, drain terminal 704, and source terminal 703. The source terminal 703 is coupled to SL (source line) via polysilicon or a metal via, where the SL is formed on Metal 0 (M0). In some embodiments, the drain terminal 704 is coupled to MOa (also metal 0) through via 705. The drain terminal 704 is coupled to electrode 107 through via 0-1 (e.g., via connecting metal 0 to metal 1 layers), metal 1 (Ml), via 1-2 (e.g., via connecting metal 1 to metal 2 layers), and Metal 2 (M2). In some embodiments, MTJ device 100 is formed in the Metal 3 (M3) region. In some embodiments, the perpendicular fixed magnet of MTJ device 100 couples to electrode 107 and the perpendicular free magnet couples to the bit-line (BL) through Via 3-4 (e.g., via connecting metal 4 region to metal 4 (M4)). In this example, bit-line is formed on M4. In other embodiments, MTJ device 100 is formed in the metal 2 region and/or Via 1-2 region. FIG. 8 illustrates a system 800 in which a mobile computing platform 805 and/or a data server machine 806 employs an MTJ device with an nano-contacted free magnet layer, for example as described elsewhere herein. Server machine 806 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes data memory and processor circuitry 850.

The mobile computing platform 805 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 805 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 810, and a battery 815.

Whether disposed within the integrated system 810 illustrated in the expanded view 820, or as a stand-alone packaged device within the server machine 806, SOC 860 includes at least an MTJ device with an nano-contacted free magnet layer. SOC 860 may further include memory circuitry and/or a processor circuitry 850 (e.g., STTM, MRAM, a microprocessor, a multi-core microprocessor, graphics processor, etc.). Any of controller 835, PMIC 830, or RF (radio frequency) integrated circuitry (RFIC) 825 may also be communicatively coupled to an MTJ device, such as an embedded STTM employing MTJ material stacks including one or more carbon-doped ferromagnetic layers.

As further illustrated, in the exemplary embodiment, RFIC 825 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these SoC modules may be integrated onto separate ICs coupled to a package substrate, interposer, or board.

FIG. 9 is a functional block diagram of a computing device 900, arranged in accordance with at least some implementations of the present disclosure. Computing device 900 may be found inside platform 805 or server machine 806, for example. Device 900 further includes a motherboard 902 hosting a number of components, such as, but not limited to, a processor 904 (e.g., an applications processor), which may further incorporate embedded magnetic memory 930 based on MTJ material stacks including one or more carbon-doped ferromagnetic layers, in accordance with embodiments of the present disclosure. Processor 904 may be physically and/or electrically coupled to motherboard 902. In some examples, processor 904 includes an integrated circuit die packaged within the processor 904. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory. In various examples, one or more communication chips 906 may also be physically and/or electrically coupled to the motherboard 902. In further implementations,

communication chips 906 may be part of processor 904. Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to motherboard 902. These other components include, but are not limited to, volatile memory (e.g., DRAM 932), other non-volatile memory 935 (e.g., flash memory), a graphics processor 922, a digital signal processor, a crypto processor, a chipset 912, an antenna 925, touchscreen display 915, touchscreen controller 975, battery 915, audio codec, video codec, power amplifier 921, global positioning system (GPS) device 940, compass 945, accelerometer, gyroscope, speaker 920, camera 941. Computing device 900 may also include a mass storage device (not depicted), such as a hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), or the like.

Communication chips 906 may enable wireless communications for the transfer of data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 906 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 900 may include a plurality of communication chips 906. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that the disclosure is not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below.

In one or more first examples, a magnetic tunneling junction (MTJ) device comprises a first electrode having a lateral width of a first critical dimension (CD), a free magnet layer over the first electrode, the free magnet layer having a lateral width of a second CD that is larger than the first CD, and wherein an edge of the free magnet layer is aligned with an edge of the first electrode, a barrier layer over the free magnet layer, a fixed magnet layer over the barrier layer, and a second electrode over the fixed magnet layer. In one or more second examples, for any of the first examples the first CD is no more than half the second CD.

In one or more third examples, for any of the first through second examples the first electrode electrically couples the free magnet layer to an underlying interconnect metallization having a minimum lateral width that is larger than the first CD.

In one or more fourth examples, for any of the first through third examples the first electrode comprises an annulus, and the first CD is equal to a difference between an inner and outer edge of the annulus.

In one or more fifth examples, for any of the fourth examples the outer edge of the annulus is aligned with the edge of the free magnet layer.

In one or more sixth examples, for any of the first through the fifth examples the first electrode has a height normal to the lateral width that is at least equal to the first CD.

In one or more seventh examples, for any of the sixth examples the first electrode comprises a metal or metal alloy having columnar grains with <100> texture normal to the lateral width.

In one or more eighth examples, for any of the first through the seventh examples the first electrode contacts the free magnet layer over a contact area that is a function of the lateral width and a lateral length, which is at least equal to the second CD.

In one or more ninth examples, for any of the first through the eighth examples the first electrode comprises first and second metal features in contact with the free magnet layer, the first and second metal features each having a lateral width of the first CD.

In one or more tenth examples a system, comprises a data processor, and a data memory coupled to the processor, the memory comprising the MTJ device in any of the first through the ninth examples.

In one or more eleventh examples, a magnetoresistive random access memory (MRAM) device comprises a first MTJ device comprising a first bottom electrode having a lateral width of a first critical dimension (CD), a first free magnet layer over the first bottom electrode, the first free magnet layer having a lateral width of a second CD that is larger than the first CD, and having an edge that is aligned with an edge of the first electrode, a first barrier layer over the first free magnet layer, a first fixed magnet layer over the first barrier layer, and a first top electrode over the first fixed magnet layer. The MRAM device comprises a second MTJ device adjacent to the first MTJ device, the second MTJ device comprising a second bottom electrode having a lateral width of the first CD, a second free magnet layer over the second bottom electrode, the second free magnet layer having a lateral width of the second CD, and having an edge that is aligned with an edge of the second electrode, a second barrier layer over the second free magnet layer, a second fixed magnet layer over the second barrier layer, and a second top electrode over the second fixed magnet layer. The MRAM device comprises a bit line and a source line coupled to the first and second MTJ devices.

In one or more twelfth examples, for any of the eleventh examples the first and second bottom electrodes each comprises first and second metal features and the edge of the free magnet layer is aligned with an edge of each of the first and second metal features. In one or more thirteenth examples, for any of the eleventh through twelfth examples the first CD is no more than half the second CD.

In one or more fourteenth examples, a method of forming a magnetic tunneling junction (MTJ) device comprises depositing a metal over a substrate surface, depositing a sacrificial material over the metal, patterning the sacrificial material into a sacrificial feature, depositing a masking material over a sidewall of the sacrificial feature, etching the masking material into a sidewall spacer, removing the sacrificial feature selectively to the sidewall spacer, forming an electrode by etching the metal unprotected by the sidewall spacer, depositing a dielectric layer over the electrode, planarizing the dielectric layer to expose a portion of the electrode, depositing a free magnet layer over the exposed portion of the electrode and over the dielectric layer, depositing a barrier layer over the free magnet layer, depositing a fixed magnet layer over the barrier layer, and depositing a second electrode over the fixed magnet layer.

In one or more fifteenth examples, for any of the fourteenth examples the method further comprises patterning the MTJ device by etching through at least the free magnet layer and exposing the dielectric layer. In one or more sixteenth examples, for any of the fifteenth examples patterning the MTJ device further comprises etching through a portion of the electrode unprotected by the free magnet layer.

In one or more seventeenth examples, for any of the fourteenth through sixteenth examples the spacer has a first CD, and the free magnet layer is etched to a second CD, larger than the first CD.

In one or more eighteenth examples the first CD is no more than half the second CD.

In one or more nineteenth examples the substrate includes metallization in contact with the metal layer, and the sacrificial feature comprises a trench or a pillar having a sidewall that extends over the metallization.

In one or more twentieth examples the sidewall extends a lateral length that exceeds a lateral pitch of two adjacent MTJ devices, the method further comprises patterning the two adjacent MTJ devices by etching through at least the free magnet layer, and through a portion of the electrode extending between the two adjacent MTJ devices.

In one or more twenty-first examples a system, comprises a data processing means, and a data storage means coupled to the processing means, the storage means comprising the MTJ device in any of the first through the ninth examples.

In one or more twenty-second examples, the system further comprises a radio signal receiving means coupled to the processing means, and an electrical energy storage means coupled to power the processing means.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:

1. A magnetic tunneling junction (MTJ) device, comprising:

a first electrode having a lateral width of a first critical dimension (CD);

a free magnet layer over the first electrode, the free magnet layer having a lateral width of a second CD that is larger than the first CD, and wherein an edge of the free magnet layer is aligned with an edge of the first electrode;

a barrier layer over the free magnet layer;

a fixed magnet layer over the barrier layer; and

a second electrode over the fixed magnet layer.

2. The MTJ device of claim 1, wherein the first CD is no more than half the second CD.

3. The MTJ device of claim 1, wherein the first electrode electrically couples the free

magnet layer to an underlying interconnect metallization having a minimum lateral width that is larger than the first CD.

4. The MTJ device of claim 3, wherein the first electrode comprises an annulus, and the first

CD is equal to a difference between an inner and outer edge of the annulus.

5. The MTJ device of claim 4, wherein the outer edge of the annulus is aligned with the edge of the free magnet layer.

6. The MTJ device of claim 1, wherein the first electrode has a height normal to the lateral width that is at least equal to the first CD.

7. The MTJ device of claim 6, wherein the first electrode comprises a metal or metal alloy having columnar grains with <100> texture normal to the lateral width.

8. The MTJ device of claim 1, wherein the first electrode contacts the free magnet layer over a contact area that is a function of the lateral width and a lateral length, which is at least equal to the second CD.

9. The MTJ device of claim 1 , wherein the first electrode comprises first and second metal features in contact with the free magnet layer, the first and second metal features each having a lateral width of the first CD.

10. A system, comprising:

a data processor; and

a data storage memory coupled to the processor, the memory comprising the MTJ device recited in any one of claims 1 -9.

11. A magnetoresistive random access memory (MRAM) device, comprising:

a first MTJ device comprising:

a first bottom electrode having a lateral width of a first critical dimension (CD); a first free magnet layer over the first bottom electrode, the first free magnet layer having a lateral width of a second CD that is larger than the first CD, and having an edge that is aligned with an edge of the first electrode; a first barrier layer over the first free magnet layer;

a first fixed magnet layer over the first barrier layer; and

a first top electrode over the first fixed magnet layer;

a second MTJ device adjacent to the first MTJ device, the second MTJ device comprising: a second bottom electrode having a lateral width of the first CD;

a second free magnet layer over the second bottom electrode, the second free magnet layer having a lateral width of the second CD, and having an edge that is aligned with an edge of the first electrode;

a second barrier layer over the second free magnet layer;

a second fixed magnet layer over the second barrier layer; and

a second top electrode over the second fixed magnet layer; and

a bit line and a source line coupled to the first and second MTJ devices.

12. The MRAM device of claim 1 1, wherein the first and second bottom electrodes each comprises first and second metal features and the edge of the free magnet layer is aligned with an edge of each of the first and second metal features.

13. The MRAM device of claim 1 1, wherein the first CD is no more than half the second

CD.

14. A method of forming a magnetic tunneling junction (MTJ) device, comprising:

depositing a metal over a substrate surface;

depositing a sacrificial material over the metal;

patterning the sacrificial material into a sacrificial feature;

depositing a masking material over a sidewall of the sacrificial feature;

etching the masking material into a sidewall spacer;

removing the sacrificial feature selectively to the sidewall spacer;

forming an electrode by etching the metal unprotected by the sidewall spacer;

depositing a dielectric layer over the electrode;

planarizing the dielectric layer to expose a portion of the electrode;

depositing a free magnet layer over the exposed portion of the electrode and over the

dielectric layer;

depositing a barrier layer over the free magnet layer;

depositing a fixed magnet layer over the barrier layer; and

depositing a second electrode over the fixed magnet layer.

15. The method of claim 14, further comprising patterning the MTJ device by etching

through at least the free magnet layer and exposing the dielectric layer.

16. The method of claim 15, wherein patterning the MTJ device further comprises etching through a portion of the electrode unprotected by the free magnet layer.

17. The method of claim 15, wherein the spacer has a first CD, and the free magnet layer is etched to a second CD, larger than the first CD.

18. The method of claim 17, wherein the first CD is no more than half the second CD.

19. The method of claim 14, wherein the substrate includes metallization in contact with the metal layer; and

wherein the sacrificial feature comprises a trench or a pillar having a sidewall that extends over the metallization.

20. The method of claim 14, wherein:

the sidewall extends a lateral length that exceeds a lateral pitch of two adjacent MTJ

devices;

the method further comprises patterning the two adjacent MTJ devices by etching through at least the free magnet layer, and through a portion of the electrode extending between the two adjacent MTJ devices.