CN112750943A - Magnetic tunnel junction structure and manufacturing method - Google Patents
Magnetic tunnel junction structure and manufacturing method Download PDFInfo
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- CN112750943A CN112750943A CN201911046315.9A CN201911046315A CN112750943A CN 112750943 A CN112750943 A CN 112750943A CN 201911046315 A CN201911046315 A CN 201911046315A CN 112750943 A CN112750943 A CN 112750943A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
Abstract
The magnetic tunnel junction structure is characterized in that a non-conductive current blocking layer is formed between the free layer and the bottom electrode, and a non-conductive interlayer dielectric layer is formed on the periphery of the bottom electrode, so that current passing through the free layer flows to the bottom electrode from the edge of the free layer along the periphery of the current blocking layer. According to the method, the non-conductive current barrier layer and the interlayer dielectric layer are added below the free layer, the current direction passing through the free layer is changed, the thickness of spin polarized electrons flowing through the free layer is increased in a phase-changing mode, and therefore the absorption rate of spin transfer torque is enhanced.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a magnetic tunnel junction structure and a manufacturing method thereof.
Background
Magnetic Random Access Memory (MRAM) in a Magnetic Tunnel Junction (MTJ) having Perpendicular Anisotropy (PMA), as a free layer for storing information, has two magnetization directions in a vertical direction, that is: upward and downward, respectively corresponding to "0" and "1" or "1" and "0" in binary, in practical application, the magnetization direction of the free layer will remain unchanged when reading information or leaving empty; during writing, if a signal different from the existing state is input, the magnetization direction of the free layer will be flipped by one hundred and eighty degrees in the vertical direction. The ability of the magnetization direction of the free layer of the magnetic random access Memory to be kept unchanged is called data retention ability or thermal stability, and the requirement is different in different application situations, for a typical Non-volatile Memory (NVM), the requirement of data retention ability is to retain data for ten years at 125 ℃, and the data retention ability or thermal stability is reduced when external magnetic field flipping, thermal disturbance, current disturbance or multiple read-write operations are performed.
Experiments show that the free layer of the magnetic random access memory shows in-plane anisotropy when the thickness of the free layer is thicker, shows perpendicular anisotropy when the thickness of the free layer is thinner, and the perpendicular magnetic anisotropy disappears when the free layer is too thick, so that the device cannot work. Meanwhile, the excessively thin free layer increases the critical switching current, and decreases the Tunneling Magnetoresistance (TMR), which increases the error rate during the read operation.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a magnetic tunnel junction structure and a manufacturing method thereof for adjusting a free layer current by disposing an insulating or low-k dielectric.
The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.
According to the magnetic tunnel junction structure provided by the application, the magnetic tunnel junction is arranged on a magnetic random access memory unit, the magnetic tunnel junction is formed on a bottom electrode, the bottom electrode is positioned on a substrate with a through hole, the magnetic tunnel junction at least comprises a free layer, a barrier layer and a reference layer from bottom to top, wherein a non-conductive current blocking layer is formed between the free layer and the bottom electrode, a non-conductive interlayer dielectric layer is formed on the periphery of the bottom electrode, and current passing through the free layer flows to the bottom electrode from the edge of the free layer along the periphery of the current blocking layer.
The technical problem solved by the application can be further realized by adopting the following technical measures.
In an embodiment of the present application, a groove is formed on a surface of the bottom electrode contacting the free layer, and the current blocking layer is formed in the groove.
In an embodiment of the present application, a part or all of the diameter length of the current blocking layer is smaller than the contact range of the bottom electrode and the free layer.
In one embodiment of the present application, the current blocking layer has a thickness of 10-30 nm.
In an embodiment of the present application, the interlayer dielectric layer is made of a low-k dielectric. In some embodiments, the interlayer dielectric layer is made of silicon dioxide, silicon nitride, magnesium oxide, aluminum oxide, green-house phosphorosilicate glass or phosphosilicate glass.
In an embodiment of the present application, the current blocking layer and the interlayer dielectric layer are made of the same or different materials.
Another objective of the present application is to provide a method for fabricating a magnetic tunnel junction structure disposed in a magnetic random access memory cell, the method comprising the steps of: forming a bottom electrode on the substrate including the via hole; the method comprises the steps of defining a region of a current blocking layer on a bottom electrode in a graphical mode, and forming a corresponding range groove in the region of the current blocking layer; the magnetic tunnel junction area is defined in a graphical mode, and a part of the bottom electrode which does not belong to the magnetic tunnel junction area is removed; configuring a non-conductive medium in the region of the current blocking layer and the periphery of the bottom electrode to form a current blocking layer and an interlayer medium layer; forming a multilayer film over the bottom electrode, the multilayer film comprising a free layer, a barrier layer, a reference layer, and a hard mask layer; and removing the part of the multilayer film which does not belong to the magnetic tunnel junction region, and forming a protective layer above the multilayer film and the interlayer dielectric layer.
In one embodiment of the present application, the thickness of the recess is 10-30 nm.
In one embodiment of the present application, the substrate having the through hole is subjected to a chemical mechanical polishing process to treat the surface, and the bottom electrode is deposited by a physical vapor deposition method; the thickness of the bottom electrode is 20-50 nm, and the material of the bottom electrode is tantalum, tantalum nitride, titanium nitride or tungsten nitride, preferably titanium nitride.
In an embodiment of the present application, the pattern definition operation is performed by a photolithography process.
In an embodiment of the present application, the forming of the current blocking region, the removing of a portion of the bottom electrode, and the removing of a portion of the multilayer film are performed by plasma etching or reactive ion etching.
In an embodiment of the present application, the protective film is formed by chemical vapor deposition, and the material of the protective film is silicon nitride.
In an embodiment of the present application, the pattern definition operation is performed by a photolithography process.
In one embodiment of the present application, the interlayer dielectric layer is formed to a thickness of 50-100 nm, and the current blocking layer is polished to be flush with the surface of the bottom electrode.
According to the method, the non-conductive current barrier layer and the interlayer dielectric layer are added below the free layer, the current direction passing through the free layer is changed, the thickness of spin polarized electrons flowing through the free layer is increased in a phase-changing mode, and therefore the absorption rate of spin transfer torque is enhanced.
Drawings
FIG. 1 is a diagram illustrating an MRAM cell and a write current direction according to an embodiment of the present invention;
fig. 2 to 8 are schematic views illustrating a process for fabricating a Magnetic Tunnel Junction (MTJ) cell.
Reference symbol: 101-bottom electrode, 102-current blocking layer, 103-interlayer dielectric layer, 201-free layer, 202-barrier layer, 203-reference layer, 204-hard mask layer, 205-protective layer
Detailed Description
Refer to the drawings wherein like reference numbers refer to like elements throughout. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.
The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. In the present application, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like are merely referring to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting.
The terms "first," "second," "third," and the like in the description and in the claims of the present application and in the above-described drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "include" and "have," as well as variations of other related examples, are intended to cover non-exclusive inclusions.
The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts of the present application. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it will be understood that terms such as "including," "having," and "containing" are intended to specify the presence of the features, integers, steps, acts, or combinations thereof disclosed in the specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.
The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.
In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of a magnetic tunnel junction structure and a method for fabricating the same according to the present invention will be provided with reference to the accompanying drawings and embodiments.
FIG. 1 is a diagram illustrating an MRAM cell and a write current direction according to an embodiment of the present invention. As shown in fig. 1, in an embodiment of the present application, a magnetic tunnel junction structure is disposed in a magnetic random access memory cell, the magnetic tunnel junction is formed on a bottom electrode 101, the bottom electrode 101 is located on a substrate having a through hole, the magnetic tunnel junction at least includes a free layer 201, a barrier layer 202, and a reference layer 203 from bottom to top, wherein a non-conductive current blocking layer 102 is formed between the free layer 201 and the bottom electrode 101, and a non-conductive interlayer dielectric layer 103 is formed on the periphery of the bottom electrode 101, so that a current passing through the free layer 201 flows from an edge of the free layer to the bottom electrode 101 along the periphery of the current blocking layer 102.
In an embodiment of the present application, a groove is formed on a surface of the bottom electrode 101 contacting the free layer 201, and the current blocking layer 102 is formed in the groove.
In an embodiment of the present application, a diameter of the current blocking layer 102 is partially or entirely smaller than a contact range of the bottom electrode 101 and the free layer 201.
In one embodiment of the present application, the current blocking layer 102 has a thickness of 10-30 nm.
In an embodiment of the present application, the material of the interlayer dielectric layer 103 is a Low dielectric constant dielectric (Low-k). In some embodiments, the interlayer dielectric layer 103 is made of silicon dioxide SiO2, SiNx, MgO, Al2O3, green phosphor silicate glass (BPSG), or phosphosilicate glass (PSG).
In an embodiment of the present application, the current blocking layer 102 and the interlayer dielectric layer 103 are made of the same material or different materials.
Fig. 2 to 8 are schematic views illustrating a process for fabricating a Magnetic Tunnel Junction (MTJ) cell, and fig. 1 is also included for understanding. The preparation process comprises the following steps:
step 1: a bottom electrode 101 is formed on the substrate including the via hole. As shown in fig. 2, the substrate with through holes is processed by a chemical mechanical polishing process, and the bottom electrode 101 is deposited by a physical vapor deposition method; the thickness of the bottom electrode 101 is 20-50 nm, and the material of the bottom electrode 101 is tantalum Ta, tantalum nitride TaN, titanium Ti, titanium nitride TiN or tungsten nitride WN, preferably titanium nitride TiN.
Step 2: the region of the current blocking layer 102 is defined on the bottom electrode 101 in a patterned manner, and a corresponding range groove is formed in the region of the current blocking layer 102. As shown in fig. 3, the position and the range of the current blocking layer 102 are defined by patterning through a photolithography process, and the bottom electrode 101 is etched through a Reactive Ion Etching (RIE) process, and a groove of the current blocking layer 102 is formed in advance. The etching gas is typically Cl 2/Ar, SF6, CF 4/TFMC 3, CF 4/O2, or CF 4/N2, and the process parameters are adjusted to etch a trench having a depth of 10-30 nm, which is about the thickness of the current blocking layer 102 to be formed later.
And step 3: the magnetic tunnel junction region is defined graphically, removing portions of the bottom electrode 101 that do not belong to the magnetic tunnel junction region. As shown in fig. 4, a photolithographic process is used to pattern and define the Magnetic Tunnel Junction (MTJ) location of the Magnetic memory cell, and a Reactive Ion Etching (RIE) process is used to etch the bottom electrode 101 to remove the portion of the bottom electrode 101 that does not belong to the MTJ region. The etching gas is generally chlorine Cl 2/argon Ar, sulfur hexafluoride SF6, carbon tetrafluoride CF 4/trifluoromethane CHF3, carbon tetrafluoride CF 4/oxygen O2 or carbon tetrafluoride CF 4/nitrogen N2, and the bottom electrode 101 which does not belong to the magnetic tunnel junction region is completely removed by adjusting the process parameters.
And step 4, configuring a non-conductive medium in the region of the current blocking layer 102 and the periphery of the bottom electrode 101 to form the current blocking layer 102 and the interlayer medium layer 103. As shown in fig. 5, an interlayer Dielectric (ILD) with a thickness of 50-100 nm is deposited by cvd, and is made of silicon dioxide (SiO2), low-k Dielectric (low-k), gate phosphosilicate glass (BPSG) or phosphosilicate glass (PSG). Next, as shown in fig. 6, an interlayer dielectric (ILD) is processed by a Chemical Mechanical Polishing (CMP) process and stops on the bottom electrode 101, so that the current blocking layer 102 is flush with the surface of the bottom electrode 101.
And 5: a multilayer film is formed over the bottom electrode 101. As shown in fig. 7, a multilayer film of a Magnetic Tunnel Junction (MTJ) is sequentially formed by physical vapor deposition, and the multilayer film includes a free layer 201, a barrier layer 202, a reference layer 203, and a hard mask layer 204. In some embodiments, the material of the free layer 201 is typically CoFeB, CoFe/CoFeB, CoFeB (Ta, W, Mo, Hf), CoFeB, and the preferred thickness is 1.2 nm to 2 nm. The barrier layer 202 is made of a non-magnetic metal oxide including magnesium oxide MgO, magnesium zinc oxide MgZnO, magnesium boron oxide MgBO, or magnesium aluminum oxide MgAlO, or a combination thereof, and more preferably, magnesium oxide MgO may be selected. The barrier layer 202 is typically 2-5 nm thick. The reference layer 203 generally includes ferromagnetic layers, ferromagnetic superlattice layers, and antiparallel ferromagnetic coupling layers, and generally has a lattice multilayer film structure of CoFeB alloys/[ cobalt Co/(nickel Ni, palladium Pd, platinum Pt) ] n/cobalt Co/ruthenium Ru (or iridium Ir)/[ cobalt Co/(nickel Ni, palladium Pd, platinum Pt) ] m/(tantalum Ta, tungsten W, molybdenum Mo, hafnium Hf, CoTa of cobalt tantalum alloys, FeTa of iron tantalum alloys, TaCoFeB of tantalum CoFeB alloys, wherein: n is greater than m, and m is greater than or equal to 0. Preferably, the total thickness of the reference layer is 5 to 20 nm. The hard mask layer 204 is typically Ta, TaN or Ta/TaN with a thickness of 60-100 nm.
In the specific process, the PVD process conditions are adjusted, the target material composition is changed, and a plasma etching process can be added to modify the material to obtain the optimal performance.
Step 6: portions of the multilayer film not belonging to the magnetic tunnel junction region are removed and a protective layer 205 is formed over the multilayer film and the interlevel dielectric layer 103. As shown in fig. 8, a lithography process is used to pattern and define the Magnetic Tunnel Junction (MTJ) location of the Magnetic memory storage unit, a Reactive Ion Etching (RIE) process is used to etch the hard mask layer 204, and then an Ar plasma Etching (IBE) process or a Reactive Ion Etching (RIE) process is used to etch the Magnetic Tunnel Junction (MTJ) multilayer film. Finally, a protective layer 205 with a certain thickness is deposited by adopting a chemical vapor deposition method, preferably silicon nitride (SiN), and the etched Magnetic Tunnel Junction (MTJ) is protected.
According to the magnetic random access memory, the non-conductive current blocking layer and the interlayer dielectric layer are added below the free layer, the current direction passing through the free layer is changed, the thickness of the free layer is increased in a phase-changing mode, the free layer still keeps vertical anisotropy, the writing current of the magnetic random access memory is reduced, meanwhile, the overturning efficiency of the free layer of the storage unit of the magnetic random access memory is improved, and the benefit of reducing power consumption is achieved.
The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.
Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (10)
1. A magnetic tunnel junction structure is arranged on a magnetic random access memory unit, the magnetic tunnel junction is formed on a bottom electrode, the bottom electrode is positioned on a substrate with a through hole, the magnetic tunnel junction at least comprises a free layer, a barrier layer and a reference layer from bottom to top, and the magnetic tunnel junction structure is characterized in that a non-conductive current blocking layer is formed between the free layer and the bottom electrode, and a non-conductive interlayer dielectric layer is formed on the periphery of the bottom electrode, so that current passing through the free layer flows to the bottom electrode from the edge of the free layer along the periphery of the current blocking layer.
2. The magnetic tunnel junction structure of claim 1 wherein a surface of the bottom electrode contacting the free layer is formed with a recess, the current blocking layer being formed within the recess.
3. The magnetic tunnel junction structure of claim 1 wherein a portion or all of the diameter length of the current blocking layer is less than the contact area of the bottom electrode and the free layer, and the thickness of the current blocking layer is 10-30 nm.
4. The magnetic tunnel junction structure of claim 1 wherein the current blocking layer is the same or different material as the interlevel dielectric layer, and the current blocking layer is preferably but not limited to silicon dioxide, silicon nitride, magnesium oxide, aluminum oxide, greenhouse phosphosilicate glass, or phosphosilicate glass.
5. A method of fabricating a magnetic tunnel junction structure disposed in a magnetic random access memory cell, the method comprising:
forming a bottom electrode on the substrate including the via hole;
the method comprises the steps of defining a region of a current blocking layer on a bottom electrode in a graphical mode, and forming a corresponding range groove in the region of the current blocking layer;
the magnetic tunnel junction area is defined in a graphical mode, and a part of the bottom electrode which does not belong to the magnetic tunnel junction area is removed;
configuring a non-conductive medium in the region of the current blocking layer and the periphery of the bottom electrode to form a current blocking layer and an interlayer medium layer;
forming a multilayer film over the bottom electrode, the multilayer film comprising a free layer, a barrier layer, a reference layer, and a hard mask layer; and
and removing the part of the multilayer film which does not belong to the magnetic tunnel junction region, and forming a protective layer above the multilayer film and the interlayer dielectric layer.
6. The method of claim 5, wherein the substrate having the through hole is subjected to a chemical mechanical polishing process to form a surface, and the bottom electrode is deposited by physical vapor deposition; the thickness of the bottom electrode is 20-50 nm, and the material of the bottom electrode is tantalum, tantalum nitride, titanium nitride or tungsten nitride, preferably titanium nitride.
7. The method of claim 5, wherein the forming of the current blocking region, the removing of a portion of the bottom electrode, and the removing of a portion of the multilayer film are performed by plasma etching or reactive ion etching.
8. The method of claim 5, wherein the protective film is formed by chemical vapor deposition, and the protective film is made of silicon nitride.
9. The method of claim 5, wherein the recess has a thickness of 10-30 nm.
10. The method of claim 5, wherein the interlayer dielectric layer is formed to a thickness of 50-100 nm and polished to make the current blocking layer flush with the bottom electrode surface.
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