WO2019005127A1

WO2019005127A1 - Magnetic tunneling junction device with nano-contact to free layer

Info

Publication number: WO2019005127A1
Application number: PCT/US2017/040403
Authority: WO
Inventors: Charles C. Kuo; Sarah ATANASOV; Mark L. Doczy; Kaan OGUZ; Kevin P. O'brien
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

MTJ material stacks including one or more nano-contact, MTJ devices employing such stacks, and computing platforms employing such MTJ devices. Nano-contacts having lateral dimensions smaller than the lateral dimensions of a free magnet layer may convey a high current density into the free magnetic layer at their point(s) of contact during device operation. With such an architecture lower write currents and/or reduced switching times may be achieved for an MTJ device having a given free magnet area (footprint). A nano-contact may be fabricated as a conductive spacer self-aligned with a sidewall of topography created in a dielectric layer.

Description

Magnetic Tunneling Junction Device

With Nano-contact To Free Layer

Non-volatile memory device performance and density can be improved by reducing memory cell dimensions while maintaining the ability to retain state. Magnetoresistive random-access memory (MRAM) holds the promise of significantly higher density than other technologies such as flash memory.

Some magnetic memory cell architectures utilize a phenomenon known as the tunneling magnetoresi stance (TMR) effect. For a structure including two ferromagnetic layers separated by a thin insulating barrier layer, it is more likely that electrons will tunnel through the barrier layer when magnetizations of the two magnetic layers are in a parallel orientation than if they are not (non-parallel or antiparallel orientation). As such, a magnetic tunneling junction (MTJ), typically comprising a fixed magnetic layer and a free magnetic layer separated by a barrier layer, can be switched between two states of electrical resistance, one state having a low resistance (impedance) and one state with a high resistance (impedance). The greater the differential in resistance, the higher the TMR ratio: (RAP-R_P)/R_P* 100 % where R_P and RAP are resistances for parallel and antiparallel alignment of the magnetizations, respectively. The higher the TMR ratio, the more readily a bit can be reliably stored in association with the MTJ resistive state. The TMR ratio of a given MTJ is therefore an important performance metric of an MTJ-based device.

In one MRAM technology referred to as spin transfer torque memory (STTM), current-induced magnetization switching may be used to set the bit states. Polarization states of one ferromagnetic layer can be switched relative to a fixed polarization of the second ferromagnetic layer via the spin transfer torque phenomenon, enabling states of the MTJ to be set by application of current. Angular momentum (spin) of the electrons may be polarized through one or more structures and techniques (e.g., direct current, spin-hall effect, etc.). These spin-polarized electrons can transfer their spin angular momentum to the

magnetization of the free layer and cause it to precess. As such, the magnetization of the free magnetic layer can be switched by a pulse of current (e.g., in about 1 -10 nanoseconds) exceeding a certain critical value, while magnetization of the fixed magnetic layer remains unchanged as long as the current pulse is below some higher threshold associated with the fixed layer architecture. BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:

FIG. 1 is an isometric illustration of material layers of an MTJ device with a nano- contact, in accordance with some embodiments; FIG. 2 is a cross-sectional view through two adjacent MTJ devices with nano- contacts, in accordance with some embodiments;

FIG. 3 is a cross-sectional view through two adjacent MTJ devices with nano- contacts, in accordance with some embodiments;

FIG. 4 is a cross-sectional view through two adjacent MTJ devices with multiple nano-contacts, in accordance with some embodiments;

FIG. 5 A is a cross-sectional view through two adjacent MTJ devices with multiple nano-contacts, in accordance with some embodiments;

FIG. 5B is a cross-sectional view through two adjacent MTJ devices with multiple nano-contacts, in accordance with some embodiments; FIG. 6 is a flow diagram illustrating methods of fabricating the MTJ devices illustrated in FIG. 1-5B, in accordance with some embodiments;

FIG. 7A, 7B, 7C, 7D, 7E, 7F, 7G and 7H are cross-sectional views through two adjacent MTJ devices evolving as operations of the methods illustrated in FIG. 6 are performed, in accordance with some embodiments; FIG. 8A, 8B, 8C, 8D, 8E, and 8F are cross-sectional views through two adjacent

MTJ evolving as operations of the methods illustrated in FIG. 6 are performed, in accordance with some embodiments; FIG. 9A, 9B, 9C, 9D, 9E, 9F and 9G are cross-sectional views through two adjacent MTJ devices evolving as operations of the methods illustrated in FIG. 6 are performed, in accordance with some embodiments;

FIG. 10 is a schematic of an MTJ-based memory cell, which includes a

perpendicular spin transfer torque element, in accordance with some embodiments;

FIG. 11 is a cross-sectional view of an MTJ-based memory cell, according to some embodiments of the disclosure.

FIG. 12 is a schematic illustrating a mobile computing platform and a data server machine employing an MTJ memory device, in accordance with embodiments; and FIG. 13 is a functional block diagram illustrating an electronic computing device, in accordance with some embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein. Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material or material "on" a second material or material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

In MTJ devices, magnetization of the free magnetic layer can be switched by a pulse of current exceeding a certain critical value. The critical current value may be dependent on current density within the free layer. For low-power memory operation, low write currents are advantageous. However, reducing the footprint of a free layer within an MTJ device for the sake of reduced write currents at a given current density has the concomitant effect of reducing device stability. The inventors have found that a reduction in the area of an electrode interfacing with a free magnet of the MTJ device can enable a reduction in write current of the device and/or enable an increase in the switching current density within the free magnet. MTJ material stacks including one or more nano-contact, MTJ devices employing such stacks, and computing platforms employing such MTJ devices are described herein. During device operation, nano-contacts having lateral dimensions smaller than the lateral dimensions of a free magnet layer may convey a high current density into the free magnetic layer at their point(s) of contact. With such an architecture, lower write currents and/or reduced switching times may be achieved for an MTJ device having a given free magnet area (footprint). Exemplary MTJ devices having one or more of the features described herein may be employed in devices, such as, but not limited to, embedded memory, embedded non-volatile memory (eNVM), magnetic random access memory (MRAM), and non-embedded or stand-alone memories. FIG. 1 illustrates an MTJ material stack 101 for an MTJ device 100, in accordance with some embodiments. In the illustrated example, MTJ device 100 is a columnar or pillar structure with material stack 101 having dot-like layers with layer thickness in a direction (e.g., z-axis) perpendicular to a plane of the device footprint (e.g., x-y axis). MTJ device 100 includes a first electrode 107 (e.g., bottom contact) and a second electrode 180 (e.g., top contact) with material stack 101 between electrodes 107 and 180. Electrode 107 interfaces MTJ device 100 to interconnect metallization 105 present in an underlying layer of an integrated circuit. Electrode 180 interfaces MTJ device 100 to interconnect metallization (not depicted) in an overlying layer of an integrated circuit. MTJ devices 100 may be embedded, or monolithically integrated with, an IC, sharing with the IC any substrate (not depicted) known to be suitable for an IC.

MTJ device 100 includes a free magnet and a fixed magnet separated by an intervening barrier layer that may filter electrons based on their Fermi wavevector. The terms "free magnet" and "fixed magnet" are employed herein to emphasize that each "magnet" may be a composite structure including a plurality of material layers that together comprise a functional component of MTJ device 100. In FIG. 1 , ellipses are drawn between illustrated material layers to further emphasize that MTJ device 100 may have any number of layers even if not specifically illustrated in FIG. 1.

In the illustrated embodiment, the free magnet includes a free magnet layer 140 over electrode 107. Free magnet layer 140 comprises a ferromagnetic material. As employed herein, the term "ferromagnetic" refers to the magnetic mechanism of the material and such a material need not be an iron alloy, although it may be. As described further below, a free magnet may also include material layers other than free magnet layer 140. A fixed magnet includes a fixed magnet layer 120 that is separated from free magnet layer 140 by at least a barrier layer 130. Fixed magnet layer 120 comprises a ferromagnetic material. As described further below, a fixed magnet may also include material layers other than fixed magnet layer 120.

In some embodiments, MTJ material stack 101 is a perpendicular system. In FIG. 1 , arrows in magnet layers 120 and 140 show the magnetic easy axis as in the z-direction out of the x-y plane of material layers in MTJ material stack 101. This perpendicular magnetic anisotropy (PMA) may advantageously reduce the switching current between "high" and "low" resistance states and may improve the scalability of MTJ material stack 101. The fixed magnet may comprise any material or stack of materials suitable for maintaining a fixed magnetization direction while the free magnet is magnetically softer (i.e.

magnetization can more easily rotate to parallel and antiparallel state with respect to the fixed magnet). Ferromagnetic layers of the fixed and/or free magnets may, for example, comprise ferromagnetic metal alloys doped with one or more non-ferromagnetic

constituents. The ferromagnetic metal alloy may include one or more ferromagnetic constituent while the non-ferromagnetic constituents may, for example, impart an amorphous phase to the alloy, at least in the layer's "as-deposited" state. While in the amorphous phase, PMA may be effectively absent from the alloy until long range order is imparted during a thermal anneal process at which point crystallization within ferromagnetic layers may become nearly lattice matched to the barrier layer crystal structure. In some embodiments, ferromagnetic layers of the fixed and/or free magnets comprise one or more of cobalt (Co), iron (Fe), or nickel (Ni). In some embodiments, ferromagnetic layers of the fixed and/or free magnets comprise a Heusler alloy. Two examples of non-ferromagnetic dopants are boron or carbon, but many other elements may have a similar functional effect.

In some exemplary embodiments, fixed magnet layer 120 comprises a CoFeB alloy. In some specific examples, Fe content within the CoFeB is at least 50 at. %. Exemplary embodiments include 20-30 at. % B with one specific alloy being Co2oFe6oB2o. This iron- rich alloy has been found to achieve perpendicular magnetic anisotropy. Other embodiments with equal parts cobalt and iron are also possible (e.g., Co4oFe4oB2o), as are more iron-rich alloys.

Fixed magnet layer 120 advantageously has crystallinity associated with the desired PMA. In some exemplary embodiments, fixed magnet layer 120 has body-centered cubic (BCC) crystal structure, which is advantageous for achieving perpendicular magnetic anisotropy in certain metal alloys comprising one or more of iron, cobalt, and nickel. Fixed magnet layer 120 may further have (001) out-of-plane texture, where texture refers to the distribution of crystallographic orientations within in fixed magnet layer 120. The inventors have found those with iron crystallize with BCC, (001) out-of-plane texture. Fixed magnet layer 120 may have a thickness between approximately 1.0 nm and 2.0 nm, for example.

In some exemplary embodiments, free magnet layer 140 also has BCC crystal structure. Free magnet layer 140 may further have (001) out-of-plane texture. Free magnet layer 140 may have a thickness between approximately 1.0 nm and 2.0 nm, for example. The composition of free magnet layer 140 may be the same as that of fixed magnet layer 120 with differences in thickness or the addition of other layers within the fixed or free magnet accounting for greater magnetic softness in the free magnet. In some exemplary

embodiments, free magnet layer 140 is also a CoFeB alloy. In some specific examples, Fe content within the CoFeB is at least 50 at. %. Exemplary embodiments include 20-30 at. % B with one specific alloy being Co2oFe6oB2o. Other embodiments with equal parts cobalt and iron are also possible (e.g., Co4oFe4oB2o), as are more iron-rich alloys. Free magnet layer 140 may be one of a stack of material layers (not depicted) making up the free magnet structure. A free magnet stack may, for example, include multiple ferromagnetic material layers with a coupling layer (not depicted) separating adjacent ferromagnetic layers. The alloy compositions for any of these layers may be any of those described above for free magnet layer 140. The coupling layer may comprise one or more of W, Mo, Ta, Nb, V, Hf and Cr, for example.

Barrier layer 130 may be any material or stack of materials for which current of a first (e.g., majority) spin passes more readily than does current of a second (e.g., minority) spin. Barrier layer 130 is therefore a quantum mechanical barrier, a spin filter, or spin- dependent barrier, through which electrons may tunnel according to probability that is dependent on their spin. The extent by which current of one spin is favored over the other impacts the tunneling magneto-resistance associated with MTJ material stack 101. Barrier layer 130 may further provide a crystallization template (e.g., BCC with (001) texture) for solid phase epitaxy of the free and/or fixed magnets within MTJ material layer stack 101. In some embodiments, barrier layer 130 comprises one or more metal and oxygen (i.e., a metal oxide). In some exemplary embodiments, barrier layer 130 is magnesium oxide (MgO). In some other embodiments, barrier layer 130 comprises predominantly metal or graphene, and may even be substantially oxygen-free in some embodiments.

The material layers within an MTJ material stack may vary considerably without deviating from the scope of the present disclosure. For example, in some embodiments, as further illustrated in FIG. 1, a cap layer 170 is between fixed magnet layer 120 and electrode 180. Cap layer 170 may comprise a metal oxide (e.g., MgO, VO, WO, TaO, HfO, MoO). Such a capping layer may be absent for some MTJ device implementations, such as a spin- hall effect (SHE) device. In further reference to FIG. 1, one or more intermediate material layers may be disposed between fixed magnet layer 120 and electrode 180. In the illustrated embodiment, for example, MTJ material stack 101 includes an anti-ferromagnetic layer or a synthetic antiferromagnetic (SAF) structure 110. Such layer(s) may be useful for countering a fringing magnetic field associated with fixed magnet layer 120. Exemplary anti- ferromagnetic layers include, but are not limited to, iridium manganese (IrMn) or platinum manganese (PtMn). Exemplary SAF structures include, but are not limited to Co/Pt bilayers, Co/Pd bilayers, CoFe/Pt bilayers, or CoFe/Pd bilayers. In some exemplary embodiments, SAF structure 110 includes a first plurality of bilayers forming a superlattice of

ferromagnetic material (e.g., Co, CoFe, Ni) and a nonmagnetic material (e.g., Pd, Pt, Ru). SAF structure 1 10 may include n bi-layers (e.g., n [Co/Pt] bilayers, or n [CoFe/Pd] bilayers, etc.) that are separated from a p bilayers (e.g.,/? [Co/Pt]) by an intervening non-magnetic spacer. The spacer may provide antiferromagnetic coupling between the bi-layers. The spacer may be a Ruthenium (Ru) layer less than 1 nm thick, for example. Other layers within SAF structure 110 may have thicknesses ranging from 0.1-0.4 nm, for example. SAF structures and/or anti-ferromagnetic layers may be considered part of a multi-layered fixed magnet.

As further shown in FIG. 1 , electrode 107 makes a nano-contact to free magnet layer 140. In the illustrated embodiment, electrode 107 is in direct contact with both a surface of free magnet layer 140 and a surface of interconnect metallization 105. Although illustrated as a linear structure, electrode 107 may have any architecture such that the nano-contact made to free magnet layer 140 has at least one lateral dimension that is significantly smaller than that of free magnet layer 140. As used herein "significantly" is more than incidental or inherent manufacturing variation (e.g., more than 15%). In some embodiments, an electrode making a nano-contact to a free magnet layer has an architecture indicative of a conductive spacer formed along a sidewall of dielectric feature. As shown in FIG. 1 , free magnet layer 140 has a first minimum dimension, referred to herein as critical dimension CDMTJ, in the plane of the layer (i.e., lateral width). CDMTJ may be associated with a minimum lithographically definable feature dimension of a given patterning technology, for example. Electrode 107, at least at the contact point with free magnet layer 140, has a lateral width of a second minimum dimension, referred to herein as critical dimension CDNC. CDNC is measured parallel to the plane of free magnet layer 140. CDNC associated with electrode 107 is significantly smaller than CDMTJ associated with free magnet layer 140. In some embodiments, CDNC is no more than half CDMTJ. In some advantageous embodiments, CDNC is between 10% and 25% of CDMTJ. Although MTJ device dimensions can be expected to scale over time, in some exemplary embodiments where CDMTJ is in the range of 20-30 nm, CDNC is in the range of 1-10 nm.

Electrode 107 may further have a lateral nano-contact length LNC of any size, which may be significantly larger than CDNC, and may be equal to, or larger than, CDMTJ. Electrode 107 makes contact to free magnet layer 140 over a nano-contact area that is a function of the lateral width and the lateral length. In the illustrated embodiment, electrode 107 has a substantially linear architecture, such that the nano-contact area is approximately CDNC multiplied with LNC. Other functions are also possible. Where electrode 107 has an annular architecture, for example, nano-contact area may be approximately n(R²-r²), and where R²-r² is approximately equal to CDNC in some embodiments.

In FIG. 1, the dashed arrows passing through electrode 107 and into free magnet layer 140 represent a write current pulse (Iwrfte) delivered by interconnect metallization 105. In FIG. 1 , interconnect metallization 105 is rectangular indicating it has been patterned separately from MTJ device 100. Because of the small cross-sectional area (e.g., x-y plane in FIG. 1), current density through the nano-contact of electrode 107 is significantly higher than would be expected for an electrode of CDMTJ, or for an electrode having the CD of interconnect metallization 105. The higher current density within electrode 107 is conveyed into free magnet layer 140 such that, at least at the contact point, current density with free magnet layer 140 is high until spreading into the larger cross-sectional area associated with the CDMTJ. The inventors have found that inducing one or more such locale of high current density within a free magnet layer can advantageously reduce the switching current associated with the free magnet layer. A high current density across the entirety of free magnet layer 140 may not be necessary to set the state of MTJ device 100. The introduction of a nano-contact in accordance with embodiments herein therefore provides a means of constricting current to induce a high current density locale within a free magnet layer of some larger minimum CDMTJ, which can be dimensioned for robust manufacture and high MTJ stability, for example, while remaining operable at low write currents.

A nano-contact may be of any composition that offers suitable conductivity and contact resistance between the free magnet layer and underlying interconnect. In some embodiments, electrode 107 is a metal or metal alloy. In some such embodiments, electrode 107 includes one or more constituents (e.g., metals or non-metal dopants) absent from interconnect metallization 105 and absent from free magnet layer 140. Electrode 107 may also include one or more constituents (e.g., metals or non-metal dopants) present within free magnet layer 140 and/or within interconnect metallization 105. In some advantageous embodiments, electrode 107 includes tantalum (Ta), tungsten (W), or ruthenium (Ru).

Direct contact (e.g., a metallurgical junction) between electrode 107 and free magnet layer 140 ensures a high current density locale within free magnet layer 140 can be developed (e.g., during a write operation). The advantages of a nano-contact may be compromised if any materials introduced between free magnet layer 140 and electrode 107 spread current significantly. For example, the practice of using a seed layer (not depicted) between free magnet layer 140 and electrode 107, could allow significant lateral current conduction under free magnet layer 140 if such a seed layer is merely inserted under free magnet layer 140 and allowed to have the minimum MTJ dimension CDMTJ. Notably however, and as described further below, electrode 107 is surrounded by a dielectric material, which, being amorphous, may reduce the need for a seed layer as templating should not occur within much of the footprint of free magnet layer 140. Hence, the difference in dimensions of electrode 107 and free magnet layer 140 may also enable their direct contact, potentially offering the further advantage of a simpler, lower resistance, MTJ material stack 101.

The composition of electrode 180 may be any suitable metal or metal alloy.

Electrode 180 may include, for example, tantalum (Ta), tungsten (W), or ruthenium (Ru). As also shown in FIG. 1, electrode 180 has an area associated with the minimum MTJ device dimension CDMTJ as current constriction at fixed magnet end of MTJ device 100 may not offer the same advantages as for electrode 107.

FIG. 2 is a cross-sectional view parallel to the x-axis in FIG. 1 and through two adjacent MTJ devices with nano-contacts, in accordance with some embodiments. Reference number labels from FIG. 1 are retained in FIG. 2 for material layers that share any of the properties described in the context of FIG. 1. As shown in FIG. 2, MTJ devices 200 have a lateral dimension CDMTJ and a nominal device pitch (PMTJ). Electrode 107 makes a nano- contact to free layer 140 that is proportional to CDNC, and is surrounded by one or more dielectric material. Within the plane illustrated, adjacent electrodes 107 are separated by a first dielectric material 211 while a second dielectric 210 is on opposite sides of electrodes 107. Dielectric materials 211 and 210 may have any composition known to be suitable as an interlay er dielectric, such as, but not limited to, silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), carbon-doped oxide (SiOC(H)), HSQ, MSQ, or porous dielectrics. In exemplary embodiments, dielectric material 210 is of a different composition than dielectric material 211. The spacing between adjacent electrodes 107 occupied by dielectric material 211 is associated with a nominal critical dimension CD2, which in the illustrated embodiment is at least equal to CDMTJ. Adjacent electrodes 107 may also have a pitch Pi that is substantially equal to the nominal MTJ pitch. As further shown in FIG. 2, interconnect metallization 105 is embedded in a dielectric material 205, which may have any composition known to be suitable as an ILD, such as, but not limited to those described for dielectric materials 211 and 210. In the example shown, there is a material interface between dielectric material 211 and dielectric material 205 as well as a material interface between dielectric material 210 and dielectric material 205. Such interfaces may be present even where dielectric material 205 has the same composition as either of dielectric materials 210 and 211.

Dielectric material 220 surrounds MJT material layers 140, 130, 120, as well as electrode 180. Dielectric material 220 may have any composition known to be suitable as an interlay er dielectric, such as, but not limited to those described for dielectric materials 211 and 210. In the example shown, there is a material interface between dielectric material 211 and dielectric material 220 as well as a material interface between dielectric material 210 and dielectric material 220. Such interfaces may be present even where dielectric material 220 has the same composition as either of dielectric materials 210 and 211. In the illustrated embodiment, the interface between dielectric material 211 and dielectric material 220 is substantially planar with the material interface between dielectric material 210 and dielectric material 220, both of which are also substantially planar with a top surface of electrodes 107. Such planarity is indicative of electrodes 107 having been planarized concurrently with dielectric layers 210 and 211. Electrode 107 has a vertical (e.g., z-dimension) nano-contact height HNC. While nano-contact height HNC may vary, in some embodiments it is at least equal to CDNC. For example, where CDNC is 1-1 Onm, HNC is also 1-1 Onm. In some embodiments where nano- contact height HNC is larger than CDNC, electrode 107 may be characterized as a vertically- oriented fin. In other embodiments where nano-contact height HNC is approximately equal to CDNC, electrode 107 may be characterized a metallized rib or ridge.

In some embodiments, an electrode making a nano-contact with a free magnet layer has crystallinity and/or texture indicative of being formed over a surface that is non-parallel to a plane of the free magnet layers. Hence, rather than displaying attributes consistent with being formed directly on a surface of interconnect metallization 105, crystallinity and/or texture of electrode 107 may instead be indicative of formation over a sidewall of either dielectric material 210 or dielectric material 211. As further illustrated in the expanded view of FIG. 2, electrode 107 has crystalline grains 250 with a directionality (i.e., anisotropic grain orientation) indicative of growth that is not in the z-dimension. In some embodiments, crystalline grains 250 have <100> texture that non-parallel to texture of free magnet layer 140, at least over a portion of height HNC. Where free magnet layer 140 has <100> out-of- plane texture, grains 250 may have <100> texture in-the-plane. For metals with a columnar grain structure similar to that shown in FIG. 2, such an orientation of crystalline grains 250 is indicative of a growth axis extending from (or toward) an dielectric interface 210A. Some crystalline grains 250 proximal to interconnect metallization 105 may further display columnar structure with a growth axis extending from an interface of interconnect metallization 105, which is more typical of being formed over interconnect metallization 105.

In some embodiments, an MTJ electrode makes a nano-contact to a free magnet layer that is of a smaller CD than that of the contact to an underlying interconnect metallization. An MTJ having an electrode with a larger dimension at the interface of the underlying interconnect metallization may display lower extrinsic resistance than if the electrode contact area to the underlying interconnect layer is substantially the same as that of the nano-contact to the free magnet layer. FIG. 3 is a cross-sectional view through two adjacent MTJ devices 300 with nano-contacts, in accordance with some embodiments where an electrode 107 A has a foot 109 with a critical dimension larger than that of the nano-contact to free magnet layer 140 (i.e., larger than CDNC). Notably, foot 109 is asymmetric with respect to the remainder of the MTJ material stack. Two adjacent electrodes 107 A, 107B may be distinguished from each other as complementary, or symmetrical about a plane of symmetry passing through the centerline (CL) denoted between adjacent MTJ devices 300. In the illustrated embodiment, foot 109 protrudes into dielectric material 211, which is indicative of one or more fabrication techniques described elsewhere herein. As further illustrated in the expanded view of FIG. 3, electrode 107B again has crystallinity and/or texture indicative of being formed over a surface that is non-parallel to a plane of the free magnet layers. The crystallinity and/or texture of electrode 107B may be indicative of formation upon a sidewall of either dielectric material 210 or dielectric material 211. As further illustrated in the expanded view of FIG. 3, electrode 107B has crystalline grains 250 with a <100> texture non-normal to the lateral width of electrode 107B, which is indicative of deposition that is not in the z-dimension. Within foot 109 however, crystalline grains 251 have <100> texture normal to the lateral width of electrode 107B, which is indicative of local deposition in the z-dimension. The texture of grains 250, for example, is indicative of a deposition axis extending to or from dielectric interface 21 OA, while the texture of grains 251 is indicative of a deposition axis extending from interconnect metallization 105. In some embodiments, an MTJ device includes an electrode having more than one nano-contact to a free magnet layer. Depending on the dimensions of the free magnet layer and nano-contact, more than one high current density locale may be generated by coupling the free magnet layer through multiple nano-contacts. FIG. 4 is a cross-sectional view through two adjacent MTJ devices 400 that have multiple nano-contacts, in accordance with some embodiments. As shown, a first free magnet layer 140 with minimum dimension

CDMTJ is in direct contact with a pair of electrodes 107 A and 107B, each having CDNC. An adjacent MTJ device includes another free magnet layer 140 with minimum dimension CDMTJ that is directly contacted by another pair of electrodes 107C and 107D. Each of electrodes 107A-107D may have any of the attributes described above in the context of electrode 107. For the illustrated embodiment, all electrodes 107A-107D are associated with a substantially constant pitch P2 that is smaller than the pitch of MTJ devices 400, and which may be approximately half of the MTJ pitch PMTJ.

FIG. 5A is a cross-sectional view through two adjacent MTJ devices 501 with multiple nano-contacts 107 A, 107B, 107C and 107D, each of which further includes a foot 109 in contact with interconnect metallization 105. Electrodes 107A, 107B, 107C and 107D may again have any of the attributes described above in the context of electrode 107. Foot 109 may also be substantially as described above in the context of FIG. 3. In this example, electrodes 107 A and 107B are substantially mirror images with foot 109 of electrode 107 A proximal to foot 109 of electrode 107B. In the adjacent MTJ device, electrodes 107C and 107D face also each other. FIG. 5B is a cross-sectional view through two adjacent MTJ devices 502 with multiple nano-contacts 107A-107D, each of which further includes foot 109 in contact with interconnect metallization 105. In this example, electrodes 107 A and 107B are substantially mirror images with foot 109 of electrode 107 A proximal to foot 109 of electrode 107D associated with an adjacent MTJ device. Differences in the foot orientation between MTJ devices 501 and 502 are indicative of different fabrication techniques, as further described below. MTJ material stacks in accordance with the architectures above may be fabricated by a variety of methods applying a variety of techniques and processing chamber

configurations. FIG. 6 is a flow diagram illustrating methods 601 for fabricating the MTJ devices illustrated in FIG. 1-5B, in accordance with some embodiments. Methods 601 leverage a self-aligned conductive spacer technique to form an electrode of sufficiently small lateral dimension to make a nano-contact with a free magnet layer that is subsequently formed over the electrode. Methods 601 begin with receiving a substrate with one or more conductive interconnect structures. Any substrate known to be suitable for microelectronic fabrication may be received, such as, but not limited to crystalline silicon substrates.

Transistors (e.g., silicon-channeled FETs) and/or one or more levels of interconnect metallization may be present on the substrate as received at operation 610, for example.

At operation 620 a trench is formed over the conductive interconnect structures. In some embodiments, the trench is formed in a dielectric layer that is over the interconnect structure. Such a dielectric layer may be deposited at operation 620, or may be present on the substrate as received at operation 610. Alternatively, a portion of the interconnect structure can be recessed relative to a surrounding dielectric material. For either

embodiment, a sidewall of the trench is in a dielectric material. Any known patterning techniques (e.g., lithography and etch) may be employed at operation 620 to form the trench. In some embodiments, the trench exposes a conductive interconnect surface.

At operation 630 a metal layer is deposited over the trench, lining a sidewall of the trench, and making contact with the exposed surface of the underlying interconnect. Any deposition process known to be suitable for the metal may be enlisted at operation 630 to line the trench. The metal deposited is not to completely backfill the trench. Instead, the metal should form a liner following the sidewall topography of the trench. Methods 601 continue at operation 640 where the metal layer is etched back, removing all but the portion along the trench sidewall and retaining a conductive spacer or stringer along topography associated with the trench sidewall. Any patterned or unpatterned etch process known to be suitable for the metal layer may be practiced at operation 640.

The remaining trench is then backfilled with a dielectric material at operation 650. Any deposition process known to be suitable for the dielectric may be enlisted at operation 650 to backfill the trench. The backfilled dielectric material is then planarized with a sidewall of the trench, exposing a surface of the metal retained along a sidewall of the trench. This retained metal has a lateral dimension dependent on a thickness of the metal layer, and does not rely on lithographic techniques to define its lateral critical dimension. As such, the portion of the metal retained along a sidewall of the trench may have nanometer critical dimensions that are sub-lithographic (i.e., below the resolution or capability of a given lithography technique).

Methods 601 continue at operation 660 where a free magnet layer is deposited over the metallized trench sidewall, over the trenched dielectric, and over the dielectric backfill. Additional layers of the MTJ device are then formed over the free magnet layer at operation 670 according to any suitable techniques. The MTJ material layers are patterned according to any known techniques to form separate MTJ devices, each having a free magnet layer coupled to an underlying interconnect through a nano-contact provided by the metal retained along a sidewall of the trench. Various thermal processes (e.g., thermal anneals), and additional ILD deposition and/or interconnect metallization processes may be performed to complete an IC including the MTJ devices. FIG. 7A, 7B, 7C, 7D, 7E, 7F, 7G and 7H are cross-sectional views through two adjacent MTJ devices evolving as operations of the methods 601 are performed, in accordance with some embodiments. FIG. 7A illustrates a substrate 701 that might be received as a starting material. Substrate 701 may be any known to be suitable for microelectronic fabrication, such as, but not limited to substrates including one or more layers of crystalline silicon. Substrate 701 may further include transistors (e.g., silicon- channeled FETs) and/or one or more levels of interconnect metallization. In the example shown in FIG. 7A, substrate 701 includes dielectric 205, a top surface of which is substantially planarized a top surface of first and second interconnect metallization 105.

As shown in FIG. 7B, ILD 210 has been deposited over the exposed surface of interconnect metallization 105, and over dielectric 205. Any deposition process known to be suitable may be employed for ILD 210, such as, but not limited to, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), flowable CVD (FCVD), or spin-on deposition. As shown in FIG. 7C, a trench 705 is patterned into ILD 210. Any patterning technique suitable for the selected ILD and dimensions of the trench may be practiced. In some embodiments, a lithographic patterning process is performed to partem a mask, and trench 705 is then etched into a region of ILD 210 that is unprotected by the mask. ILD 210 may be etched with any etch process, such as, but not limited to a plasma (dry) etch. Trench 705 extends through the thickness of ILD 210 to expose a portion of one or more interconnect metallization 105. As shown in FIG. 7C, trench 705 has a sidewall aligned over first and second interconnect metallization 105.

As shown in FIG. 7D, a metal layer 708 is formed over a top surface ILD 210 and over the sidewall of trench 705. Any technique known for lining a metal within a trench may be practiced to form metal layer 708. Metal layer 708 may be of any composition known to be suitable as an MTJ electrode and is also suitable for forming a sidewall spacer along the sidewall of trench705, for example as described further below. Any deposition technique known to be suitable for the chosen conductive material may be enlisted. In some embodiments, where metal layer 708 includes at least one tantalum (Ta), tungsten (W), or ruthenium (Ru), a PVD, CVD, ALD, or ionized metal plasma (IMP) process is employed to deposit a 1-20 nm thick layer of metal or metal alloy. More or less metal may be deposited, depending on conformality of the deposition technique, to have a thickness over the trench sidewall (as a measured in a direction normal from the trench sidewall) that is 1-10 nm, for example.

As shown in FIG. 7E, metal layer 708 is then anisotropically etched back to form electrode 107 as a metal spacer along the trench sidewall. The etch back may be without a mask (i.e., a blanket etch) or it may be masked if metal layer 708 is also employed for interconnect routing (not depicted). As a result of the topography associated with the trench sidewall, a self-aligned metal spacer is retained adjacent to the sidewall. Metal layer 708 may be etched with any anisotropic etch process suitable for the composition of metal layer 708, such as a plasma (dry) etch. As shown in FIG. 7E, the lateral CD of electrode 107 is some function of the thickness at which metal layer 708 was deposited and the extent of chemical (isotropic) etch associated with the etch back process. In some embodiments, the etch back of metal layer 708 forms a metal spacer with a lateral CD of 1-lOnm. In some further embodiments, a metal spacer may be deliberately etched isotropically or partially oxidized to reduce the lateral CD of the metal spacer. The metal spacer can be expected to demark an enclosed perimeter of a polygon. A masked isotropic etch of the metal spacer may be performed to form electrically isolated segments of the metal spacer from such an enclosed polygon.

As shown in FIG. 7F, ILD 211 is deposited into the remaining trench with any suitable dielectric deposition process. ILD 211 may be then planarized, for example with any suitable chemical-mechanical planarization (CMP) process, to expose a nano-contact surface of electrodes 107 and substantially planarize a top surface of ILD 211 with that of ILD 210. As shown in FIG. 7G, layers of an MTJ material stack are deposited over ILD 210, over ILD 211, and over the nano-contact surface of electrodes 107. In the illustrated example, free magnet layer 140 is deposited directly on ILD 210, on ILD 211, and on the nano-contact surface of electrodes 107. Barrier layer 130 is deposited over free magnet layer 140. Fixed magnet layer 120 is deposited over barrier layer 130, and electrode 180 is deposited over fixed magnet layer 120. Any deposition techniques may be employed to deposit the MTJ layers as embodiments herein are not limited in this respect. As shown in FIG. 7H, the MTJ material stack is patterned into separate MTJ devices

200, for example with any lithographic masking process and anisotropic etch process compatible with the various layers of the MTJ material stack. The MTJ device patterning etch exposes ILD layers 210 and/or 211, forming MTJ devices with a lateral dimension of some nominal CD that is significantly larger than that of electrode 107. Dielectric layer 220 is then deposited over MTJ devices 200 and planarized with a top surface of electrode 180 in preparation for subsequent interconnect metallization that may be fabricated according to any known techniques.

FIG. 8A, 8B, 8C, 8D, 8E, and 8F are cross-sectional views through two adjacent MTJ devices evolving as operations of the methods 601 are performed, in accordance with some alternative embodiments that utilize a self-aligned dielectric spacer to protect an MTJ electrode. Such a self-aligned dielectric spacer may be advantageous where a metal layer can not be readily etched anistropically into a suitable self-aligned conductive spacer, and/or where an a electrode of larger bottom CD is desired. For these embodiments, operations 610, 620 and 630 (FIG. 6) may be performed substantially as described above, for example as illustrated in FIG. 7A-7D. Then, as shown in FIG. 8 A, a dielectric material layer 807 is deposited over metal layer 708. Dielectric material layer 807 may be any material known to be suitable for forming a dielectric spacer, such as, but not limited to SiO, SiN, or SiON. As next shown in FIG. 8B, dielectric material layer 807 is anistropically etched to clear the nominal thickness of the dielectric layer and expose underlying metal layer 708. As a result of the topography associated with the trench sidewall, a self-aligned dielectric spacer 809 is retained adjacent to the metal-lined trench sidewall. The lateral CD of dielectric spacer 809 is a function of the thickness at which dielectric spacer 809 was deposited, which may vary (e.g.,l-10nm).

As shown in FIG. 8C, metal layer 708 is then etch back to form electrodes 107 A and 107B along the trench sidewalk The etch back may again be anisotropic, but may also be isotropic as the sidewall of metal layer 708 is protected by dielectric spacer 809. The metal etch back may be without a mask (i.e., a blanket etch) or it may be masked if metal layer 708 is also employed for interconnect routing (not depicted). As shown in FIG. 7E, the lateral CD of the top of electrodes 107 A, 107B is a function of the thickness at which metal layer 708 was deposited, while the lateral CD of the bottom of electrodes 107A, 107B is a function of the of the thickness at which metal layer 708 was deposited as well as the lateral width of dielectric spacer 809 that defines foot 109. In some embodiments, the etch back of metal layer 708 forms a conductive feature with a top lateral CD of 1-1 Onm and a bottom lateral CD of 10-20 nm. A masked isotropic etch of dielectric spacer 809 and/or metal layer 708 may be performed to form electrically isolated electrodes (i.e., bifurcate electrode 107A from 107B).

As shown in FIG. 8D, ILD 211 is deposited into the remaining trench with any suitable dielectric deposition process. ILD 211 is then planarized, for example with any suitable CMP process, to expose a nano-contact surface of electrodes 107A, 107B, and to substantially planarize a top surface of ILD 211 with that of ILD 210. As shown in FIG. 8E, layers of an MTJ material stack are deposited over ILD 210, over ILD 211, and over the nano-contact surface of electrodes 107 A, 107B. In the illustrated example, free magnet layer 140 is deposited directly on ILD 210, on ILD 211, and the on nano-contact surface of electrodes 107A, 107B. Barrier layer 130 is deposited over free magnet layer 140. Fixed magnet layer 120 is deposited over barrier layer 130, and electrode 180 is deposited over fixed magnet layer 120. Any deposition techniques may be employed to deposit the MTJ layers as embodiments herein are not limited in this respect.

As shown in FIG. 8F, the MTJ material stack is patterned into separate MTJ devices 300, for example with any lithographic masking process and anisotropic etch process compatible with the various layers of the MTJ material stack. The MTJ device patterning etch exposes ILD layer 210 and/or ILD layer 211, forming MTJ devices with a lateral diameter of some nominal CD that is significantly larger than that of electrodes 107 A, 107B. dielectric layer 220 is then deposited over MTJ devices 300 and planarized with a top surface of electrodes 180 in preparation for subsequent interconnect metallization that may be fabricated according to any known techniques.

FIG. 9A, 9B, 9C, 9D, 9E, 9F and 9G are cross-sectional views through two adjacent MTJ devices evolving as operations of the methods 601 are performed, in accordance with some alternative embodiments where a free magnetic layer is contacted by a plurality of electrodes. As shown in FIG. 9A, ILD 210 is deposited over interconnect metallization 105, for example substantially as describe elsewhere herein. In FIG. 9B, a plurality of trenches 705 are patterned into ILD 210 with sidewalls of at least two trenches overlapping each interconnect metallization 105. As such, the trench patterning shown in FIG. 9B is performed at a smaller pitch and trench CD than is illustrated in FIG. 7C. In some embodiments, the trench pattern has the same pitch and trench CD as that employed to form interconnect metallization 105 with alignment between these layers shifted by a half pitch. As shown in FIG. 9C, metal layer 708 and dielectric layer 807 is deposited over the remaining features of dielectric 210 and/or into trenches 705. As shown in FIG. 9D, electrodes 107A, 107B, 107C, and 107D are fabricated by etching back dielectric layer 807 and metal layer 708, for example substantially as described elsewhere herein. As shown in FIG. 9E, ILD layer 211 is deposited and planarized with ILD 210, exposing a nano-contact surface of electrodes 107A-107D. As shown in FIG. 9F, an MTJ material stack is deposited over ILD 210, over ILD 211, and over the nano-contact surface of electrodes 107A-107D. The MTJ material stack is then patterned into MTJ devices 402, as shown in FIG. 9G, and substantially as described elsewhere herein.

In some embodiments, the MTJ devices having one or more of the features or attributes described above function essentially as a resistor, where the resistance of an electrical path through the MTJ may exist in two resistive states, either "high" or "low," depending on the direction or orientation of magnetization in the free magnetic layer(s) and in the fixed magnetic layer(s). In the case that the spin direction is down (minority) in the free magnetic layer(s), a high resistive state exists and the directions of magnetization in the coupled free magnet and the fixed magnet are substantially opposed or anti-parallel with one another. In the case that the spin direction is up (majority) in a ferromagnetic material layer of the coupled free magnet, a low resistive state exists, and the directions of magnetization in the ferromagnetic layers of the coupled free magnet and the fixed magnet are substantially aligned or parallel with one another. The terms "low" and "high" with regard to the resistive state of the MTJ device and are relative to one another. In other words, the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa. Thus, with a detectible difference in resistance, the low and high resistive states can represent different bits of information (i.e. a "0" or a "1"). The direction of magnetization in the ferromagnetic layer(s) may be switched through a process called spin transfer torque ("STT") using a spin-polarized current. An electrical current is generally non-polarized (e.g. consisting of about 50% spin-up and about 50% spin-down electrons). A spin-polarized current is one with a greater number of electrons of either spin-up or spin-down. The spin-polarized current may be generated by passing a current through the fixed magnetic layer. The electrons of the spin polarized current from the fixed magnet may tunnel through the barrier layer and transfer spin angular momentum to a ferromagnetic layer of the free magnet, wherein the ferromagnetic layer will orient its magnetic direction from anti-parallel to that of the fixed magnet, or parallel.

The spin-hall effect may also be employed to generate spin-polarized current through a particular electrode material that is in contact with a free magnet. For such embodiments, the ferromagnetic material layer(s) of a free magnet may be oriented without applying current through the fixed magnet and other material layers of the MTJ device. In either implementation, the free magnetic layer may be returned to its original orientation by reversing the current. Thus, an MTJ device may store a single bit of information ("0" or "1") by its state of magnetization. The information stored in the MTJ device is sensed by driving a current through the MTJ material stack. The magnetic layer(s) of the free magnet do not require power to retain their magnetic orientations. As such, the state of the MTJ device may be preserved when power to the device is removed. Therefore, a spin transfer torque memory bit cell including the MTJ material stacks described herein are considered non- volatile.

FIG. 10 is a schematic of an MTJ memory bit cell 1001, which includes a spin transfer torque element 1010, in accordance with some embodiments. The spin transfer torque element 1010 includes a free magnet including at least one fixed magnet layer 120 and one free magnet layer 140. Element 1010 further includes electrode 107 making a nano- contact to the free magnet layer 140. Barrier layer 130 is located between the free magnet and the fixed magnet. Electrode 180 is proximate to the fixed magnet. Electrode 180 is electrically coupled to a first metal interconnect 1092 (e.g., bit line). Electrode 107 is electrically connected to a second metal interconnect 1091 (e.g., source line) through a selector. In the exemplary embodiment, the selector is transistor 1010 that is further connected to a third metal interconnect 1093 (e.g., word line) in any manner conventional in the art. Alternatively, for example in a cross-point architecture, transistor 1015 may replaced with a two-terminal selector. In SHE implementations electrode 180 may also be coupled to a fourth metal interconnect 1094 (e.g., maintained at a reference potential relative to first metal interconnect 1092).

The spin transfer torque memory bit cell 1001 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as understood by those skilled in the art of solid state non-volatile memory devices. A plurality of the spin transfer torque memory bit cells 1001 may be operably connected to one another to form a memory array (not shown), and the memory array can be incorporated into a non-volatile memory device following any known techniques and architectures. In some embodiments, transistors are formed in the front end of the line (FEOL) while an MTJ device is formed within the back end of the line (BEOL). Fig. 1 1 illustrates a cross-section 1 100 of a die layout including MTJ device 100 located in metal 3 and metal 2 layer regions, according to some embodiments of the disclosure. Elements in FIG. 1 1 having the same reference numbers (or names) as the elements of any other figures or description provided herein can comprise materials, operate, or function substantially as described elsewhere herein.

Cross-section 1100 illustrates an active region having a transistor MN comprising diffusion region 1101 , a gate terminal 1102, drain terminal 1104, and source terminal 1103. The source terminal 1103 is coupled to SL (source line) via poly silicon or a metal via, where the SL is formed on Metal 0 (M0). In some embodiments, the drain terminal 1 104 is coupled to MOa (also metal 0) through via 1 105. The drain terminal 1 104 is coupled to electrode 107 through via 0-1 (e.g., via connecting metal 0 to metal 1 layers), metal 1 (Ml), via 1-2 (e.g., via connecting metal 1 to metal 2 layers), and Metal 2 (M2). In some embodiments, MTJ device 100 is formed in the Metal 3 (M3) region. In some embodiments, the perpendicular fixed magnet of MTJ device 100 couples to electrode 107 and the perpendicular free magnet couples to the bit-line (BL) through Via 3-4 (e.g., via connecting metal 4 region to metal 4 (M4)). In this example, bit-line is formed on M4. In other embodiments, MTJ device 100 is formed in the metal 2 region and/or Via 1-2 region.

FIG. 12 illustrates a system 1200 in which a mobile computing platform 1205 and/or a data server machine 1206 employs an MTJ device with an nano-contacted free magnet layer, for example as described elsewhere herein. Server machine 1206 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes data processor circuitry 1250.

The mobile computing platform 1205 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1205 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1210, and a battery 1215. Whether disposed within the integrated system 1210 illustrated in the expanded view

1220, or as a stand-alone packaged device within the server machine 1206, SOC 1260 includes at least an MTJ device with an nano-contacted free magnet layer. SOC 1260 may further include memory circuitry and/or a processor circuitry 1250 (e.g., STTM, MRAM, a microprocessor, a multi-core microprocessor, graphics processor, etc.). Any of controller 1235, PMIC 1230, or RF (radio frequency) integrated circuitry (RFIC) 1225 may also be communicatively coupled to an MTJ device, such as an embedded STTM employing MTJ material stacks including one or more carbon-doped ferromagnetic layers.

As further illustrated, in the exemplary embodiment, RFIC 1225 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these SoC modules may be integrated onto separate ICs coupled to a package substrate, interposer, or board. FIG. 12 is a functional block diagram of a computing device 1200, arranged in accordance with at least some implementations of the present disclosure. Computing device 1200 may be found inside platform 1205 or server machine 1206, for example. Device 1200 further includes a motherboard 1202 hosting a number of components, such as, but not limited to, a processor 1204 (e.g., an applications processor), which may further incorporate embedded magnetic memory 1230 based on MTJ material stacks including one or more carbon-doped ferromagnetic layers, in accordance with embodiments of the present disclosure. Processor 1204 may be physically and/or electrically coupled to motherboard 1202. In some examples, processor 1204 includes an integrated circuit die packaged within the processor 1204. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips 1206 may also be physically and/or electrically coupled to the motherboard 1202. In further implementations, communication chips 1206 may be part of processor 1204. Depending on its applications, computing device 1200 may include other components that may or may not be physically and electrically coupled to motherboard 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM 1235), other non-volatile memory 1235 (e.g., flash memory), a graphics processor 1222, a digital signal processor, a crypto processor, a chipset 1212, an antenna 1225, touchscreen display 1215, touchscreen controller 1275, battery 1215, audio codec, video codec, power amplifier 1221, global positioning system (GPS) device 1240, compass 1245, accelerometer, gyroscope, speaker 1220, camera 1240. Computing device 1200 may also include a mass storage device (not depicted), such as a hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), or the like.

Communication chips 1206 may enable wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 1206 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1200 may include a plurality of communication chips 1206. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless

communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that the disclosure is not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below. In one or more first examples, a magnetic tunneling junction (MTJ) device comprises a first electrode having a lateral width of a first critical dimension (CD), a free magnet layer over the first electrode, the free magnet layer having a lateral width of a second CD that is larger than the first CD, a barrier layer over the free magnet layer, a fixed magnet layer over the barrier layer, and a second electrode over the fixed magnet layer. In one or more second examples, for any of the first examples the first CD is no more than half the second CD.

In one or more third examples, for any of the first or second examples the first electrode electrically couples the free magnet layer to an underlying interconnect metallization having a minimum lateral width that is larger than the first CD. In one or more fourth examples, for any of the first through third examples the first electrode comprises a foot having a minimum lateral width that is larger than the first CD, the foot contacting the interconnect metallization.

In one or more fifth examples, for any of the fourth examples the minimum lateral width of the foot is less than the minimum lateral width of the interconnect metallization. In one or more sixth examples, for any of the first through the fifth examples the first electrode has a height normal to the lateral width that is at least equal to the first CD.

In one or more seventh examples for any of the sixth examples the first electrode comprises a metal or metal alloy having columnar grains with <100> texture non-normal to the free magnet layer over a least a portion of the height.

In one or more eighth examples, for any of first through the seventh examples the first electrode contacts the free magnet layer over a contact area that is a function of the lateral width and a lateral length, which is at least equal to the second CD.

In one or more ninth examples, for any of the first through the eighth examples the first electrode comprises a first and second metal features in contact with the free magnet layer, the first and second metal features each having a lateral width of the first CD.

In one or more tenth examples a system comprises a data processor, and a data memory coupled to the processor, the memory comprising the MTJ device recited in any of the first through the ninth examples.

In one or more eleventh examples, an MRAM device comprises a first MTJ device comprising a first bottom electrode having a lateral width of a first critical dimension (CD), a first free magnet layer over the first bottom electrode, the first free magnet layer having a lateral width of a second CD that is larger than the first CD, a first barrier layer over the first free magnet layer, and a first fixed magnet layer over the first barrier layer, and a first top electrode over the first fixed magnet layer. The mRAM device comprises a second MTJ device adjacent to the first MTJ device, the second MTJ device comprising a second bottom electrode having a lateral width of the first CD, a second free magnet layer over the second bottom electrode, the second free magnet layer having a lateral width of the second CD, a second barrier layer over the second free magnet layer, a second fixed magnet layer over the second barrier layer, and a second top electrode over the second fixed magnet layer. The first and second bottom electrodes have a pitch that is substantially equal to that of the first and second free magnet layers.

In one or more twelfth examples, for any of the eleventh examples the first and second bottom electrodes each further comprises a foot having a minimum lateral width that is larger than the first CD, and wherein crystal texture within the foot has a different orientation than crystal texture within a remainder of the first and second electrodes.

In one or more thirteenth examples, for any of the eleventh or twelfth examples the first bottom electrode is asymmetric with respect to the first MTJ device, the second bottom electrode is asymmetric with respect to the second MTJ device, and a plane of symmetry between the first and second bottom electrodes extends through a space between the first and second MTJ devices.

In one or more fourteenth examples, a method of forming a magnetic tunneling junction (MTJ) device comprises forming a trench over an interconnect metallization, depositing a metal layer over a sidewall of the trench, depositing a dielectric layer over the metal layer, planarizing the dielectric layer with the sidewall of the trench to expose a portion of the metal layer, depositing a free magnet layer over the exposed portion of the metal layer and over the dielectric layer, depositing a barrier layer over the free magnet layer, depositing a fixed magnet layer over the barrier layer, and depositing a second electrode over the fixed magnet layer.

In one or more fifteenth examples, for any of the fourteenth examples the method further comprises patterning the MTJ device by etching through at least the free magnet layer and exposing the dielectric layer.

In one or more sixteenth examples, for any of the fourteenth through fifteenth examples the method further comprises anisotropically etching the metal layer into a conductive sidewall spacer aligned to the sidewall of the trench.

In one or more seventeenth examples, for any of the fourteenth through sixteenth examples depositing the dielectric layer over the metal layer further comprises depositing a first dielectric layer over the metal layer, anisotropically etching the first dielectric layer into a dielectric sidewall spacer aligned to the sidewall of the trench, and depositing a second dielectric layer over the dielectric sidewall spacer after etching a portion of the metal layer unprotected by the dielectric sidewall spacer.

In one or more eighteenth examples, for any of the fourteenth through seventeenth examples forming the trench further comprises etching the trench through the thickness of a dielectric layer, with a sidewall of the trench intersecting the interconnect metallization. In one or more nineteenth examples, for any of the eighteenth examples a sidewall of the trench also intersects a second interconnect metallization and planarizing the dielectric layer with the sidewall of the trench exposes two separate portions of the metal layer.

In one or more twentieth examples, for any of the fourteenth through eighteenth examples forming the fixed and free magnetic layers further comprises depositing a first amorphous layer of a ferromagnetic alloy, depositing the barrier layer over the first amorphous layer, depositing a second amorphous layer of a ferromagnetic alloy over the barrier layer, and annealing the MTJ device at a temperature of at least 350 °C to convert the first and second amorphous layers into poly crystalline layers.

In one or more twenty-first examples, a system, comprises a data processing means, and a data storage means coupled to the processing means, the data storage means comprising the MTJ device in any of the first through the ninth examples.

In one or more twenty-second examples, for any of the twenty -first examples, the system further comprises a wireless receiving means coupled to the processing means, and an electrical power storage means coupled to power the processing means.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:

1. A magnetic tunneling junction (MTJ) device, comprising:

a first electrode having a lateral width of a first critical dimension (CD);

a free magnet layer over the first electrode, the free magnet layer having a lateral width of a second CD that is larger than the first CD;

a barrier layer over the free magnet layer;

a fixed magnet layer over the barrier layer; and

a second electrode over the fixed magnet layer.

2. The MTJ device of claim 1, wherein the first CD is no more than half the second CD.

3. The MTJ device of claim 1, wherein the first electrode electrically couples the free

magnet layer to an underlying interconnect metallization having a minimum lateral width that is larger than the first CD.

4. The MTJ device of claim 3, wherein the first electrode comprises a foot having a

minimum lateral width that is larger than the first CD, the foot contacting the interconnect metallization.

5. The MTJ device of claim 4, wherein the minimum lateral width of the foot is less than the minimum lateral width of the interconnect metallization.

6. The MTJ device of claim 1, wherein the first electrode has a height normal to the lateral width that is at least equal to the first CD.

7. The MTJ device of claim 6, wherein the first electrode comprises a metal or metal alloy having columnar grains with <100> texture non-normal to the free magnet layer over a least a portion of the height.

8. The MTJ device of claim 1, wherein the first electrode contacts the free magnet layer over a contact area that is a function of the lateral width and a lateral length, which is at least equal to the second CD.

9. The MTJ device of claim 1, wherein the first electrode comprises a first and second metal features in contact with the free magnet layer, the first and second metal features each having a lateral width of the first CD.

10. A system, comprising:

a data processor; and

a data memory coupled to the processor, the memory comprising the MTJ device recited in any one of claims 1 -9.

1 1. A magnetoresistive random access memory (MRAM) device, comprising:

a first MTJ device comprising:

a first bottom electrode having a lateral width of a first critical dimension (CD); a first free magnet layer over the first bottom electrode, the first free magnet layer having a lateral width of a second CD that is larger than the first CD;

a first barrier layer over the first free magnet layer;

a first fixed magnet layer over the first barrier layer; and

a first top electrode over the first fixed magnet layer; and

a second MTJ device adjacent to the first MTJ device, the second MTJ device comprising: a second bottom electrode having a lateral width of the first CD;

a second free magnet layer over the second bottom electrode, the second free magnet layer having a lateral width of the second CD;

a second barrier layer over the second free magnet layer;

a second fixed magnet layer over the second barrier layer; and

a second top electrode over the second fixed magnet layer, wherein the first and second bottom electrodes have a pitch that is substantially equal to that of the first and second free magnet layers.

12. The MRAM device of claim 1 1, wherein the first and second bottom electrodes each further comprises a foot having a minimum lateral width that is larger than the first CD, and wherein crystal texture within the foot has a different orientation than crystal texture within a remainder of the first and second electrodes.

13. The MRAM device of claim 11, wherein the first bottom electrode is asymmetric with respect to the first MTJ device, the second bottom electrode is asymmetric with respect to the second MTJ device, and a plane of symmetry between the first and second bottom electrodes extends through a space between the first and second MTJ devices.

14. A method of forming a magnetic tunneling junction (MTJ) device, comprising:

forming a trench over an interconnect metallization;

depositing a metal layer over a sidewall of the trench;

depositing a dielectric layer over the metal layer;

planarizing the dielectric layer with the sidewall of the trench to expose a portion of the metal layer;

depositing a free magnet layer over the exposed portion of the metal layer and over the dielectric layer;

depositing a barrier layer over the free magnet layer;

depositing a fixed magnet layer over the barrier layer; and

depositing a second electrode over the fixed magnet layer.

15. The method of claim 14, further comprising patterning the MTJ device by etching

through at least the free magnet layer and exposing the dielectric layer.

16. The method of claim 14, further comprising anisotropically etching the metal layer into a conductive sidewall spacer aligned to the sidewall of the trench.

17. The method of claim 14, wherein depositing the dielectric layer over the metal layer further comprises:

depositing a first dielectric layer over the metal layer;

anisotropically etching the first dielectric layer into a dielectric sidewall spacer aligned to the sidewall of the trench; and

depositing a second dielectric layer over the dielectric sidewall spacer after etching a portion of the metal layer unprotected by the dielectric sidewall spacer.

18. The method of claim 14, wherein forming the trench further comprises etching the trench through the thickness of a dielectric layer, with a sidewall of the trench intersecting the interconnect metallization.

19. The method of claim 18, wherein a sidewall of the trench also intersects a second

interconnect metallization and planarizing the dielectric layer with the sidewall of the trench exposes two separate portions of the metal layer.

20. The method of claim 14, wherein forming the fixed and free magnetic layers further comprises:

depositing a first amorphous layer of a ferromagnetic alloy;

depositing the barrier layer over the first amorphous layer;

depositing a second amorphous layer of a ferromagnetic alloy over the barrier layer; and annealing the MTJ device at a temperature of at least 350 °C to convert the first and second amorphous layers into poly crystalline layers.