WO2019000703A1 - Laminated electric field modulation high-voltage mosfet structure and fabrication method therefor - Google Patents

Laminated electric field modulation high-voltage mosfet structure and fabrication method therefor Download PDF

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WO2019000703A1
WO2019000703A1 PCT/CN2017/105907 CN2017105907W WO2019000703A1 WO 2019000703 A1 WO2019000703 A1 WO 2019000703A1 CN 2017105907 W CN2017105907 W CN 2017105907W WO 2019000703 A1 WO2019000703 A1 WO 2019000703A1
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electric field
semiconductor
field modulation
semiconductor film
ion implantation
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PCT/CN2017/105907
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French (fr)
Chinese (zh)
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杨霏
潘艳
李玲
郑柳
査祎英
赵岩
田丽欣
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全球能源互联网研究院有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

Definitions

  • the invention relates to a MOSFET structure, in particular to a laminated electric field modulation high voltage MOSFET structure and a manufacturing method thereof.
  • Metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)) is a field-effect transistor that can be widely used in high-voltage and high-power fields. .
  • the blocking voltage and forward conduction resistance of the conventional power semiconductor device MOSFET have mutually restricting effects, increasing the thickness of the epitaxial layer, reducing the doping concentration can increase the blocking voltage, but also increasing the on-resistance, thereby reducing the positive To the current density, conversely, reducing the thickness of the epitaxial layer and increasing the doping concentration can reduce the on-resistance, but at the same time break the blocking voltage.
  • the drift region in the vertical power MOSFET is replaced with a crossed P/N column structure to form a vertical super junction power device.
  • This super-junction power device is based on the principle of charge balance, neutralizing the excess charge in the drift region, so that the on-resistance reduction and the blocking voltage increase can be simultaneously achieved.
  • the object of the embodiments of the present invention is to provide a MOSFET device that realizes high-voltage low on-resistance and reduces the difficulty of process operation by using a laminated electric field modulation structure, and the laminated electric field modulation structure is composed of a multi-layer cross-cycle N/P column structure.
  • the anti-type semiconductor is doped in the drift region of the MOSFET device.
  • a depletion layer is formed between the stacked N/P pillar structures, and more blocking voltage is taken.
  • the laminated electric field modulation structure can reduce the fabrication difficulty of each layer of the electric field modulation structure semiconductor process while achieving higher blocking voltage.
  • the embodiments of the present invention provide the following technical solutions:
  • an embodiment of the present invention provides a laminated electric field modulation high voltage MOSFET structure including a semiconductor substrate, an epitaxial layer having a laminated electric field modulation structure on the semiconductor substrate, and a metal on the laminated electric field modulation structure - Oxide-semiconductor (MOS) structure.
  • MOSFET laminated electric field modulation high voltage MOSFET structure
  • MOS Oxide-semiconductor
  • the laminated electric field modulation structure is an N/P/N/P structure or a P/N/P/N structure composed of an n-type semiconductor and a p-type semiconductor cross-cycle; an N/P structure semiconductor material and a semiconductor substrate Consistently, the laminated electric field modulation structure has an N-doped region and a P-doped region in each layer aligned with each other.
  • the material of the substrate is silicon carbide, silicon, gallium nitride or gallium arsenide.
  • the number of layers of the laminated electric field modulation structure is 1 to 10 layers; and/or,
  • Each layer has a thickness of 0.1 to 100 ⁇ m; and/or,
  • the thickness of the epitaxial layer is 10 to 200 ⁇ m.
  • an embodiment of the present invention provides a method for fabricating a laminated electric field modulated high voltage MOSFET structure by using a high energy ion implantation method, including:
  • Step 1 epitaxially depositing a layer of the same type of semiconductor film on the semiconductor substrate, and the semiconductor film serves as a basis for the first layer of the electric field modulation structure;
  • Step 2 injecting an anti-ion ion on the semiconductor film by high-energy ion implantation to form a cross-circular N/P structure as a first-layer electric field modulation structure;
  • Step 3 repeat steps 1 and 2 to form a laminated electric field modulation structure
  • Step 4 A metal-oxide-semiconductor (MOS) structure is fabricated on the laminated electric field modulation structure.
  • MOS metal-oxide-semiconductor
  • the semiconductor film of the same type as the substrate in the step 1 has a thickness of 0.1 to 100 ⁇ m; and/or
  • the depth of ion implantation is 0.1 to 3 ⁇ m; and/or,
  • the pattern of ion implantation is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
  • the graphic size is from 0.1 ⁇ m to 10 cm.
  • the semiconductor material implanted by the high energy ion implantation method is inverse to the semiconductor film.
  • the implantation depth of the high energy ion implantation method is 0.1 to 3 ⁇ m; and/or,
  • the injected energy is from 1 keV to 500 MeV; and/or,
  • the temperature of the injection is 0 to 1000 ° C; and / or,
  • the dose of ion implantation is 1 ⁇ 10 10 - 1 ⁇ 10 16 cm -2 ; and / or,
  • the ions are nitrogen, phosphorus n-type impurity ions, or aluminum or boron p-type impurity ions.
  • an embodiment of the present invention provides a method for fabricating a laminated electric field modulated high voltage MOSFET structure by etching a deep trench and a filling method, including:
  • Step 1 epitaxially depositing a layer of the same type of semiconductor film on the semiconductor substrate, and the semiconductor film serves as a basis for the first layer of the electric field modulation structure;
  • Step 2 etching the semiconductor film to form a deep trench having a number greater than one
  • Step 3 filling the deep trenches by epitaxial growth techniques to form a crossed N/P structure
  • Step 4 repeat steps 1, 2 and 3 to form a laminated electric field modulation structure
  • Step 5 A metal-oxide-semiconductor (MOS) structure is fabricated on the laminated electric field modulation structure.
  • MOS metal-oxide-semiconductor
  • the thickness of the semiconductor film of the epitaxial layer is 0.1-100 ⁇ m;
  • the shape of the deep trench front view is a rectangle or an inverted trapezoid, and the trapezoidal deep trench is wide and narrow; and/or
  • the depth of the deep trench is 0.1 to 50 ⁇ m; and/or,
  • the etched deep trench pattern is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
  • the pattern size is from 0.1 ⁇ m to 10 cm.
  • the semiconductor material filled by the filling method is inverse to the semiconductor film.
  • an embodiment of the present invention provides a method for fabricating a laminated electric field modulated high voltage MOSFET structure by etching deep trenches and sidewall ion implantation, including:
  • Step 1 epitaxially depositing a layer of the same type of semiconductor film on the semiconductor substrate, and the semiconductor film serves as a basis for the first layer of the electric field modulation structure;
  • Step 2 etching the semiconductor film to form a deep trench having a number greater than one
  • Step 3 injecting anti-ion ions into the sidewall or bottom of the trench by high-energy ion implantation to form a cross-cycled N/P structure;
  • Step 4 filling the deep trench with SiO 2 medium to form a structure of N/P/SiO 2 cross-circulation;
  • Step 5 repeat steps 1, 2, 3 and 4 to form a laminated electric field modulation structure
  • Step 6 A metal-oxide-semiconductor (MOS) structure is fabricated on the laminated electric field modulation structure.
  • MOS metal-oxide-semiconductor
  • the thickness of the semiconductor film of the epitaxial layer is 0.1-100 ⁇ m;
  • the shape of the deep groove front view is rectangular or trapezoidal, and the trapezoidal deep groove is narrow and narrow; and/or,
  • the depth of the deep trench is 0.1 to 50 ⁇ m; and/or,
  • the etched deep trench pattern is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
  • the pattern size is from 0.1 ⁇ m to 10 cm.
  • the semiconductor material and the semiconducting layer injected into the sidewall by the high energy ion implantation method The bulk film is inverted.
  • the front view is a rectangular deep trench, and the oblique angle of the high energy ion implantation is 0 to 90°.
  • the pattern of the ion implantation pattern and the etched deep trench is an interdigitated structure or a parallel strip or a circular or square mesa or a combination thereof; and/or, the pattern size is 0.1 ⁇ m to 10 cm.
  • the implantation depth of the high energy ion implantation method is 0.1 to 3 ⁇ m; and/or the energy of the implantation is 1 keV to 500 MeV; and/or the temperature of the implantation is 0 to 1000 ° C; and/or the dose of ion implantation is 1 ⁇ 10 10 to 1 ⁇ 10 16 cm -2 ; and/or the ions are nitrogen, phosphorus n-type impurity ions, or aluminum or boron p-type impurity ions.
  • the technical solution provided by the embodiment of the present invention has the following excellent effects:
  • the MOSFET provided by the embodiment of the invention adopts a laminated electric field modulation structure, which not only inherits the advantages of the conventional semi-super junction structure, can increase the blocking voltage and reduce the on-resistance; and also realizes high blocking of the MOSFET device. At the same time of voltage, the processing difficulty of each layer of electric field modulation structure is reduced.
  • High energy ion implantation method for preparing N/P structure, etching deep trench and filling method, etching deep trench and sidewall ion implantation method provided by embodiments of the present invention, and preparation method of three different laminated electric field modulation structures It lays the foundation for the fabrication of MOSFET devices.
  • FIG. 1 is a schematic view showing a structure of a laminated electric field modulation high voltage MOSFET prepared by ion implantation and etching deep trench and filling method according to an embodiment of the present invention
  • FIG. 2 is a schematic view showing a structure of a laminated electric field modulation high voltage MOSFET prepared by etching deep trenches and sidewall ion implantation according to an embodiment of the present invention
  • FIG. 3 is a schematic view showing a laminated cyclic N/P structure prepared by high energy ion implantation in an embodiment of the present invention
  • a deep trench and a filling method are used to prepare a laminated cyclic N/P structure rectangle. Deep trench diagram;
  • FIG. 5 is a schematic view showing the lamellar deep trench and the filling method for preparing a laminated cyclic N/P structure trapezoidal deep trench in the embodiment of the present invention
  • FIG. 6 is a schematic view showing a rectangular deep trench of a cyclic N/P/SiO 2 structure prepared by etching deep trenches and sidewall ion implantation in an embodiment of the present invention
  • FIG. 7 is a schematic view showing the preparation of a cyclic deep trench of a cyclic N/P/SiO 2 structure by etching deep trenches and sidewall ion implantation in an embodiment of the present invention
  • a stacked electric field modulated n-channel MOSFET device is fabricated by taking an silicon carbide material of an n-type substrate as an example, and another important structure of the MOSFET device is a double-diffused metal-oxide-semiconductor structure.
  • p-channel MOSFET devices and trench MOSFETs are also suitable for use in the methods of the embodiments of the present invention.
  • a method for fabricating a laminated electric field modulated high voltage MOSFET high energy ion implantation, etching deep trench and fill, and etching deep trench and sidewall ion implantation.
  • 3 to 7 are schematic views showing the fabrication of a stacked electric field modulation structure of a MOSFET device according to an embodiment of the present invention.
  • the n-type silicon carbide substrate 01 is cleaned, and the epitaxial layer 02 is epitaxially grown on the substrate to obtain a first epitaxial film 05, which forms a sample as shown in FIG. 3(a), the first layer.
  • the film 05 has a thickness of 0.1 to 100 ⁇ m, and is implanted with Al ions by high energy ion implantation to form p-type doping of silicon carbide, and the depth of ion implantation is 0.1 to 3 ⁇ m, forming a second layer electric field as shown in FIG. 3(b). Modulation structure diagram.
  • the pattern of the ion implantation pattern is an interdigitated structure, a parallel strip shape, a circular ring shape, a square mesa or a combination thereof, and the pattern size is 0.01 ⁇ m to 10 cm.
  • the homoepitaxial growth is repeated on the prepared sample of FIG. 3(b) to obtain a second epitaxial film 06 as shown in FIG. 3(c), and high energy ion implantation is repeated to form the second layer electric field modulation structure of FIG. 3(d). .
  • repeating epitaxy and high-energy ion implantation are performed 1 to 10 times to form a laminated electric field modulation structure, and the thickness of the epitaxial layer of the laminated electric field modulation structure is 10 to 200 ⁇ m.
  • the n-type silicon carbide substrate 01 is cleaned, and the epitaxial layer 02 is epitaxially grown on the substrate to obtain a first epitaxial film 05 as shown in FIGS. 4(a) and 5(a).
  • the thickness is 0.1 to 100 ⁇ m.
  • the trapezoidal deep trench is wide and narrow, and the etching depth is 0.1 to 50 ⁇ m;
  • the pattern of etching the deep trench is an interdigitated structure, a parallel strip, a circular ring, a square mesa or a combination thereof, and the pattern size is 0.01 ⁇ m to 10 cm.
  • the deep trench is filled by epitaxial growth to form a crossed N/P structure, and the deep trench is filled with a semiconductor material opposite to the semiconductor film (drift region) to obtain as shown in FIGS. 4(c) and 5(c).
  • the sample is repeatedly epitaxially formed on the basis of the completed sample to obtain a second epitaxial film 06, which is then etched and filled to obtain a laminated electric field modulation structure as shown in FIGS. 4(d) and 5(d).
  • the thickness of the epitaxial layer of the electric field modulation structure is 10 to 200 ⁇ m.
  • the n-type silicon carbide substrate 01 is cleaned, and the epitaxial layer 02 is epitaxially grown on the substrate to obtain a first epitaxial film 05 as shown in FIGS. 6(a) and 7(a).
  • the thickness is 0.1-100 ⁇ m
  • the deep trenches as shown in FIG. 6(b) and FIG. 7(b) are formed by etching, and the shape of the deep trench is an interdigitated structure or a parallel strip or a circular ring. Or a square mesa or a combination thereof, the pattern size is 0.1 ⁇ m to 10 cm, and the etching depth is 0.1 to 50 ⁇ m.
  • the etching depth is 0.1 to 50 ⁇ m.
  • Al ions are implanted into the sidewalls by oblique high energy ion implantation to form a p-type doped semiconductor as shown in Fig. 6(c), using SiO 2 Filling the etched deep trenches to form a structure in which the N/P/SiO 2 pillars are crossed as shown in Fig. 6(d).
  • the inclination angle of the sidewall ion implantation is determined according to the width and depth of the deep trench, and the tilt angle determined by the embodiment of the present invention is 0 to 90°.
  • high-energy ion implantation vertically implants Al ions onto the sidewalls and the bottom to form a sidewall and bottom p-doped semiconductor as shown in Figure 7(c). 2
  • the etched deep trench is filled to form a structure of N/P/SiO 2 cross-circulation as shown in Fig. 7(d).
  • FIGS. 1 and 2 are schematic views showing the structure of a laminated electric field modulating high voltage MOSFET. Figs. 1 and 2 are only two types of embodiments of the present invention.
  • the embodiment of the invention not only inherits the advantages that the traditional semi-super junction structure can increase the blocking voltage and reduce the on-resistance; but also realizes the high blocking voltage of the MOSFET device, and reduces the processing difficulty of the electric field modulation structure of each layer. .

Abstract

A laminated electric field modulation high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) structure and a fabrication method therefor. The MOSFET structure comprises: a semiconductor substrate (01), an epitaxial layer (02) having a laminated electric field modulation structure on the semiconductor substrate, and a metal-oxide semiconductor (MOS) structure (03) on the laminated electric field modulation structure. The laminated electric field modulation structure is an N/P/N/P structure composed of an n-type semiconductor and a p-type semiconductor in an alternative and cyclic manner; the N/P structure has the same material as the semiconductor substrate, and the N-doped region and P-doped region of each layer are aligned with each other.

Description

一种叠层电场调制高压MOSFET结构及其制作方法Laminated electric field modulation high voltage MOSFET structure and manufacturing method thereof
相关申请的交叉引用Cross-reference to related applications
本申请基于申请号为201710513956.5、申请日为2017年06月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。The present application is based on a Chinese patent application filed on Jan. 29, 2017, the entire disclosure of which is hereby incorporated by reference.
技术领域Technical field
本发明涉及一种MOSFET结构，具体涉及一种叠层电场调制高压MOSFET结构及其制作方法。The invention relates to a MOSFET structure, in particular to a laminated electric field modulation high voltage MOSFET structure and a manufacturing method thereof.
背景技术Background technique
金属-氧化物半导体场效应晶体管，简称金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)是一种可以广泛使用在高压大功率领域的场效应晶体管(field-effect transistor)。传统的功率半导体器件MOSFET的阻断电压和正向导通电阻有互相制约作用，增大外延层厚度，减小掺杂浓度能够提高阻断电压，但同时也增大了导通电阻，进而降低了正向电流密度，反之，减小外延层厚度，增大掺杂浓度能降低导通电阻，但同时折损了阻断电压。现有技术中将纵向功率MOSFET中的漂移区用交叉的P/N柱区结构代替，形成纵向超结功率器件。这种超结功率器件以电荷平衡原理为基础，中和漂移区多余的电荷，因此可以同时实现导通电阻的降低与阻断电压的增大。Metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)) is a field-effect transistor that can be widely used in high-voltage and high-power fields. . The blocking voltage and forward conduction resistance of the conventional power semiconductor device MOSFET have mutually restricting effects, increasing the thickness of the epitaxial layer, reducing the doping concentration can increase the blocking voltage, but also increasing the on-resistance, thereby reducing the positive To the current density, conversely, reducing the thickness of the epitaxial layer and increasing the doping concentration can reduce the on-resistance, but at the same time break the blocking voltage. In the prior art, the drift region in the vertical power MOSFET is replaced with a crossed P/N column structure to form a vertical super junction power device. This super-junction power device is based on the principle of charge balance, neutralizing the excess charge in the drift region, so that the on-resistance reduction and the blocking voltage increase can be simultaneously achieved.
对于高压大功率的MOSFET而言，较厚的外延层厚度对超结和半超结的制作工艺都提出了更高的要求，因此需要提供一种技术方案来满足现有技术的需要。 For high-voltage and high-power MOSFETs, thicker epitaxial layer thicknesses place higher demands on the fabrication process of both superjunction and semi-superjunction. Therefore, it is necessary to provide a technical solution to meet the needs of the prior art.
发明内容Summary of the invention
本发明实施例的目的是提供了一种采用叠层电场调制结构实现高压低导通电阻且降低工艺操作难度的MOSFET器件，叠层电场调制结构是由多层交叉循环的N/P柱结构组成，根据电荷平衡原理，MOSFET器件漂移区中掺入反型的半导体，在阻断的过程中，叠层交叉循环的N/P柱结构之间形成耗尽层，承担更多的阻断电压。同时叠层的电场调制结构在能够实现更高的阻断电压的同时，也能降低每层电场调制结构半导体工艺的制作难度。为了达到上述目的，本发明实施例提供了下述技术方案：The object of the embodiments of the present invention is to provide a MOSFET device that realizes high-voltage low on-resistance and reduces the difficulty of process operation by using a laminated electric field modulation structure, and the laminated electric field modulation structure is composed of a multi-layer cross-cycle N/P column structure. According to the principle of charge balance, the anti-type semiconductor is doped in the drift region of the MOSFET device. During the blocking process, a depletion layer is formed between the stacked N/P pillar structures, and more blocking voltage is taken. At the same time, the laminated electric field modulation structure can reduce the fabrication difficulty of each layer of the electric field modulation structure semiconductor process while achieving higher blocking voltage. In order to achieve the above objective, the embodiments of the present invention provide the following technical solutions:
第一方面，本发明实施例提供了一种叠层电场调制高压MOSFET结构，该结构包括半导体衬底、半导体衬底上有叠层电场调制结构的外延层和叠层电场调制结构上的金属-氧化物-半导体(MOS)结构。In a first aspect, an embodiment of the present invention provides a laminated electric field modulation high voltage MOSFET structure including a semiconductor substrate, an epitaxial layer having a laminated electric field modulation structure on the semiconductor substrate, and a metal on the laminated electric field modulation structure - Oxide-semiconductor (MOS) structure.
上述方案中，叠层电场调制结构为由n型半导体和p型半导体交叉循环组成的N/P/N/P结构或P/N/P/N结构；N/P结构半导体材料和半导体衬底一致，叠层电场调制结构，每层的N掺杂区域和P掺杂区域相互对齐。In the above solution, the laminated electric field modulation structure is an N/P/N/P structure or a P/N/P/N structure composed of an n-type semiconductor and a p-type semiconductor cross-cycle; an N/P structure semiconductor material and a semiconductor substrate Consistently, the laminated electric field modulation structure has an N-doped region and a P-doped region in each layer aligned with each other.
上述方案中，衬底的材料为碳化硅、硅、氮化镓或砷化镓。In the above solution, the material of the substrate is silicon carbide, silicon, gallium nitride or gallium arsenide.
上述方案中，叠层电场调制结构的层数为1～10层；和/或，In the above solution, the number of layers of the laminated electric field modulation structure is 1 to 10 layers; and/or,
每一层的厚度为0.1～100μm；和/或，Each layer has a thickness of 0.1 to 100 μm; and/or,
外延层的厚度为10～200μm。The thickness of the epitaxial layer is 10 to 200 μm.
第二方面，本发明实施例提供了一种利用高能离子注入法制备叠层电场调制高压MOSFET结构的方法，包括：In a second aspect, an embodiment of the present invention provides a method for fabricating a laminated electric field modulated high voltage MOSFET structure by using a high energy ion implantation method, including:
步骤1：在半导体衬底上外延一层同型的半导体薄膜，半导体薄膜作为第一层电场调制结构的基础；Step 1: epitaxially depositing a layer of the same type of semiconductor film on the semiconductor substrate, and the semiconductor film serves as a basis for the first layer of the electric field modulation structure;
步骤2：用高能离子注入法在半导体薄膜上注入反型离子，形成作为第一层电场调制结构的交叉循环N/P结构；Step 2: injecting an anti-ion ion on the semiconductor film by high-energy ion implantation to form a cross-circular N/P structure as a first-layer electric field modulation structure;
步骤3：重复步骤1和2步，形成叠层的电场调制结构； Step 3: repeat steps 1 and 2 to form a laminated electric field modulation structure;
步骤4：在叠层电场调制结构上，制作金属-氧化物-半导体(MOS)结构。Step 4: A metal-oxide-semiconductor (MOS) structure is fabricated on the laminated electric field modulation structure.
上述方案中，步骤1中的与衬底同型的半导体薄膜厚度为0.1～100μm；和/或，In the above solution, the semiconductor film of the same type as the substrate in the step 1 has a thickness of 0.1 to 100 μm; and/or
离子注入的深度为0.1～3μm；和/或，The depth of ion implantation is 0.1 to 3 μm; and/or,
离子注入的图形为叉指结构、平行长条状、圆环形、方形台面或它们的组合图形；和/或，The pattern of ion implantation is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
图形尺寸为0.1μm～10cm。The graphic size is from 0.1 μm to 10 cm.
上述方案中，采用所述高能离子注入法注入的半导体材料与半导体薄膜是反型的。In the above solution, the semiconductor material implanted by the high energy ion implantation method is inverse to the semiconductor film.
上述方案中，所述高能离子注入法的注入深度为0.1～3μm；和/或，In the above solution, the implantation depth of the high energy ion implantation method is 0.1 to 3 μm; and/or,
注入的能量为1keV～500MeV；和/或，The injected energy is from 1 keV to 500 MeV; and/or,
注入的温度为0～1000℃；和/或，The temperature of the injection is 0 to 1000 ° C; and / or,
离子注入的剂量为1×1010～1×1016cm-2；和/或，The dose of ion implantation is 1 × 10 10 - 1 × 10 16 cm -2 ; and / or,
所述离子为氮、磷n型杂质离子，或铝、硼p型杂质离子。The ions are nitrogen, phosphorus n-type impurity ions, or aluminum or boron p-type impurity ions.
第三方面，本发明实施例提供了一种利用刻蚀深沟槽与填充法制备叠层电场调制高压MOSFET结构的方法，包括：In a third aspect, an embodiment of the present invention provides a method for fabricating a laminated electric field modulated high voltage MOSFET structure by etching a deep trench and a filling method, including:
步骤1：在半导体衬底上外延一层同型的半导体薄膜，半导体薄膜作为第一层电场调制结构的基础；Step 1: epitaxially depositing a layer of the same type of semiconductor film on the semiconductor substrate, and the semiconductor film serves as a basis for the first layer of the electric field modulation structure;
步骤2：刻蚀半导体薄膜，形成数目大于1的深沟槽；Step 2: etching the semiconductor film to form a deep trench having a number greater than one;
步骤3：用外延生长技术填充深沟槽，形成交叉的N/P结构；Step 3: filling the deep trenches by epitaxial growth techniques to form a crossed N/P structure;
步骤4：重复1、2和3步，形成叠层的电场调制结构；Step 4: repeat steps 1, 2 and 3 to form a laminated electric field modulation structure;
步骤5：在叠层电场调制结构上，制作金属-氧化物-半导体(MOS)结构。Step 5: A metal-oxide-semiconductor (MOS) structure is fabricated on the laminated electric field modulation structure.
上述方案中，所述外延层同型的半导体薄膜厚度为0.1～100μm；和/或， In the above solution, the thickness of the semiconductor film of the epitaxial layer is 0.1-100 μm; and/or
所述深沟槽正视图的形状为矩形或倒梯形，梯形深沟槽上宽下窄；和/或，The shape of the deep trench front view is a rectangle or an inverted trapezoid, and the trapezoidal deep trench is wide and narrow; and/or
所述深沟槽的深度为0.1～50μm；和/或，The depth of the deep trench is 0.1 to 50 μm; and/or,
所述刻蚀的深沟槽的图形为叉指结构、平行长条状、圆环形、方形台面或它们的组合图形；和/或，The etched deep trench pattern is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
所述图形尺寸为0.1μm～10cm。The pattern size is from 0.1 μm to 10 cm.
上述方案中，采用填充法填充的半导体材料与半导体薄膜是反型的。In the above scheme, the semiconductor material filled by the filling method is inverse to the semiconductor film.
第四方面，本发明实施例提供了一种利用刻蚀深沟槽与侧壁离子注入法制备叠层电场调制高压MOSFET结构的方法，包括：In a fourth aspect, an embodiment of the present invention provides a method for fabricating a laminated electric field modulated high voltage MOSFET structure by etching deep trenches and sidewall ion implantation, including:
步骤1：在半导体衬底上外延一层同型的半导体薄膜，半导体薄膜作为第一层电场调制结构的基础；Step 1: epitaxially depositing a layer of the same type of semiconductor film on the semiconductor substrate, and the semiconductor film serves as a basis for the first layer of the electric field modulation structure;
步骤2：刻蚀所述半导体薄膜，形成数目大于1的深沟槽；Step 2: etching the semiconductor film to form a deep trench having a number greater than one;
步骤3：采用高能离子注入法在所述沟槽侧壁或底部注入反型离子，形成交叉循环的N/P结构；Step 3: injecting anti-ion ions into the sidewall or bottom of the trench by high-energy ion implantation to form a cross-cycled N/P structure;
步骤4：在深沟槽中填充SiO2介质，形成N/P/SiO2交叉循环的结构；Step 4: filling the deep trench with SiO 2 medium to form a structure of N/P/SiO 2 cross-circulation;
步骤5：重复步骤1、2、3和4，形成叠层的电场调制结构；Step 5: repeat steps 1, 2, 3 and 4 to form a laminated electric field modulation structure;
步骤6：在叠层电场调制结构上，制作金属-氧化物-半导体(MOS)结构。Step 6: A metal-oxide-semiconductor (MOS) structure is fabricated on the laminated electric field modulation structure.
上述方案中，外延层同型的半导体薄膜厚度为0.1～100μm；和/或，In the above solution, the thickness of the semiconductor film of the epitaxial layer is 0.1-100 μm; and/or
深沟槽正视图的形状为矩形或者梯形，梯形深沟槽上宽下窄；和/或，The shape of the deep groove front view is rectangular or trapezoidal, and the trapezoidal deep groove is narrow and narrow; and/or,
深沟槽的深度为0.1～50μm；和/或，The depth of the deep trench is 0.1 to 50 μm; and/or,
所述刻蚀的深沟槽的图形为叉指结构、平行长条状、圆环形、方形台面或它们的组合图形；和/或，The etched deep trench pattern is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
所述图形尺寸为0.1μm～10cm。The pattern size is from 0.1 μm to 10 cm.
上述方案中，采用所述高能离子注入法注入侧壁的半导体材料与半导 体薄膜是反型的。In the above solution, the semiconductor material and the semiconducting layer injected into the sidewall by the high energy ion implantation method The bulk film is inverted.
上述方案中，正视图为矩形的深沟槽，高能离子注入的倾斜角度为0～90°。In the above solution, the front view is a rectangular deep trench, and the oblique angle of the high energy ion implantation is 0 to 90°.
上述方案中，离子注入图形和刻蚀深沟槽的图形为叉指结构或平行长条状或圆环形或方形台面或它们的组合图形；和/或，图形尺寸为0.1μm～10cm。In the above solution, the pattern of the ion implantation pattern and the etched deep trench is an interdigitated structure or a parallel strip or a circular or square mesa or a combination thereof; and/or, the pattern size is 0.1 μm to 10 cm.
其中，高能离子注入法的注入深度为0.1～3μm；和/或，注入的能量为1keV～500MeV；和/或，注入的温度为0～1000℃；和/或，离子注入的剂量为1×1010～1×1016cm-2；和/或，离子为氮、磷n型杂质离子，或铝、硼p型杂质离子。Wherein, the implantation depth of the high energy ion implantation method is 0.1 to 3 μm; and/or the energy of the implantation is 1 keV to 500 MeV; and/or the temperature of the implantation is 0 to 1000 ° C; and/or the dose of ion implantation is 1× 10 10 to 1 × 10 16 cm -2 ; and/or the ions are nitrogen, phosphorus n-type impurity ions, or aluminum or boron p-type impurity ions.
与最接近的现有技术相比，本发明实施例提供的技术方案具有以下优异效果：Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following excellent effects:
本发明实施例提供的MOSFET采用的是叠层电场调制结构，这种结构不仅继承了传统的半超结结构能够增大阻断电压、降低导通电阻的优点；也在实现MOSFET器件高阻断电压的同时，降低了每层电场调制结构的加工工艺难度。本发明实施例提供的制备N/P结构的高能离子注入法、刻蚀深沟槽与填充法以及刻蚀深沟槽与侧壁离子注入法，三种不同的叠层电场调制结构的制备方法为MOSFET器件的制作提供奠定了基础。The MOSFET provided by the embodiment of the invention adopts a laminated electric field modulation structure, which not only inherits the advantages of the conventional semi-super junction structure, can increase the blocking voltage and reduce the on-resistance; and also realizes high blocking of the MOSFET device. At the same time of voltage, the processing difficulty of each layer of electric field modulation structure is reduced. High energy ion implantation method for preparing N/P structure, etching deep trench and filling method, etching deep trench and sidewall ion implantation method provided by embodiments of the present invention, and preparation method of three different laminated electric field modulation structures It lays the foundation for the fabrication of MOSFET devices.
附图说明DRAWINGS
图1：本发明实施例采用离子注入法和刻蚀深沟槽与填充法制备的叠层电场调制高压MOSFET结构的示意图；FIG. 1 is a schematic view showing a structure of a laminated electric field modulation high voltage MOSFET prepared by ion implantation and etching deep trench and filling method according to an embodiment of the present invention; FIG.
图2：本发明实施例采用刻蚀深沟槽与侧壁离子注入法制备的叠层电场调制高压MOSFET结构的示意图；2 is a schematic view showing a structure of a laminated electric field modulation high voltage MOSFET prepared by etching deep trenches and sidewall ion implantation according to an embodiment of the present invention;
图3：本发明实施例中高能离子注入法制备叠层循环N/P结构示意图；3 is a schematic view showing a laminated cyclic N/P structure prepared by high energy ion implantation in an embodiment of the present invention;
图4：本发明实施例中刻蚀深沟槽与填充法制备叠层循环N/P结构矩形 深沟槽示意图；4: In the embodiment of the present invention, a deep trench and a filling method are used to prepare a laminated cyclic N/P structure rectangle. Deep trench diagram;
图5：本发明实施例中刻蚀深沟槽与填充法制备叠层循环N/P结构梯形深沟槽示意图；FIG. 5 is a schematic view showing the lamellar deep trench and the filling method for preparing a laminated cyclic N/P structure trapezoidal deep trench in the embodiment of the present invention; FIG.
图6：本发明实施例中刻蚀深沟槽与侧壁离子注入法制备循环N/P/SiO2结构矩形深沟槽示意图；6 is a schematic view showing a rectangular deep trench of a cyclic N/P/SiO 2 structure prepared by etching deep trenches and sidewall ion implantation in an embodiment of the present invention;
图7：本发明实施例中刻蚀深沟槽与侧壁离子注入法制备循环N/P/SiO2结构梯形深沟槽示意图；7 is a schematic view showing the preparation of a cyclic deep trench of a cyclic N/P/SiO 2 structure by etching deep trenches and sidewall ion implantation in an embodiment of the present invention;
其中，01衬底，02外延层，03MOS结构，04欧姆接触，05第一层外延薄膜；06第二层外延薄膜。Among them, 01 substrate, 02 epitaxial layer, 03MOS structure, 04 ohmic contact, 05 first epitaxial film; 06 second epitaxial film.
具体实施方式Detailed ways
下面结合附图和具体实施例作进一步详细说明，对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。The embodiments of the present invention are described in detail with reference to the accompanying drawings and specific embodiments. FIG. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
本发明实施例以n型衬底的碳化硅材料为例制作叠层电场调制n沟道MOSFET器件，其中MOSFET器件的另一重要结构选用双扩散金属-氧化物-半导体结构。同样的，p沟道MOSFET器件和沟槽MOSFET也适用于本发明实施例方法。In the embodiment of the present invention, a stacked electric field modulated n-channel MOSFET device is fabricated by taking an silicon carbide material of an n-type substrate as an example, and another important structure of the MOSFET device is a double-diffused metal-oxide-semiconductor structure. Similarly, p-channel MOSFET devices and trench MOSFETs are also suitable for use in the methods of the embodiments of the present invention.
一种叠层电场调制高压MOSFET的制作方法：高能离子注入法、刻蚀深沟槽与填充法以及刻蚀深沟槽与侧壁离子注入法。图3～7分别是本发明实施例MOSFET器件叠层电场调制结构的制作示意图。A method for fabricating a laminated electric field modulated high voltage MOSFET: high energy ion implantation, etching deep trench and fill, and etching deep trench and sidewall ion implantation. 3 to 7 are schematic views showing the fabrication of a stacked electric field modulation structure of a MOSFET device according to an embodiment of the present invention.
1.高能离子注入法：1. High energy ion implantation method:
如图3所示，清洗n型碳化硅衬底01，并在衬底上同质外延生长外延层02得到第一层外延薄膜05，形成如图3(a)所示的样品，第一层外延 薄膜05的厚度为0.1～100μm，通过高能离子注入的方法注入Al离子形成碳化硅的p型掺杂，离子注入的深度为0.1～3μm，形成如图3(b)所示的第二层电场调制结构图。离子注入图形的图形为叉指结构、平行长条状、圆环形、方形台面或它们的组合图形，图形尺寸为0.01μm～10cm。于制作好的图3(b)样品上重复同质外延得到如样品图3(c)所示的第二层外延薄膜06，重复进行高能离子注入形成图3(d)第二层电场调制结构。在此基础上，重复外延和高能离子注入1～10次形成叠层的电场调制结构，叠层电场调制结构的外延层的厚度为10～200μm。As shown in FIG. 3, the n-type silicon carbide substrate 01 is cleaned, and the epitaxial layer 02 is epitaxially grown on the substrate to obtain a first epitaxial film 05, which forms a sample as shown in FIG. 3(a), the first layer. Extension The film 05 has a thickness of 0.1 to 100 μm, and is implanted with Al ions by high energy ion implantation to form p-type doping of silicon carbide, and the depth of ion implantation is 0.1 to 3 μm, forming a second layer electric field as shown in FIG. 3(b). Modulation structure diagram. The pattern of the ion implantation pattern is an interdigitated structure, a parallel strip shape, a circular ring shape, a square mesa or a combination thereof, and the pattern size is 0.01 μm to 10 cm. The homoepitaxial growth is repeated on the prepared sample of FIG. 3(b) to obtain a second epitaxial film 06 as shown in FIG. 3(c), and high energy ion implantation is repeated to form the second layer electric field modulation structure of FIG. 3(d). . On the basis of this, repeating epitaxy and high-energy ion implantation are performed 1 to 10 times to form a laminated electric field modulation structure, and the thickness of the epitaxial layer of the laminated electric field modulation structure is 10 to 200 μm.
2.刻蚀深沟槽与填充法：2. Etching deep trenches and filling methods:
如图4和5所示，清洗n型碳化硅衬底01，并在衬底上同质外延生长外延层02得到如图4(a)和5(a)所示的第一层外延薄膜05，厚度为0.1～100μm。通过刻蚀的方法形成如图4(b)和图5(b)所示多个形状为矩形或者梯形的深沟槽，梯形深沟槽上宽下窄，刻蚀的深度为0.1～50μm；刻蚀深沟槽的图形为叉指结构、平行长条状、圆环形、方形台面或它们的组合图形，图形尺寸为0.01μm～10cm。深沟槽通过外延生长的方式填充，形成交叉的N/P结构，用与半导体薄膜(漂移区)反型的半导体材料填充深沟槽得到如图4(c)和图5(c)所示的样品，在完成的样品基础上重复外延得到第二层外延薄膜06，再进行刻蚀和填充，得到如图4(d)和图5(d)所示的叠层电场调制结构，叠层电场调制结构的外延层的厚度为10～200μm。As shown in FIGS. 4 and 5, the n-type silicon carbide substrate 01 is cleaned, and the epitaxial layer 02 is epitaxially grown on the substrate to obtain a first epitaxial film 05 as shown in FIGS. 4(a) and 5(a). The thickness is 0.1 to 100 μm. A plurality of deep trenches having a rectangular or trapezoidal shape as shown in FIG. 4(b) and FIG. 5(b) are formed by etching, and the trapezoidal deep trench is wide and narrow, and the etching depth is 0.1 to 50 μm; The pattern of etching the deep trench is an interdigitated structure, a parallel strip, a circular ring, a square mesa or a combination thereof, and the pattern size is 0.01 μm to 10 cm. The deep trench is filled by epitaxial growth to form a crossed N/P structure, and the deep trench is filled with a semiconductor material opposite to the semiconductor film (drift region) to obtain as shown in FIGS. 4(c) and 5(c). The sample is repeatedly epitaxially formed on the basis of the completed sample to obtain a second epitaxial film 06, which is then etched and filled to obtain a laminated electric field modulation structure as shown in FIGS. 4(d) and 5(d). The thickness of the epitaxial layer of the electric field modulation structure is 10 to 200 μm.
3.刻蚀深沟槽与侧壁离子注入法：3. Etching deep trench and sidewall ion implantation:
如图6和7所示，清洗n型碳化硅衬底01，并在衬底上同质外延生长外延层02得到如图6(a)和7(a)所示的第一层外延薄膜05，厚度为0.1～100μm，通过刻蚀的方法形成如图6(b)和图7(b)所示的深沟槽，深沟槽的形状为叉指结构或平行长条状或圆环形或方形台面或它们的组合图形，图形尺寸为0.1μm～10cm，刻蚀的深度为0.1～50μm。于图6(b)所 示的样品上，采用倾斜的高能离子注入法将Al离子注入到侧壁上，形成如图6(c)所示的侧壁为p型掺杂的半导体，用SiO2填充刻蚀的深沟槽，形成如图6(d)所示的N/P/SiO2柱交叉循环的结构。侧壁离子注入的倾斜角度根据深沟槽的宽度和深度来确定，本发明实施例确定的倾斜角度为0～90°。于7(b)所示的样品上，高能离子注入法将Al离子垂直注入到侧壁上和底部，形成如图7(c)所示的侧壁与底部p型掺杂的半导体，用SiO2填充刻蚀的深沟槽，形成如图7(d)所示的N/P/SiO2交叉循环的结构。重复外延得到第二层外延薄膜06，再进行刻蚀、注入和填充得到如图6(e)和7(e)所述的叠层电场调制的结构，叠层电场调制结构的外延层的厚度为10～200μm。As shown in FIGS. 6 and 7, the n-type silicon carbide substrate 01 is cleaned, and the epitaxial layer 02 is epitaxially grown on the substrate to obtain a first epitaxial film 05 as shown in FIGS. 6(a) and 7(a). The thickness is 0.1-100 μm, and the deep trenches as shown in FIG. 6(b) and FIG. 7(b) are formed by etching, and the shape of the deep trench is an interdigitated structure or a parallel strip or a circular ring. Or a square mesa or a combination thereof, the pattern size is 0.1 μm to 10 cm, and the etching depth is 0.1 to 50 μm. On the sample shown in Fig. 6(b), Al ions are implanted into the sidewalls by oblique high energy ion implantation to form a p-type doped semiconductor as shown in Fig. 6(c), using SiO 2 Filling the etched deep trenches to form a structure in which the N/P/SiO 2 pillars are crossed as shown in Fig. 6(d). The inclination angle of the sidewall ion implantation is determined according to the width and depth of the deep trench, and the tilt angle determined by the embodiment of the present invention is 0 to 90°. On the sample shown in 7(b), high-energy ion implantation vertically implants Al ions onto the sidewalls and the bottom to form a sidewall and bottom p-doped semiconductor as shown in Figure 7(c). 2 The etched deep trench is filled to form a structure of N/P/SiO 2 cross-circulation as shown in Fig. 7(d). Repeat epitaxy to obtain a second epitaxial film 06, and then etching, implanting and filling to obtain a laminated electric field modulation structure as shown in FIGS. 6(e) and 7(e), and the thickness of the epitaxial layer of the laminated electric field modulation structure It is 10 to 200 μm.
形成上述叠层电场调制结构后，制作MOS结构03，淀积金属形成欧姆接触04，形成如图1和图2所示的样品。图1和图2直观展示了叠层电场调制高压MOSFET的结构示意图，图1和图2仅是本发明实施例实施例中的2种。After the above laminated electric field modulation structure is formed, the MOS structure 03 is formed, and the metal is deposited to form an ohmic contact 04 to form a sample as shown in FIGS. 1 and 2. 1 and 2 are schematic views showing the structure of a laminated electric field modulating high voltage MOSFET. Figs. 1 and 2 are only two types of embodiments of the present invention.
以上实施例仅用以说明本发明的技术方案而非对其进行限制，所属领域的普通技术人员应当理解，参照上述实施例可以对本发明的具体实施方式进行修改或者等同替换，这些未脱离本发明精神和范围的任何修改或者等同替换均在申请待批的权利要求保护范围之内。The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to be limiting, and those skilled in the art should understand that the embodiments of the present invention may be modified or equivalently substituted without departing from the invention. Any modification or equivalent substitution of the spirit and scope is within the scope of the appended claims.
工业实用性Industrial applicability
本发明实施例不仅继承了传统的半超结结构能够增大阻断电压、降低导通电阻的优点；也在实现MOSFET器件高阻断电压的同时，降低了每层电场调制结构的加工工艺难度。 The embodiment of the invention not only inherits the advantages that the traditional semi-super junction structure can increase the blocking voltage and reduce the on-resistance; but also realizes the high blocking voltage of the MOSFET device, and reduces the processing difficulty of the electric field modulation structure of each layer. .

Claims (15)

  1. 一种叠层电场调制高压MOSFET结构，所述结构包括半导体衬底、所述半导体衬底上有叠层电场调制结构的外延层和所述叠层电场调制结构上的金属-氧化物-半导体(MOS)结构。A stacked electric field modulating high voltage MOSFET structure, the structure comprising a semiconductor substrate, an epitaxial layer having a stacked electric field modulating structure on the semiconductor substrate, and a metal-oxide-semiconductor on the stacked electric field modulating structure ( MOS) structure.
  2. 如权利要求1所述的叠层电场调制高压MOSFET结构，其中，所述叠层电场调制结构为由n型半导体和p型半导体交叉循环组成的N/P/N/P或P/N/P/N结构；所述的N/P结构半导体材料和半导体衬底一致，所述的叠层电场调制结构，每层的N掺杂区域和P掺杂区域相互对齐。The stacked electric field modulation high voltage MOSFET structure according to claim 1, wherein said stacked electric field modulation structure is N/P/N/P or P/N/P composed of an n-type semiconductor and a p-type semiconductor cross-cycle. /N structure; the N/P structure semiconductor material is identical to the semiconductor substrate, the laminated electric field modulation structure, the N-doped region and the P-doped region of each layer are aligned with each other.
  3. 如权利要求1所述的叠层电场调制高压MOSFET结构，其中，所述衬底的材料为碳化硅、硅、氮化镓或砷化镓。The stacked field modulated high voltage MOSFET structure of claim 1 wherein the material of the substrate is silicon carbide, silicon, gallium nitride or gallium arsenide.
  4. 如权利要求1所述的叠层电场调制高压MOSFET结构，其中，所述叠层电场调制结构的层数为1～10层；和/或，The stacked electric field modulation high voltage MOSFET structure according to claim 1, wherein said laminated electric field modulation structure has a number of layers of 1 to 10 layers; and/or
    每一层的厚度为0.1～100μm；和/或，Each layer has a thickness of 0.1 to 100 μm; and/or,
    所述外延层的厚度为10～200μm。The epitaxial layer has a thickness of 10 to 200 μm.
  5. 一种如权利要求1所述的叠层电场调制高压MOSFET结构的制作方法，所述方法包括：A method of fabricating a stacked electric field modulated high voltage MOSFET structure according to claim 1, the method comprising:
    步骤1：在半导体衬底上外延一层同型的半导体薄膜，所述的半导体薄膜作为第一层电场调制结构的基础；Step 1: epitaxially depositing a layer of a similar semiconductor film on the semiconductor substrate, the semiconductor film being used as a basis for the first layer of the electric field modulation structure;
    步骤2：采用高能离子注入法在所述的半导体薄膜上注入反型离子，形成作为所述第一层电场调制结构的交叉循环N/P结构；Step 2: implanting an inversion ion on the semiconductor film by a high energy ion implantation method to form a cross-circular N/P structure as the first layer electric field modulation structure;
    步骤3：重复步骤1和2步，形成叠层的电场调制结构；Step 3: repeat steps 1 and 2 to form a laminated electric field modulation structure;
    步骤4：在所述叠层电场调制结构上，制作金属-氧化物-半导体(MOS)结构。Step 4: Fabricating a metal-oxide-semiconductor (MOS) structure on the laminated electric field modulation structure.
  6. 如权利要求5所述的制作方法，其中，The manufacturing method according to claim 5, wherein
    所述步骤1中的与衬底同型的半导体薄膜厚度为0.1～100μm；和/或， The semiconductor film of the same type as the substrate in the step 1 has a thickness of 0.1 to 100 μm; and/or
    所述离子注入的深度为0.1～3μm；和/或，The depth of the ion implantation is 0.1 to 3 μm; and/or,
    离子注入的图形为叉指结构、平行长条状、圆环形、方形台面或它们的组合图形；和/或，The pattern of ion implantation is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
    所述图形尺寸为0.1μm～10cm。The pattern size is from 0.1 μm to 10 cm.
  7. 如权利要求5或6所述的制作方法，其中，The manufacturing method according to claim 5 or 6, wherein
    采用所述高能离子注入法注入的半导体材料与半导体薄膜是反型的。The semiconductor material implanted by the high energy ion implantation is inverse to the semiconductor film.
  8. 如权利要求7所述的制作方法，其中，The manufacturing method according to claim 7, wherein
    所述高能离子注入法的注入深度为0.1～3μm；和/或，The implantation depth of the high energy ion implantation method is 0.1 to 3 μm; and/or
    注入的能量为1keV～500MeV；和/或，The injected energy is from 1 keV to 500 MeV; and/or,
    注入的温度为0～1000℃；和/或，The temperature of the injection is 0 to 1000 ° C; and / or,
    离子注入的剂量为1×1010～1×1016cm-2；和/或，The dose of ion implantation is 1 × 10 10 - 1 × 10 16 cm -2 ; and / or,
    所述离子为氮、磷n型杂质离子，或铝、硼p型杂质离子。The ions are nitrogen, phosphorus n-type impurity ions, or aluminum or boron p-type impurity ions.
  9. 一种如权利要求1所述的叠层电场调制高压MOSFET结构的制作方法，所述方法包括：A method of fabricating a stacked electric field modulated high voltage MOSFET structure according to claim 1, the method comprising:
    步骤1：在半导体衬底上外延一层同型的半导体薄膜，所述的半导体薄膜作为第一层电场调制结构的基础；Step 1: epitaxially depositing a layer of a similar semiconductor film on the semiconductor substrate, the semiconductor film being used as a basis for the first layer of the electric field modulation structure;
    步骤2：刻蚀所述半导体薄膜，形成数目大于1的深沟槽；Step 2: etching the semiconductor film to form a deep trench having a number greater than one;
    步骤3：用外延生长技术填充深沟槽，形成交叉循环的N/P结构；Step 3: filling the deep trenches by epitaxial growth techniques to form a cross-cycled N/P structure;
    步骤4：重复1、2和3步，形成叠层的电场调制结构；Step 4: repeat steps 1, 2 and 3 to form a laminated electric field modulation structure;
    步骤5：在所述叠层电场调制结构上，制作金属-氧化物-半导体(MOS)结构。Step 5: Fabricating a metal-oxide-semiconductor (MOS) structure on the laminated electric field modulation structure.
  10. 如权利要求9所述的制作方法，其中，The production method according to claim 9, wherein
    所述外延层同型的半导体薄膜厚度为0.1～100μm；和/或，The thickness of the semiconductor film of the epitaxial layer is 0.1-100 μm; and/or
    所述深沟槽正视图的形状为矩形或倒梯形；和/或，The shape of the deep trench front view is rectangular or inverted trapezoid; and/or,
    所述深沟槽的深度为0.1～50μm；和/或， The depth of the deep trench is 0.1 to 50 μm; and/or,
    所述刻蚀的深沟槽的图形为叉指结构、平行长条状、圆环形、方形台面或它们的组合图形；和/或，The etched deep trench pattern is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
    所述图形尺寸为0.1μm～10cm。The pattern size is from 0.1 μm to 10 cm.
  11. 如权利要求9或10所述的制作方法，其中，The manufacturing method according to claim 9 or 10, wherein
    采用填充法填充的半导体材料与半导体薄膜是反型的。The semiconductor material filled by the filling method is inverse to the semiconductor film.
  12. 一种如权利要求1所述的叠层电场调制高压MOSFET结构的制作方法，所述方法包括：A method of fabricating a stacked electric field modulated high voltage MOSFET structure according to claim 1, the method comprising:
    步骤1：在半导体衬底上外延一层同型的半导体薄膜，所述的半导体薄膜作为第一层电场调制结构的基础；Step 1: epitaxially depositing a layer of a similar semiconductor film on the semiconductor substrate, the semiconductor film being used as a basis for the first layer of the electric field modulation structure;
    步骤2：刻蚀所述半导体薄膜，形成数目大于1的深沟槽；Step 2: etching the semiconductor film to form a deep trench having a number greater than one;
    步骤3：采用高能离子注入法在所述沟槽侧壁或底部注入反型离子，形成交叉循环的N/P结构；Step 3: injecting anti-ion ions into the sidewall or bottom of the trench by high-energy ion implantation to form a cross-cycled N/P structure;
    步骤4：在所述的深沟槽中填充SiO2介质，形成N/P/SiO2交叉循环的结构；Step 4: filling the deep trench with SiO 2 medium to form a structure of N/P/SiO 2 cross-circulation;
    步骤5：重复步骤1、2、3和4，形成叠层的电场调制结构；Step 5: repeat steps 1, 2, 3 and 4 to form a laminated electric field modulation structure;
    步骤6：在所述叠层电场调制结构上，制作金属-氧化物-半导体(MOS)结构。Step 6: Fabricating a metal-oxide-semiconductor (MOS) structure on the laminated electric field modulation structure.
  13. 如权利要求12所述的制作方法，其中，The production method according to claim 12, wherein
    所述外延层同型的半导体薄膜厚度为0.1～100μm；和/或，The thickness of the semiconductor film of the epitaxial layer is 0.1-100 μm; and/or
    所述深沟槽正视图的形状为矩形或倒梯形；和/或，The shape of the deep trench front view is rectangular or inverted trapezoid; and/or,
    所述深沟槽的深度为0.1～50μm；和/或，The depth of the deep trench is 0.1 to 50 μm; and/or,
    所述刻蚀的深沟槽的图形为叉指结构、平行长条状、圆环形、方形台面或它们的组合图形；和/或，The etched deep trench pattern is an interdigitated structure, a parallel strip, a circular ring, a square mesa, or a combination thereof; and/or
    所述图形尺寸为0.1μm～10cm。The pattern size is from 0.1 μm to 10 cm.
  14. 如权利要求12或13所述的制作方法，其中，采用所述高能离子 注入法注入侧壁的半导体材料与半导体薄膜是反型的。The manufacturing method according to claim 12 or 13, wherein the high energy ion is used The semiconductor material injected into the sidewall by the implantation method is inverse to the semiconductor film.
  15. 如权利要求12所述的制作方法，其中，The production method according to claim 12, wherein
    正视图为矩形的所述深沟槽，高能离子注入的倾斜角度为0～90°；和/或，The front view is a rectangular deep trench, and the high energy ion implantation has an inclination angle of 0 to 90°; and/or
    所述高能离子注入法的注入深度为0.1～3μm；和/或，The implantation depth of the high energy ion implantation method is 0.1 to 3 μm; and/or
    注入的能量为1keV～500MeV；和/或，The injected energy is from 1 keV to 500 MeV; and/or,
    注入的温度为0～1000℃；和/或，The temperature of the injection is 0 to 1000 ° C; and / or,
    离子注入的剂量为1×1010～1×1016cm-2；和/或，The dose of ion implantation is 1 × 10 10 - 1 × 10 16 cm -2 ; and / or,
    所述离子为氮、磷n型杂质离子，或铝、硼p型杂质离子。 The ions are nitrogen, phosphorus n-type impurity ions, or aluminum or boron p-type impurity ions.
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* Cited by examiner, † Cited by third party
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CN107221561A (en) * 2017-06-29 2017-09-29 全球能源互联网研究院 A kind of lamination Electric Field Modulated high-voltage MOSFET structure and preparation method thereof
CN110212015A (en) * 2019-04-30 2019-09-06 上海功成半导体科技有限公司 Super junction device structure and preparation method thereof
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CN112993008A (en) * 2019-12-13 2021-06-18 南通尚阳通集成电路有限公司 Charge balance device and method of manufacturing the same
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275016A1 (en) * 2004-06-04 2005-12-15 International Rectifier Corp. Deep trench super switch device
CN102306659A (en) * 2011-09-08 2012-01-04 浙江大学 LDMOS (laterally double-diffused metal-oxide-semiconductor field effect transistor) device based on internal electric field modulation
CN106206742A (en) * 2016-09-12 2016-12-07 厦门元顺微电子技术有限公司 The high-voltage MOSFET in a kind of superjunction P district with Heterogeneous Permutation and manufacture method thereof
CN107221561A (en) * 2017-06-29 2017-09-29 全球能源互联网研究院 A kind of lamination Electric Field Modulated high-voltage MOSFET structure and preparation method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6803626B2 (en) * 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
CN103515242A (en) * 2012-06-29 2014-01-15 无锡维赛半导体有限公司 Power transistor and manufacturing method thereof
US9735237B2 (en) * 2015-06-26 2017-08-15 General Electric Company Active area designs for silicon carbide super-junction power devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275016A1 (en) * 2004-06-04 2005-12-15 International Rectifier Corp. Deep trench super switch device
CN102306659A (en) * 2011-09-08 2012-01-04 浙江大学 LDMOS (laterally double-diffused metal-oxide-semiconductor field effect transistor) device based on internal electric field modulation
CN106206742A (en) * 2016-09-12 2016-12-07 厦门元顺微电子技术有限公司 The high-voltage MOSFET in a kind of superjunction P district with Heterogeneous Permutation and manufacture method thereof
CN107221561A (en) * 2017-06-29 2017-09-29 全球能源互联网研究院 A kind of lamination Electric Field Modulated high-voltage MOSFET structure and preparation method thereof

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