WO2018233422A1 - 一种同时同频全双工系统及移动终端 - Google Patents

一种同时同频全双工系统及移动终端 Download PDF

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Publication number
WO2018233422A1
WO2018233422A1 PCT/CN2018/087643 CN2018087643W WO2018233422A1 WO 2018233422 A1 WO2018233422 A1 WO 2018233422A1 CN 2018087643 W CN2018087643 W CN 2018087643W WO 2018233422 A1 WO2018233422 A1 WO 2018233422A1
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Prior art keywords
processing circuit
signal
signal processing
transmitting
receiving
Prior art date
Application number
PCT/CN2018/087643
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English (en)
French (fr)
Inventor
王柏钢
Original Assignee
维沃移动通信有限公司
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Publication date
Application filed by 维沃移动通信有限公司 filed Critical 维沃移动通信有限公司
Priority to EP18819614.1A priority Critical patent/EP3644543B1/en
Priority to ES18819614T priority patent/ES2900059T3/es
Priority to US16/624,546 priority patent/US11316551B2/en
Publication of WO2018233422A1 publication Critical patent/WO2018233422A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/44—Transmit/receive switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/50—Circuits using different frequencies for the two directions of communication
    • H04B1/52—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
    • H04B1/525—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/54—Circuits using the same frequency for two directions of communication
    • H04B1/56—Circuits using the same frequency for two directions of communication with provision for simultaneous communication in two directions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1423—Two-way operation using the same type of signal, i.e. duplex for simultaneous baseband signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1461—Suppression of signals in the return path, i.e. bidirectional control circuits

Definitions

  • the present disclosure relates to the field of communications technologies, and in particular, to a simultaneous co-frequency full-duplex system and a mobile terminal.
  • 5G mobile communication systems need to support higher uplink and downlink rates, so they need more bandwidth and higher spectrum efficiency support.
  • the current 4G LTE (Long Term Evolution) communication system only supports TDD time division duplexing. (Time Division Duplexing, TDD) or Frequency Division Duplexing (FDD), the configuration is not flexible, and the spectrum utilization is low. Therefore, the same-frequency full-duplex technology is proposed as one of the key technologies of 5G.
  • the effect to be achieved is that the uplink and the downlink are on the same frequency, and communication is performed at the same time.
  • the transmitting antenna and the receiving antenna need to be separated, and the isolation of the antenna is ensured by spatial isolation, so that When the link is implemented, two filters in the same frequency band are needed, and two sets of antenna switches have complicated links and high cost.
  • the embodiments of the present disclosure provide a simultaneous co-frequency full-duplex system and a mobile terminal to solve the problem that the radio frequency link in the simultaneous co-frequency full-duplex system in the related art is complicated and high in cost.
  • a simultaneous co-frequency full-duplex system comprising: a baseband processing circuit, a transmitting end signal processing circuit, a receiving end signal processing circuit, and a signal transceiving circuit, wherein:
  • the first end of the baseband processing circuit is electrically connected to the first end of the signal processing circuit of the transmitting end; the second end of the signal processing circuit of the transmitting end is electrically connected to the first end of the signal transmitting and receiving circuit;
  • the second end of the baseband processing circuit is electrically connected to the first end of the signal processing circuit of the receiving end; the second end of the signal processing circuit of the receiving end is electrically connected to the second end of the signal transmitting and receiving circuit;
  • the signal transceiver circuit is configured to simultaneously send an uplink signal and receive a downlink signal, and isolate the uplink signal and the downlink signal.
  • a mobile terminal comprising: a simultaneous co-frequency full duplex system as described above.
  • the above technical solution adopts a signal transmitting and receiving circuit to perform uplink signal transmission and downlink signal reception, and isolates the uplink signal and the downlink signal to complete self-interference suppression, which reduces link complexity and reduces cost.
  • FIG. 1 is a schematic diagram showing a simultaneous co-frequency full-duplex system provided by an embodiment of the present disclosure
  • FIG. 2 is a second schematic diagram of a simultaneous co-frequency full-duplex system according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a co-frequency isolator provided by an embodiment of the present disclosure
  • FIG. 4 is a block diagram of a mobile terminal provided by an embodiment of the present disclosure.
  • a simultaneous co-frequency full-duplex system 100 is provided, as shown in FIG. 1, including: a baseband processing circuit 101, a transmitting end signal processing circuit 102, a receiving end signal processing circuit 103, and a signal.
  • Transceiver circuit 104 Transceiver circuit 104.
  • the transmitting end signal processing circuit 102 and the receiving end signal processing circuit 103 are both electrically connected to the baseband processing circuit 101, and the signal transmitting and receiving circuit 104 is electrically connected to the transmitting end signal processing circuit 102 and the receiving end signal processing circuit 103, respectively.
  • the first end of the baseband processing circuit 101 is electrically connected to the first end of the signal processing circuit 102 of the transmitting end
  • the second end of the signal processing circuit 102 of the transmitting end is electrically connected to the first end of the signal transmitting and receiving circuit 104.
  • the second end of the baseband processing circuit 101 is electrically coupled to the first end of the receive signal processing circuit 103
  • the second end of the receive signal processing circuit 103 is electrically coupled to the second end of the signal transceiving circuit 104.
  • the baseband processing circuit 101 encodes the uplink signal to be transmitted, or decodes the received downlink signal, and the like.
  • the transmitting end signal processing circuit 102 is configured to perform frequency conversion, modulation, and the like on the uplink signal output by the baseband processing circuit 101, and transmit the processed uplink signal to the signal transmitting and receiving circuit 104.
  • the signal transmitting and receiving circuit 104 is configured to transmit the uplink signal output by the signal processing circuit 102 of the transmitting end, receive the downlink signal sent by the network device such as the base station or the communication satellite, and send the received downlink signal to the signal processing circuit 103 of the receiving end.
  • the signal transceiver circuit 104 can isolate the uplink signal and the downlink signal to reduce interference of the uplink signal to the downlink signal.
  • the receiving end signal processing circuit 103 is configured to perform frequency conversion, demodulation, and the like on the downlink signal outputted by the signal transmitting and receiving circuit 104, and send the processed downlink signal to the baseband processing circuit 101, and decode the downlink signal by the baseband processing circuit 101. .
  • the signal transceiver circuit 104 can simultaneously transmit an uplink signal and receive a downlink signal, and isolate the uplink signal and the downlink signal. In this way, the receiving, transmitting and isolating of signals can be completed by one transceiver circuit, which reduces the link complexity of the simultaneous full-frequency full-duplex system 100 and reduces the cost.
  • the signal processing circuit 102 of the transmitting end is further electrically connected to the signal processing circuit 103 of the receiving end. Specifically, the signal processing of the third end and the receiving end of the signal processing circuit 102 of the transmitting end is performed. The third end of the circuit 103 is electrically connected.
  • the transmitting end signal processing circuit 102 processes the uplink signal received from the baseband processing circuit 101, the envelope information (such as the amplitude parameter and the phase parameter) of the uplink signal is also extracted, and the interference self-cancellation reference signal is formed and sent to the receiving end.
  • the signal processing circuit 103 when the uplink signal and the downlink signal are mixed together, enters the signal processing circuit 103 of the receiving end, can suppress the uplink signal by interfering with the self-cancelling reference signal, and reduce the interference of the uplink signal on the downlink signal.
  • the transmitting end processing circuit includes: a transmitting end digital signal processing circuit 1021 and a transmitting end analog signal processing circuit 1022.
  • the baseband processing circuit 101 is electrically connected to the transmitting end digital signal processing circuit 1021
  • the transmitting end digital signal processing circuit 1021 is electrically connected to the transmitting end analog signal processing circuit 1022
  • the transmitting end analog signal processing circuit 1022 is The signal transceiving circuit 104 is electrically connected.
  • the first end of the digital signal processing circuit 1021 of the transmitting end is electrically connected to the first end of the baseband processing circuit 101
  • the second end of the digital signal processing circuit 1021 of the transmitting end is electrically connected to the first end of the analog signal processing circuit 1022 of the transmitting end.
  • the second end of the transmit-end analog signal processing circuit 1022 is electrically coupled to the first end of the signal transceiving circuit 104.
  • the transmitting end digital signal processing circuit 1021 is configured to receive the uplink signal sent by the baseband processing circuit 101, and digitize the received uplink signal, and then send the signal to the transmitting end analog signal processing circuit 1022.
  • the transmitting end analog signal processing circuit 1022 is configured to up-convert and modulate the uplink signal received from the transmitting-end digital signal processing circuit 1021, and then transmit the signal to the signal transmitting and receiving circuit 104.
  • the baseband processing processing circuit provides a useful uplink signal to be transmitted
  • the transmitting end digital signal processing circuit 1021 receives the uplink signal sent by the baseband processing circuit 101, and digitizes the received uplink signal, and then sends the uplink signal.
  • the transmitting end analog signal processing circuit 1022 converts the uplink signal from the digital signal into an analog signal by the transmitting end analog signal processing circuit 1022, performs up-conversion and modulation, and sends the uplink signal to the signal transmitting and receiving circuit 104, and the signal is
  • the transceiver circuit 104 transmits the uplink signal to a network device such as a base station or a communication satellite.
  • the receiving end signal processing circuit 103 includes a receiving end digital signal processing circuit 1031 and a receiving end analog signal processing circuit 1032.
  • the baseband processing circuit 101 is electrically connected to the receiving end digital signal processing circuit 1031
  • the receiving end digital signal processing circuit 1031 is electrically connected to the receiving end analog signal processing circuit 1032
  • the receiving end analog signal processing circuit 1032 is The signal transceiving circuit 104 is electrically connected.
  • the first end of the receiving end digital signal processing circuit 1031 is electrically connected to the first end of the baseband processing circuit 101
  • the second end of the receiving end digital signal processing circuit 1031 and the first end of the receiving end analog signal processing circuit 1032 are electrically connected.
  • the second end of the receiving end analog signal processing circuit 1032 is electrically coupled to the second end of the signal transceiving circuit 104.
  • the receiving end analog signal processing circuit 1032 is configured to receive the downlink signal sent by the signal transmitting and receiving circuit 104, downconvert and demodulate the downlink signal, and then send the signal to the receiving end digital signal processing circuit 1031.
  • the receiving end digital signal processing circuit 1031 is for digitizing the downlink signal received from the receiving end analog signal processing circuit 1032, and then transmitting it to the baseband processing circuit 101.
  • the transceiver circuit receives a useful downlink signal sent by a network device such as a base station or a communication satellite, and the receiving end analog signal processing circuit 1032 receives the downlink signal output by the signal transceiver circuit 104, and performs down-conversion and demodulation on the downlink signal.
  • the downlink signal is transmitted to the receiving terminal digital signal processing circuit 1031, and the downlink signal is digitized by the receiving terminal digital signal processing circuit 1031, and then the downlink signal is transmitted to the baseband processing circuit 101.
  • the transmitting end digital signal processing circuit 1021 is also electrically connected to the receiving end digital signal processing circuit 1031
  • the transmitting end analog signal processing circuit 1022 is also electrically connected to the receiving end analog signal processing circuit 1032.
  • the third end of the digital signal processing circuit 1021 of the transmitting end is electrically connected to the third end of the digital signal processing circuit 1031 of the receiving end
  • the third end of the analog signal processing circuit 1022 of the transmitting end and the analog signal processing circuit 1032 of the receiving end are first. Three-terminal electrical connection.
  • the transmitting end digital signal processing circuit 1021 is further configured to: when digitizing the uplink signal, extract a digital interference cancellation reference signal of the uplink signal, and send the digital interference self-cancellation reference signal to the receiving end digital signal processing circuit 1031 .
  • the transmitting end analog signal processing circuit 1022 is further configured to: when up-converting and modulating the uplink signal, extract an analog interference self-cancellation reference signal of the uplink signal, and send the analog interference self-cancellation reference signal to the receiving end analog signal processing circuit 1032.
  • the digital interference self-cancellation reference signal is: a reference signal formed according to envelope information (such as an amplitude parameter and a phase parameter) of the uplink signal extracted by the digital signal processing circuit 1021 of the transmitting end.
  • the analog interference self-cancellation reference signal is a reference signal formed according to the envelope information (such as the amplitude parameter and the phase parameter) of the uplink signal extracted by the transmitting end analog signal processing circuit 1022.
  • the signal transceiver circuit 104 when receiving the useful downlink signal sent by the network device such as the base station or the communication satellite, the signal transceiver circuit 104 also receives a part of the uplink signal leaked from the transmission path, and mixes with the useful downlink signal to form self-interference.
  • the digital signal processing circuit 1021 of the transmitting end extracts the envelope information of the uplink signal as the digital interference self-cancellation reference signal, and the transmitting end analog signal processing circuit 1022 processes the uplink signal while processing the uplink signal.
  • the envelope information of the uplink signal is extracted as an analog interference self-cancellation reference signal, so that when the downlink signal mixed with the uplink signal passes through the analog signal processing circuit 1032 of the receiving end, under the action of the analog interference self-cancellation reference signal A part of the uplink interference signal is reduced.
  • the digital signal processing circuit 1031 is received by the receiving end, the uplink interference signal is further reduced by the digital interference self-cancelling reference signal to achieve self-interference suppression.
  • the signal transceiving circuit 104 includes an intra-frequency isolator 1041, a transceiving filter 1042, an antenna switch 1043, and a transceiving antenna 1044.
  • the transmitting end analog signal processing circuit 1022 and the receiving end digital signal processing circuit 1031 are both electrically connected to the same frequency isolator 1041, and the same frequency isolator 1041 is electrically connected to the transceiver filter 1042.
  • 1042 is electrically connected to the antenna switch 1043, and the antenna switch 1043 is electrically connected to the transmitting and receiving antenna 1044.
  • the first end of the same-frequency isolator 1041 is electrically connected to the second end of the transmitting-end analog signal processing circuit 1022, and the second end of the same-frequency isolator 1041 is electrically connected to the second end of the receiving-end digital signal processing circuit 1031.
  • the third end of the same frequency isolating device 1041 is electrically connected to the first end of the transceiver filter 1042, the second end of the transceiver filter 1042 is electrically connected to the first end of the antenna switch 1043, and the second end of the antenna switch 1043 is connected to and received.
  • the antenna 1044 is electrically connected.
  • the same-frequency isolator 1041 is further configured to send the uplink signal to the transceiver filter 1042; the transceiver filter 1042 is also used to The uplink signal sent by the same-frequency isolator 1041 is filtered; the antenna switch 1043 is configured to send the uplink signal filtered by the transceiver filter 1042 to the transceiver antenna 1044, and the transceiver antenna 1044 is configured to transmit the uplink signal sent by the antenna switch 1043.
  • the transceiver antenna 1044 is further configured to send the received downlink signal to the antenna switch 1043.
  • the antenna switch 1043 is further configured to send the downlink signal sent by the transceiver antenna 1044 to the transceiver filter.
  • the transceiver 1042 is further configured to filter the downlink signal sent by the antenna switch 1043, and send the filtered downlink signal to the same frequency isolator 1041.
  • the same frequency isolator 1041 is also used for the uplink signal and the downlink signal. Transceiver isolation.
  • the transmitting end analog signal processing circuit 1022 sends the processed uplink signal to the same frequency isolator 1041.
  • the same frequency isolator 1041 After receiving the uplink signal, the same frequency isolator 1041 sends the uplink signal to the transceiver filter 1042 for filtering, and passes.
  • the antenna switch 1043 sends the filtered uplink signal to the transceiver antenna 1044 for transmission.
  • the transceiver antenna 1044 receives the downlink signal, and the downlink signal is sent to the transceiver filter 1042 through the antenna switch 1043 for filtering, and the filtered downlink signal is sent.
  • the same-frequency isolator 1041 isolates and transmits the uplink signal and the downlink signal to suppress interference of the uplink signal to the downlink signal.
  • the intra-frequency isolator 1041 includes a transmit pin 10411, a receive pin 10412, an antenna pin 10413, and a load ground pin 10414.
  • the transmitting pin 10411 is electrically connected to the transmitting end analog signal processing circuit 1022 (specifically, the transmitting pin 10411 is electrically connected to the second end of the transmitting end analog signal processing circuit 1022), and the transmitting pin 10411 and the antenna pin are respectively 10413 is connected to a transmission path that forms an uplink signal.
  • the receiving pin 10412 is electrically connected to the receiving end analog signal processing circuit 1032 (specifically, the receiving pin 10412 is electrically connected to the second end of the receiving end analog signal processing circuit 1032), and the receiving pin 10412 is connected to the antenna pin 10413. A receiving path that forms a downlink signal.
  • the antenna pin 10413 is electrically coupled to the transceiver filter 1042.
  • the load ground pin 10414 is connected to the outer casing of the same frequency isolator 1041, or the load ground pin 10414 is electrically connected to the ground terminal in the internal line of the same frequency isolator 1041.
  • the same frequency isolator 1041 further includes: a transmit path and a receive path.
  • the transmit path connects the transmit pin 10411 and the antenna pin 10413
  • the receive path connects the receive pin 10412 and the antenna pin 10413.
  • both the transmit path and the receive path are unidirectional paths, and the transmit path only allows signals to be transmitted from the transmit pin 10411 to the antenna pin 10413, but not to the reverse; the receive path only allows the signal to be received by the antenna pin 10413 The transmission of pin 10412 is not reversed.
  • the transmitting path and the receiving path are implemented by the transmission line inside the same-frequency isolator 1041, that is, the transmitting path and the receiving path are both formed by a transmission line, and the load power loss can be reduced due to the small load of the transmission line. , reduce insertion loss.
  • the space between the transmission pin 10411 and the receiving pin 10412 and the space between the transmission path and the receiving path are both greater than or equal to three times the width of the line.
  • a spatial isolation greater than 40 dB is provided to ensure isolation of the upstream and downstream signals by the same frequency isolator 1041.
  • the spatial isolation is not less than the amplitude suppression of the limiter 10415.
  • a limiter 10415 is further connected to the receiving path.
  • the main function of the limiter 10415 is to limit the amplitude of the input signal and output a signal of a fixed amplitude, so that when the signal strength of the uplink signal (such as 26dBm) and the signal strength of the downlink signal (such as -70dBm) enter the reception simultaneously
  • the limiter 10415 of the path is used, the uplink signal is limited to a fixed amplitude, thereby reducing the interference of the uplink signal to the downlink signal, and since the amplitude of the uplink signal entering the receiving path is reduced, the nonlinear distortion of the back-end circuit due to saturation is generated. It will be smaller, which also ensures the self-interference cancellation performance of the back-end circuit.
  • the output power of the limiter 10415 is designed to be -10 dBm.
  • the output of the uplink interference signal is -10 dBm after passing through the limiter 10415, which is equivalent to an increase. 36dB self-interference suppression.
  • the positions of the transceiver filter 1042 and the on-channel isolator 1041 are interchangeable, depending on the requirements of the specific link indicator. For example, when the filter is on the left side, the out-of-band spurious signal generated by the pre-stage circuit can be first suppressed to ensure the performance of the same-frequency isolator 1041. If the out-of-band spurious signal generated by the pre-stage circuit is low, the same frequency The isolator 1041 can be placed before the filter.
  • the simultaneous co-frequency full-duplex system 100 provided by the embodiment of the present disclosure can realize simultaneous co-frequency full-duplex transmission on the basis of one antenna, one antenna switch 1043 and one transceiver filter 1042, and reduces the frequency.
  • the link complexity reduces the cost, and under the action of the limiter 10415 in the same frequency isolator 1041, a better co-channel self-interference suppression index can be achieved, and the self-interference cancellation level of the system is improved.
  • a mobile terminal comprising: a simultaneous co-frequency full duplex system 100 as described above.
  • the simultaneous co-frequency full-duplex system 100 in the mobile terminal uses a signal transmitting and receiving circuit 104 to perform uplink signal transmission and downlink signal reception, and isolates the uplink signal and the downlink signal to perform self-interference. Suppression reduces the complexity of the same-frequency full-duplex system 100 link and reduces the cost.
  • a mobile terminal 400 is provided.
  • the mobile terminal 400 can be a mobile phone, a tablet computer, a personal digital assistant (PDA), or a car computer.
  • PDA personal digital assistant
  • the mobile terminal 400 includes a radio frequency (RF) circuit 401, a memory 402, an input unit 403, a display unit 404, a processor 406, an audio circuit 407, a WiFi (Wireless Fidelity) module 408, and a power supply 409. .
  • RF radio frequency
  • the input unit 403 can be configured to receive numeric or character information input by the user, and to generate signal inputs related to user settings and function control of the mobile terminal 400.
  • the input unit 403 may include a touch panel 4031.
  • the touch panel 4031 also referred to as a touch screen, can collect touch operations on or near the user (such as the operation of the user using any suitable object or accessory such as a finger or a stylus on the touch panel 4031), and according to the preset The programmed program drives the corresponding connection device.
  • the touch panel 4031 may include two parts of a touch detection device and a touch controller.
  • the touch detection device detects a touch orientation of the user, and detects a signal brought by the touch operation, and transmits a signal to the touch controller; the touch controller receives the touch information from the touch detection device and converts it into contact coordinates. And then sent to the processor 406, and can receive the command sent by the processor 406 and execute it.
  • the touch panel 4031 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic waves.
  • the input unit 403 may further include other input devices 4032.
  • the other input devices 4032 may include, but are not limited to, a physical keyboard, function keys (such as a volume control button, a switch button, etc.), a trackball, a mouse, a joystick, and the like. One or more of them.
  • the display unit 404 can be used to display information input by the user or information provided to the user and various menu interfaces of the mobile terminal 400.
  • the display unit 404 can include a display panel 4041.
  • the display panel 4041 can be configured in the form of an LCD or an Organic Light-Emitting Diode (OLED).
  • the touch panel 4031 can cover the display panel 4041 to form a touch display screen, and when the touch display screen detects a touch operation on or near it, it is transmitted to the processor 406 to determine the type of the touch event, and then the processor 406 provides a corresponding visual output on the touch display depending on the type of touch event.
  • the touch display includes an application interface display area and a common control display area.
  • the arrangement manner of the application interface display area and the display area of the common control is not limited, and the arrangement manner of the two display areas can be distinguished by up-and-down arrangement, left-right arrangement, and the like.
  • the application interface display area can be used to display the interface of the application. Each interface can contain interface elements such as at least one application's icon and/or widget desktop control.
  • the application interface display area can also be an empty interface that does not contain any content.
  • the common control display area is used to display controls with high usage, such as setting buttons, interface numbers, scroll bars, phone book icons, and the like.
  • the processor 406 is a control center of the mobile terminal 400 that connects various portions of the entire handset with various interfaces and lines, by running or executing software programs and/or modules stored in the first memory 4021, and invoking storage
  • the data in the second memory 4022 performs various functions and processing data of the mobile terminal 400, thereby performing overall monitoring of the mobile terminal 400.
  • processor 406 can include one or more processing units.
  • software programs and/or modules within the first memory 4021 and/or data within the second memory 4022 are stored by calling.
  • the mobile terminal further includes: a simultaneous intra-frequency full-duplex system 100.
  • the simultaneous co-frequency full-duplex system 100 includes a baseband processing circuit 101, a transmitting end signal processing circuit 102, a receiving end signal processing circuit 103, and a signal transceiving circuit 104, wherein:
  • the first end of the baseband processing circuit 101 is electrically connected to the first end of the signal processing circuit 102 of the transmitting end; the second end of the signal processing circuit 102 of the transmitting end is electrically connected to the first end of the signal transmitting and receiving circuit 104;
  • the second end of the baseband processing circuit 101 is electrically connected to the first end of the signal processing circuit 103 of the receiving end; the second end of the signal processing circuit 103 of the receiving end is electrically connected to the second end of the signal transmitting and receiving circuit 104;
  • the signal transceiver circuit 104 is configured to simultaneously transmit an uplink signal and receive a downlink signal, and isolate the uplink signal and the downlink signal.
  • the third end of the transmitting end signal processing circuit 102 is electrically connected to the third end of the receiving end signal processing circuit 103.
  • the signal processing circuit 102 of the transmitting end is further configured to: when receiving the uplink signal sent by the baseband processing circuit 101, extract an interference self-cancellation reference signal of the uplink signal, and send the interference self-cancellation reference signal to the signal processing circuit at the receiving end. 103.
  • the transmitting end signal processing circuit 102 includes: a transmitting end digital signal processing circuit 1021 and a transmitting end analog signal processing circuit 1022, wherein:
  • the first end of the digital signal processing circuit 1021 of the transmitting end is electrically connected to the first end of the baseband processing circuit 101, and the second end of the digital signal processing circuit 1021 of the transmitting end is electrically connected to the first end of the analog signal processing circuit 1022 of the transmitting end, and is transmitted.
  • the second end of the analog signal processing circuit 1022 is electrically coupled to the first end of the signal transceiving circuit 104.
  • the transmitting end digital signal processing circuit 1021 is configured to receive the uplink signal sent by the baseband processing circuit 101, and digitize the received uplink signal, and then send the signal to the transmitting end analog signal processing circuit 1022.
  • the transmitting end analog signal processing circuit 1022 is configured to up-convert and modulate the uplink signal received from the transmitting-end digital signal processing circuit 1021, and then transmit the signal to the signal transmitting and receiving circuit 104.
  • the receiving end signal processing circuit 103 includes: a receiving end digital signal processing circuit 1031 and a receiving end analog signal processing circuit 1032, wherein:
  • the first end of the receiving end digital signal processing circuit 1031 is electrically connected to the first end of the baseband processing circuit 101, and the second end of the receiving end digital signal processing circuit 1031 is electrically connected to the first end of the receiving end analog signal processing circuit 1032, and receives The second end of the analog signal processing circuit 1032 is electrically coupled to the second end of the signal transceiving circuit 104.
  • the receiving end analog signal processing circuit 1032 is configured to receive the downlink signal sent by the signal transmitting and receiving circuit 104, downconvert and demodulate the downlink signal, and then send the signal to the receiving end digital signal processing circuit 1031.
  • the receiving end digital signal processing circuit 1031 is for digitizing the downlink signal received from the receiving end analog signal processing circuit 1032, and then transmitting it to the baseband processing circuit 101.
  • the third end of the transmitting end digital signal processing circuit 1021 is electrically connected to the third end of the receiving end digital signal processing circuit 1031.
  • the transmitting end digital signal processing circuit 1021 is further configured to: when digitizing the uplink signal, extract a digital interference self-cancellation reference signal of the uplink signal, and send the digital interference self-cancellation reference signal to the receiving end digital signal processing circuit 1031.
  • the third end of the transmitting end analog signal processing circuit 1022 is electrically connected to the third end of the receiving end analog signal processing circuit 1032.
  • the transmitting end analog signal processing circuit 1022 is further configured to: when up-converting and modulating the uplink signal, extract an analog interference self-cancellation reference signal of the uplink signal, and send the analog interference self-cancellation reference signal to the receiving end analog signal processing circuit 1032.
  • the signal transceiving circuit 104 includes: an isochronous isolator 1041, a transceiving filter 1042, an antenna switch 1043, and a transceiving antenna 1044, wherein:
  • the first end of the same-frequency isolator 1041 is electrically connected to the second end of the transmitting-end analog signal processing circuit 1022; the second end of the same-frequency isolator 1041 is electrically connected to the second end of the receiving-end digital signal processing circuit 1031; The third end of the isolator 1041 is electrically connected to the first end of the transceiver filter 1042; the second end of the transceiver filter 1042 is electrically connected to the first end of the antenna switch 1043, and the second end of the antenna switch 1043 is electrically connected to the transceiver antenna 1044. connection.
  • the same-frequency isolator 1041 is further configured to send the uplink signal to the transceiver filter 1042, where the transceiver filter 1042 is also used.
  • the uplink signal sent by the same-frequency isolator 1041 is filtered, and the antenna switch 1043 is configured to send the uplink signal filtered by the transceiver filter 1042 to the transceiver antenna 1044, and the transceiver antenna 1044 is configured to transmit the uplink signal sent by the antenna switch 1043.
  • the transceiver antenna 1044 is further configured to send the received downlink signal to the antenna switch 1043.
  • the antenna switch 1043 is further configured to send the downlink signal sent by the transceiver antenna 1044 to the transceiver filter 1042, and send and receive the downlink signal.
  • the filter 1042 is further configured to filter the downlink signal sent by the antenna switch 1043, and send the filtered downlink signal to the same-frequency isolator 1041.
  • the same-frequency isolator 1041 is further configured to transmit and receive the uplink signal and the downlink signal.
  • the intra-frequency isolator 1041 includes a transmit pin 10411, a receive pin 10412, an antenna pin 10413, and a load ground pin 10414.
  • the transmit pin 10411 is electrically coupled to the second end of the transmit analog signal processing circuit 1022, and the transmit pin 10411 is coupled to the antenna pin 10413 to form a transmit path for the upstream signal.
  • the receiving pin 10412 is electrically connected to the second end of the receiving end analog signal processing circuit 1032, the receiving pin 10412 is connected to the antenna pin 10413 to form a receiving path of the downlink signal, and the antenna pin 10413 is electrically connected to the transceiver filter 1042.
  • the load ground pin 10414 is connected to the outer casing of the same frequency isolator 1041, or the load ground pin 10414 is electrically connected to the ground terminal in the internal line of the same frequency isolator 1041.
  • a limiter 10415 is connected to the receiving path.
  • the transmission path is formed by a transmission line.
  • the spacing between the routing pins 10411 and the receiving pins 10412 and the spacing between the transmitting channels and the receiving paths are greater than or equal to three times the width of the traces.
  • the mobile terminal 400 uses a signal transmitting and receiving circuit 104 to perform uplink signal transmission and downlink signal reception, and isolates the uplink signal and the downlink signal to complete self-interference suppression and reduce link complexity. Degree, reducing costs.

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Abstract

提供了一种同时同频全双工系统及移动终端。该同时同频全双工系统包括：基带处理电路、发射端信号处理电路、接收端信号处理电路和信号收发电路。其中，基带处理电路的第一端与发射端信号处理电路的第一端电连接；发射端信号处理电路的第二端与信号收发电路的第一端电连接；基带处理电路的第二端与接收端信号处理电路的第一端电连接；接收端信号处理电路的第二端与信号收发电路的第二端电连接；其中，信号收发电路用于同时发送上行信号和接收下行信号，并对上行信号和下行信号进行隔离。

Description

一种同时同频全双工系统及移动终端
相关申请的交叉引用
本申请主张在2017年6月22日在中国提交的中国专利申请No.201710480593.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及通信技术领域，尤其涉及一种同时同频全双工系统及移动终端。
背景技术
5G移动通信系统，需要支持更高的上下行速率，因此需要更大的带宽以及更高的频谱效率支持，而目前的4G LTE(Long Term Evolution，长期演进)通信系统，只支持TDD时分双工(Time Division Duplexing，TDD)或者频分双工(Frequency Division Duplexing，FDD)方式，配置不灵活，频谱利用率低，因此，同时同频全双工技术作为5G的关键技术之一被提了出来，其要达到的效果是：上下行在同一频率上，同时的进行通信。相关技术中的同时同频全双工系统，为了实现自干扰抑制(即发射信号对接收信号的干扰)，发射天线和接收天线需要分开，通过空间上的隔离来保证天线隔离度，这样在具体链路实现时，就需要两个同频段的滤波器，两套天线开关，链路复杂，成本高。
发明内容
本公开实施例提供了一种同时同频全双工系统及移动终端，以解决相关技术中的同时同频全双工系统中的射频链路复杂、成本高的问题。
第一方面，提供了一种同时同频全双工系统，包括：基带处理电路、发射端信号处理电路、接收端信号处理电路和信号收发电路，其中：
所述基带处理电路的第一端与所述发射端信号处理电路的第一端电连接；所述发射端信号处理电路的第二端与所述信号收发电路的第一端电连接；
所述基带处理电路的第二端与所述接收端信号处理电路的第一端电连接；所述接收端信号处理电路的第二端与所述信号收发电路的第二端电连接；
其中，所述信号收发电路用于同时发送上行信号和接收下行信号，并对所述上行信号和下行信号进行隔离。
第二方面，提供了一种移动终端，包括：如上所述的同时同频全双工系统。
上述技术方案，采用一路信号收发电路，进行上行信号的发送和下行信号的接收，并对上行信号和下行信号进行隔离，完成自干扰抑制，降低了链路复杂度，减少了成本。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示本公开实施例提供的同时同频全双工系统的示意图之一；
图2表示本公开实施例提供的同时同频全双工系统的示意图之二；
图3表示本公开实施例提供的同频隔离器的结构示意图；
图4表示本公开实施例提供的移动终端的框图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
依据本公开实施例的一个方面，提供了一种同时同频全双工系统100，如图1所示，包括：基带处理电路101、发射端信号处理电路102、接收端信号处理电路103以及信号收发电路104。
在本公开实施例中，发射端信号处理电路102和接收端信号处理电路103 均与基带处理电路101电连接，信号收发电路104分别与发射端信号处理电路102和接收端信号处理电路103电连接。具体地，基带处理电路101的第一端与发射端信号处理电路102的第一端电连接，发射端信号处理电路102的第二端与信号收发电路104的第一端电连接。基带处理电路101的第二端与接收端信号处理电路103的第一端电连接，接收端信号处理电路103的第二端与信号收发电路104的第二端电连接。
可选地，基带处理电路101用于对待发射的上行信号进行编码，或对接收到的下行信号进行解码等。
发射端信号处理电路102用于对由基带处理电路101输出的上行信号进行变频及调制等，并将处理后的上行信号发送至信号收发电路104。
信号收发电路104用于将发射端信号处理电路102输出的上行信号发射出去，同时接收由基站、通讯卫星等网络设备发送的下行信号，并将接收到的下行信号发送至接收端信号处理电路103。可选地，信号收发电路104能够隔离上行信号和下行信号，以降低上行信号对下行信号的干扰。
接收端信号处理电路103用于对信号收发电路104输出的下行信号进行变频及解调等，并将处理后的下行信号发送至基带处理电路101，由基带处理电路101对该下行信号进行解码等。
本公开实施例中，信号收发电路104能够同时发送上行信号和接收下行信号，并对上行信号和下行信号进行隔离。这样，通过一路收发电路即可完成信号的接收、发射以及隔离，降低了同时同频全双工系统100的链路复杂度，减少了成本。
进一步地，如图1所示，本公开实施例中，发射端信号处理电路102还与接收端信号处理电路103电连接，具体地，发射端信号处理电路102的第三端与接收端信号处理电路103的第三端电连接。在发射端信号处理电路102处理从基带处理电路101接收到的上行信号时，还会提取该上行信号的包络信息(如幅度参数和相位参数)，形成干扰自消参考信号，发送至接收端信号处理电路103，这样，当该上行信号与下行信号混合在一起，进入接收端信号处理电路103时，可通过干扰自消参考信号，抑制上行信号，减少上行信号对下行信号的干扰。
具体地，发射端处理电路包括：发射端数字信号处理电路1021和发射端模拟信号处理电路1022。
如图2所示，依次地，基带处理电路101与发射端数字信号处理电路1021电连接，发射端数字信号处理电路1021与发射端模拟信号处理电路1022电连接，发射端模拟信号处理电路1022与信号收发电路104电连接。具体地，发射端数字信号处理电路1021的第一端与基带处理电路101的第一端电连接，发射端数字信号处理电路1021的第二端与发射端模拟信号处理电路1022的第一端电连接，发射端模拟信号处理电路1022的第二端与信号收发电路104的第一端电连接。
可选地，发射端数字信号处理电路1021用于接收基带处理电路101发送的上行信号，并将接收到的上行信号进行数字化处理后，发送至发射端模拟信号处理电路1022。发射端模拟信号处理电路1022用于将从发射端数字信号处理电路1021接收到的上行信号进行上变频及调制后，发送至信号收发电路104。
可选地，基带处理处理电路提供要发射的有用上行信号，发射端数字信号处理电路1021接收基带处理电路101发送的上行信号，并将接收到的上行信号进行数字化处理后，将该上行信号发送至发射端模拟信号处理电路1022，由发射端模拟信号处理电路1022将该上行信号由数字信号转换为模拟信号，进行上变频及调制后，将该上行信号发送至信号收发电路104，并由信号收发电路104将该上行信号发送至基站、通讯卫星等网络设备。
具体地，接收端信号处理电路103包括：接收端数字信号处理电路1031和接收端模拟信号处理电路1032。
如图2所示，依次地，基带处理电路101与接收端数字信号处理电路1031电连接，接收端数字信号处理电路1031与接收端模拟信号处理电路1032电连接，接收端模拟信号处理电路1032与信号收发电路104电连接。具体地，接收端数字信号处理电路1031的第一端与基带处理电路101的第一端电连接，接收端数字信号处理电路1031的第二端与接收端模拟信号处理电路1032的第一端电连接，接收端模拟信号处理电路1032的第二端与信号收发电路104的第二端电连接。
可选地，接收端模拟信号处理电路1032用于接收信号收发电路104发送的下行信号，对下行信号进行下变频及解调后，发送至接收端数字信号处理电路1031。接收端数字信号处理电路1031用于将从接收端模拟信号处理电路1032接收到的下行信号进行数字化处理后，发送至基带处理电路101。
可选地，收发电路接收基站、通讯卫星等网络设备发送的有用下行信号，接收端模拟信号处理电路1032接收信号收发电路104输出的下行信号，并对该下行信号进行下变频及解调后，将该下行信号发送至接收端数字信号处理电路1031，由接收端数字信号处理电路1031对该下行信号进行数字化处理后，将该下行信号发送至基带处理电路101。
进一步地，如图2所示，发射端数字信号处理电路1021还与接收端数字信号处理电路1031电连接，发射端模拟信号处理电路1022还与接收端模拟信号处理电路1032电连接。具体地，发射端数字信号处理电路1021的第三端与接收端数字信号处理电路1031的第三端电连接，发射端模拟信号处理电路1022的第三端与接收端模拟信号处理电路1032的第三端电连接。
可选地，发射端数字信号处理电路1021还用于在对上行信号进行数字化处理时，提取上行信号的数字干扰消除参考信号，将该数字干扰自消参考信号发送至接收端数字信号处理电路1031。发射端模拟信号处理电路1022还用于在对上行信号进行上变频及调制时，提取上行信号的模拟干扰自消参考信号，将该模拟干扰自消参考信号发送至接收端模拟信号处理电路1032。
可选地，数字干扰自消参考信号为：根据发射端数字信号处理电路1021提取出的上行信号的包络信息(如幅度参数和相位参数)而形成的参考信号。模拟干扰自消参考信号为：根据发射端模拟信号处理电路1022提取出的上行信号的包络信息(如幅度参数和相位参数)而形成的参考信号。
具体地，信号收发电路104在接收基站、通讯卫星等网络设备发送的有用下行信号时，也同时会接收发射通路泄露过来的一部分上行信号，与有用的下行信号混合在一起，形成自干扰。为了抑制该上行信号的干扰，发射端数字信号处理电路1021在处理上行信号的同时，提取该上行信号的包络信息，作为数字干扰自消参考信号，发射端模拟信号处理电路1022在处理上行信号的同时，提取该上行信号的包络信息，作为模拟干扰自消参考信号，这 样，当混有上行信号的下行信号经过接收端模拟信号处理电路1032时，在模拟干扰自消参考信号的作用下，会消减一部分上行干扰信号，在经过接收端数字信号处理电路1031时，在数字干扰自消参考信号的作用下，会进一步地消减上行干扰信号，以实现自干扰抑制。
进一步地，信号收发电路104包括：同频隔离器1041、收发滤波器1042、天线开关1043和收发天线1044。
如图2所示，依次地，发射端模拟信号处理电路1022和接收端数字信号处理电路1031均与同频隔离器1041电连接，同频隔离器1041与收发滤波器1042电连接，收发滤波器1042与天线开关1043电连接，天线开关1043与收发天线1044电连接。具体地，同频隔离器1041的第一端与发射端模拟信号处理电路1022的第二端电连接，同频隔离器1041的第二端与接收端数字信号处理电路1031的第二端电连接，同频隔离器1041的第三端与收发滤波器1042的第一端电连接，收发滤波器1042的第二端与天线开关1043的第一端电连接，天线开关1043的第二端与收发天线1044电连接。
可选地，在同频隔离器1041接收到发射端模拟信号处理电路1022发送的上行信号后，同频隔离器1041还用于将上行信号发送至收发滤波器1042；收发滤波器1042还用于对同频隔离器1041发送的上行信号进行滤波；天线开关1043用于将收发滤波器1042滤波之后的上行信号发送至收发天线1044，收发天线1044用于将天线开关1043发送的上行信号发送出去。
可选地，收发天线1044在接收到下行信号后，收发天线1044还用于将接收到的下行信号发送至天线开关1043；天线开关1043还用于将收发天线1044发送的下行信号发送至收发滤波器1042；收发滤波器1042还用于对天线开关1043发送的下行信号进行滤波，并将滤波之后的下行信号发送至同频隔离器1041；同频隔离器1041还用于对上行信号和下行信号进行收发隔离。
也就是，发射端模拟信号处理电路1022将处理后的上行信号发送至同频隔离器1041，同频隔离器1041在接收到上行信号后，将上行信号发送给收发滤波器1042进行滤波，并通过天线开关1043将滤波之后的上行信号，发送给收发天线1044发送出去；同时收发天线1044接收下行信号，通过天线开关1043将下行信号发送给收发滤波器1042进行滤波，并将滤波之后的下 行信号发送至同频隔离器1041，由同频隔离器1041对上行信号和下行信号进行收发隔离，抑制上行信号对下行信号的干扰。
具体地，如图3所示，同频隔离器1041包括：发送引脚10411、接收引脚10412、天线引脚10413和负载接地引脚10414。
可选地，发送引脚10411与发射端模拟信号处理电路1022电连接(具体地，发送引脚10411与发射端模拟信号处理电路1022的第二端电连接)，发送引脚10411与天线引脚10413连接形成上行信号的发射通路。接收引脚10412与接收端模拟信号处理电路1032电连接(具体地，接收引脚10412与所述接收端模拟信号处理电路1032的第二端电连接)，接收引脚10412与天线引脚10413连接形成下行信号的接收通路。天线引脚10413与收发滤波器1042电连接。负载接地引脚10414与同频隔离器1041的外壳连接，或负载接地引脚10414与同频隔离器1041的内部线路中的地端电连接。
本公开实施例中，同频隔离器1041是一种新型的四端口器件，发送引脚10411(即图中的TX引脚)的功能为上行信号的输入；接收引脚10412(即图中的RX引脚)的功能为下行信号的输出；天线引脚10413(即图中的ANT引脚)的功能为上行信号的输出及下行信号的输入；负载接地引脚10414(GND)的功能是为同频隔离器1041提供参考地。
除了上述四个引脚，该同频隔离器1041还包括：发射通路和接收通路。发射通路连接发送引脚10411和天线引脚10413，接收通路连接接收引脚10412和天线引脚10413。可选地，发射通路和接收通路均为单向通路，发射通路只允许信号由发送引脚10411到天线引脚10413的传输，而不能反向；接收通路只允许信号由天线引脚10413到接收引脚10412的传输，而不能反向。
可选地，发射通路和接收通路在同频隔离器1041内部是通过传输线实现的，即发射通路和接收通路均是由一传输线形成的，由于传输线的负载小，因此这样能够降低负载功率的损耗，减少插入损耗。
进一步地，本公开实施例中，发送引脚10411与接收引脚10412之间的走线空间间距和发射通路与接收通路之间的走线空间间距均大于或等于走线宽度的3倍，以提供大于40dB的空间隔离度，保证同频隔离器1041对上行 信号和下行信号的隔离。可选地，该空间隔离度不小于限幅器10415的幅度抑制。
进一步地，如图3所示，本公开实施例中，接收通路上还连接有一限幅器10415。该限幅器10415的主要功能是：限制输入信号的幅度，输出一个固定幅度的信号，这样当信号强度大的上行信号(比如26dBm)和信号强度小的下行信号(比如-70dBm)同时进入接收通路的限幅器10415时，上行信号会被限制到固定的幅度，从而降低上行信号对下行信号的干扰，并且由于进入接收通路的上行信号幅度降低了，后端电路由于饱和产生的非线性失真会较小，从而也保证了后端电路自干扰消除的性能。
举例，假设限幅器10415的输出功率设计为-10dBm，当26dBm的上行信号通过天线引脚10413进入接收通路时，经过限幅器10415后，输出的上行干扰信号为-10dBm，等效于增加了36dB的自干扰抑制。
最后需要说明的是，收发滤波器1042和同频隔离器1041的位置可互换，取决于具体的链路指标的需求。例如，滤波器在左侧时，可以先抑制掉前级电路产生的带外杂散信号，保证同频隔离器1041的性能，如果前级电路产生的带外杂散信号较低，则同频隔离器1041可以放在滤波器之前。
综上所述，本公开实施例提供的同时同频全双工系统100，可以在一路天线，一个天线开关1043以及一个收发滤波器1042的基础上，实现同时同频全双工传输，降低了链路复杂度，减少了成本，并且在同频隔离器1041中的限幅器10415的作用下，可以达到更好的同频自干扰抑制指标，提升了系统的自干扰消除水平。
依据本公开实施例的另一个方面，提供了一种移动终端，包括：如上所述的同时同频全双工系统100。
本公开实施例提供的移动终端中的同时同频全双工系统100，采用一路信号收发电路104，进行上行信号的发送和下行信号的接收，并对上行信号和下行信号进行隔离，进行自干扰抑制，降低了同时同频全双工系统100链路复杂度，减少了成本。
依据本公开实施例的另一个方面，提供了一种移动终端400。
该移动终端400可以为手机、平板电脑、个人数字助理(Personal Digital  Assistant，PDA)或车载电脑等。
如图4所示，该移动终端400包括射频(Radio Frequency，RF)电路401、存储器402、输入单元403、显示单元404、处理器406、音频电路407、WiFi(Wireless Fidelity)模块408和电源409。
可选地，输入单元403可用于接收用户输入的数字或字符信息，以及产生与移动终端400的用户设置以及功能控制有关的信号输入。具体地，本公开实施例中，该输入单元403可以包括触控面板4031。触控面板4031，也称为触摸屏，可收集用户在其上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触控面板4031上的操作)，并根据预先设定的程式驱动相应的连接装置。可选地，触控面板4031可包括触摸检测装置和触摸控制器两个部分。可选地，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给该处理器406，并能接收处理器406发来的命令并加以执行。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触控面板4031。除了触控面板4031，输入单元403还可以包括其他输入设备4032，其他输入设备4032可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆等中的一种或多种。
可选地，显示单元404可用于显示由用户输入的信息或提供给用户的信息以及移动终端400的各种菜单界面。显示单元404可包括显示面板4041，可选地，可以采用LCD或有机发光二极管(Organic Light-Emitting Diode，OLED)等形式来配置显示面板4041。
应注意，触控面板4031可以覆盖显示面板4041，形成触摸显示屏，当该触摸显示屏检测到在其上或附近的触摸操作后，传送给处理器406以确定触摸事件的类型，随后处理器406根据触摸事件的类型在触摸显示屏上提供相应的视觉输出。
触摸显示屏包括应用程序界面显示区及常用控件显示区。该应用程序界面显示区及该常用控件显示区的排列方式并不限定，可以为上下排列、左右排列等可以区分两个显示区的排列方式。该应用程序界面显示区可以用于显 示应用程序的界面。每一个界面可以包含至少一个应用程序的图标和/或widget桌面控件等界面元素。该应用程序界面显示区也可以为不包含任何内容的空界面。该常用控件显示区用于显示使用率较高的控件，例如，设置按钮、界面编号、滚动条、电话本图标等应用程序图标等。
可选地，处理器406是移动终端400的控制中心，利用各种接口和线路连接整个手机的各个部分，通过运行或执行存储在第一存储器4021内的软件程序和/或模块，以及调用存储在第二存储器4022内的数据，执行移动终端400的各种功能和处理数据，从而对移动终端400进行整体监控。可选地，处理器406可包括一个或多个处理单元。
在本公开实施例中，通过调用存储该第一存储器4021内的软件程序和/或模块和/或该第二存储器4022内的数据。
如图1所示，本公开实施例中，该移动终端还包括：一种同时同频全双工系统100。该同时同频全双工系统100包括：基带处理电路101、发射端信号处理电路102、接收端信号处理电路103和信号收发电路104，其中：
基带处理电路101的第一端与发射端信号处理电路102的第一端电连接；发射端信号处理电路102的第二端与信号收发电路104的第一端电连接；
基带处理电路101的第二端与接收端信号处理电路103的第一端电连接；接收端信号处理电路103的第二端与信号收发电路104的第二端电连接；
其中，信号收发电路104用于同时发送上行信号和接收下行信号，并对上行信号和下行信号进行隔离。
进一步地，如图1所示，发射端信号处理电路102的第三端与接收端信号处理电路103的第三端电连接。
可选地，发射端信号处理电路102还用于在接收到基带处理电路101发送的上行信号时，提取上行信号的干扰自消参考信号，并将干扰自消参考信号发送至接收端信号处理电路103。
进一步地，如图2所示，该发射端信号处理电路102包括：发射端数字信号处理电路1021和发射端模拟信号处理电路1022，其中：
发射端数字信号处理电路1021的第一端与基带处理电路101的第一端电连接，发射端数字信号处理电路1021的第二端与发射端模拟信号处理电路 1022的第一端电连接，发射端模拟信号处理电路1022的第二端与信号收发电路104的第一端电连接。
发射端数字信号处理电路1021用于接收基带处理电路101发送的上行信号，并将接收到的上行信号进行数字化处理后，发送至发射端模拟信号处理电路1022。
发射端模拟信号处理电路1022用于将从发射端数字信号处理电路1021接收到的上行信号进行上变频及调制后，发送至信号收发电路104。
进一步地，如图2所示，接收端信号处理电路103包括：接收端数字信号处理电路1031和接收端模拟信号处理电路1032，其中：
接收端数字信号处理电路1031的第一端与基带处理电路101的第一端电连接，接收端数字信号处理电路1031的第二端与接收端模拟信号处理电路1032的第一端电连接，接收端模拟信号处理电路1032的第二端与信号收发电路104的第二端电连接。
接收端模拟信号处理电路1032用于接收信号收发电路104发送的下行信号，对下行信号进行下变频及解调后，发送至接收端数字信号处理电路1031。
接收端数字信号处理电路1031用于将从接收端模拟信号处理电路1032接收到的下行信号进行数字化处理后，发送至基带处理电路101。
进一步地，如图2所示，发射端数字信号处理电路1021的第三端与接收端数字信号处理电路1031的第三端电连接。
发射端数字信号处理电路1021还用于在对上行信号进行数字化处理时，提取上行信号的数字干扰自消参考信号，将数字干扰自消参考信号发送至接收端数字信号处理电路1031。
进一步地，如图2所示，发射端模拟信号处理电路1022的第三端与接收端模拟信号处理电路1032的第三端电连接。
发射端模拟信号处理电路1022还用于在对上行信号进行上变频及调制时，提取上行信号的模拟干扰自消参考信号，将模拟干扰自消参考信号发送至接收端模拟信号处理电路1032。
进一步地，如图2所示，信号收发电路104包括：同频隔离器1041、收发滤波器1042、天线开关1043和收发天线1044，其中：
同频隔离器1041的第一端与发射端模拟信号处理电路1022的第二端电连接；同频隔离器1041的第二端与接收端数字信号处理电路1031的第二端电连接；同频隔离器1041的第三端与收发滤波器1042的第一端电连接；收发滤波器1042的第二端与天线开关1043的第一端电连接，天线开关1043的第二端与收发天线1044电连接。
可选地，在同频隔离器1041接收到发射端模拟信号处理电路1022发送的上行信号后，同频隔离器1041还用于将上行信号发送至收发滤波器1042，收发滤波器1042还用于对同频隔离器1041发送的上行信号进行滤波，天线开关1043用于将收发滤波器1042滤波之后的上行信号发送至收发天线1044，收发天线1044用于将天线开关1043发送的上行信号发送出去。
收发天线1044在接收到下行信号后，收发天线1044还用于将接收到的下行信号发送至天线开关1043，天线开关1043还用于将收发天线1044发送的下行信号发送至收发滤波器1042，收发滤波器1042还用于对天线开关1043发送的下行信号进行滤波，并将滤波之后的下行信号发送至同频隔离器1041，同频隔离器1041还用于对上行信号和下行信号进行收发隔离。
进一步地，如图3所示，同频隔离器1041包括：发送引脚10411、接收引脚10412、天线引脚10413和负载接地引脚10414。
可选地，发送引脚10411与发射端模拟信号处理电路1022的第二端电连接，发送引脚10411与天线引脚10413连接形成上行信号的发射通路。
接收引脚10412与接收端模拟信号处理电路1032的第二端电连接，接收引脚10412与天线引脚10413连接形成下行信号的接收通路，天线引脚10413与收发滤波器1042电连接。
进一步地，负载接地引脚10414与同频隔离器1041的外壳连接，或负载接地引脚10414与同频隔离器1041的内部线路中的地端电连接。
进一步地，如图3所示，接收通路上连接有一限幅器10415。
进一步地，发射通路由一传输线形成。
进一步地，发送引脚10411与接收引脚10412之间的走线空间间距和发射通路与接收通路之间的走线空间间距均大于或等于走线宽度的3倍。
可见，本公开实施例提供的移动终端400，采用一路信号收发电路104， 进行上行信号的发送和下行信号的接收，并对上行信号和下行信号进行隔离，完成自干扰抑制，降低了链路复杂度，降低了成本。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
尽管已描述了本公开实施例的实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括可选实施例以及落入本公开实施例范围的所有变更和修改。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者终端设备中还存在另外的相同要素。
以上所述的是本公开的优选实施方式，应当指出对于本技术领域的普通人员来说，在不脱离本公开所述的原理前提下还可以作出若干改进和润饰，这些改进和润饰也在本公开的保护范围内。

Claims (13)

  1. 一种同时同频全双工系统，包括：基带处理电路、发射端信号处理电路、接收端信号处理电路和信号收发电路，其中：
    所述基带处理电路的第一端与所述发射端信号处理电路的第一端电连接；所述发射端信号处理电路的第二端与所述信号收发电路的第一端电连接；
    所述基带处理电路的第二端与所述接收端信号处理电路的第一端电连接；所述接收端信号处理电路的第二端与所述信号收发电路的第二端电连接；
    其中，所述信号收发电路用于同时发送上行信号和接收下行信号，并对所述上行信号和下行信号进行隔离。
  2. 根据权利要求1所述的同时同频全双工系统，其中，所述发射端信号处理电路的第三端与所述接收端信号处理电路的第三端电连接；
    其中，所述发射端信号处理电路还用于在接收到所述基带处理电路发送的上行信号时，提取所述上行信号的干扰自消参考信号，并将所述干扰自消参考信号发送至所述接收端信号处理电路。
  3. 根据权利要求1或2所述的同时同频全双工系统，其中，所述发射端信号处理电路包括：发射端数字信号处理电路和发射端模拟信号处理电路，其中：
    所述发射端数字信号处理电路的第一端与所述基带处理电路的第一端电连接，所述发射端数字信号处理电路的第二端与所述发射端模拟信号处理电路的第一端电连接，所述发射端模拟信号处理电路的第二端与所述信号收发电路的第一端电连接；
    所述发射端数字信号处理电路用于接收所述基带处理电路发送的上行信号，并将接收到的所述上行信号进行数字化处理后，发送至所述发射端模拟信号处理电路；
    所述发射端模拟信号处理电路用于将从所述发射端数字信号处理电路接收到的所述上行信号进行上变频及调制后，发送至所述信号收发电路。
  4. 根据权利要求3所述的同时同频全双工系统，其中，所述接收端信号处理电路包括：接收端数字信号处理电路和接收端模拟信号处理电路，其中：
    所述接收端数字信号处理电路的第一端与所述基带处理电路的第一端电连接，所述接收端数字信号处理电路的第二端与所述接收端模拟信号处理电路的第一端电连接，所述接收端模拟信号处理电路的第二端与所述信号收发电路的第二端电连接；
    所述接收端模拟信号处理电路用于接收所述信号收发电路发送的下行信号，对所述下行信号进行下变频及解调后，发送至所述接收端数字信号处理电路；
    所述接收端数字信号处理电路用于将从所述接收端模拟信号处理电路接收到的所述下行信号进行数字化处理后，发送至基带处理电路。
  5. 根据权利要求4所述的同时同频全双工系统，其中，所述发射端数字信号处理电路的第三端与所述接收端数字信号处理电路的第三端电连接；
    所述发射端数字信号处理电路还用于在对上行信号进行数字化处理时，提取所述上行信号的数字干扰自消参考信号，将所述数字干扰自消参考信号发送至所述接收端数字信号处理电路。
  6. 根据权利要求4所述的同时同频全双工系统，其中，所述发射端模拟信号处理电路的第三端与所述接收端模拟信号处理电路的第三端电连接；
    所述发射端模拟信号处理电路还用于在对上行信号进行上变频及调制时，提取上行信号的模拟干扰自消参考信号，将所述模拟干扰自消参考信号发送至所述接收端模拟信号处理电路。
  7. 根据权利要求4所述的同时同频全双工系统，其中，所述信号收发电路包括：同频隔离器、收发滤波器、天线开关和收发天线，其中：
    所述同频隔离器的第一端与所述发射端模拟信号处理电路的第二端电连接；所述同频隔离器的第二端与所述接收端数字信号处理电路的第二端电连接；所述同频隔离器的第三端与所述收发滤波器的第一端电连接；所述收发滤波器的第二端与所述天线开关的第一端电连接，所述天线开关的第二端与所述收发天线电连接；
    其中，在所述同频隔离器接收到所述发射端模拟信号处理电路发送的上行信号后，所述同频隔离器还用于将所述上行信号发送至所述收发滤波器，所述收发滤波器还用于对所述同频隔离器发送的所述上行信号进行滤波，所 述天线开关用于将所述收发滤波器滤波之后的上行信号发送至所述收发天线，所述收发天线用于将所述天线开关发送的所述上行信号发送出去；
    所述收发天线在接收到下行信号后，所述收发天线还用于将接收到的所述下行信号发送至所述天线开关，所述天线开关还用于将所述收发天线发送的下行信号发送至所述收发滤波器，所述收发滤波器还用于对所述天线开关发送的所述下行信号进行滤波，并将滤波之后的下行信号发送至所述同频隔离器，所述同频隔离器还用于对所述上行信号和所述下行信号进行收发隔离。
  8. 根据权利要求7所述的同时同频全双工系统，其中，所述同频隔离器包括：发送引脚、接收引脚、天线引脚和负载接地引脚；
    其中，所述发送引脚与所述发射端模拟信号处理电路的第二端电连接，所述发送引脚与所述天线引脚连接形成上行信号的发射通路；
    所述接收引脚与所述接收端模拟信号处理电路的第二端电连接，所述接收引脚与所述天线引脚连接形成下行信号的接收通路，所述天线引脚与所述收发滤波器电连接。
  9. 根据权利要求8所述的同时同频全双工系统，其中，所述负载接地引脚与所述同频隔离器的外壳连接，或所述负载接地引脚与所述同频隔离器的内部线路中的地端电连接。
  10. 根据权利要求8所述的同时同频全双工系统，其中，所述接收通路上连接有一限幅器。
  11. 根据权利要求8所述的同时同频全双工系统，其中，所述发射通路由一传输线形成。
  12. 根据权利要求8所述的同时同频全双工系统，其中，所述发送引脚与所述接收引脚之间的走线空间间距和所述发射通路与所述接收通路之间的走线空间间距均大于或等于走线宽度的3倍。
  13. 一种移动终端，包括：如权利要求1至12中任一项所述的同时同频全双工系统。
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