WO2018233157A1 - 显示面板的驱动方法、驱动装置及显示装置 - Google Patents

显示面板的驱动方法、驱动装置及显示装置 Download PDF

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Publication number
WO2018233157A1
WO2018233157A1 PCT/CN2017/106755 CN2017106755W WO2018233157A1 WO 2018233157 A1 WO2018233157 A1 WO 2018233157A1 CN 2017106755 W CN2017106755 W CN 2017106755W WO 2018233157 A1 WO2018233157 A1 WO 2018233157A1
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Prior art keywords
frequency
clock signal
timing control
control chip
signal
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Ceased
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PCT/CN2017/106755
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English (en)
French (fr)
Inventor
王明良
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US15/740,799 priority Critical patent/US11200863B2/en
Publication of WO2018233157A1 publication Critical patent/WO2018233157A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present application relates to the field of display technologies, and in particular, to a driving method, a driving device, and a display device for a display panel.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • PCB printed circuit board
  • TCON Timing Controller
  • LCD TVs are increasingly moving toward large size and high resolution.
  • EMI electromagnetic interference
  • the country's verification standards, so how to reduce the electromagnetic interference effect of the power supply is a problem that most manufacturers pay more and more attention to.
  • the commonly used method is to add an electromagnetic interference suppression component to the power supply output, or to use a snubber circuit of RC (resistor and capacitor in series), but the electromagnetic interference suppression component can only weaken a part of the conducted interference.
  • RC resistor and capacitor in series
  • the RC snubber circuit can have a certain effect on the low-power circuit, but it is generally ineffective for high-power circuits.
  • a driving method of a display panel comprising:
  • the timing control chip Acquiring, by the timing control chip, the first clock signal, and multiplying a second clock signal, where the second clock signal is a preset multiple of the first clock signal;
  • the second clock signal is used as a clock signal inside the power chip circuit, and the second clock signal is input to the power chip circuit.
  • a driving device comprising:
  • a timing control chip configured to receive a first data signal of the control board, and convert the first data signal into a second data signal that drives the data line; set to generate a first clock signal with a frequency change, and to generate the second data Transmitting the signal and the first clock signal to the source driving chip; setting to acquire the first clock signal and multiplying the second clock signal, wherein the second clock signal is a preset multiple of the first clock signal;
  • the power chip circuit is configured to receive the second clock signal and drive the internal circuit of the power chip circuit according to the second clock signal.
  • a display device comprising:
  • a display panel and the above-described driving device are identical to the above-described driving device.
  • a driving method of a display panel comprising:
  • the second clock signal is used as a clock signal inside the power chip circuit, and the second clock signal is input to the power chip circuit.
  • the timing control chip receives the first data signal transmitted by the front end system control board; then converts the first data signal into the second data signal of the driving data line; and then generates a frequency change a first clock signal, and then transmitting the second data signal and the first clock signal to the source driving chip; simultaneously acquiring the first clock signal and multiplying the second clock signal, the second clock signal being the first clock signal a preset multiple; the second clock signal is then used as a clock signal inside the power chip circuit, and the second clock signal is input to the power chip circuit.
  • the internal clock signal of the power chip circuit is no longer generated internally by itself, but is an external input, and is a clock signal with a frequency change, thereby improving the serious problem of electromagnetic interference radiation of the power supply circuit, and is easy to implement, low in cost, and at the same time, the power chip can be simplified.
  • Internal circuit architecture Internal circuit architecture.
  • FIG. 1 is a flow chart showing a driving method of a display panel in an embodiment
  • 2 is a control architecture of a power chip circuit in an embodiment
  • FIG. 3 is a schematic diagram of electromagnetic radiation of a power chip circuit in an embodiment
  • FIG. 4 is a schematic diagram of a first clock signal in an embodiment
  • FIG. 5 is a schematic diagram of a second clock signal in an embodiment
  • FIG. 6 is a schematic diagram of electromagnetic radiation of a second clock signal in an embodiment
  • Figure 7 is a block diagram of a driving device in an embodiment
  • Figure 8 is a block diagram of a driving device in another embodiment
  • FIG. 9 is a flow chart of a driving method of a display panel in another embodiment.
  • FIG. 1 is a flow chart of a method of driving a display panel, the method including steps S110-S150. among them:
  • Step S110 receiving the first data signal of the control board by using the timing control chip.
  • Step S120 Converting the first data signal into the second data signal by using the timing control chip.
  • Step S130 generating a frequency change first clock signal by using the timing control chip, and transmitting the second data signal and the first clock signal to the source driving chip.
  • Step S140 Acquire a first clock signal by using a timing control chip, and multiply a second clock signal, where the second clock signal is a preset multiple of the first clock signal.
  • Step S150 The second clock signal is used as a clock signal inside the power chip circuit, and the second clock signal is input to the power chip circuit.
  • a timing control chip receives a first data signal transmitted by the front end system control board, and then converts the first data signal into a second data signal that drives the data line; and then generates a frequency change a first clock signal, and then transmitting the second data signal and the first clock signal to the source driving chip; simultaneously acquiring the first clock signal and multiplying the second clock signal, wherein the second clock signal is a preset of the first clock signal A multiple; the second clock signal is then used as a clock signal inside the power chip circuit, and the second clock signal is input to the power chip circuit.
  • TCON timing control chip
  • the internal clock signal of the power chip circuit is no longer generated internally by itself, but is an external input, and is a clock signal with a frequency change, thereby improving the serious problem of electromagnetic interference radiation of the power supply circuit, and is easy to implement, low in cost, and at the same time, the power chip can be simplified.
  • Internal circuit architecture Internal circuit architecture.
  • FIG. 2 is a control architecture of the power chip circuit in the embodiment, wherein the power source Vi is an input power source, the field effect transistor Q1 is a switch tube inside the power chip circuit, the inductor L is an external inductor, and the diode D1 is an external diode.
  • the capacitor C is a voltage stabilizing capacitor at the load end.
  • the working principle of the power chip circuit is that the internal switch tube Q1 is continuously turned on and off, and the input power source Vi continuously charges and discharges the external inductor L to achieve the purpose of adjusting the voltage.
  • the switching signal of the switching transistor Q1 is a driving signal with a fixed period of Ts
  • the switching signal of the switching transistor Q1 of the embodiment adopts a second clock signal with a frequency change to disperse the radiant energy of the power source on different frequency segments, thereby avoiding excessive concentration of energy and causing radiation exceeding a certain frequency.
  • the step S140 includes: acquiring a first clock signal by using a phase locked loop module of the timing control chip, and multiplying the second clock signal. Acquiring the first clock signal through the phase-locked loop module is more accurate and stable.
  • step S140 includes: dividing the second clock signal by a predetermined multiple to generate a comparison clock signal; acquiring the first clock signal, and obtaining a frequency difference value compared with the comparison clock signal; generating an adjustment voltage according to the frequency difference;
  • the regulated voltage produces a second clock signal of a predetermined multiple of the first clock signal.
  • the second clock signal of the preset multiple of the first clock signal can be obtained by the above steps, and the comparison clock signal is generated by dividing the second clock signal by a preset multiple, and then the frequency difference is obtained by comparing with the first clock signal to obtain a real-time adjustment of the frequency difference.
  • the preset multiple is determined by the relationship between the second clock signal required inside the power chip circuit and the first clock signal generated by the timing control chip.
  • the step S130 uses the timing control chip to generate the first clock signal of the frequency change, and the first frequency of the first clock signal is obtained by using the timing control chip.
  • the frequency can be a standard frequency or a frequency set according to the need; the maximum frequency that is greater than the first frequency is set to be the second frequency according to the first frequency, and the minimum change smaller than the first frequency is set according to the first frequency.
  • the frequency is a third frequency; the frequency of controlling the first clock signal varies between the second frequency and the third frequency.
  • the frequency of controlling the first clock signal is cyclically varied between the second frequency, the first frequency, and the third frequency.
  • the frequency change period T1 is set; the maximum change frequency f2 larger than the standard frequency and the minimum change frequency f0 smaller than the standard frequency are set according to the standard frequency f1; during the frequency change period T1, the frequency of the first clock signal is The minimum variation frequency f0, the standard frequency f1, and the maximum variation frequency f2 vary.
  • the frequency-changed second clock signal can be acquired only by multiplying the first clock signal.
  • the frequency f of the first clock signal output by the timing control chip is set to be non-fixed, that is, the variation period and the variation size are set to be changed near a standard frequency, such as a standard.
  • the frequency is f1
  • the minimum frequency is f0
  • the maximum frequency is f2
  • the set variation period is T1.
  • the frequency of the first clock signal continuously changes cyclically from f0, f1, and f2, as shown in the figure. 4 is shown.
  • the frequency of the obtained second clock signal is continuously changed from N*f0, N*f1, and N*f2, where N is a preset multiple.
  • the frequency of the first clock signal changes periodically from f0 to f1, f1 to f2, f2 to f1, f1 to f0, and may also vary from f1 to f2, f2 to f1, f1 to f0, f0 to f1, and the like.
  • FIG. 5 it is a schematic diagram of the variation of the second clock signal.
  • Figure 6 is a schematic illustration of the reduction in radiant energy. In this way, the radiant energy of the power source can be dispersed on different frequency segments, so as to avoid excessive concentration of energy and cause radiation exceeding a certain frequency.
  • the timing control chip of the signal receiving and processing since the timing control chip of the signal receiving and processing has a phase-locked loop module itself, a simple frequency multiplying circuit can be added to realize the above functions, and the cost is not excessively increased. Moreover, it is also possible to save the switching frequency generating circuit inside the power chip circuit itself. It is also possible to add a phase-locked loop module with a multiplier circuit.
  • the second clock signal of the switching frequency of the corresponding power chip circuit is generated by using the first clock signal of the signal frequency of the system output terminal timing control, and the effect of reducing the radiation interference is achieved by dispersing the switching frequency.
  • FIG. 7 is a block diagram of a driving device including a timing control chip 100 and a power chip circuit 300.
  • the timing control chip 100 is configured to receive a first data signal of the control board, and convert the first data signal into a second data signal that drives the data line; the timing control chip 100 is further configured to generate a first clock signal with a frequency change, and Transmitting the second data signal and the first clock signal to the source driving chip; the timing control chip 100 is further configured to acquire the first clock signal and multiply the second clock signal, where the second clock signal is a preset of the first clock signal multiple.
  • the power chip circuit 300 is configured to receive the second clock signal and drive the internal circuit of the power chip circuit according to the second clock signal.
  • the timing control chip receives the first data signal sent by the front end system control board, and then converts the first data into a second data signal that drives the data line; then generates a first clock signal with a frequency change, and then the second data signal and the first
  • the clock signal is sent out to the source driver chip.
  • the phase locked loop module simultaneously acquires the first clock signal and multiplies the second clock signal, and the second clock signal is a preset multiple of the first clock signal.
  • the power chip circuit is configured to receive the second clock signal and drive the internal circuit of the power chip circuit according to the second clock signal.
  • the internal clock signal of the power chip circuit is no longer generated internally by itself, but is an external input, and is a clock signal with a frequency change, thereby improving the serious problem of electromagnetic interference radiation of the power supply circuit, and is easy to implement, low in cost, and at the same time, the power chip can be simplified.
  • Internal circuit architecture Internal circuit architecture.
  • FIG. 2 is a control architecture of the power chip circuit in the embodiment, wherein the power source Vi is an input power source, the field effect transistor Q1 is a switch tube inside the power chip circuit, the inductor L is an external inductor, and the diode D1 is an external diode.
  • the capacitor C is a voltage stabilizing capacitor at the load end.
  • the working principle of the power chip circuit is that the internal switch tube Q1 is continuously turned on and off, and the input power source Vi continuously charges and discharges the external inductor L to achieve the purpose of adjusting the voltage. If the switching signal of the switching transistor Q1 is a driving signal with a fixed period of Ts, the radiation interference of the power supply portion is concentrated.
  • the switching signal of the switching transistor Q1 of the embodiment adopts a second clock signal with a frequency change to disperse the radiant energy of the power source on different frequency segments, thereby avoiding excessive concentration of energy and causing radiation exceeding a certain frequency.
  • the timing control chip 100 includes a phase-locked loop module 110, and the phase-locked loop module 110 is configured to acquire a first clock signal and multiply a second clock signal, where the second clock signal is a first clock signal.
  • the preset multiple is also transmitted to the power chip circuit 300 as a clock signal inside the power chip circuit. Acquiring the first clock signal through the phase locked loop is more accurate and stable.
  • the timing control chip 100 receives the first data signal of the front end system end 200, such as the control board, such as display data, processes the first data signal into a second data signal that drives the data line, and changes the second data signal and the generated frequency.
  • a clock signal is sent to the source driver chip driver of the back end.
  • the phase locked loop module 110 includes a phase detecting module 111 , a charge pump 112 , an oscillator 113 , and a frequency divider 114 . among them:
  • the frequency divider 114 is configured to divide the second clock signal by a predetermined multiple to generate a comparison clock signal.
  • the phase detecting module 111 is configured to phase-lock the first clock signal and compare the compared clock signal to obtain a frequency difference.
  • the charge pump 112 is operative to generate a regulated voltage based on the frequency difference.
  • the oscillator 113 is configured to generate a second clock signal by a preset multiple of the first clock signal according to the adjustment voltage.
  • the oscillator 113 obtains a second clock signal of a preset multiple of the first clock signal, and divides the second clock signal Fs by a predetermined multiple N by the frequency divider 114 to generate a comparison clock signal Fs/N, and then the phase detecting module 111 (Phase detect) compares the comparison clock signal Fs/N with the first clock signal f to obtain a frequency difference ⁇ F, and the charge pump 113 obtains a regulated voltage ⁇ V according to the frequency difference ⁇ F for real-time adjustment to obtain a more accurate second clock. signal.
  • the preset multiple is determined by the relationship between the second clock signal required inside the power chip circuit and the first clock signal generated by the timing control chip.
  • the timing control chip of this embodiment further includes a frequency changing device, configured to acquire a first frequency of the first clock signal; and set a maximum change frequency greater than the first frequency according to the first frequency For the second frequency, setting a minimum change smaller than the first frequency according to the first frequency
  • the frequency is a third frequency; wherein the frequency varying means is further configured to control the frequency of the first clock signal to vary between the second frequency and the third frequency.
  • the frequency varying device can be placed outside the phase locked loop.
  • the phase locked loop can acquire the second clock signal with the frequency change only by multiplying the frequency.
  • the frequency f of the first clock signal output by the timing control chip is set to be non-fixed, that is, the variation period and the variation size are set to be changed near a standard frequency, such as a standard.
  • the frequency is f1, the minimum frequency is f0, the maximum frequency is f2, and the set variation period is T1.
  • the frequency of the first clock signal continuously changes cyclically from f0, f1, and f2, as shown in the figure. 4 is shown.
  • the frequency of the obtained second clock signal is continuously changed from N*f0, N*f1, and N*f2, where N is a preset multiple.
  • the frequency of the first clock signal changes periodically from f0 to f1, f1 to f2, f2 to f1, f1 to f0, and may also vary from f1 to f2, f2 to f1, f1 to f0, f0 to f1, and the like.
  • FIG. 5 it is a schematic diagram of the variation of the second clock signal
  • FIG. 6 is a schematic diagram of the reduction of the radiation energy. In this way, the radiant energy of the power source can be dispersed on different frequency segments, so as to avoid excessive concentration of energy and cause radiation exceeding a certain frequency.
  • the timing control chip of the signal receiving and processing since the timing control chip of the signal receiving and processing has a phase-locked loop module itself, a simple frequency multiplying circuit can be added to realize the above functions, and the cost is not excessively increased. Moreover, it is also possible to save the switching frequency generating circuit inside the power chip circuit itself. It is also possible to add a phase-locked loop module with a multiplier circuit.
  • the second clock signal of the switching frequency of the corresponding power chip circuit is generated by using the first clock signal of the signal frequency of the system output terminal timing control, and the effect of reducing the radiation interference is achieved by dispersing the switching frequency.
  • a display device comprising: a display panel and the driving device of any of the above.
  • the driving device can improve the electromagnetic interference of the display panel power chip circuit.
  • the display panel can be TN (Twisted Nematic), OCB (Optically Compensated Birefringence), VA (Vertical Alignment) type liquid crystal display panel, or OLED (Organic Light Emitting Diode, organic Light-emitting diodes, QLED (Quantum dots Light-emitting Diodes) type display panels, But it is not limited to this.
  • the display panel may be an RGB three primary color panel, an RGBW four color panel, or an RGBY four color panel, but is not limited thereto. This driving method is also applicable to the case when the display panel is a curved panel.
  • FIG. 9 is a flowchart of a driving method of a display panel according to another embodiment, the method comprising the following steps:
  • Step S210 receiving the first data signal of the control board by using the timing control chip.
  • Step S220 Converting the first data signal into a second data signal by using a timing control chip.
  • Step S230 The first clock signal of the frequency change is generated by the timing control chip, and the second data signal and the first clock signal are sent to the source driving chip.
  • Step S240 Acquire the first clock signal by using a phase locked loop module of the timing control chip, and multiply the second clock signal, and the frequency of the second clock signal is a preset multiple of the first clock signal.
  • Step S250 The second clock signal is used as a clock signal inside the power chip circuit, and the second clock signal is input to the power chip circuit.
  • Step S260 Dividing the second clock signal by the preset multiple to generate a comparison clock signal.
  • Step S270 Comparing the first clock signal with the comparison clock signal to obtain a frequency difference value.
  • Step S280 generating an adjustment voltage according to the frequency difference value.
  • Step S290 Generate a second clock signal of a preset multiple of the first clock signal according to the adjustment voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板的驱动方法，包括：利用时序控制芯片(100)接收控制板的第一数据信号(S110)；利用时序控制芯片(100)将第一数据信号转换成第二数据信号(S120)；利用时序控制芯片(100)生成频率变化的第一时钟信号，将第二数据信号和第一时钟信号发送至源极驱动芯片(S130)；利用时序控制芯片(100)获取第一时钟信号，并倍频生成第二时钟信号，第二时钟信号为第一时钟信号的预设倍数(S140)；以及将第二时钟信号作为电源芯片电路(300)内部的时钟信号，并将第二时钟信号输入电源芯片电路(300)(S150)。

Description

显示面板的驱动方法、驱动装置及显示装置
相关申请的交叉引用
本申请要求于2017年06月20日提交中国专利局、申请号为201710471820.2、申请名称为“显示面板的驱动方法、驱动装置及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种显示面板的驱动方法、驱动装置及显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)是当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。TFT-LCD主要驱动原理为，系统主板将红/绿/蓝压缩信号、控制信号及动力通过线材与印刷电路板(PCB板)上的连接器(connector)相连接，数据经过印刷电路板上的TCON(Timing Controller，时序控制器)IC处理后，经印刷电路板，通过S-COF(Source-Chip on Film)和G-COF(Gate-Chip on Film)与显示区连接，从而使得LCD获得所需的电源、信号。
液晶电视目前越来越向大尺寸，高解析度发展，随着电视功耗的增加，电磁干扰(EMI)的问题变得日益严重，这其中来自电源辐射的最为严重，由于产品出货必须满足国家的验证标准，所以如何减弱电源端的电磁干扰效应是各大厂商越来越重视的问题。
目前常用的方式是电源输出端加电磁干扰抑制元件，或使用RC(电阻和电容串联)的缓冲电路，但是电磁干扰抑制元件只能减弱一部分传导干扰， 针对辐射干扰则无能为力，RC缓冲电路对小功率电路可以起到一定效果，但对于大功率电路一般无效。
发明内容
基于此，有必要提供一种能够降低电源电路电磁干扰的显示面板的驱动方法、驱动装置及显示装置。
一种显示面板的驱动方法，包括：
利用时序控制芯片接收控制板的第一数据信号；
利用时序控制芯片将所述第一数据信号转换成第二数据信号；
利用时序控制芯片生成频率变化的第一时钟信号，将所述第二数据信号和所述第一时钟信号发送至源极驱动芯片；
利用时序控制芯片获取所述第一时钟信号，并倍频生成第二时钟信号，所述第二时钟信号为第一时钟信号的预设倍数；以及
将所述第二时钟信号作为电源芯片电路内部的时钟信号，并将所述第二时钟信号输入所述电源芯片电路。
一种驱动装置，包括：
时序控制芯片，设置为接收控制板的第一数据信号，并将所述第一数据信号转换成驱动数据线的第二数据信号；设置为生成频率变化的第一时钟信号，并将第二数据信号和第一时钟信号发送至源极驱动芯片；设置为获取第一时钟信号并倍频生成第二时钟信号，所述第二时钟信号为第一时钟信号的预设倍数；以及
电源芯片电路，设置为接收所述第二时钟信号，并根据第二时钟信号驱动电源芯片电路内部电路。
一种显示装置，包括：
显示面板以及上述的驱动装置。
一种显示面板的驱动方法，包括：
利用时序控制芯片接收控制板的第一数据信号；
利用时序控制芯片将所述第一数据信号转换成第二数据信号；
利用时序控制芯片生成频率变化的第一时钟信号，将所述第二数据信号和所述第一时钟信号发送至源极驱动芯片；
利用时序控制芯片的锁相环模块获取所述第一时钟信号，并倍频生成第二时钟信号，所述第二时钟信号的频率为第一时钟信号的预设倍数；
将第二时钟信号按所述预设倍数分频产生一比较时钟信号；
将所述第一时钟信号与所述比较时钟信号比较获得频率差值；
根据所述频率差值产生一个调节电压；
根据所述调节电压产生第一时钟信号预设倍数的第二时钟信号；以及
将所述第二时钟信号作为电源芯片电路内部的时钟信号，并将所述第二时钟信号输入所述电源芯片电路。
上述显示面板的驱动方法、驱动装置及显示装置中，时序控制芯片接收前端系统控制板发送的第一数据信号；接着将第一数据信号转换成驱动数据线的第二数据信号；然后生成频率变化的第一时钟信号，接着将第二数据信号和第一时钟信号发送至源极驱动芯片；同时获取第一时钟信号并倍频生成第二时钟信号，所述第二时钟信号为第一时钟信号的预设倍数；然后将第二时钟信号作为电源芯片电路内部的时钟信号，并将第二时钟信号输入所述电源芯片电路。电源芯片电路的内部时钟信号不再是内部自己产生，而是外部输入，而且是频率变化的时钟信号，从而改善电源电路电磁干扰辐射严重的问题，并且易于实现，成本低廉，同时可精简电源芯片内部的电路架构。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的显示面板的驱动方法的流程图；
图2为一实施例中的电源芯片电路的控制架构；
图3为一实施例中的电源芯片电路电磁辐射的示意图；
图4为一实施例中的第一时钟信号的示意图；
图5为一实施例中的第二时钟信号的示意图；
图6为一实施例中的第二时钟信号的电磁辐射示意图；
图7为一实施例中的驱动装置的框图；
图8为另一实施例中的驱动装置的框图；
图9为另一实施例中的显示面板的驱动方法的流程图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
图1是一种显示面板的驱动方法的流程图，该方法包括步骤S110-S150。其中：
步骤S110：利用时序控制芯片接收控制板的第一数据信号。
步骤S120：利用时序控制芯片将第一数据信号转换成第二数据信号。
步骤S130：利用时序控制芯片生成频率变化的第一时钟信号，将第二数据信号和第一时钟信号发送至源极驱动芯片。
步骤S140：利用时序控制芯片获取第一时钟信号，并倍频生成第二时钟信号，第二时钟信号为第一时钟信号的预设倍数。
步骤S150：将第二时钟信号作为电源芯片电路内部的时钟信号，并将第二时钟信号输入电源芯片电路。
时序控制芯片(TCON)接收前端系统控制板发送的第一数据信号，接着将第一数据信号转换成驱动数据线的第二数据信号；然后生成频率变化的 第一时钟信号，接着将第二数据信号和第一时钟信号发送至源极驱动芯片；同时获取第一时钟信号并倍频生成第二时钟信号，第二时钟信号为第一时钟信号的预设倍数；然后将第二时钟信号作为电源芯片电路内部的时钟信号，并将第二时钟信号输入电源芯片电路。电源芯片电路的内部时钟信号不再是内部自己产生，而是外部输入，而且是频率变化的时钟信号，从而改善电源电路电磁干扰辐射严重的问题，并且易于实现，成本低廉，同时可精简电源芯片内部的电路架构。
具体的，图2是本实施例中的电源芯片电路的控制架构，其中电源Vi为输入电源，场效应管Q1是电源芯片电路内部的开关管，电感L是外部电感，二极管D1是外部二极管，电容C是负载端的稳压电容，电源芯片电路的工作原理是内部的开关管Q1通过不断地开和关，输入电源Vi对外部电感L进行不断地充电和放电，实现调节电压的目的。如果开关管Q1的开关信号是一个固定周期为Ts的驱动信号，所以会造成电源部分的辐射干扰集中在1/Ts＝Fs这个频率段，造成辐射的幅值超标，如图3所示。本实施例的开关管Q1的开关信号采用频率变化的第二时钟信号则可以将电源的辐射能量分散在不同的频率段上，避免能量的过度集中造成某一频率的辐射超标。
其中，步骤S140包括：利用时序控制芯片的锁相环模块获取第一时钟信号，并倍频生成第二时钟信号。通过锁相环模块获取第一时钟信号更准确和稳定。
进一步地，步骤S140包括：将第二时钟信号按预设倍数分频产生比较时钟信号；获取第一时钟信号，并与比较时钟信号比较获得频率差值；根据频率差值产生一个调节电压；根据调节电压产生第一时钟信号预设倍数的第二时钟信号。通过上述步骤可以获得第一时钟信号预设倍数的第二时钟信号，并且通过第二时钟信号按预设倍数分频产生比较时钟信号，然后与第一时钟信号比较获得频率差值实时调节获得更准确的第二时钟信号。预设倍数通过电源芯片电路内部需要的第二时钟信号与时序控制芯片产生的第一时钟信号的关系确定。
在一个实施例中，本实施例与上述实施例的主要区别在于，步骤S130利用时序控制芯片生成频率变化的第一时钟信号包括：利用时序控制芯片获取第一时钟信号的第一频率，第一频率可以为标准频率，也可以根据需要自行设定的频率；根据第一频率设定比第一频率大的最大变化频率为第二频率，根据第一频率设定比第一频率小的最小变化频率为第三频率；控制第一时钟信号的频率在第二频率、第三频率之间变化。
进一步地，控制第一时钟信号的频率在第二频率、第一频率和第三频率之间循环变化。
具体的，设定频率变化周期T1；根据标准频率f1设定比标准频率大的最大变化频率f2和比标准频率小的最小变化频率f0；在变频变化周期T1内，第一时钟信号的频率在最小变化频率f0、标准频率f1和最大变化频率f2之间变化。
如此，只需倍频第一时钟信号就能获取频率变化的第二时钟信号。具体的，为了减弱传输信号的电磁干扰效应，将时序控制芯片输出的第一时钟信号的频率f设定为不固定的，即在一个标准频率附近设定变动周期和变动大小进行变动，如标准频率为f1，最小频率为f0，最大频率为f2，设定变动周期为T1，那么在T1的时间内，第一时钟信号的频率从f0、f1、f2之间不断地进行循环变动，如图4所示。那么得到的第二时钟信号的频率是从N*f0、N*f1、N*f2的不断循环变动的，其中N为预设倍数。其中第一时钟信号的频率从f0到f1、f1到f2、f2到f1、f1到f0周期变化，也可以f1到f2、f2到f1、f1到f0、f0到f1周期变化等等。如图5所示，是第二时钟信号的变动示意图。图6是辐射能量降低的示意图。以此便可以将电源的辐射能量分散在不同的频率段上，避免能量的过度集中造成某一频率的辐射超标。
同时由于信号接收和处理的时序控制芯片内部本身就有锁相环模块，可以再增加一个简单的倍频电路就能实现上述功能，并不会造成成本的过多上升。而且也可以节省本身电源芯片电路内部的开关频率产生电路。也可以增设一个带倍频电路的锁相环模块。
通过采用系统输出端时序控制芯片变动的信号频率第一时钟信号，产生对应的电源芯片电路的开关频率第二时钟信号，通过分散开关频率达到降低辐射干扰的效果。
图7是一种驱动装置的框图，该驱动装置包括时序控制芯片100和电源芯片电路300。
其中时序控制芯片100用于接收控制板的第一数据信号，并将第一数据信号转换成驱动数据线的第二数据信号；时序控制芯片100还用于生成频率变化的第一时钟信号，并将第二数据信号和第一时钟信号发送至源极驱动芯片；时序控制芯片100还用于获取第一时钟信号并倍频生成第二时钟信号，第二时钟信号为第一时钟信号的预设倍数。
电源芯片电路300用于接收第二时钟信号，并根据第二时钟信号驱动电源芯片电路内部电路。
时序控制芯片接收前端系统控制板发送的第一数据信号，接着将第一数据转换成驱动数据线的第二数据信号；然后生成频率变化的第一时钟信号，接着将第二数据信号和第一时钟信号发送出去至源极驱动芯片。锁相环模块同时获取第一时钟信号并倍频生成第二时钟信号，第二时钟信号为第一时钟信号的预设倍数。电源芯片电路用于接收第二时钟信号，并根据第二时钟信号驱动电源芯片电路内部电路。电源芯片电路的内部时钟信号不再是内部自己产生，而是外部输入，而且是频率变化的时钟信号，从而改善电源电路电磁干扰辐射严重的问题，并且易于实现，成本低廉，同时可精简电源芯片内部的电路架构。
具体的，图2为本实施例中的电源芯片电路的控制架构，其中电源Vi为输入电源，场效应管Q1是电源芯片电路内部的开关管，电感L是外部电感，二极管D1是外部二极管，电容C是负载端的稳压电容，电源芯片电路的工作原理是内部的开关管Q1通过不断地开和关，输入电源Vi对外部电感L进行不断地充电和放电，实现调节电压的目的。如果开关管Q1的开关信号是一个固定周期为Ts的驱动信号，所以会造成电源部分的辐射干扰集中在 1/Ts＝Fs这个频率段，造成辐射的幅值超标。本实施例的开关管Q1的开关信号采用频率变化的第二时钟信号则可以将电源的辐射能量分散在不同的频率段上，避免能量的过度集中造成某一频率的辐射超标。
其中，如图7所示，时序控制芯片100包括锁相环模块110，锁相环模块110用于获取第一时钟信号并倍频生成第二时钟信号，第二时钟信号为第一时钟信号的预设倍数，还将第二时钟信号传送给电源芯片电路300作为电源芯片电路内部的时钟信号。通过锁相环获取第一时钟信号更准确和稳定。时序控制芯片100接收前端系统端200如控制板的第一数据信号如显示数据，将第一数据信号处理成驱动数据线的第二数据信号，并将第二数据信号和生成的频率变化的第一时钟信号发送给后端的源极驱动芯片驱动。
进一步地，如图8所示，锁相环模块110包括：相位侦测模块111、电荷泵112、振荡器113和分频器114。其中：
分频器114，用于将第二时钟信号按预设倍数分频产生比较时钟信号。
相位侦测模块111用于锁相采集第一时钟信号，并与比较时钟信号比较获得频率差值。
电荷泵112用于根据频率差值产生一个调节电压。
振荡器113用于根据调节电压按第一时钟信号预设倍数产生第二时钟信号。
振荡器113可以获得第一时钟信号预设倍数的第二时钟信号，通过分频器114将第二时钟信号Fs按预设倍数N分频产生比较时钟信号Fs/N，然后相位侦测模块111(Phase detect)将比较时钟信号Fs/N与第一时钟信号f比较获得频率差值ΔF，电荷泵113(charge pump)根据频率差值ΔF获得一个调节电压ΔV实时调节获得更准确的第二时钟信号。预设倍数通过电源芯片电路内部需要的第二时钟信号与时序控制芯片产生的第一时钟信号的关系确定。
在一个实施例中，本实施例的时序控制芯片还包括频率变化装置，频率变化装置用于获取第一时钟信号的第一频率；并根据第一频率设定比第一频率大的最大变化频率为第二频率，根据第一频率设定比第一频率小的最小变 化频率为第三频率；其中，频率变化装置还用于控制第一时钟信号的频率在第二频率、第三频率之间变化。
频率变化装置可以设置在锁相环外。如此，锁相环只需倍频就能获取频率变化的第二时钟信号。具体的，为了减弱传输信号的电磁干扰效应，将时序控制芯片输出的第一时钟信号的频率f设定为不固定的，即在一个标准频率附近设定变动周期和变动大小进行变动，如标准频率为f1，最小频率为f0，最大频率为f2，设定变动周期为T1，那么在T1的时间内，第一时钟信号的频率从f0、f1、f2之间不断地进行循环变动，如图4所示。那么得到的第二时钟信号的频率是从N*f0、N*f1、N*f2的不断循环变动的，其中N为预设倍数。其中第一时钟信号的频率从f0到f1、f1到f2、f2到f1、f1到f0周期变化，也可以f1到f2、f2到f1、f1到f0、f0到f1周期变化等等。如图5所示，是第二时钟信号的变动示意图，图6是辐射能量降低的示意图。以此便可以将电源的辐射能量分散在不同的频率段上，避免能量的过度集中造成某一频率的辐射超标。
同时由于信号接收和处理的时序控制芯片内部本身就有锁相环模块，可以再增加一个简单的倍频电路就能实现上述功能，并不会造成成本的过多上升。而且也可以节省本身电源芯片电路内部的开关频率产生电路。也可以增设一个带倍频电路的锁相环模块。
通过采用系统输出端时序控制芯片变动的信号频率第一时钟信号，产生对应的电源芯片电路的开关频率第二时钟信号，通过分散开关频率达到降低辐射干扰的效果。
一种显示装置，包括：显示面板以及上述任一所述的驱动装置。该驱动装置可以改善显示面板电源芯片电路电磁干扰严重的问题。显示面板可以为TN(Twisted Nematic，扭曲向列)、OCB(Optically Compensated Birefringence，光学补偿弯曲排列)、VA(Vertical Alignment，垂直配向)型液晶显示面板，还可以为OLED(Organic Light Emitting Diode，有机发光二极管)、QLED(Quantum dots Light-emitting Diodes，量子点电致发光二极管)型显示面板， 但并不限于此。该显示面板可以为RGB三原色面板、RGBW四色面板或者RGBY四色面板，但并不限于此。该驱动方法同样适用于显示面板为曲面面板时的情形。
图9为另一实施例的显示面板的驱动方法流程图，该方法包括以下步骤：
步骤S210：利用时序控制芯片接收控制板的第一数据信号。
步骤S220：利用时序控制芯片将所述第一数据信号转换成第二数据信号。
步骤S230：利用时序控制芯片生成频率变化的第一时钟信号，将所述第二数据信号和所述第一时钟信号发送至源极驱动芯片。
步骤S240：利用时序控制芯片的锁相环模块获取所述第一时钟信号，并倍频生成第二时钟信号，所述第二时钟信号的频率为第一时钟信号的预设倍数。
步骤S250：将所述第二时钟信号作为电源芯片电路内部的时钟信号，并将所述第二时钟信号输入所述电源芯片电路。
步骤S260：将第二时钟信号按所述预设倍数分频产生一比较时钟信号。
步骤S270：将所述第一时钟信号与所述比较时钟信号比较获得频率差值。
步骤S280：根据所述频率差值产生一个调节电压。
步骤S290：根据所述调节电压产生第一时钟信号预设倍数的第二时钟信号。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种显示面板的驱动方法，包括：
    利用时序控制芯片接收控制板的第一数据信号；
    利用时序控制芯片将所述第一数据信号转换成第二数据信号；
    利用时序控制芯片生成频率变化的第一时钟信号，将所述第二数据信号和所述第一时钟信号发送至源极驱动芯片；
    利用时序控制芯片获取所述第一时钟信号，并倍频生成第二时钟信号，所述第二时钟信号的频率为第一时钟信号的预设倍数；以及
    将所述第二时钟信号作为电源芯片电路内部的时钟信号，并将所述第二时钟信号输入所述电源芯片电路。
  2. 根据权利要求1所述的方法，其中，所述利用时序控制芯片获取所述第一时钟信号，并倍频生成第二时钟信号的步骤包括：
    利用时序控制芯片的锁相环模块获取所述第一时钟信号，并倍频生成第二时钟信号。
  3. 根据权利要求1所述的方法，其中，所述利用时序控制芯片获取所述第一时钟信号，并倍频生成第二时钟信号的步骤包括：
    将第二时钟信号按所述预设倍数分频产生一比较时钟信号；
    获取第一时钟信号，将所述第一时钟信号与所述比较时钟信号比较获得频率差值；
    根据所述频率差值产生一个调节电压；以及
    根据所述调节电压产生第一时钟信号预设倍数的第二时钟信号。
  4. 根据权利要求1所述的方法，其中，所述利用时序控制芯片生成频率变化的第一时钟信号的步骤包括：
    利用时序控制芯片获取第一时钟信号的第一频率；
    根据所述第一频率设定比所述第一频率大的最大变化频率为第二频率，根据所述第一频率设定比所述第一频率小的最小变化频率为第三频率；以及
    控制所述第一时钟信号的频率在第二频率、第三频率之间变化。
  5. 根据权利要求4所述的方法，其中，所述控制所述第一时钟信号的频率在第二频率、第三频率之间变化的步骤包括：
    控制所述第一时钟信号的频率在第二频率、第一频率和第三频率之间循环变化。
  6. 根据权利要求5所述的方法，其中，所述控制所述第一时钟信号的频率在第二频率、第一频率和第三频率之间循环变化的步骤包括：
    控制所述第一时钟信号的频率从第三频率到第一频率、第一频率到第二频率、第二频率到第一频率、第一频率到第三频率周期变化。
  7. 根据权利要求5所述的方法，其中，所述控制所述第一时钟信号的频率在第二频率、第一频率和第三频率之间循环变化的步骤包括：
    控制所述第一时钟信号的频率从第一频率到第二频率、第二频率到第一频率、第一频率到第三频率、第三频率到第一频率周期变化。
  8. 一种驱动装置，包括：
    时序控制芯片，设置为接收控制板的第一数据信号，并将所述第一数据信号转换成驱动数据线的第二数据信号；还设置为生成频率变化的第一时钟信号，并将所述第二数据信号和第一时钟信号发送至源极驱动芯片；还设置为获取第一时钟信号并倍频生成第二时钟信号，所述第二时钟信号为第一时钟信号的预设倍数；以及
    电源芯片电路，设置为接收所述第二时钟信号，并根据第二时钟信号驱动电源芯片电路内部电路。
  9. 根据权利要求8所述的驱动装置，其中，所述时序控制芯片包括锁相环模块，所述锁相环模块设置为获取第一时钟信号，并倍频生成第二时钟信号。
  10. 根据权利要求9所述的驱动装置，其中，所述锁相环模块包括：
    分频器，设置为将所述第二时钟信号按所述预设倍数分频产生比较时钟信号；
    相位侦测模块，设置为获取第一时钟信号，并与所述比较时钟信号比较 获得频率差值；
    电荷泵，设置为根据所述频率差值产生一个调节电压；以及
    振荡器，设置为根据所述调节电压按所述第一时钟信号预设倍数产生所述第二时钟信号。
  11. 根据权利要求8所述的驱动装置，所述时序控制芯片还包括：
    频率变化装置，所述频率变化装置设置为获取第一时钟信号的第一频率；并根据所述第一频率设定比第一频率大的最大变化频率为第二频率，根据所述第一频率设定比第一频率小的最小变化频率为第三频率；以及设置为控制第一时钟信号的频率在第二频率、第三频率之间变化。
  12. 根据权利要求11所述的驱动装置，其中，所述频率变化装置还设置为控制所述第一时钟信号的频率从第三频率到第一频率、第一频率到第二频率、第二频率到第一频率、第一频率到第三频率周期变化。
  13. 根据权利要求11所述的驱动装置，其中，所述频率变化装置还设置为控制所述第一时钟信号的频率从第一频率到第二频率、第二频率到第一频率、第一频率到第三频率、第三频率到第一频率周期变化。
  14. 一种显示面板的驱动方法，包括：
    利用时序控制芯片接收控制板的第一数据信号；
    利用时序控制芯片将所述第一数据信号转换成第二数据信号；
    利用时序控制芯片生成频率变化的第一时钟信号，将所述第二数据信号和所述第一时钟信号发送至源极驱动芯片；
    利用时序控制芯片的锁相环模块获取所述第一时钟信号，并倍频生成第二时钟信号，所述第二时钟信号的频率为第一时钟信号的预设倍数；
    将第二时钟信号按所述预设倍数分频产生一比较时钟信号；
    将所述第一时钟信号与所述比较时钟信号比较获得频率差值；
    根据所述频率差值产生一个调节电压；
    根据所述调节电压产生第一时钟信号预设倍数的第二时钟信号；以及
    将所述第二时钟信号作为电源芯片电路内部的时钟信号，并将所述第二 时钟信号输入所述电源芯片电路。
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