WO2018228592A1 - 一种极化Polar码的交织处理方法及装置 - Google Patents

一种极化Polar码的交织处理方法及装置 Download PDF

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Publication number
WO2018228592A1
WO2018228592A1 PCT/CN2018/091836 CN2018091836W WO2018228592A1 WO 2018228592 A1 WO2018228592 A1 WO 2018228592A1 CN 2018091836 W CN2018091836 W CN 2018091836W WO 2018228592 A1 WO2018228592 A1 WO 2018228592A1
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Prior art keywords
bits
sequence
bit
coded
interleaved
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PCT/CN2018/091836
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English (en)
French (fr)
Inventor
王桂杰
张公正
李榕
陈伟
王俊
徐晨
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华为技术有限公司
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Priority claimed from CN201710459780.XA external-priority patent/CN109150199B/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18816704.3A priority Critical patent/EP3641139B1/en
Publication of WO2018228592A1 publication Critical patent/WO2018228592A1/zh
Priority to US16/717,777 priority patent/US11343018B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/251—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with block coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2717—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions the interleaver involves 3 or more directions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present application relates to the field of wireless communication technologies, and in particular, to an interleaving processing method and apparatus for a polarized Polar code.
  • Arikan's Polar Codes based on channel polarization are selected as the channel coding method, and the Polar code has lower calculation in coding and decoding. the complexity.
  • Channel coding is often used in digital communication to improve the reliability of data transmission.
  • the interleaving module is added to the channel coding, which can further improve the anti-interference performance.
  • the ability to reduce the error correction ability in order to improve the system's anti-interference, first discard the burst error into a random error, and then correct the random error.
  • the Polar code performs an interleaving operation at the transmitting end and performs a deinterleaving operation at the receiving end.
  • the interleaving function is to scramble the original data sequence, so that the correlation of the data sequence before and after the interleaving is weakened, and the data burst error is reduced. Influence and improve anti-interference performance.
  • the prior art provides a random interleaving method.
  • the interleaving sequence is offline, the permutation sequence needs to be stored for interleaving and deinterleaving.
  • the storage of the permutation sequence results in a large storage resource required for the random interleaving mode and is complicated to implement.
  • the embodiment of the present application provides a method and device for processing a Polar code interleaving, and a communication device, which can save the use of storage resources in the interleaving process, and the interleaving process is simple to implement.
  • the present invention provides a method for interpolating a Polar code, including:
  • N a positive integer
  • the coded bits are interleaved according to a first sequence.
  • performing the interleaving processing on the coded bit according to the first sequence includes:
  • the coded bits are ordered according to the interleaved sequence to obtain interleaved bits.
  • performing the interleaving processing on the coded bit according to the first sequence includes:
  • the sorted coded bits are input to an interleaver to obtain interleaved bits.
  • the inputting the coded bits into the interleaver to obtain the interleaved bits includes:
  • the sorted coded bits are directly input to the interleaver to obtain interleaved bits.
  • the inputting the coded bits into the interleaver to obtain the interleaved bits includes:
  • the rate matched coded bits are input to an interleaver to obtain interleaved bits.
  • the method further includes:
  • Rate-coding the coded bits to obtain rate-matched coded bits
  • Interleaving the coded bits according to the first sequence includes:
  • the sorted coded bits are input to an interleaver to obtain interleaved bits.
  • performing the interleaving processing on the coded bit according to the first sequence includes:
  • a second coded bit of the coded bit located at a position other than the information bit is input to the second interleaver to obtain a second interleaved bit.
  • the method further includes:
  • Rate-coding the coded bits to obtain rate-matched coded bits
  • Interleaving the coded bits according to the first sequence includes:
  • a second coded bit located at a position other than the information bit among the coded bits after the rate matching is input to the second interleaver to obtain a second interleaved bit.
  • the method further includes:
  • the coded bits are repeatedly coded to obtain (M-N) repetition bits, M is a target code length of the Polar code output, and M is a positive integer greater than N;
  • Interleaving the coded bits according to the first sequence includes:
  • the method also includes:
  • the first sort result and the second sort result are interleaved to obtain interleaved bits.
  • Sorting the repeated bits according to the first sequence to obtain a second sorting result includes:
  • the repeated bits are sorted according to the second sequence to obtain a second sorting result, wherein the second sequence is a sequence of length M-N obtained from the first sequence;
  • the repeated bits are divided into L-segment repeat bits, each of the repeating bits of the first (L-1)-segment repeating bits are sorted according to the first sequence, and the L-th repeating bits are sorted according to the second sequence, wherein The length of each repeat bit in the pre (L-1) segment repeat bit is N, the length of the L segment repeat bit is ML*N, and the second sequence is a sequence of length ML*N obtained from the first sequence. .
  • performing the interleaving processing to obtain the interleaved bits by using the first sorting result and the second sorting result includes:
  • the first sort result and the second sort result are sequentially input to the interleaver to obtain interleaved bits.
  • the performing the interleaving processing to obtain the interleaving bits by using the first sorting result and the second sorting result includes:
  • the second ordering result is input to the second interleaver to obtain a second interleaved bit, and the first interleaved bit and the second interleaved bit constitute the interleaved bit.
  • the present invention provides a Polar code interleaving processing apparatus having a function of realizing the behavior of an interleaving processing apparatus in the method example of the first aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or the software includes one or more modules corresponding to the functions described above.
  • the structure of the interleaving processing apparatus includes a determining module, an obtaining module, a polarization encoding module, and an interleaving module, and the modules may perform corresponding functions in the foregoing method examples.
  • the modules may perform corresponding functions in the foregoing method examples. For details, refer to the detailed description in the method examples. I will not repeat them here.
  • the present invention provides a communication device, including:
  • a processor configured to execute the program stored in the memory, when the program is executed, the processor is configured to perform any one of the foregoing first aspect or the first aspect.
  • Yet another aspect of the present application is directed to a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the methods described in the various aspects above.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
  • Yet another aspect of the present application provides a computer program that, when run on a computer, causes the computer to perform the methods described in the various aspects above.
  • the coded bits encoded by the Polar code are interleaved according to the first sequence. Since the first sequence used to indicate the reliability of the polarized channel is a sequence already existing in the Polar code encoding process, the foregoing The interleaving process does not need to use additional storage resources to store the first sequence, which reduces the use of the storage resources; and interleaves the encoded bits according to the existing first sequence, and the interleaving process is simple to implement.
  • FIG. 1 is a structural diagram of a wireless communication system provided by the present invention.
  • FIG. 2 is a flowchart of a method for interpolating a polarized Polar code according to an embodiment of the present invention
  • FIG. 3 is a flowchart of an implementation of step S240 in the process of the interleaving processing method according to an embodiment of the present disclosure
  • Figure 5 is a row-row interleaver for row readout according to the present invention.
  • Figure 6 is a row and column interleaver for reading from the two sides to the middle in a row according to the present invention
  • Figure 7 is a row and column interleaver for reading from the two sides to the middle in columns according to the present invention.
  • FIG. 8 is a flowchart of still another implementation of step S240 in the flow of the interleaving processing method according to the embodiment of the present invention.
  • FIG. 9 is a flowchart of still another method for interpolating a polarized Polar code according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of still another implementation of step S240 in the process of the interleaving processing method according to the embodiment of the present invention.
  • FIG. 11 is a flowchart of still another method for interpolating a polarized Polar code according to an embodiment of the present invention.
  • FIG. 12 is a flowchart of still another method for interpolating a polarized Polar code according to an embodiment of the present invention.
  • FIG. 13 is a structural diagram of an apparatus for interpolating a polarized Polar code according to an embodiment of the present invention.
  • FIG. 14 is a structural diagram of an interleave module in an interleave processing apparatus according to an embodiment of the present invention.
  • FIG. 15 is a structural diagram of still another apparatus for interpolating a polarized Polar code according to an embodiment of the present invention.
  • FIG. 16 is a structural diagram of another apparatus for interpolating a polarized Polar code according to an embodiment of the present invention.
  • FIG. 17a is a structural diagram of a communication apparatus according to an embodiment of the present invention.
  • FIG. 17b is a structural diagram of still another communication apparatus according to an embodiment of the present invention.
  • the present application provides a method and an apparatus for polarizing a Polar code to solve the problem of large storage resource occupation in the interleaving process in the prior art.
  • the method and the device are based on the same inventive concept. Since the principles of the method and the device are similar, the implementation of the device and the method can be referred to each other, and the repeated description is not repeated.
  • An access terminal may also be called a system, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, a user device, or a UE (User Equipment, User equipment).
  • the access terminal may be a cellular phone, a cordless phone, a SIP (Session Initiation Protocol) phone, a WLL (Wireless Local Loop) station, a PDA (Personal Digital Assistant), and a wireless communication.
  • the base station can be used for communication with a mobile device, and the base station can be a BTS (Base Transceiver Station) in GSM (Global System of Mobile communication) or CDMA (Code Division Multiple Access), or
  • the NB (NodeB, base station) in the WCDMA (Wideband Code Division Multiple Access) may be an eNB or an eNodeB (Evolved Node B) in LTE (Long Term Evolution).
  • the wireless communication system 100 includes a base station 102 that can include multiple antenna groups.
  • Each antenna group may include one or more antennas, for example, one antenna group may include antennas 104 and 106, another antenna group may include antennas 108 and 110, and an additional group may include antennas 112 and 114.
  • Two antennas are shown in Figure 1 for each antenna group, although more or fewer antennas may be used for each group.
  • Base station 102 can additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which can include multiple components associated with signal transmission and reception (e.g., processor, modulator, multiplexer, demodulation) , demultiplexer or antenna, etc.).
  • a transmitter chain and a receiver chain can include multiple components associated with signal transmission and reception (e.g., processor, modulator, multiplexer, demodulation) , demultiplexer or antenna, etc.).
  • Base station 102 can communicate with one or more access terminals, such as access terminal 116 and access terminal 122. However, it will be appreciated that base station 102 can communicate with any number of access terminals similar to access terminal 116 or 122. Access terminals 116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other for communicating over wireless communication system 100. Suitable for equipment. As shown in FIG. 1, access terminal 116 is in communication with antennas 112 and 114, wherein antennas 112 and 114 transmit information to access terminal 116 over forward link 118 and receive information from access terminal 116 over reverse link 120. .
  • access terminal 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to access terminal 122 over forward link 124 and receive information from access terminal 122 over reverse link 126.
  • FDD Frequency Division Duplex
  • the forward link 118 can utilize a different frequency band than that used by the reverse link 120, and the forward link 124 can utilize the reverse link 126. Different frequency bands used.
  • the forward link 118 and the reverse link 120 can use a common frequency band, and the forward link 124 and the reverse link 126 can use a common frequency band.
  • Each set of antennas and/or regions designed for communication is referred to as a sector of base station 102.
  • the antenna group can be designed to communicate with access terminals in sectors of the coverage area of base station 102.
  • the transmit antenna of base station 102 may utilize beamforming to improve the signal to noise ratio of forward links 118 and 124.
  • the base station 102 uses beamforming to transmit signals to the randomly dispersed access terminals 116 and 122 in the relevant coverage area, the base station 102 uses a single antenna to transmit signals to all of its access terminals. Mobile devices are subject to less interference.
  • base station 102, access terminal 116 or access terminal 122 may be a wireless communication transmitting device and/or a wireless communication receiving device.
  • the wireless communication transmitting device can encode the data for transmission.
  • the wireless communication transmitting device may acquire (eg, generate, receive from other communication devices, or store in memory, etc.) a certain number of data bits to be transmitted over the channel to the wireless communication receiving device.
  • Such data bits may be included in a transport block (or multiple transport blocks) of data that may be segmented to produce multiple code blocks.
  • the wireless communication transmitting device may encode each code block using a Polar code encoder (not shown).
  • FIG. 2 is a flowchart of a method for interleaving a polarization Polar code provided by the present application.
  • the interleaving processing method includes:
  • N may be determined according to M, where M is a target code length of the Polar code output, and M is equal to a positive integer power of 2;
  • N M; for the rate matching scenario, symbol Indicates rounding up.
  • the reliability of the N polarized channels may be calculated first, and the polarized channels are sorted according to the reliability, and then the first sequence for indicating the reliability of the N polarized channels is obtained, where The elements in the first sequence are used to indicate the sequence number of the polarized channel;
  • different N values corresponding to different first sequences may be pre-stored in the form of a table in the memory, so that the first sequence containing N polarized channel numbers can be obtained by querying the memory without online calculation.
  • the sequence is obtained by acquiring the first sequence corresponding to the current mother code length N.
  • the maximum reliability sequence corresponding to the maximum mother code length N max may be stored in the memory, and the first sequence corresponding to the current mother code length N is determined based on the maximum reliability sequence, the maximum reliability. for indicating the reliability of the collating sequence number N max of the polarization channels, N max is a positive integer greater than N.
  • the encoding process of the bit to be encoded may be completed by using the encoding matrix F N of the Polar code, thereby obtaining the encoded code of the Polar encoding.
  • step S240 performing interleaving processing on the coded bits according to the first sequence includes:
  • S2401 Input an element in the first sequence into an interleaver to obtain an interleaving sequence
  • the interleaver may be a row-column interleaver, and the dimension of the row-column interleaver may be determined according to a modulation order.
  • the interleaver can adopt multiple reading modes, for example, travel list, line out, column out or column list, travel column ZIGZAG read, column into ZIGZAG read. Etc., where ZIGZAG reads are used to indicate "Zigzag" reading.
  • travel list line out, column out or column list
  • ZIGZAG reads are used to indicate "Zigzag” reading.
  • the manner in which several exemplary interleavers are read is given below.
  • Figure 4 shows the row and column interleaver read by column grouping
  • S is the number of elements of the input row and column interleaver
  • P is the number of columns of the row and column interleaver.
  • T column is reversed for the reading order of the column, where T can be a constant or a modulation order.
  • T can be 1, 3 or 5; for example, the modulation order is In 64QAM, T is 1, 5, 6, or 32, and T is a positive integer not greater than (S/P).
  • Fig. 5 shows the row and column interleaver read in rows
  • S is the number of elements of the input row and column interleaver
  • P is the number of columns of the row and column interleaver.
  • every One line reverses the reading order of the lines, that is, reads from right to left in the figure.
  • T is a positive integer not larger than (S/P).
  • Figure 6 shows the row and column interleaver read from the two sides to the middle in the row, that is, after reading from the top row, it jumps to the last row to read, and then jumps to the top row to read, thereby reading, completing the whole Reading of the row and column interleaver.
  • Figure 7 shows the row and column interleaver read from the two sides to the middle by column. After reading from the leftmost column, it jumps to the rightmost column and then reads to the leftmost column to read. Complete the reading of the entire row and column interleaver.
  • the column can be further cyclically shifted, and the cyclic shift size of each column can be determined by a function, such as 5*i, or f 1 *i+f 2 *i 2, etc., i is the currently read column number, and f 1 and f 2 are the function parameters used.
  • the interleaver may be a row-column interleaver, or may be other interleavers such as QPP interleaving, congruence interleaving, and S-distance interleaving.
  • the present invention does not limit the specific implementation of the interleaver.
  • S2402 Sort the coded bits according to the interleaving sequence to obtain interleaved bits.
  • the coded bits encoded by the Polar code are sorted according to an interleaving sequence to obtain interleaved bits, and the interleaved bits are the output interleaved bits. For example, if the coded bit is (1100) and the interleave sequence is (1324), the output interleave bit is (1010).
  • step S240 performing interleaving processing on the coded bits according to the first sequence includes:
  • S2404 Input the sorted coded bits into an interleaver to obtain interleaved bits.
  • the rate matching scenario is performed on the sorted coded bits.
  • the sorted coded bits are rate-matched to obtain rate-matched coded bits, and the rate-matched coded bits are input to the interleaver to obtain interleaved bits.
  • the coded bits are first sorted, and then whether the rate matching is performed is performed, and finally the sorted coded bits are input to the interleaver to obtain the interleaved bits; in fact, whether or not the first bit can be considered first Rate matching is performed on the coded bits, then the coded bits are sorted, and finally the sorted coded bits are input to the interleaver to obtain interleaved bits.
  • the following embodiment corresponding to FIG. 9 describes the case.
  • the interleaving processing method further includes:
  • step S240 performing interleaving processing on the coded bits according to the first sequence includes:
  • S2405. Sort the rate-matched coded bits according to the second sequence to obtain the sequenced coded bits, where the second sequence is a sequence of length M obtained from the first sequence, and M is a target code of the Polar code output. Long and M is a positive integer;
  • S2406 Input the sorted coded bits into an interleaver to obtain interleaved bits.
  • step S240 performing interleaving processing on the coded bits according to the first sequence includes:
  • non-information bits refer to bits other than the information bits.
  • first interleaver and the second interleaver may be the same interleaver or different interleavers, and the use of the first interleaver and the second interleaver involves possible three.
  • the first interleaver is the same as the second interleaver, that is, a unique interleaver is used, and the first coded bit and the second coded bit are input as a whole to the interleaver, and the whole may be the first coded bit before the second code.
  • the first coded bit is in the following order, and the input to the insufficient position in the interleaver corresponds to zero padding.
  • first interleaver When the first interleaver is different from the second interleaver, two interleavers are used, and the first coded bit is input to the first interleaver, and the input of the first interleaver is corresponding to zero padding, and the second coded bit input is input.
  • the second interleaver inputs the insufficient position in the second interleaver corresponding to zero padding.
  • the first interleaver is different from the second interleaver, that is, two interleavers are used, and the first coded bit is input to the first interleaver, and the insufficient position in the first interleaver is input to start entering the second coded bit, and the remaining The second coded bit is input to the second interleaver, and the input to the insufficient position in the second interleaver corresponds to zero padding.
  • the embodiment corresponding to FIG. 10 describes that the coded bits are not subjected to a rate matching scenario.
  • the following embodiment corresponding to FIG. 11 describes a coded bit for rate matching scenario.
  • the interleaving processing method further includes:
  • step S240 performing interleaving processing on the coded bits according to the first sequence includes:
  • S2409 Determine, according to the number K of information bits in the N to-be-coded bits, a position of the information bit and a position of the non-information bit from the first sequence, where K is a positive integer less than or equal to N;
  • first interleaver and the second interleaver may be the same interleaver or different interleavers.
  • the interleaving processing method further includes:
  • the repetitive coding refers to extending the coding bits to implement the target code length M coding bits.
  • the repetition coding process may select (MN) coding bits from the N coding bits as the repetition bits, and N coding bits.
  • (MN) repeating bits are the target code length M coded bits.
  • the (MN) repeating bits are divided into L-segment repeating bits, and each of the preceding (L-1)-segment repeating bits is sorted according to the first sequence, and the L-th repeating bits are in accordance with the second sequence. Sorting, wherein the length of each repeating bit in the preceding (L-1) segment repeating bit is N, the length of the Lth repeating bit is ML*N, and the second sequence is the length obtained from the first sequence is ML *N sequence; further, when the length of the L-th repeat bit is N, the length of the second sequence is N, and the second sequence is the same as the first sequence.
  • step S240 performing interleaving processing on the coded bits according to the first sequence includes:
  • S2411 Sort the coded bits according to the first sequence to obtain a first sort result.
  • the interleaving processing method further includes:
  • performing interleaving processing on the first sorting result and the second sorting result to obtain interleaved bits includes:
  • first interleaver and the second interleaver may be the same interleaver or different interleavers.
  • the encoded code encoded by the Polar code is interleaved according to the first sequence, and the first sequence used for indicating the reliability of the polarized channel is a sequence already existing in the Polar code encoding process, and therefore, the foregoing interleaving There is no need to use additional storage resources to store the first sequence during processing, which reduces the use of storage resources; and interleaves the encoded bits according to the existing first sequence, and the interleaving process is simple to implement.
  • the polarized Polar code interleaving processing apparatus 1300 provided by the embodiment of the present invention is described below with reference to FIG. 13, and the interleaving processing apparatus 1300 includes:
  • a determining module 1310 configured to determine N bits to be encoded, where N is a positive integer
  • N may be determined according to M, where M is the target code length of the Polar code output, and M is equal to the positive integer power of 2.
  • M the target code length of the Polar code output
  • M the positive integer power of 2.
  • the obtaining module 1320 is configured to obtain a first sequence that includes N polarization channel numbers, where the first sequence is used to indicate reliability ordering of the N polarization channels.
  • the polarization coding module 1330 is configured to perform Polar coding on the N to-be-coded bits to obtain coded bits.
  • the encoding process of the bit to be encoded may be completed by using the encoding matrix F N of the Polar code, thereby obtaining the encoded code of the Polar encoding.
  • the interleaving module 1340 is configured to perform interleaving processing on the coded bits according to the first sequence.
  • the interleaving module 1340 is specifically configured to:
  • a second coded bit of the coded bit located at a position other than the information bit is input to the second interleaver to obtain a second interleaved bit.
  • first interleaver and the second interleaver For the use of the first interleaver and the second interleaver, refer to the related description in the method embodiment, and details are not described herein again.
  • the interleaving module 1340 includes:
  • a first interleaving sub-module 1341 configured to input an element in the first sequence into an interleaver to obtain an interleaving sequence
  • the second interleaving sub-module 1342 is configured to sort the encoded bits according to the interleaving sequence to obtain interleaved bits.
  • the interleaving module 1340 includes:
  • a first interleaving sub-module 1341 configured to sort the encoded bits according to the first sequence to obtain the sorted encoded bits
  • the second interleaving sub-module 1342 is configured to input the sorted coded bits into the interleaver to obtain interleaved bits.
  • the second interleaving submodule 1342 is specifically configured to:
  • the sorted coded bits are rate matched to obtain rate matched coded bits; the rate matched coded bits are input to an interleaver to obtain interleaved bits.
  • the interleaving processing apparatus 1300 further includes:
  • a rate matching module 1350 configured to rate-match the coded bits to obtain rate-matched coded bits
  • the interleaving module 1340 is specifically configured to:
  • the sorted coded bits are input to an interleaver to obtain interleaved bits.
  • the interleaving processing apparatus 1300 further includes:
  • a rate matching module 1350 configured to rate-match the coded bits to obtain rate-matched coded bits
  • the interleaving module 1340 is specifically configured to:
  • a second coded bit located at a position other than the information bit among the coded bits after the rate matching is input to the second interleaver to obtain a second interleaved bit.
  • the interleaving module 1340 is specifically configured to:
  • the coded bits are sorted according to the first sequence to obtain a first sort result.
  • the interleaving processing apparatus 1300 further includes:
  • a repetition coding module 1360 configured to repeatedly code the coded bits to obtain (M-N) repetition bits, where M is a target code length of the Polar code output and M is a positive integer greater than N;
  • a sorting module 1370 configured to sort the repeated bits according to the first sequence to obtain a second sorting result
  • the interleaving bit obtaining module 1380 is configured to perform interleaving processing on the first sorting result and the second sorting result to obtain interleaved bits.
  • sorting module 1370 is specifically configured to:
  • the repeated bits are sorted according to the second sequence to obtain a second sorting result, wherein the second sequence is a sequence of length MN obtained from the first sequence.
  • the repeated bits are divided into L-segment repeat bits, each of the repeating bits of the first (L-1)-segment repeating bits are sorted according to the first sequence, and the L-th repeating bits are sorted according to the second sequence, wherein The length of each repeat bit in the pre (L-1) segment repeat bit is N, the length of the L segment repeat bit is ML*N, and the second sequence is a sequence of length ML*N obtained from the first sequence. .
  • interleaved bit obtaining module 1380 is specifically configured to:
  • the Polar code interleaving processing apparatus performs interleaving processing on the encoded code encoded by the Polar code according to the first sequence, because the first sequence for indicating the reliability of the polarized channel is a sequence already existing in the Polar code encoding process. Therefore, the foregoing interleaving process does not need to use additional storage resources to store the first sequence, which reduces the use of the storage resources; and performs interleaving processing on the encoded bits according to the existing first sequence, and the interleaving process is simple to implement.
  • a communication device 1700 for implementing interleaving processing of coded bits encoded by a Polar code.
  • the communication device 1700 includes:
  • the processing device 1710 is configured to process data received by the transceiver 1720.
  • the transceiver 1720 is configured to receive or send data.
  • the communication device further includes:
  • transceiver 1720 specifically receives or transmits data via antenna 1730.
  • the processing device 1710 When the processing device 1710 is implemented by software, as shown in FIG. 17a, the processing device 1710 includes:
  • a memory 1712 configured to store a program
  • the processor 1711 is configured to execute the program stored in the memory, and when the program is executed, perform an implementation in the foregoing method embodiment, for example, the method corresponding to any one of FIG. 2 or FIG. 8 to FIG.
  • the execution process of the processor 1711 will not be described herein.
  • the memory 1712 may be a physically separate unit or may be integrated with the processor 1711, as shown in FIG. 17b.
  • the communication device in the embodiment of the present application may be a wireless communication device such as an access point, a station, a base station, or a user terminal.
  • the Polar code in the embodiment of the present application may also be a CA-Polar code or a PC-Polar code.
  • Arikan Polar refers to the original Polar code, which is not cascaded with other codes, only information bits and frozen bits.
  • the CA-Polar code is a Polar code cascading a Cyclic Redundancy Check (CRC) Polar code
  • the PC-Polar code is a Polar code cascading Parity Check (PC) code.
  • PC-Polar and CA-Polar improve the performance of Polar codes by cascading different codes.
  • the unit and method processes of the examples described in the embodiments of the present application can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. The skilled person can use different methods for each particular application to implement the described functionality.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division, and the actual implementation may have another division manner.
  • multiple units or components may be combined or integrated into another system, or some steps may be omitted or not performed.
  • the coupling or direct coupling or communication connection of the various units to each other may be through some interfaces, which may be in electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separate, and may be located in one place or on multiple network elements.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

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Abstract

一种极化Polar码的交织处理的方法及装置。该方法包括：确定N个待编码比特，N为正整数（S210）；获取包含N个极化信道序号的第一序列，第一序列用于指示N个极化信道的可靠度排序（S220）；对该N个待编码比特进行Polar编码以得到编码比特（S230）；根据第一序列对该编码比特进行交织处理（S240）。由于用于指示极化信道可靠度的第一序列为Polar码编码过程中已经存在的序列，因此，上述交织处理过程中无需使用额外的存储资源来存储第一序列，减少了存储资源的使用；并且根据已存在的第一序列来对编码比特进行交织处理，交织处理实现简单。

Description

一种极化Polar码的交织处理方法及装置
本申请要求于2017年06月17日提交中国专利局、申请号为201710459780.X、申请名称为“一种极化Polar码的交织处理方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及无线通信技术领域，尤其涉及一种极化Polar码的交织处理方法及装置。
背景技术
随着第五代移动通信技术(5-Generation，5G)的发展，Arikan基于信道极化提出的极化码(Polar Codes)被选作信道编码方式，Polar码在编译码方面具有较低的计算复杂度。
在数字通信中经常使用信道编码来提高数据传输的可靠性，在信道编码加入了交织模块，可以进一步提高抗干扰性能。具体的，在许多同时出现随机错误和突发错误的复合信道上，如短波、对流层散射等信道中，发生一个错误时，波及后面一串数据，导致突发误码超过纠错码的纠错能力，使纠错能力下降，为了提高系统的抗干扰性，首先把突发错误离散成随机错误，然后再去纠随机错误。在实际应用中，Polar码在发送端进行交织操作，在接收端进行解交织的操作，交织的作用是将原始数据序列打乱，使得交织前后数据序列的相关性减弱，降低数据突发错误的影响，提高抗干扰性能。
现有技术提供了随机交织方式，随机交织方式在离线计算交织序列时，需要存储置换序列来供交织和解交织使用，置换序列的存储导致随机交织方式所需的存储资源较大，且实现复杂。
发明内容
本申请实施例提供Polar码交织处理方法及装置、通信装置，能够节省交织过程中存储资源的使用，并且交织处理实现简单。
第一方面，本发明提供一种Polar码交织处理方法，包括：
确定N个待编码比特，N为正整数；
获取包含N个极化信道序号的第一序列，第一序列用于指示N个极化信道的可靠度排序；
对该N个待编码比特进行Polar编码以得到编码比特；
根据第一序列对所述编码比特进行交织处理。
结合第一方面，在第一方面的第一种可能的实现方式中，根据第一序列对该编码比特进行交织处理包括：
将第一序列中元素输入交织器以得到交织序列；
将该编码比特按照该交织序列进行排序以得到交织比特。
结合第一方面，在第一方面的第二种可能的实现方式中，根据第一序列对该编码比特进行交织处理包括：
将该编码比特按照第一序列进行排序以得到排序后的编码比特；
将排序后的编码比特输入交织器以得到交织比特。
结合第一方面的第二种可能的实现方式，在第一方面的第三种可能的实现方式中，将排序后的编码比特输入交织器以得到交织比特包括：
将排序后的编码比特直接输入交织器以得到交织比特。
结合第一方面的第二种可能的实现方式，在第一方面的第四种可能的实现方式中，将排序后的编码比特输入交织器以得到交织比特包括：
将排序后的编码比特进行速率匹配以得到速率匹配后的编码比特；
将速率匹配后的编码比特输入交织器以得到交织比特。
结合第一方面，在第一方面的第五种可能的实现方式中，在对该N个待编码比特进行Polar编码以得到编码比特之后，该方法还包括：
将该编码比特进行速率匹配以得到速率匹配后的编码比特；
根据第一序列对编码比特进行交织处理包括：
将速率匹配后的编码比特按照第二序列进行排序以得到排序后的编码比特，其中，第二序列为从第一序列中获取的长度为M的序列，M为Polar码输出的目标码长且M为正整数；
将排序后的编码比特输入交织器以得到交织比特。
结合第一方面，在第一方面的第六种可能的实现方式中，根据第一序列对该编码比特进行交织处理包括：
根据该N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
将该编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及
将该编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
结合第一方面，在第一方面的第七种可能的实现方式中，对该N个待编码比特进行Polar编码以得到编码比特之后，该方法还包括：
将该编码比特进行速率匹配以得到速率匹配后的编码比特；
根据第一序列对该编码比特进行交织处理包括：
根据该N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
将速率匹配后的编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及
将速率匹配后的编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
结合第一方面，在第一方面的第八种可能的实现方式中，对该N个待编码比特进 行Polar编码以得到编码比特之后，该方法还包括：
对该编码比特进行重复编码以得到(M-N)个重复比特，M为Polar码输出的目标码长且M为大于N的正整数；
根据第一序列对重复比特进行排序以得到第二排序结果；
根据第一序列对该编码比特进行交织处理包括：
将编码比特按照第一序列进行排序以得到第一排序结果；
该方法还包括：
将第一排序结果和第二排序结果进行交织处理以得到交织比特。
结合第一方面的第八种可能的实现方式，在第一方面的第九种可能的实现方式中，
Figure PCTCN2018091836-appb-000001
根据第一序列对所述重复比特进行排序以得到第二排序结果包括：
在L＝1时，将重复比特按照第二序列进行排序以得到第二排序结果，其中，第二序列为从第一序列中获取的长度为M-N的序列；
在L>1时，将重复比特划分成L段重复比特，前(L-1)段重复比特中每段重复比特按照第一序列进行排序，第L段重复比特按照第二序列进行排序，其中，前(L-1)段重复比特中每段重复比特的长度为N，第L段重复比特的长度为M-L*N，第二序列为从第一序列中获取的长度为M-L*N的序列。
结合第一方面的第八或第九种可能的实现方式，在第一方面的第十种可能的实现方式中，将第一排序结果和第二排序结果进行交织处理以得到交织比特包括：
将第一排序结果和第二排序结果依次输入交织器以得到交织比特。
结合第一方面的第八或第九种可能的实现方式，在第一方面的第十一种可能的实现方式中，将第一排序结果和第二排序结果进行交织处理以得到交织比特包括：
将第一排序结果输入第一交织器以得到第一交织比特；以及
将第二排序结果输入第二交织器以得到第二交织比特，第一交织比特和第二交织比特组成该交织比特。
第二方面，本发明提供了一种Polar码交织处理装置，该交织处理装置具有实现上述第一方面方法示例中交织处理装置行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或所述软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，所述交织处理装置的结构中包括确定模块、获取模块、极化编码模块和交织模块，这些模块可以执行上述方法示例中相应功能，具体参见方法示例中的详细描述，此处不做赘述。
第三方面，本发明提供一种通信装置，包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行上述第一方面或第一方面的任意一种可能的实现方式。
本申请的又一方面提了供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请的又一方面提供了一种计算机程序，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
在本发明实施例中，根据第一序列对Polar码编码后的编码比特进行交织处理，由于用于指示极化信道可靠度的第一序列为Polar码编码过程中已经存在的序列，因此，上述交织处理过程中无需使用额外的存储资源来存储第一序列，减少了存储资源的使用；并且根据已存在的第一序列来对编码比特进行交织处理，交织处理实现简单。
附图说明
图1为本发明提供的无线通信系统结构图；
图2为本发明实施例提供的一种极化Polar码的交织处理方法流程图；
图3为本发明实施例提供的交织处理方法流程中步骤S240的一种实现流程图；
图4为本发明提供的按列分组读出的行列交织器；
图5为本发明提供的按行读出的行列交织器；
图6为本发明提供的按行从两边往中间读的行列交织器；
图7为本发明提供的按列从两边往中间读的行列交织器；
图8为本发明实施例提供的交织处理方法流程中步骤S240的又一种实现流程图；
图9为本发明实施例提供的又一种极化Polar码的交织处理方法流程图；
图10为本发明实施例提供的交织处理方法流程中步骤S240的又一种实现流程图；
图11为本发明实施例提供的又一种极化Polar码的交织处理方法流程图；
图12为本发明实施例提供的又一种极化Polar码的交织处理方法流程图；
图13为本发明实施例提供的一种极化Polar码的交织处理装置结构图；
图14为本发明实施例提供的交织处理装置中交织模块的结构图；
图15为本发明实施例提供的又一种极化Polar码的交织处理装置结构图；
图16为本发明实施例提供的又一种极化Polar码的交织处理装置结构图；
图17a为本发明实施例提供的一种通信装置的结构图；
图17b为本发明实施例提供的又一种通信装置的结构图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
本申请提供一种极化Polar码的方法及装置，用以解决现有技术中交织处理中存储资源占用大的问题。其中，方法和装置是基于同一发明构思的，由于方法及装置解 决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。
本申请中结合接入终端描述了各个实施例。接入终端也可以称为系统、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信装置、用户代理、用户装置或UE(User Equipment，用户设备)。接入终端可以是蜂窝电话、无绳电话、SIP(Session Initiation Protocol，会话启动协议)电话、WLL(Wireless Local Loop，无线本地环路)站、PDA(Personal Digital Assistant，个人数字处理)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备。此外，结合基站描述了各个实施例。基站可用于与移动设备通信，基站可以是GSM(Global System of Mobile communication，全球移动通讯)或CDMA(Code Division Multiple Access，码分多址)中的BTS(Base Transceiver Station，基站)，也可以是WCDMA(Wideband Code Division Multiple Access，宽带码分多址)中的NB(NodeB，基站)，还可以是LTE(Long Term Evolution，长期演进)中的eNB或eNodeB(Evolutional Node B，演进型基站)，或者中继站或接入点，或者未来5G网络中的基站设备等。
参照图1，示出根据本文所述的各个实施例的无线通信系统100。无线通信系统100包括基站102，基站102可包括多个天线组。每个天线组可以包括一个或多个天线，例如，一个天线组可包括天线104和106，另一个天线组可包括天线108和110，附加组可包括天线112和114。图1中对于每个天线组示出了2个天线，然而可对于每个组使用更多或更少的天线。基站102可附加地包括发射机链和接收机链，本领域普通技术人员可以理解，它们均可包括与信号发送和接收相关的多个部件(例如处理器、调制器、复用器、解调器、解复用器或天线等)。
基站102可以与一个或多个接入终端(例如接入终端116和接入终端122)通信。然而，可以理解，基站102可以与类似于接入终端116或122的任意数目的接入终端通信。接入终端116和122可以是例如蜂窝电话、智能电话、便携式电脑、手持通信装置、手持计算设备、卫星无线电装置、全球定位系统、PDA和/或用于在无线通信系统100上通信的任意其它适合设备。如图1所示，接入终端116与天线112和114通信，其中天线112和114通过前向链路118向接入终端116发送信息，并通过反向链路120从接入终端116接收信息。此外，接入终端122与天线104和106通信，其中天线104和106通过前向链路124向接入终端122发送信息，并通过反向链路126从接入终端122接收信息。在FDD(Frequency Division Duplex，频分双工)系统中，例如，前向链路118可利用与反向链路120所使用的不同频带，前向链路124可利用与反向链路126所使用的不同频带。此外，在TDD(Time Division Duplex，时分双工)系统中，前向链路118和反向链路120可使用共同频带，前向链路124和反向链路126可使用共同频带。
被设计用于通信的每组天线和/或区域称为基站102的扇区。例如，可将天线组设计为与基站102覆盖区域的扇区中的接入终端通信。在基站102通过前向链路118和124分别与接入终端116和122进行通信的过程中，基站102的发射天线可利用波束成形来改善前向链路118和124的信噪比。此外，与基站通过单个天线向它所有的接入终端发送信号的方式相比，在基站102利用波束成形向相关覆盖区域中随机分散的 接入终端116和122发送信号时，相邻小区中的移动设备会受到较少的干扰。
在给定时间，基站102、接入终端116或接入终端122可以是无线通信发送装置和/或无线通信接收装置。当发送数据时，无线通信发送装置可对数据进行编码以用于传输。具体地，无线通信发送装置可获取(例如生成、从其它通信装置接收、或在存储器中保存等)要通过信道发送至无线通信接收装置的一定数目的数据比特。这种数据比特可包含在数据的传输块(或多个传输块)中，传输块可被分段以产生多个码块。此外，无线通信发送装置可使用Polar码编码器(未示出)来对每个码块编码。
图2为本申请提供的一种极化Polar码的交织处理方法流程图。该交织处理方法包括：
S210、确定N个待编码比特，N为正整数；
具体地，可以根据M确定N,其中，M为Polar码输出的目标码长，M等于2的正整数次幂；
针对不进行速率匹配场景，N＝M；针对进行速率匹配场景，
Figure PCTCN2018091836-appb-000002
符号
Figure PCTCN2018091836-appb-000003
表示向上取整。
S220、获取包含N个极化信道序号的第一序列，第一序列用于指示N个极化信道的可靠度排序；
在一个实施例中，可以首先计算N个极化信道的可靠度，并根据可靠度大小对极化信道进行排序，进而获取用于指示N个极化信道的可靠度的第一序列，其中，第一序列中的元素用于指示极化信道的序号；
需要说明的是，上述可靠度的度量可以通过错误概率、互信息量、极化权重等反应，本发明对此不做限制。
在又一个实施例中，可以在存储器中通过表的形式预先存储不同的N值对应不同的第一序列，这样无需通过在线计算，通过查询存储器即可获取包含N个极化信道序号的第一序列，即获取当前母码码长N所对应的第一序列。
在又一个实施例中，可以在存储器中存储最大母码码长N max对应的最大可靠度序列，基于该最大可靠度序列确定当前母码码长N所对应的第一序列，该最大可靠度序列用于指示N max个极化信道的可靠度排序，N max为大于N的正整数。
S230、对该N个待编码比特进行Polar编码以得到编码比特；
具体地，可以使用Polar码的编码矩阵F N完成待编码比特的编码过程，进而得到Polar编码后的编码比特。
S240、根据第一序列对编码比特进行交织处理。
在本发明的一个实施例中，如图3所示，在S240步骤中，根据第一序列对编码比特进行交织处理包括：
S2401、将第一序列中元素输入交织器以得到交织序列；
在本发明实施例中，交织器具体可以是行列交织器，行列交织器的维数可以根据调制阶数确定，例如，行列交织器的行数或列数等于log 2(Mod)，其中，Mod用于指示调制阶数，比如，Mod＝16，行列交织器的行数等于4，Mod＝64，行列交织器的行数等 于6。
进一步，在本发明实施例中，交织器可以采用多种读取方式，例如，行进列出、行进行出、列进行出或列进列出、行进列ZIGZAG读取、列进列ZIGZAG读取等，其中，ZIGZAG读取用于指示“之字型”读取。下面给出了几种示例性的交织器的读取方式。
图4给出了按列分组读出的行列交织器，S为输入行列交织器的元素的数目，P为行列交织器的列数，由图4可知，在按列读出的过程中，每隔T列则反转列的读出顺序，其中，T可以是常数，也可以与调制阶数相关，如调制阶数为16QAM时，T可以为1、3或5等；如调制阶数为64QAM时，T为1、5、6或者32等，T为不大于(S/P)的正整数。
图5给出了按行读出的行列交织器，S为输入行列交织器的元素的数目，P为行列交织器的列数，由图5可知，在按行读出的过程中，每隔1行则反转行的读出顺序，即图中从右往左读，实际上，也可以按T行反转行的读出顺序，T为不大于(S/P)的正整数。
图6给出了按行从两边往中间读的行列交织器，即从最上一行读出之后，则跳到最后一行读出，然后又跳到最上面一行读出，以此读取，完成整个行列交织器的读取。
图7给出了按列从两边往中间读的行列交织器，即从最左一列读出之后，则跳到最右一列读出，然后又跳到最左一列读出，以此读取，完成整个行列交织器的读取。
针对按列读出的行列交织器，列读出后，可以进一步针对该列进行循环移位，每列的循环移位大小可以由函数确定，如5*i,或者f 1*i+f 2*i 2等，i为当前读出的列号,f 1和f 2为所采用的函数参数。
需要说明的是，交织器可以是行列交织器，也可以是QPP交织、同余交织、S-距离交织等其他交织器，本发明对于交织器的具体实现不做限定。
S2402、将该编码比特按照该交织序列进行排序以得到交织比特。
具体地，将Polar码编码后的编码比特按照交织序列排序以得到交织比特，交织比特即为输出的交织比特。例如，编码比特为(1100)，交织序列为(1324)，则输出的交织比特为(1010)。
在本发明的又一个实施例中，如图8所示，在S240步骤中，根据第一序列对编码比特进行交织处理包括：
S2403、将编码比特按照第一序列进行排序以得到排序后的编码比特；
S2404、将排序后的编码比特输入交织器以得到交织比特。
在图8所对应的实施例，针对排序后的编码比特是否进行速率匹配存在如下两种场景：
针对排序后的编码比特不进行速率匹配场景，将排序后的编码比特直接输入该交织器以得到交织比特；
针对排序后的编码比特进行速率匹配场景，首先将排序后的编码比特进行速率匹配以得到速率匹配后的编码比特，再将速率匹配后的编码比特输入该交织器以得到交织比特。
由上可知，在图8所对应的实施例中，首先将编码比特进行排序，然后考虑是否进行速率匹配，最后将排序的编码比特输入交织器以得到交织比特；实际上，也可以 首先考虑是否对编码比特进行速率匹配，然后将编码比特进行排序，最后将排序后的编码比特输入交织器以得到交织比特，图9对应的如下实施例即是描述该种情况。
在本发明的又一个实施例中，如图9所示，在S230步骤之后，该交织处理方法还包括：
S250、将编码比特进行速率匹配以得到速率匹配后的编码比特；
对应地，在S240步骤中，根据第一序列对编码比特进行交织处理包括：
S2405、将速率匹配后的编码比特按照第二序列进行排序以得到排序后的编码比特，其中，第二序列为从第一序列中获取的长度为M的序列，M为Polar码输出的目标码长且M为正整数；
S2406、将排序后的编码比特输入交织器以得到交织比特。
在本发明的有一个实施例中，如图10所示，在S240步骤中，根据第一序列对编码比特进行交织处理包括：
S2407、根据该N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
需要说明的是，非信息比特是指除了信息比特之外的比特。
S2408、将编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及将编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
需要说明的是，在本发明中，第一交织器和第二交织器可以是相同的交织器，也可以是不同的交织器，第一交织器与第二交织器的使用涉及到可能的三种情况：
一、当第一交织器与第二交织器相同时，即采用唯一一个交织器，第一编码比特与第二编码比特作为整体输入该交织器，整体可以是第一编码比特在前第二编码比特在后的顺序，或者第二编码比特在前，第一编码比特在后的顺序，输入该交织器中不足的位置对应补零。
二、当第一交织器与第二交织器不同时，即采用两个交织器，第一编码比特输入第一交织器，输入第一交织器中不足的位置对应补零，第二编码比特输入第二交织器，输入第二交织器中不足的位置对应补零。
三、当第一交织器与第二交织器不同时，即采用两个交织器，第一编码比特输入第一交织器，输入第一交织器中不足的位置开始进入第二编码比特，将剩余的第二编码比特输入第二交织器，输入第二交织器中不足的位置对应补零。
图10所对应的实施例描述的是编码比特不进行速率匹配场景，相应地，图11对应的如下实施例描述的是编码比特进行速率匹配场景。
在本发明的有一个实施例中，如图11所示，在S230步骤之后，该交织处理方法还包括：
S250、将编码比特进行速率匹配以得到速率匹配后的编码比特；
对应地，在S240步骤中，根据第一序列对编码比特进行交织处理包括：
S2409、根据N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
S2410、将速率匹配后的编码比特中位于信息比特的位置的第一编码比特输入第一 交织器以得到第一交织比特；以及将速率匹配后的编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
需要说明的是，第一交织器和第二交织器可以是相同的交织器，也可以是不同的交织器。
在本发明的又一个实施例中，如图12所示，在上述S230步骤中得到编码比特之后，由于编码比特的数量少于Polar码的目标码长M，可以通过重复编码的方式以达到目标码长，因此，在S230步骤之后，该交织处理方法还包括：
S260、对编码比特进行重复编码以得到(M-N)个重复比特，M为Polar码输出的目标码长且M为大于N的正整数；
其中，重复编码是指对编码比特进行扩展以实现目标码长M个编码比特，具体地，重复编码过程可以为从N个编码比特中选取(M-N)个编码比特作为重复比特，N个编码比特和(M-N)个重复比特即为目标码长M个编码比特。
需要说明的是，本发明对于如何从N个编码比特中选取(M-N)个编码比特作为重复比特不做限定。
S270、根据第一序列对重复比特进行排序以得到第二排序结果。
具体地，
Figure PCTCN2018091836-appb-000004
在L＝1时，将(M-N)个重复比特按照第二序列进行排序以得到第二排序结果，其中，第二序列为从第一序列中获取的长度为M-N的序列；进一步，在M-N＝N时，即第二序列的长度为N，此时第二序列和第一序列相同。
在L>1时，将(M-N)个重复比特划分成L段重复比特，前(L-1)段重复比特中每段重复比特按照第一序列进行排序，第L段重复比特按照第二序列进行排序，其中，前(L-1)段重复比特中每段重复比特的长度为N，第L段重复比特的长度为M-L*N，第二序列为从第一序列中获取的长度为M-L*N的序列；进一步，在第L段重复比特的长度为N时，第二序列的长度为N，此时第二序列和第一序列相同。
对应地，在S240步骤中，根据第一序列对编码比特进行交织处理包括：
S2411、将编码比特按照第一序列进行排序以得到第一排序结果。
在获取上述第一排序结果和第二排序结果之后，该交织处理方法还包括：
S280、将第一排序结果和第二排序结果进行交织处理以得到交织比特。
具体地，将第一排序结果和第二排序结果进行交织处理以得到交织比特包括：
将第一排序结果和第二排序结果依次输入交织器以得到交织比特；或者，
将第一排序结果输入第一交织器以得到第一交织比特；以及将第二排序结果输入第二交织器以得到第二交织比特，第一交织比特和第二交织比特组成输出的交织比特。
需要说明的是，第一交织器和第二交织器可以是相同的交织器，也可以是不同的交织器。
在上述实施例中，根据第一序列对Polar码编码后的编码比特进行交织处理，由于用于指示极化信道可靠度的第一序列为Polar码编码过程中已经存在的序列，因此，上述交织处理过程中无需使用额外的存储资源来存储第一序列，减少了存储资源的使用；并且根据已存在的第一序列来对编码比特进行交织处理，交织处理实现简单。
如下将结合图13来描述本发明实施例提供的极化Polar码交织处理装置1300，该交织处理装置1300包括：
确定模块1310，用于确定N个待编码比特，N为正整数；
具体地，可以根据M确定N,其中，M为Polar码输出的目标码长，M等于2的正整数次幂。针对不进行速率匹配场景，N＝M；针对进行速率匹配场景，
Figure PCTCN2018091836-appb-000005
符号
Figure PCTCN2018091836-appb-000006
表示向上取整。
获取模块1320，用于获取包含N个极化信道序号的第一序列，第一序列用于指示N个极化信道的可靠度排序；
极化编码模块1330，用于对N个待编码比特进行Polar编码以得到编码比特；
具体地，可以使用Polar码的编码矩阵F N完成待编码比特的编码过程，进而得到Polar编码后的编码比特。
交织模块1340，用于根据第一序列对该编码比特进行交织处理。
在本发明的一个实施例中，交织模块1340具体用于：
根据N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
将编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及
将编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
其中，第一交织器和第二交织器的使用可以参考方法实施例中相关描述，此处不再赘述。
在本发明的又一个实施例中，如图14所示，交织模块1340包括：
第一交织子模块1341，用于将第一序列中元素输入交织器以得到交织序列；
第二交织子模块1342，用于将编码比特按照该交织序列进行排序以得到交织比特。
在本发明的又一个实施例中，如图14所示，交织模块1340包括：
第一交织子模块1341，用于将编码比特按照第一序列进行排序以得到排序后的编码比特；
第二交织子模块1342，用于将排序后的编码比特输入交织器以得到交织比特。
进一步，第二交织子模块1342具体用于：
将排序后的编码比特直接输入交织器以得到交织比特；或者，
将排序后的编码比特进行速率匹配以得到速率匹配后的编码比特；将速率匹配后的编码比特输入交织器以得到交织比特。
在本发明的又一个实施例中，如图15所示，该交织处理装置1300还包括：
速率匹配模块1350，用于将编码比特进行速率匹配以得到速率匹配后的编码比特；
对应地，交织模块1340具体用于：
将速率匹配后的编码比特按照第二序列进行排序以得到排序后的编码比特，其中，第二序列为从第一序列中获取的长度为M的序列，M为Polar码输出的目标码长且M为正整数；
将排序后的编码比特输入交织器以得到交织比特。
在本发明的又一个实施例中，如图15所示，该交织处理装置1300还包括：
速率匹配模块1350，用于将编码比特进行速率匹配以得到速率匹配后的编码比特；
对应地，交织模块1340具体用于：
根据该N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
将速率匹配后的编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及
将速率匹配后的编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
在本发明的又一个实施例中，如图16所示，交织模块1340具体用于：
将编码比特按照第一序列进行排序以得到第一排序结果。
该交织处理装置1300还包括：
重复编码模块1360，用于对编码比特进行重复编码以得到(M-N)个重复比特，M为Polar码输出的目标码长且M为大于N的正整数；
排序模块1370，用于根据第一序列对重复比特进行排序以得到第二排序结果；
交织比特获取模块1380，用于将第一排序结果和第二排序结果进行交织处理以得到交织比特。
进一步，排序模块1370具体用于：
在L＝1时，将重复比特按照第二序列进行排序以得到第二排序结果，其中，第二序列为从第一序列中获取的长度为M-N的序列，
Figure PCTCN2018091836-appb-000007
在L>1时，将重复比特划分成L段重复比特，前(L-1)段重复比特中每段重复比特按照第一序列进行排序，第L段重复比特按照第二序列进行排序，其中，前(L-1)段重复比特中每段重复比特的长度为N，第L段重复比特的长度为M-L*N，第二序列为从第一序列中获取的长度为M-L*N的序列。
进一步，交织比特获取模块1380具体用于：
将第一排序结果和第二排序结果依次输入交织器以得到所述交织比特；或者，
将第一排序结果输入第一交织器以得到第一交织比特；以及将第二排序结果输入第二交织器以得到第二交织比特，第一交织比特和第二交织比特组成输出的交织比特。
在上述实施例中，Polar码交织处理装置根据第一序列对Polar码编码后的编码比特进行交织处理，由于用于指示极化信道可靠度的第一序列为Polar码编码过程中已经存在的序列，因此，上述交织处理过程中无需使用额外的存储资源来存储第一序列，减少了存储资源的使用；并且根据已存在的第一序列来对编码比特进行交织处理，交织处理实现简单。
参见图17a所示，为本发明实施例提供一种通信装置1700，用于实现对Polar码编码后的编码比特的交织处理，该通信装置1700包括：
处理装置1710，用于对收发器1720接收的数据进行处理；
收发器1720，用于接收或发送数据。
可选的，该通信装置还包括：
天线1730，收发器1720具体通过天线1730接收或发送数据。
当该处理装置1710通过软件实现时，参见图17a所示，该处理装置1710包括：
存储器1712，用于存储程序；
处理器1711，用于执行所述存储器存储的所述程序，当所述程序被执行时，执行上述方法实施例中的实现，例如图2或图8到图12中任一图所对应的方法实施例，具体请见前面方法实施例中的描述，在此不再对处理器1711的执行过程进行赘述。
上述存储器1712可以是物理上独立的单元，也可以与处理器1711集成在一起，具体参见图17b所示。
本申请实施例所说的通信装置，可以是接入点、站点、基站或者用户终端等无线通信装置。
本申请实施例所说的的Polar码，包括但不限于Arikan Polar码，还可以是CA-Polar码或者PC-Polar码。Arikan Polar是指原始的Polar码，没有与其它码级联，只有信息比特和冻结比特。CA-Polar码是Polar码级联了循环冗余校验(Cyclic Redundancy Check，简称CRC)的Polar码，PC-Polar码是Polar码级联了奇偶校验(Parity Check，简称PC)的码。PC-Polar和CA-Polar是通过级联不同的码来提高Polar码的性能。
本申请实施例描述的各示例的单元及方法过程，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如多个单元或组件可以结合或者可以集成到另一个系统，或一些步骤可以忽略，或不执行。此外，各个单元相互之间的耦合或直接耦合或通信连接可以是通过一些接口实现，这些可以是电性、机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，既可以位于一个地方，也可以分布到多个网络单元上。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储 介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。

Claims (28)

  1. 一种极化Polar码的交织处理方法，其特征在于，包括：
    确定N个待编码比特，N为正整数；
    获取包含N个极化信道序号的第一序列，所述第一序列用于指示N个极化信道的可靠度排序；
    对所述N个待编码比特进行Polar编码以得到编码比特；
    根据所述第一序列对所述编码比特进行交织处理。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述第一序列对所述编码比特进行交织处理包括：
    将第一序列中元素输入交织器以得到交织序列；
    将所述编码比特按照所述交织序列进行排序以得到交织比特。
  3. 根据权利要求1所述的方法，其特征在于，所述根据所述第一序列对所述编码比特进行交织处理包括：
    将所述编码比特按照第一序列进行排序以得到排序后的编码比特；
    将排序后的编码比特输入交织器以得到交织比特。
  4. 根据权利要求3所述的方法，其特征在于，所述将排序后的编码比特输入交织器以得到交织比特包括：
    将排序后的编码比特直接输入所述交织器以得到所述交织比特。
  5. 根据权利要求3所述的方法，其特征在于，所述将排序后的编码比特输入交织器以得到交织比特包括：
    将排序后的编码比特进行速率匹配以得到速率匹配后的编码比特；
    将速率匹配后的编码比特输入所述交织器以得到所述交织比特。
  6. 根据权利要求1所述的方法，其特征在于，在对所述N个待编码比特进行Polar编码以得到编码比特之后，所述方法还包括：
    将所述编码比特进行速率匹配以得到速率匹配后的编码比特；
    所述根据第一序列对所述编码比特进行交织处理包括：
    将速率匹配后的编码比特按照第二序列进行排序以得到排序后的编码比特，其中，第二序列为从第一序列中获取的长度为M的序列，M为Polar码输出的目标码长且M为正整数；
    将排序后的编码比特输入交织器以得到交织比特。
  7. 根据权利要求1所述的方法，其特征在于，所述根据第一序列对所述编码比特进行交织处理包括：
    根据所述N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
    将所述编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及
    将所述编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
  8. 根据权利要求1所述的方法，其特征在于，所述对所述N个待编码比特进行 Polar编码以得到编码比特之后，所述方法还包括：
    将所述编码比特进行速率匹配以得到速率匹配后的编码比特；
    所述根据第一序列对所述编码比特进行交织处理包括：
    根据所述N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
    将所述速率匹配后的编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及
    将所述速率匹配后的编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
  9. 根据权利要求1所述的方法，其特征在于，所述根据所述第一序列对所述编码比特进行交织处理包括：
    将所述编码比特按照第一序列进行排序以得到第一排序结果；
    所述对所述N个待编码比特进行Polar编码以得到编码比特之后，所述方法还包括：
    对所述编码比特进行重复编码以得到(M-N)个重复比特，M为Polar码输出的目标码长且M为大于N的正整数；
    根据所述第一序列对所述重复比特进行排序以得到第二排序结果；
    将第一排序结果和第二排序结果进行交织处理以得到交织比特。
  10. 根据权利要求9所述的方法，其特征在于，
    Figure PCTCN2018091836-appb-100001
    所述根据所述第一序列对所述重复比特进行排序以得到第二排序结果包括：
    在L＝1时，将所述重复比特按照第二序列进行排序以得到第二排序结果，其中，第二序列为从第一序列中获取的长度为M-N的序列；
    在L>1时，将所述重复比特划分成L段重复比特，前(L-1)段重复比特中每段重复比特按照第一序列进行排序，第L段重复比特按照第二序列进行排序，其中，前(L-1)段重复比特中每段重复比特的长度为N，第L段重复比特的长度为M-L*N，第二序列为从第一序列中获取的长度为M-L*N的序列。
  11. 根据权利要求9或10所述的方法，其特征在于，所述将第一排序结果和第二排序结果进行交织处理以得到交织比特包括：
    将第一排序结果和第二排序结果依次输入交织器以得到所述交织比特。
  12. 根据权利要求9或10所述的方法，其特征在于，所述将第一排序结果和第二排序结果进行交织处理以得到交织比特包括：
    将第一排序结果输入第一交织器以得到第一交织比特；以及
    将第二排序结果输入第二交织器以得到第二交织比特，所述第一交织比特和所述第二交织比特组成所述交织比特。
  13. 一种极化Polar码的交织处理装置，其特征在于，包括：
    确定模块，用于确定N个待编码比特，N为正整数；
    获取模块，用于获取包含N个极化信道序号的第一序列，所述第一序列用于指示N个极化信道的可靠度排序；
    极化编码模块，用于对所述N个待编码比特进行Polar编码以得到编码比特；
    交织模块，用于根据所述第一序列对所述编码比特进行交织处理。
  14. 根据权利要求13所述的装置，其特征在于，所述交织模块包括：
    第一交织子模块，用于将第一序列中元素输入交织器以得到交织序列；
    第二交织子模块，用于将所述编码比特按照所述交织序列进行排序以得到交织比特。
  15. 根据权利要求13所述的装置，其特征在于，所述交织模块包括：
    第一交织子模块，用于将所述编码比特按照第一序列进行排序以得到排序后的编码比特；
    第二交织子模块，用于将排序后的编码比特输入交织器以得到交织比特。
  16. 根据权利要求15所述的装置，其特征在于，所述第二交织子模块具体用于：
    将排序后的编码比特直接输入所述交织器以得到所述交织比特。
  17. 根据权利要求15所述的装置，其特征在于，所述第二交织子模块具体用于：
    将排序后的编码比特进行速率匹配以得到速率匹配后的编码比特；
    将速率匹配后的编码比特输入所述交织器以得到所述交织比特。
  18. 根据权利要求13所述的装置，其特征在于，所述装置还包括：
    速率匹配模块，用于将所述编码比特进行速率匹配以得到速率匹配后的编码比特；
    所述交织模块具体用于：
    将速率匹配后的编码比特按照第二序列进行排序以得到排序后的编码比特，其中，第二序列为从第一序列中获取的长度为M的序列，M为Polar码输出的目标码长且M为正整数；
    将排序后的编码比特输入交织器以得到交织比特。
  19. 根据权利要求13所述的装置，其特征在于，所述交织模块具体用于：
    根据所述N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
    将所述编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及
    将所述编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
  20. 根据权利要求13所述的装置，其特征在于，所述装置还包括：
    速率匹配模块，用于将所述编码比特进行速率匹配以得到速率匹配后的编码比特；
    所述交织模块具体用于：
    根据所述N个待编码比特中信息比特的数目K从第一序列中确定信息比特的位置和非信息比特的位置，K为小于或等于N的正整数；
    将所述速率匹配后的编码比特中位于信息比特的位置的第一编码比特输入第一交织器以得到第一交织比特；以及
    将所述速率匹配后的编码比特中位于非信息比特的位置的第二编码比特输入第二交织器以得到第二交织比特。
  21. 根据权利要求13所述的装置，其特征在于，所述交织模块具体用于：
    将所述编码比特按照第一序列进行排序以得到第一排序结果。
    所述装置还包括：
    重复编码模块，用于对所述编码比特进行重复编码以得到(M-N)个重复比特，M为Polar码输出的目标码长且M为大于N的正整数；
    排序模块，用于根据所述第一序列对所述重复比特进行排序以得到第二排序结果；
    交织比特获取模块，用于将第一排序结果和第二排序结果进行交织处理以得到交织比特。
  22. 根据权利要求21所述的装置，其特征在于，所述排序模块具体用于：
    在L＝1时，将所述重复比特按照第二序列进行排序以得到第二排序结果，其中，第二序列为从第一序列中获取的长度为M-N的序列，
    Figure PCTCN2018091836-appb-100002
    在L>1时，将所述重复比特划分成L段重复比特，前(L-1)段重复比特中每段重复比特按照第一序列进行排序，第L段重复比特按照第二序列进行排序，其中，前(L-1)段重复比特中每段重复比特的长度为N，第L段重复比特的长度为M-L*N，第二序列为从第一序列中获取的长度为M-L*N的序列。
  23. 根据权利要求21或22所述的装置，其特征在于，所述交织比特获取模块具体用于：
    将第一排序结果和第二排序结果依次输入交织器以得到所述交织比特。
  24. 根据权利要求21或22所述的装置，其特征在于，所述交织比特获取模块具体用于：
    将第一排序结果输入第一交织器以得到第一交织比特；以及
    将第二排序结果输入第二交织器以得到第二交织比特，所述第一交织比特和所述第二交织比特组成所述交织比特。
  25. 一种通信装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1-12中任一所述的步骤。
  26. 一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行如权利要求1-12任意一项所述的方法。
  27. 一种计算机程序产品，其特征在于，所述计算机程序包括指令，当所述指令在计算机上运行时，计算机执行如权利要求1-12中任一项所述的方法。
  28. 一种计算机程序，其特征在于，当其在计算机上运行时，计算机执行如权利要求1-12中任一项所述的方法。
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