WO2018228524A1 - 一种ssd控制芯片的中断控制方法、装置及ssd设备 - Google Patents

一种ssd控制芯片的中断控制方法、装置及ssd设备 Download PDF

Info

Publication number
WO2018228524A1
WO2018228524A1 PCT/CN2018/091471 CN2018091471W WO2018228524A1 WO 2018228524 A1 WO2018228524 A1 WO 2018228524A1 CN 2018091471 W CN2018091471 W CN 2018091471W WO 2018228524 A1 WO2018228524 A1 WO 2018228524A1
Authority
WO
WIPO (PCT)
Prior art keywords
interrupt
interrupt request
control chip
ssd
host
Prior art date
Application number
PCT/CN2018/091471
Other languages
English (en)
French (fr)
Inventor
夏杰旭
王凤海
杨骥
张建涛
王嵩
Original Assignee
北京紫光得瑞科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京紫光得瑞科技有限公司 filed Critical 北京紫光得瑞科技有限公司
Publication of WO2018228524A1 publication Critical patent/WO2018228524A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals

Definitions

  • the present invention relates to the field of data storage technologies, and in particular, to an interrupt control method, apparatus, and SSD device for an SSD control chip.
  • SSD Solid State Drives
  • SSDs have the same specifications and definitions, functions, and usage methods as those of ordinary hard disks, but their performance exceeds that of traditional hard disks by several orders of magnitude. As the capacity requirements of SSD storage increase, the desire for large-capacity SSDs is growing.
  • the invention provides an interrupt control method and device for an SSD control chip and an SSD device, which can effectively reduce a certain number of repeated interrupts, thereby reducing the CPU overhead and improving the overall performance of the SSD.
  • One aspect of the present invention provides an interrupt control method for an SSD control chip, the method comprising:
  • the main state machine When it is detected that the SSD control chip sends an interrupt request to the host, determining a current state of the preset main state machine, the main state machine is configured to enter a transmission interrupt state after the SSD control chip sends an interrupt request to the host ;
  • the interrupt request is intercepted so that it cannot continue to be sent to the host.
  • the method further includes:
  • the interrupt request is sent to the host, and the master state machine is controlled to enter a transmit interrupt state until the interrupt request transmission is completed.
  • the monitoring the interrupt request of the SSD control chip includes:
  • the interrupt request corresponding to the task in the same interrupt queue sent by the SSD control chip is monitored.
  • the method before the intercepting the interrupt request, the method further includes:
  • the intercepting the interrupt request specifically includes: intercepting an interrupt request with an invalid interrupt request identifier.
  • an interrupt control apparatus for an SSD control chip comprising:
  • a monitoring module for monitoring an interrupt request of the SSD control chip
  • a determining module configured to determine a current state of a preset primary state machine when the SSD control chip is detected to send an interrupt request to the host, where the primary state machine is configured to send an interrupt request to the host at the SSD control chip After entering the transmission interrupt state;
  • the control module is configured to intercept the interrupt request, if the result of the determination by the determining module is that the primary state machine is in a sending interrupt state, so that the continuous state cannot be sent to the host.
  • control module is further configured to: if the determination result of the determining module is that the primary state machine is not a transmission interrupt state, send the interrupt request to a host, and control the primary state machine to enter and send The state is interrupted until the interrupt request is sent.
  • the monitoring module is specifically configured to monitor, by the SSD control chip, an interrupt request corresponding to a task in the same interrupt queue.
  • the device further includes:
  • An identifier module configured to identify the interrupt request as an invalid interrupt request before the intercepting the interrupt request
  • control module is specifically configured to intercept an interrupt request with an invalid interrupt request identifier.
  • an embodiment of the present invention further provides an SSD device, where the SSD device includes an SSD control chip and an interrupt control device of the SSD control chip as described above;
  • the interrupt control device of the SSD control chip monitors an interrupt request sent by the SSD control chip, and when detecting that the SSD control chip sends an interrupt request to the host, determining a current state of the preset main state machine, the main state
  • the machine is configured to enter a transmit interrupt state after the SSD control chip sends an interrupt request to the host, and when the primary state machine is in a transmit interrupt state, intercept the interrupt request so that it cannot continue to send to the host.
  • the method, device and SSD device for interrupt control of the SSD control chip provided by the embodiment of the present invention monitor the interrupt request of the SSD control chip, so as to intercept the interrupt request of the repeated transmission, so that the interrupt cannot be continuously sent to the host, and further Effectively reduce a certain number of repeated interrupts to reduce CPU overhead and improve the overall performance of the SSD.
  • FIG. 1 is a flowchart of an interrupt control method of an SSD control chip according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an interrupt control apparatus of an SSD control chip according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing an implementation of interrupt control of a SSD control chip by a conventional SSD device
  • FIG. 5 is a schematic diagram of an implementation of interrupt control of an SSD control chip implemented by an SSD device according to an embodiment of the present invention.
  • FIG. 1 is a flow chart schematically showing an interrupt control method of an SSD control chip according to an embodiment of the present invention.
  • the method for interrupt control of an SSD control chip according to an embodiment of the present invention specifically includes the following steps:
  • the SSD control chip When it is detected that the SSD control chip sends an interrupt request to the host, determine a current state of the preset main state machine, where the main state machine is disposed inside the chip, and is configured to send the SSD control chip to the host. After the interrupt request, enter the transmission interrupt state;
  • the interrupt control method of the SSD control chip monitors the interrupt request of the SSD control chip, so as to intercept the interrupt request of the repeated transmission, so that the interrupt cannot be continuously sent to the host, thereby effectively reducing the number. Repeated interrupts to reduce the CPU overhead and improve the overall performance of the SSD.
  • the interrupt request is sent to the host, and the primary state machine is controlled to enter a transmission interrupt state until the interrupt request transmission is completed.
  • the interrupt request sent by the SSD control chip when the interrupt request sent by the SSD control chip is detected, if the interrupt request does not belong to the interrupt request for repeated transmission, that is, the preset main state machine is not in the transmission interrupt state, according to the normal interrupt operation flow, The interrupt request is sent to the host, and the main state machine is controlled to enter a transmission interrupt state until the interrupt request transmission is completed, so that the interrupt request for repeated transmission is intercepted, and the interrupt request for repeated transmission is intercepted.
  • FIG. 2 is a timing diagram of implementing repeated interrupt reduction in an embodiment of the present invention. Referring to Figure 2, it can be seen from the timing diagram that after the queue Queue 1 has issued an interrupt request, the default primary state machine will enter the transmit interrupt state, and if in the transmit interrupt state, the queue Queue 1 has another interrupt. The request, the interrupt request will be intercepted, that is, it can not continue to send to the host, and then considered invalid.
  • the embodiment of the present invention specifically monitors an interrupt request corresponding to a task in the same interrupt queue sent by the SSD control chip, so as to implement an interrupt request for the SSD control chip.
  • the method before the intercepting the interrupt request, the method further includes:
  • the intercepting the interrupt request specifically includes: intercepting an interrupt request with an invalid interrupt request identifier.
  • the storage medium of the SSD is a non-reliable NAND, it is possible to find a large number of bits different from the written data in one read operation, so that it is first necessary to try these erroneous data.
  • ECC error correction if the error correction fails, you will need to use raid to recover. If you still can't, you need to try to read it again and other remedial measures. These remedies take a certain amount of time.
  • the scenario is simulated as follows:
  • the host Host sends a read command in a queue Queue.
  • the host Host sends a write command in the queue Queue.
  • the processing time required for the write command is short and Fixed, so in the worst case of a read error, the interrupt processing module will first receive an interrupt request for a late write command, and then immediately receive an interrupt request for the previous read command during the send interrupt, in this case Next, the interrupt request for the read command is identified as an invalid interrupt request.
  • the interrupt control method of the SSD control chip provided by the embodiment of the present invention is simple in implementation and easy to understand; the host host does not need to be modified, is easy to implement, and has low cost, if multiple highs are inserted in one Host When performance SSDs, the reduced CPU load can be significant.
  • FIG. 3 is a schematic block diagram showing the structure of an interrupt control device of an SSD control chip according to an embodiment of the present invention.
  • the interrupt control apparatus of the SSD control chip of the embodiment of the present invention specifically includes a monitoring module 301, a determining module 302, and a control module 303, where:
  • the monitoring module 301 is configured to monitor an interrupt request of the SSD control chip
  • the determining module 302 is configured to determine, when the SSD control chip sends an interrupt request to the host, a current state of the preset primary state machine, where the primary state machine is configured to send an interrupt to the host at the SSD control chip. After the request, the transmission interrupt status is entered;
  • the control module 303 is configured to: if the determination result of the determining module 302 is that the primary state machine is in a sending interrupt state, intercept the interrupt request, so that the terminal state cannot be continuously sent to the host.
  • control module 303 is further configured to: if the determination result of the determining module 502 is that the primary state machine is not in a sending interrupt state, send the interrupt request to the host, And controlling the main state machine to enter a transmission interrupt state until the interrupt request transmission is completed.
  • the monitoring module 301 is specifically configured to monitor an interrupt request corresponding to a task in the same interrupt queue sent by the SSD control chip.
  • the apparatus further includes an identification module not shown in the figure, the identification module, configured to identify the interrupt request as invalid before the intercepting the interrupt request Interrupt request
  • control module 303 is specifically configured to intercept an interrupt request with an invalid interrupt request identifier.
  • the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.
  • an embodiment of the present invention further provides an SSD device, where the SSD device includes an SSD control chip and an interrupt control device of the SSD control chip provided by any of the above embodiments.
  • the interrupt control device of the SSD control chip monitors the interrupt request sent by the SSD control chip, and when the SSD control chip detects that the interrupt request is sent to the host, determines the current state of the preset main state machine.
  • the primary state machine is configured to enter a transmit interrupt state after the SSD control chip sends an interrupt request to the host, and when the primary state machine is in a transmit interrupt state, intercept the interrupt request to prevent the host from continuing to the host. send.
  • the conventional SSD device does not reduce the repeated interrupts during the interrupt control process of the SSD control chip, so the CPU on the host side must process a large number of interrupt requests, increase CPU overhead, and affect the performance of the SSD device.
  • the interrupt request that is repeatedly sent is intercepted, so that the interrupt cannot be continuously sent to the host, so that a certain amount of interrupt can be reduced to reduce the invalidity of the CPU.
  • 4 is a schematic diagram of an implementation of interrupt control of a SSD control chip by a conventional SSD device.
  • FIG. 5 is a schematic diagram of an implementation of interrupt control of an SSD control chip implemented by an SSD device according to an embodiment of the present invention.
  • the method, device and SSD device for interrupt control of the SSD control chip provided by the embodiment of the present invention monitor the interrupt request of the SSD control chip, so as to intercept the interrupt request of the repeated transmission, so that the interrupt cannot be continuously sent to the host, and further Effectively reduce a certain number of repeated interrupts to reduce CPU overhead and improve the overall performance of the SSD.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

本发明提供了一种SSD控制芯片的中断控制方法、装置及SSD设备，所述方法包括：对SSD控制芯片的中断请求进行监测；当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态；若所述主状态机为发送中断状态，则拦截所述中断请求，使其无法继续向主机发送。本发明实施例提出的SSD控制芯片的中断控制方法、装置及SSD设备，能够有效地减少一定数量的重复中断，以减少CPU的无效开销，提升SSD的整体性能。

Description

一种SSD控制芯片的中断控制方法、装置及SSD设备 技术领域
本发明涉及数据存储技术领域，尤其涉及一种SSD控制芯片的中断控制方法、装置及SSD设备。
背景技术
SSD(Solid State Drives，固态硬盘)由固态电子存储芯片阵列而制成的硬盘，由主控芯片和存储单元组成。固态硬盘在接口的规范和定义、功能及使用方法上与普通硬盘的完全相同，但是性能超越了传统硬盘几个数量级。随着SSD存储的容量需求越来越大，对于大容量SSD的渴求越来越旺盛。
但是，随着当前大容量高速固态硬盘发展迅速，IOPS(Input/Output Per Second，每秒进行读写I/O操作的次数)性能已经达到百万级，而且延迟也越来越低，SSD在进行数据读写操作时，每个IO的完成都需要SSD发送中断给Host，Host CPU需要不停的停下正在处理中的任务而去响应中断。由于SSD的IOPS()性能是传统硬盘的IOPS性能的指数倍，大量的IO的产生大量的重复中断，导致Host CPU需要足够的运算性能来处理这些中断，从而增加了Host CPU的无效开销，影响SSD的整体性能，在多个高性能SSD并发大量IO的时候尤为明显。
发明内容
本发明提出了一种SSD控制芯片的中断控制方法、装置及SSD设备，能够有效地减少一定数量的重复中断，以减少CPU的无效开销，提升SSD的整体性能。
为解决上述技术问题，本发明采用如下技术方案：
本发明的一个方面，提供了一种SSD控制芯片的中断控制方法，该方法包括：
对SSD控制芯片的中断请求进行监测；
当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态；
若所述主状态机为发送中断状态，则拦截所述中断请求，使其无法继续向主机发送。
可选地，所述方法还包括：
若所述主状态机不是发送中断状态，则将所述中断请求发送到主机，并控制所述主状态机进入发送中断状态，直到所述中断请求发送完成。
可选地，所述对SSD控制芯片的中断请求进行监测，包括：
对所述SSD控制芯片发送的属于同一中断队列中的任务对应的中断请求进行监测。
可选地，在所述拦截所述中断请求之前，所述方法还包括：
将所述中断请求标识为无效中断请求；
拦截所述中断请求，具体包括：拦截具有无效中断请求标识的中断请求。
本发明的又一个方面，提供了一种SSD控制芯片的中断控制装置，该装置包括：
监测模块，用于对SSD控制芯片的中断请求进行监测；
判定模块，用于当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态；
控制模块，用于若所述判定模块的判定结果为所述主状态机为发送中断状态时，拦截所述中断请求，使其无法继续向主机发送。
可选地，所述控制模块，还用于若所述判定模块的判定结果为所述主状态机不是发送中断状态时，将所述中断请求发送到主机，并控制所述主状态机进入发送中断状态，直到所述中断请求发送完成。
可选地，所述监测模块，具体用于对所述SSD控制芯片发送的属于同一中断队列中的任务对应的中断请求进行监测。
可选地，所述装置还包括：
标识模块，用于在所述拦截所述中断请求之前，将所述中断请求标识为无效中断请求；
相应的，所述控制模块，具体用于拦截具有无效中断请求标识的中断请求。
此外，本发明实施例还提供了一种SSD设备，该SSD设备包括SSD控制芯片以及如上所述的SSD控制芯片的中断控制装置；
所述SSD控制芯片的中断控制装置对SSD控制芯片发送的中断请求进行监测，当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机 被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态，当所述主状态机为发送中断状态时，拦截所述中断请求，使其无法继续向主机发送。
与现有技术相比，本发明技术方案主要的优点如下：
本发明实施例提供的SSD控制芯片的中断控制方法、装置及SSD设备，通过对SSD控制芯片的中断请求进行监测，以实现对重复发送的中断请求进行拦截，使其无法继续向主机发送，进而有效地减少一定数量的重复中断，以减少CPU的无效开销，提升SSD的整体性能。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1为本发明实施例的一种SSD控制芯片的中断控制方法的流程图；
图2为本发明实施例中实现重复中断减少的时序图；
图3为本发明实施例的一种SSD控制芯片的中断控制装置的结构示意图；
图4为传统SSD设备实现SSD控制芯片的中断控制的实现原理图；
图5为本发明实施例中SSD设备实现SSD控制芯片的中断控制的实现原理图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和 科学术语)，具有与本发明所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非被特定定义，否则不会用理想化或过于正式的含义来解释。
图1示意性示出了本发明一个实施例的SSD控制芯片的中断控制方法的流程图。参照图1，本发明实施例的SSD控制芯片的中断控制方法具体包括以下步骤：
S11、对SSD控制芯片的中断请求进行监测；
S12、当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机设置于芯片内部，被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态；
S13、若所述主状态机为发送中断状态，则拦截所述中断请求，使其无法继续向主机发送。
本发明实施例提供的SSD控制芯片的中断控制方法，通过对SSD控制芯片的中断请求进行监测，以实现对重复发送的中断请求进行拦截，使其无法继续向主机发送，进而有效地减少一定数量的重复中断，以减少CPU的无效开销，提升SSD的整体性能。
本发明实施例中，若所述主状态机不是发送中断状态，则将所述中断请求发送到主机，并控制所述主状态机进入发送中断状态，直到所述中断请求发送完成。
本实施例中，当监测到SSD控制芯片发送的中断请求时，如果该中断请求不属于重复发送的中断请求，即预设的主状态机没有处于发送中断状态，则按照正常中断操作流程，将中断请求发送到主机，并控制所述主状态机进入发送中断状态，直到所述中断请求发送完成，以便再次监测到重复发送的中断请求时，实现对重复发送的中断请求进行拦截。
图2为本发明实施例中实现重复中断减少的时序图。参见图2，从时序图里看出，在队列Queue 1已经发出中断请求后，预设的主状态机就会进入发送中断状态，而如果在发送中断状态中，队列Queue 1又来了一次中断请求，此次中断申请就会被拦截，即无法继续向主机发送，进而认作无效。
其中，本发明实施例具体通过对所述SSD控制芯片发送的属于同一中断队列中的任务对应的中断请求进行监测，以实现对SSD控制芯片的中断请求进行监测。
在一个可选实施例中，在所述拦截所述中断请求之前，所述方法还包括：
将所述中断请求标识为无效中断请求；
拦截所述中断请求，具体包括：拦截具有无效中断请求标识的中断请求。
在一个具体实施例中，由于SSD的存储介质是并不太可靠的NAND，所以就有可能在一次读操作时发现大量的与写入数据不相同的bit，这样首先会需要把这些错误数据尝试用ECC纠错，如果纠错失败，就会需要使用raid来恢复，如果还不行，就需要尝试再读一次等补救措施，这些补救措施都需要耗费一定时间。
场景模拟如下：
主机Host在一个队列Queue里发了一个读命令，在SSD正在处理这个读命令，并且需要纠错时，主机Host又在这个队列Queue里发了一个写命令，由于写命令需要的处理时间短并且固定，所以在读出错的最坏情况下，中断处理模块会先收到晚来的写命令的中断申请，而后在发送中断过程中，马上又收到了之前的读命令的中断申请，在这种情况下，读命令的中断申请就会被标识为无效中断请求。
需要说明的是，以上示例只是用于帮助理解的一种可应用场景，更有可能在实际中会出现的是主机Host在一个队列Queue里压了一连串的任务，例如，任务数为100，可能其中3号任务和50号任务的中断申请是一起来的，则3号任务和50号任务对应的中断请求被判定为重复中断请求，后者会被标识为无效中断请求，并被拦截，使其无法发送到主机，进而减少主机的CPU负载。
本发明实施例的提供的SSD控制芯片的中断控制方法，实际应用实现简单，原理容易理解；对于Host主机而言无需做任何改动，易实现、成本低，如果在一个Host上插有多个高性能SSD时，减少的CPU负载会非常可观。
对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明实施例并不受所描述的动作顺序的限制，因为依据本发明实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本发明实施例所必须的。
图3示意性示出了本发明一个实施例的SSD控制芯片的中断控制装置的结构示意图。参照图3，本发明实施例的SSD控制芯片的中断控制装置具体包括监测模块301、判定模块302以及控制模块303，其中：
监测模块301，用于对SSD控制芯片的中断请求进行监测；
判定模块302，用于当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态；
控制模块303，用于若所述判定模块302的判定结果为所述主状态机为发送中断状态时，拦截所述中断请求，使其无法继续向主机发送。
在本发明的一个可选实施例中，所述控制模块303，还用于若所述判定模块502的判定结果为所述主状态机不是发送中断状态时，将所述中断请求发送到主机，并控制所述主状态机进入发送中断状态，直到所述中断请求发送完成。
本发明实施例中，所述监测模块301，具体用于对所述SSD控制芯片发送的属于同一中断队列中的任务对应的中断请求进行监测。
在本发明的一个可选实施例中，所述装置还包括附图中未示出的标识模块，该标识模块，用于在所述拦截所述中断请求之前，将所述中断请求标识为无效中断请求；
进一步地，所述控制模块303，具体用于拦截具有无效中断请求标识的中断请求。
对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
此外，本发明实施例还提供了一种SSD设备，该SSD设备包括SSD控制芯片以及如上任一实施例提供的SSD控制芯片的中断控制装置。
本实施例中，该SSD控制芯片的中断控制装置通过对SSD控制芯片发送的中断请求进行监测，当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态，当所述主状态机为发送中断状态时，拦截所述中断请求，使其无法继续向主机发送。
对比图4与图5，可知传统SSD设备实现SSD控制芯片的中断控制过程中并没有对重复中断进行减少，所以主机侧的CPU一定会处理大量的中断请求，增加CPU开销，影响SSD设备性能。而本发明实施例中SSD设备实现SSD控制芯片的中断控制中，对重复发送的中断请求进行拦截，使其无法继续向主机发送，就可以减少一定量的中断，来减少CPU的无效开销。其中，图4为传统SSD设备实现SSD控制芯片的中断控制的实现原理图。图5为本发明实施例中SSD设备实现SSD控制芯片的中断控制的实现原理图。
与现有技术相比，本发明技术方案主要的优点如下：
本发明实施例提供的SSD控制芯片的中断控制方法、装置及SSD设备，通过对SSD控制芯片的中断请求进行监测，以实现对重复发送的中断请求进行拦截，使其无法继续向主机发送，进而有效地减少一定数量的重复中断，以减少CPU的无效开销，提升SSD的整体性 能。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、装置(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (9)

  1. 一种SSD控制芯片的中断控制方法，其特征在于，该方法包括:
    对SSD控制芯片的中断请求进行监测；
    当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态；
    若所述主状态机为发送中断状态，则拦截所述中断请求，使其无法继续向主机发送。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    若所述主状态机不是发送中断状态，则将所述中断请求发送到主机，并控制所述主状态机进入发送中断状态，直到所述中断请求发送完成。
  3. 根据权利要求1或2所述的方法，其特征在于，所述对SSD控制芯片的中断请求进行监测，包括：
    对所述SSD控制芯片发送的属于同一中断队列中的任务对应的中断请求进行监测。
  4. 根据权利要求1所述的方法，其特征在于，在所述拦截所述中断请求之前，所述方法还包括：
    将所述中断请求标识为无效中断请求；
    拦截所述中断请求，具体包括：拦截具有无效中断请求标识的中断请求。
  5. 一种SSD控制芯片的中断控制装置，其特征在于，该装置包括:
    监测模块，用于对SSD控制芯片的中断请求进行监测；
    判定模块，用于当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态；
    控制模块，用于若所述判定模块的判定结果为所述主状态机为发送中断状态时，拦截所述中断请求，使其无法继续向主机发送。
  6. 根据权利要求5所述的装置，其特征在于，所述控制模块，还用于若所述判定模块的判定结果为所述主状态机不是发送中断状态时，将所述中断请求发送到主机，并控制所述主状态机进入发送中断状态，直到所述中断请求发送完成。
  7. 根据权利要求5或6所述的装置，其特征在于，所述监测模块，具体用于对所述SSD 控制芯片发送的属于同一中断队列中的任务对应的中断请求进行监测。
  8. 根据权利要求5所述的装置，其特征在于，所述装置还包括：
    标识模块，用于在所述拦截所述中断请求之前，将所述中断请求标识为无效中断请求；
    相应的，所述控制模块，具体用于拦截具有无效中断请求标识的中断请求。
  9. 一种SSD设备，其特征在于，该SSD设备包括SSD控制芯片以及如权利要求5-8任一项所述的SSD控制芯片的中断控制装置；
    所述SSD控制芯片的中断控制装置对SSD控制芯片发送的中断请求进行监测，当监测到所述SSD控制芯片向主机发送中断请求时，判断预设的主状态机的当前状态，所述主状态机被配置为在所述SSD控制芯片向主机发送中断请求后进入发送中断状态，当所述主状态机为发送中断状态时，拦截所述中断请求，使其无法继续向主机发送。
PCT/CN2018/091471 2017-06-16 2018-06-15 一种ssd控制芯片的中断控制方法、装置及ssd设备 WO2018228524A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710457168.9 2017-06-16
CN201710457168.9A CN107273198B (zh) 2017-06-16 2017-06-16 一种ssd控制芯片的中断控制方法、装置及ssd设备

Publications (1)

Publication Number Publication Date
WO2018228524A1 true WO2018228524A1 (zh) 2018-12-20

Family

ID=60066785

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/091471 WO2018228524A1 (zh) 2017-06-16 2018-06-15 一种ssd控制芯片的中断控制方法、装置及ssd设备

Country Status (2)

Country Link
CN (1) CN107273198B (zh)
WO (1) WO2018228524A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107273198B (zh) * 2017-06-16 2018-12-18 北京得瑞领新科技有限公司 一种ssd控制芯片的中断控制方法、装置及ssd设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1086329A (zh) * 1992-10-02 1994-05-04 国际商业机器公司 控制数据传送的接口电路
CN102855156A (zh) * 2011-06-30 2013-01-02 重庆重邮信科通信技术有限公司 一种中断控制器及中断控制方法
US8635379B2 (en) * 2010-05-07 2014-01-21 Samsung Electronics Co., Ltd Data storage device and method of operating the same
CN105095128A (zh) * 2014-05-22 2015-11-25 中兴通讯股份有限公司 中断处理方法及中断控制器
CN107273198A (zh) * 2017-06-16 2017-10-20 北京得瑞领新科技有限公司 一种ssd控制芯片的中断控制方法、装置及ssd设备

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7062684B2 (en) * 2002-12-19 2006-06-13 International Business Machines Corporation Enabling tracing of a repeat instruction
CN101876953B (zh) * 2009-11-30 2012-05-30 成都市华为赛门铁克科技有限公司 提升硬盘与主机交互效率的方法、装置及系统
CN104123179A (zh) * 2013-04-29 2014-10-29 敦南科技股份有限公司 中断控制方法及其电子系统
KR20170032502A (ko) * 2015-09-14 2017-03-23 삼성전자주식회사 스토리지 장치 및 그것의 인터럽트 발생 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1086329A (zh) * 1992-10-02 1994-05-04 国际商业机器公司 控制数据传送的接口电路
US8635379B2 (en) * 2010-05-07 2014-01-21 Samsung Electronics Co., Ltd Data storage device and method of operating the same
CN102855156A (zh) * 2011-06-30 2013-01-02 重庆重邮信科通信技术有限公司 一种中断控制器及中断控制方法
CN105095128A (zh) * 2014-05-22 2015-11-25 中兴通讯股份有限公司 中断处理方法及中断控制器
CN107273198A (zh) * 2017-06-16 2017-10-20 北京得瑞领新科技有限公司 一种ssd控制芯片的中断控制方法、装置及ssd设备

Also Published As

Publication number Publication date
CN107273198B (zh) 2018-12-18
CN107273198A (zh) 2017-10-20

Similar Documents

Publication Publication Date Title
US11095315B1 (en) Intelligent error correction in a storage device
US10261853B1 (en) Dynamic replication error retry and recovery
US10459661B2 (en) Stream identifier based storage system for managing an array of SSDs
US10282250B1 (en) Apparatus and method for a coherent, efficient, and configurable cyclic redundancy check retry implementation for synchronous dynamic random access memory
KR101541132B1 (ko) 크로스 바운더리 하이브리드 및 다이나믹 저장 장치 및 메모리 상황 인식 캐시 시스템
US8843663B2 (en) Data transmission device and method for merging multiple commands
KR20170131738A (ko) 적응 인터럽트 제어를 수행하는 컴퓨터 시스템 및 그것의 인터럽트 제어 방법
US20140195708A1 (en) Determining when to throttle interrupts to limit interrupt processing to an interrupt processing time period
US10645164B1 (en) Consistent latency for solid state drives
WO2021104383A1 (zh) 数据备份的方法和装置、设备和存储介质
US20180120918A1 (en) Storage device and method of controlling link state thereof
CN109840047A (zh) 一种降低读延时的方法及装置
US10089041B2 (en) Efficient connection management in a SAS target
WO2021174698A1 (zh) 虚拟机快照创建方法、装置、存储介质及计算机设备
US9377966B2 (en) Method and apparatus for efficiently processing storage commands
CN108153582B (zh) Io命令处理方法与介质接口控制器
WO2018228524A1 (zh) 一种ssd控制芯片的中断控制方法、装置及ssd设备
CN105556462A (zh) 写入文件和文件元数据
US10599530B2 (en) Method and apparatus for recovering in-memory data processing system
US10534683B2 (en) Communicating outstanding maintenance tasks to improve disk data integrity
US9063669B2 (en) Self-detecting storage bottleneck while handling sequential I/O operations
TW202207041A (zh) 儲存裝置及對邏輯區塊位址中的重疊進行檢查的方法
JP2011192053A (ja) ディスクアレイ装置、ディスクアレイシステム、及びキャッシュ制御方法
WO2020042388A1 (zh) 一种提升固态硬盘顺序读性能的方法
CN112506675A (zh) 任务完成系统

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18816858

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18816858

Country of ref document: EP

Kind code of ref document: A1