WO2018214670A1 - 一种极性控制的方法及装置 - Google Patents

一种极性控制的方法及装置 Download PDF

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Publication number
WO2018214670A1
WO2018214670A1 PCT/CN2018/083227 CN2018083227W WO2018214670A1 WO 2018214670 A1 WO2018214670 A1 WO 2018214670A1 CN 2018083227 W CN2018083227 W CN 2018083227W WO 2018214670 A1 WO2018214670 A1 WO 2018214670A1
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polarity
polarity control
integrated circuit
data line
control signals
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PCT/CN2018/083227
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English (en)
French (fr)
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许益祯
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Publication of WO2018214670A1 publication Critical patent/WO2018214670A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • Some embodiments of the present disclosure are directed to a method and apparatus for polarity control.
  • each of the source driver ICs in the related art includes a plurality of output terminals, and each of the output terminals is respectively connected to one data line.
  • the data lines include odd data lines and even data lines, and the polarity output of the data lines is controlled by a polarity control signal (POL).
  • POL polarity control signal
  • Some embodiments of the present disclosure provide a polarity control method including: a time control integrated circuit outputs at least two polarity control signals to a source driving integrated circuit; and a source driving integrated circuit according to the received at least two polarity control signals, Polarity output control is performed on at least two pre-delimited packet data lines such that data lines of corresponding packets controlled by each of the at least two polarity control signals are polarity inverted at different times.
  • the pre-delimited packets include: odd-numbered data line packets, even-numbered data line packets.
  • the polarity control signal includes a first polarity control signal and a second polarity control signal
  • the outputting the at least two polarity control signals to the source driving integrated circuit includes: corresponding to an odd numbered
  • the data line group outputs the first polarity control signal
  • the second polarity control signal is output corresponding to the data line group numbered even.
  • the method further includes: when the data line performs polarity inversion according to the polarity control signal, the DC power source supplies an inversion current to the data line that performs the polarity inversion.
  • the inverting the polarity of the data lines of the corresponding packets controlled by each of the at least two polarity control signals at different times comprises: controlling each of the at least two polarity control signals The data lines of the corresponding group are reversed in polarity at different times of one data frame length.
  • the time interval at which the polarity of the data line of the corresponding packet controlled by each of the at least two polarity control signals is reversed is half a frame length.
  • a polarity control apparatus including a time control integrated circuit and at least one source drive integrated circuit, wherein the time control integrated circuit is configured to: output at least two polarity control signals to the source drive integrated circuit;
  • the at least one source driving integrated circuit is configured to perform polarity output control on the at least two pre-delimited packet data lines according to the received at least two polarity control signals such that each of the at least two polarity control signals The data lines of the corresponding controlled packets are polarity inverted at different times.
  • the pre-delimited packets include: odd-numbered data line packets, even-numbered data line packets.
  • the polarity control signal includes a first polarity control signal and a second polarity control signal, the time control integrated circuit configured to: output the number corresponding to the data line grouping numbered odd A polarity control signal outputs the second polarity control signal corresponding to the data line group numbered even.
  • the apparatus further includes a DC circuit, wherein the DC current is configured to: perform data of the polarity inversion when the data line performs polarity inversion according to the polarity control signal The line provides a reverse current.
  • the source driving integrated circuit is configured to perform polarity output control on at least two pre-delimited packetized data lines according to the received at least two polarity control signals to be controlled by at least two polarities
  • the data lines of the corresponding packets of each control in the signal are polarity inverted at different times of the length of one data frame.
  • the time interval at which the polarity of the data line of the corresponding packet controlled by each of the at least two polarity control signals is reversed is half a frame length.
  • Figure 1 is a schematic diagram of the control of the output polarity of a pin using a POL
  • FIG. 2 is a schematic diagram showing the relationship between a polarity control signal and data
  • 3 is a schematic circuit diagram of performing polarity output control
  • FIG. 4 is a flow chart of a method of polarity control according to an embodiment of the present disclosure
  • FIG. 5 is a circuit diagram of control of output polarity by two POLs according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of signals for controlling output polarity by two POLs according to an embodiment of the present disclosure
  • FIG. 7 is a structural block diagram of a device for polarity control according to an embodiment of the present disclosure.
  • Figure 1 is a schematic diagram of the control of the output polarity using a POL.
  • a time control integrated circuit outputs a POL to each of the signal input terminals of each of the source driver integrated circuits, and a DC circuit (DC-DC IC) supplies a reverse output voltage of the polarity output to the source driver integrated circuit.
  • Figure 2 is a schematic diagram showing the relationship between the polarity control signal and the data. As shown in Fig. 2, when each frame of data is input, the output polarity of the data lines connected to all the output terminals is controlled by one POL.
  • Figure 3 is a schematic diagram of a circuit for performing polarity output control. As shown in Figure 3, the output polarity of the data line is controlled by only one POL.
  • the DC circuit When the output polarity changes (for example, when the POL has a falling edge and the output polarity changes), the DC circuit provides all the data lines. The reverse current of the polarity reversal occurs, and the instantaneous current peak occurs. The instantaneous current peak affects the reference voltage, causing a voltage ripple on the reference voltage.
  • the driving voltage refers to the reference voltage to drive the liquid crystal. If the voltage ripple occurs in the reference voltage, the line residual phenomenon will be caused, which will affect the display effect.
  • FIG. 4 is a flow chart of a method of polarity control in accordance with an embodiment of the present disclosure. As shown in FIG. 4, the method includes:
  • Step 400 The time control integrated circuit outputs at least two polarity control signals (POL) to the source driving integrated circuit.
  • POL polarity control signals
  • time control integrated circuit is the same for the output of different numbers of polarity control signals, and are not described herein.
  • Step 401 The source driving integrated circuit performs polarity output control on the data lines of the at least two pre-delimited packets according to the received at least two POLs, so that the corresponding group controlled by each of the at least two polarity control signals The data lines are polarity inverted at different times.
  • the timing of the polarity inversion can be controlled according to the polarity control signal. For example, with the falling edge as the moment of polarity inversion, when the falling edges of at least two POLs are at different times, the data lines of different groups can be reversed at different times by different POLs, thereby avoiding all data. The line simultaneously extracts the current peak caused by the reverse current.
  • Polarization inversion at different times in one embodiment of the present disclosure includes polarity inversion at different times of a data frame length.
  • a pre-delimited packet of one embodiment of the present disclosure includes: an odd-numbered data line packet, and an even-numbered data line packet.
  • the embodiments of the present disclosure may also be grouped in other manners.
  • the odd-numbered data lines are grouped into at least two packets according to the source driver integrated circuit to which the data lines are connected.
  • the packet of the data line numbered even is subdivided into at least two packets.
  • the POL of one embodiment of the present disclosure includes a first POL and a second POL, and outputting two POLs to the source driving integrated circuit includes: outputting a first POL to the odd-numbered data line group, and outputting the data line grouped to the even-numbered data line Second POL.
  • the time interval at which the first POL and the second POL control data line perform polarity inversion may be set to have a time interval of half a frame length.
  • the method of one embodiment of the present disclosure further includes: when the data line is inverted in polarity according to the POL, the reverse current is supplied from the DC power source to the data line that performs polarity inversion.
  • FIG. 5 is a circuit diagram showing control of output polarity by two POLs in accordance with one embodiment of the present disclosure.
  • two POLs are respectively transmitted to the source driver integrated circuit to perform polarity output control of the data lines. Since the timings of polarity inversion of the two POL control data lines are different, the data lines of different groups are output. When the polarity is changed, there is a time interval between the DC circuit and the data line to supply the reverse current, thereby avoiding the influence of the instantaneous current peak on the reference voltage.
  • FIG. 6 is a schematic diagram of signals for controlling the output polarity by two POLs according to an embodiment of the present disclosure. As shown in FIG. 6, the control of the polarity output is completed by POL1 and POL2 for one frame of data through different POLs.
  • the technical solution of the present disclosure includes: the time control integrated circuit outputs at least two polarity control signals (POL) to the source driving integrated circuit, and the source driving integrated circuit pairs at least two pre-delimited grouped data lines according to the received at least two POL pairs
  • the polarity output control is performed such that the data lines of the corresponding packets controlled by the at least two polarity control signals are polarity inverted at different times.
  • the embodiments of the present disclosure avoid the instantaneous current peak caused by the simultaneous polarity output of the data lines, thereby avoiding the line afterimage phenomenon caused by the instantaneous current peak.
  • FIG. 7 is a structural block diagram of a device for polarity control according to an embodiment of the present disclosure. As shown in FIG. 7, the apparatus includes a time control integrated circuit and at least one source drive integrated circuit.
  • the time control integrated circuit is configured to output at least two polarity control signals (POL) to the source driver integrated circuit.
  • POL polarity control signals
  • POL1, POL2, etc. represent at least two POLs.
  • the implementation principle of the time control integrated circuit is the same for outputting different numbers of polarity control signals, and details are not described herein.
  • the time control integrated circuit outputs the at least two polarity control signals to the source driving integrated circuit including: the time control integrated circuit outputs at least two polarity control signals to the source driving integrated circuit within one data frame length.
  • the source driving integrated circuit is configured to perform polarity output control on at least two pre-delimited packet data lines according to the received at least two POLs to enable data of corresponding groups controlled by each of the at least two polarity control signals The line is reversed at different times.
  • the timing of the polarity inversion can be controlled according to the polarity control signal. For example, with the falling edge as the moment of polarity inversion, when the falling edges of at least two POLs are at different times, the data lines of different groups can be reversed at different times by different POLs, thereby avoiding all data. The line simultaneously extracts the current peak caused by the reverse current.
  • the source driving integrated circuit of one embodiment of the present disclosure is configured to perform polarity output control on the data lines of the pre-delimited packets according to the received polarity control signals, so that the data lines of different groups are at different times of one data frame length. Perform polarity reversal.
  • the pre-defined packet of the embodiment of the present disclosure includes: an odd-numbered data line group, and an even-numbered data line group.
  • the embodiments of the present disclosure may also be grouped in other manners.
  • the odd-numbered data lines are grouped into at least two packets according to the source driver integrated circuit to which the data lines are connected.
  • the packet of the data line numbered even is subdivided into at least two packets.
  • the POL of one embodiment of the present disclosure includes a first POL and a second POL, and the time control integrated circuit is configured to output a first POL for the odd-numbered data line group and a second POL for the even-numbered data line group .
  • the time interval at which the first POL and the second POL control data line perform polarity inversion may be set to have a time interval of half a frame length.
  • the apparatus of one embodiment of the present disclosure further includes: a direct current circuit.
  • the DC current is configured such that when the data line is inverted in polarity according to the POL, a reverse current is supplied to the data line that performs polarity inversion.
  • the technical solution of the present disclosure includes: the time control integrated circuit outputs at least two polarity control signals (POL) to the source driving integrated circuit; and the source driving integrated circuit pairs at least two pre-delimited data lines according to the received at least two POL pairs
  • the polarity output control is performed such that the data lines of the corresponding packets controlled by each of the at least two polarity control signals are polarity inverted at different times.
  • the embodiment of the present disclosure avoids the instantaneous current peak caused by the polarity output of the data line at the same time, thereby avoiding the line afterimage phenomenon caused by the instantaneous current peak.
  • each module/unit in the foregoing embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, being executed by a processor and stored in a memory. Programs/instructions to implement their respective functions.
  • the present disclosure is not limited to any specific form of combination of hardware and software.

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Abstract

一种极性控制的方法及装置。极性控制的方法包括：时间控制集成电路向源驱动集成电路输出至少两个极性控制信号（400）；源驱动集成电路根据接收的至少两个极性控制信号，对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在不同时刻进行极性反转（401）。避免了数据线同时进行极性输出造成瞬间电流峰值，进而避免了由瞬间电流峰值造成的线残像现象。

Description

一种极性控制的方法及装置
本申请要求于2017年5月25日递交的中国专利申请第201710380128.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的一些实施例涉及一种极性控制的方法及装置。
背景技术
目前，相关技术中每一个源驱动器集成电路(Source driver IC)包含若干个输出端，每一个输出端分别连接一根数据线。数据线包括奇数数据线和偶数数据线，数据线的极性输出由一个极性控制信号(POL)进行控制。
发明内容
本公开的一些实施例提供了一种极性控制方法，包括：时间控制集成电路向源驱动集成电路输出至少两个极性控制信号；源驱动集成电路根据接收的至少两个极性控制信号，对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在不同时刻进行极性反转。
在一些示例中，所述预先划定的分组包括：编号为奇数的数据线分组，编号为偶数的数据线分组。
在一些示例中，所述极性控制信号包括第一极性控制信号和第二极性控制信号，所述向源驱动集成电路输出至少两个极性控制信号包括：对应于编号为奇数的所述数据线分组输出所述第一极性控制信号，对应于编号为偶数的所述数据线分组输出所述第二极性控制信号。
在一些示例中，所述方法还包括：所述数据线根据所述极性控制信号进行极性反转时，直流电源向进行所述极性反转的数据线提供反转电流。
在一些示例中，所述使由至少两个极性控制信号中的每个控制的对应分 组的数据线在不同时刻进行极性反转包括：由至少两个极性控制信号中的每个控制的对应分组的数据线在一个数据帧长的不同时刻进行极性反转。
在一些示例中,由至少两个极性控制信号中的每个控制的对应分组的数据线进行极性反转的时刻的时间间隔是半个帧长。
本公开的一些实施例提供一种极性控制装置，包括时间控制集成电路和至少一个源驱动集成电路，其中，时间控制集成电路配置为：向源驱动集成电路输出至少两个极性控制信号；至少一个源驱动集成电路配置为：根据接收的至少两个极性控制信号对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在不同时刻进行极性反转。
在一些示例中,所述预先划定的分组包括：编号为奇数的数据线分组，编号为偶数的数据线分组。
在一些示例中，所述极性控制信号包括第一极性控制信号和第二极性控制信号，所述时间控制集成电路配置为：对应于编号为奇数的所述数据线分组输出所述第一极性控制信号，对应于编号为偶数的所述数据线分组输出所述第二极性控制信号。
在一些示例中,所述装置还包括直流电路，其中，所述直流电流配置为：所述数据线根据所述极性控制信号进行极性反转时，向进行所述极性反转的数据线提供反转电流。
在一些示例中,所述源驱动集成电路配置为：根据接收的至少两个极性控制信号对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在一个数据帧长的不同时刻进行极性反转。
在一些示例中,由至少两个极性控制信号中的每个控制的对应分组的数据线进行极性反转的时刻的时间间隔是半个帧长。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为采用一个POL进行管脚的输出极性的控制的示意图；
图2为极性控制信号和数据的关系示意图；
图3为进行极性输出控制的电路示意图；
图4为本公开的一个实施例的极性控制的方法的流程图；
图5为本公开的一个实施例的由两个POL实现输出极性的控制的电路示意图；
图6为本公开的一个实施例的由两个POL实现输出极性的控制的信号示意图；
图7为本公开的一个实施例的极性控制的装置的结构框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1为采用一个POL进行输出极性的控制的示意图。如图1所示，由时间控制集成电路向每一个源驱动器集成电路的信号输入端分别输出一个POL，直流电路(DC-DC IC)为源驱动器集成电路提供极性输出的反转电压。图2为极性控制信号和数据的关系示意图。如图2所示，每一帧数据输入时，由一个POL对所有输出端连接的数据线的输出极性进行控制。图3为进行极性输出控制的电路示意图。如图3所示，只由一个POL进行数据线的输出极性的控制，当输出极性发生变更(例如、当POL出现下降沿，输出极性发生改变)时，直流电路为所有数据线提供进行极性反转的反转电流，此时会出现瞬间电流峰值，瞬间电流峰值会影响参考电压，从而造成参考电压出现电压纹波(ripple)。而驱动电压参考参考电压来驱动液晶，如果参考电压出现电压纹波，则会造成线残像现象，影响显示效果。
图4为本公开的一个实施例的极性控制的方法的流程图。如图4所示，该方法包括：
步骤400、时间控制集成电路向源驱动集成电路输出至少两个极性控制信号(POL)。
需要说明的是，本公开实施例对输出不同个数的极性控制信号，时间控制集成电路的实现原理相同，在此不做赘述。
步骤401、源驱动集成电路根据接收的至少两个POL对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在不同时刻进行极性反转。
需要说明的是，极性反转的时刻可以根据极性控制信号进行控制。例如，以下降沿作为极性反转的时刻，则至少两个POL的下降沿在不同时间时，通过不同的POL可以实现不同分组的数据线在不同时刻进行极性反转，从而避免所有数据线同时抽取反转电流造成的电流峰值。
本公开的一个实施例在不同时刻进行极性反转包括：在一个数据帧长的不同时刻进行极性反转。
本公开的一个实施例预先划定的分组包括：编号为奇数的数据线分组，编号为偶数的数据线分组。
需要说明的是，本公开的实施例还可以采用其他方式进行分组。例如，将编号为奇数的数据线分组，按照数据线所连接的源驱动集成电路的不同划分为至少两个分组。同理，将编号是偶数的数据线的分组再次细分为至少两个分组。对不同的分组采用不同的POL后，由于各分组进行极性反转的时刻不同，因此，各分组数据线在进行极性反转时不会出现所有数据线同时抽取反转电流造成的电流峰值。
本公开的一个实施例的POL包括第一POL和第二POL，向源驱动集成电路输出两个POL包括：对编号为奇数的数据线分组输出第一POL，对编号为偶数的数据线分组输出第二POL。
本公开的实施例的POL包括第一POL和第二POL时，可以设置第一POL与第二POL控制数据线进行极性反转的时间存在半个帧长的时间间隔。
本公开的一个实施例的方法还包括：数据线根据POL进行极性反转时，由直流电源向进行极性反转的数据线提供反转电流。
图5为本公开的一个实施例由两个POL实现输出极性的控制的电路示意图。如图5所示，两个POL分别传输至源驱动器集成电路，进行数据线的极 性输出控制，由于两个POL控制数据线进行极性反转的时刻不同，因此不同分组的数据线在输出极性发生变更时，从直流电路向数据线提供反转电流的时间存在间隔，从而避免了由于瞬间电流峰值对参考电压的影响。图6为本公开的一个实施例的由两个POL实现输出极性的控制的信号示意图。如图6所示，由POL1和POL2对一帧数据通过不同的POL完成极性输出的控制。
本公开的技术方案包括：时间控制集成电路向源驱动集成电路输出至少两个极性控制信号(POL)，源驱动集成电路根据接收的至少两个POL对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号控制的对应分组的数据线在不同时刻进行极性反转。本公开的实施例避免了数据线同时进行极性输出造成瞬间电流峰值，进而避免了由瞬间电流峰值造成的线残像现象。
图7为本公开的一个实施例的极性控制的装置的结构框图。如图7所示，该装置包括：时间控制集成电路和至少一个源驱动集成电路。
时间控制集成电路配置为：向源驱动集成电路输出至少两个极性控制信号(POL)。图中POL1、POL2等表示至少两个POL。
需要说明的是，本公开的一个实施例对输出不同个数的极性控制信号，时间控制集成电路的实现原理相同，在此不做赘述。这里，时间控制集成电路向源驱动集成电路输出至少两个极性控制信号包括：在一个数据帧长内，时间控制集成电路向源驱动集成电路输出至少两个极性控制信号。
源驱动集成电路配置为：根据接收的至少两个POL对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号的每个控制的对应分组的数据线在不同时刻进行极性反转。
需要说明的是，极性反转的时刻可以根据极性控制信号进行控制。例如，以下降沿作为极性反转的时刻，则至少两个POL的下降沿在不同时间时，通过不同的POL可以实现不同分组的数据线在不同时刻进行极性反转，从而避免所有数据线同时抽取反转电流造成的电流峰值。
本公开的一个实施例的源驱动集成电路配置为：根据接收的极性控制信号对预先划定分组的数据线进行极性输出控制，以使不同分组的数据线在一个数据帧长的不同时刻进行极性反转。
可选的，本公开实施例预先划定的分组包括：编号为奇数的数据线分组， 编号为偶数的数据线分组。
需要说明的是，本公开实施例还可以采用其他方式进行分组。例如，将编号为奇数的数据线分组，按照数据线所连接的源驱动集成电路的不同划分为至少两个分组。同理，将编号是偶数的数据线的分组再次细分为至少两个分组。对不同的分组采用不同的POL后，由于各分组进行极性反转的时刻不同，各分组数据线在进行极性反转时不会出现所有数据线同时抽取反转电流造成的电流峰值。
本公开的一个实施例的POL包括第一POL和第二POL，并且时间控制集成电路配置为：对编号为奇数的数据线分组输出第一POL，对编号为偶数的数据线分组输出第二POL。
本公开的实施例的POL包括第一POL和第二POL时，可以设置第一POL与第二POL控制数据线进行极性反转的时间存在半个帧长的时间间隔。
本公开的一个实施例的装置还包括：直流电路。直流电流配置为：数据线根据POL进行极性反转时，向进行极性反转的数据线提供反转电流。
本公开的技术方案包括：时间控制集成电路向源驱动集成电路输出至少两个极性控制信号(POL)；源驱动集成电路根据接收的至少两个POL对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在不同时刻进行极性反转。本公开实施例避免了数据线同时进行极性输出造成瞬间电流峰值，进而避免了由瞬间电流峰值造成的线残像现象。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的每个模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本公开不限制于任何特定形式的硬件和软件的结合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (13)

  1. 一种极性控制方法，包括：
    时间控制集成电路向源驱动集成电路输出至少两个极性控制信号；
    源驱动集成电路根据接收的至少两个极性控制信号，对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在不同时刻进行极性反转。
  2. 根据权利要求1所述的方法，其中，所述预先划定的分组包括：编号为奇数的数据线分组，编号为偶数的数据线分组。
  3. 根据权利要求2所述的方法，其中，所述极性控制信号包括第一极性控制信号和第二极性控制信号，所述向源驱动集成电路输出至少两个极性控制信号包括：
    对应于编号为奇数的所述数据线分组输出所述第一极性控制信号，对应于编号为偶数的所述数据线分组输出所述第二极性控制信号。
  4. 根据权利要求1或2所述的方法，还包括：所述数据线根据所述极性控制信号进行极性反转时，直流电源向进行所述极性反转的数据线提供反转电流。
  5. 根据权利要求1～3任一项所述的方法，其中，所述使由至少两个极性控制信号中的每个控制的对应分组的数据线在不同时刻进行极性反转包括：
    由至少两个极性控制信号中的每个控制的对应分组的数据线在一个数据帧长的不同时刻进行极性反转。
  6. 根据权利要求5所述的方法，其中，由至少两个极性控制信号中的每个控制的对应分组的数据线进行极性反转的时刻的时间间隔是半个帧长。
  7. 一种极性控制装置，包括时间控制集成电路和至少一个源驱动集成电路，其中，
    时间控制集成电路配置为：向源驱动集成电路输出至少两个极性控制信号；
    至少一个源驱动集成电路配置为：根据接收的至少两个极性控制信号对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在不同时刻进行极性反转。
  8. 根据权利要求7所述的装置，其中，所述预先划定的分组包括：编号为奇数的数据线分组，编号为偶数的数据线分组。
  9. 根据权利要求8所述的装置，其中，所述极性控制信号包括第一极性控制信号和第二极性控制信号，所述时间控制集成电路配置为：
    对应于编号为奇数的所述数据线分组输出所述第一极性控制信号，对应于编号为偶数的所述数据线分组输出所述第二极性控制信号。
  10. 根据权利要求7或8所述的装置，还包括直流电路，其中，所述直流电流配置为：所述数据线根据所述极性控制信号进行极性反转时，向进行所述极性反转的数据线提供反转电流。
  11. 根据权利要求7～9任一项所述的装置，其中，所述源驱动集成电路配置为：根据接收的至少两个极性控制信号对至少两个预先划定分组的数据线进行极性输出控制，以使由至少两个极性控制信号中的每个控制的对应分组的数据线在一个数据帧长的不同时刻进行极性反转。
  12. 根据权利要求11所述的装置，其中，由至少两个极性控制信号中的每个控制的对应分组的数据线进行极性反转的时刻的时间间隔是半个帧长。
  13. 一种显示装置，包括权利要求7-12中任一项所述的极性控制装置。
PCT/CN2018/083227 2017-05-25 2018-04-16 一种极性控制的方法及装置 WO2018214670A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335721B1 (en) * 1998-03-27 2002-01-01 Hyundai Electronics Industries Co., Ltd. LCD source driver
CN101118326A (zh) * 2006-08-02 2008-02-06 奇景光电股份有限公司 像素结构的电压极性的控制方法及电路
CN101556769A (zh) * 2008-04-10 2009-10-14 奇美电子股份有限公司 液晶显示面板的数据线信号极性转换控制装置及其方法
CN102629453A (zh) * 2011-05-25 2012-08-08 京东方科技集团股份有限公司 液晶显示器面板极性反转驱动方法及装置
CN102789771A (zh) * 2012-08-03 2012-11-21 京东方科技集团股份有限公司 极性反转信号转换方法、装置及显示器
CN102930840A (zh) * 2012-08-09 2013-02-13 京东方科技集团股份有限公司 液晶显示驱动电路及其驱动方法、液晶显示器
CN106960664A (zh) * 2017-05-25 2017-07-18 重庆京东方光电科技有限公司 一种实现极性控制的方法及装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103208265B (zh) * 2013-04-15 2015-08-19 合肥京东方光电科技有限公司 液晶显示器件极性反转驱动方法、装置及液晶显示器件

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335721B1 (en) * 1998-03-27 2002-01-01 Hyundai Electronics Industries Co., Ltd. LCD source driver
CN101118326A (zh) * 2006-08-02 2008-02-06 奇景光电股份有限公司 像素结构的电压极性的控制方法及电路
CN101556769A (zh) * 2008-04-10 2009-10-14 奇美电子股份有限公司 液晶显示面板的数据线信号极性转换控制装置及其方法
CN102629453A (zh) * 2011-05-25 2012-08-08 京东方科技集团股份有限公司 液晶显示器面板极性反转驱动方法及装置
CN102789771A (zh) * 2012-08-03 2012-11-21 京东方科技集团股份有限公司 极性反转信号转换方法、装置及显示器
CN102930840A (zh) * 2012-08-09 2013-02-13 京东方科技集团股份有限公司 液晶显示驱动电路及其驱动方法、液晶显示器
CN106960664A (zh) * 2017-05-25 2017-07-18 重庆京东方光电科技有限公司 一种实现极性控制的方法及装置

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