WO2018214491A1 - 阵列基板、显示装置及其驱动方法 - Google Patents

阵列基板、显示装置及其驱动方法 Download PDF

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WO2018214491A1
WO2018214491A1 PCT/CN2017/117476 CN2017117476W WO2018214491A1 WO 2018214491 A1 WO2018214491 A1 WO 2018214491A1 CN 2017117476 W CN2017117476 W CN 2017117476W WO 2018214491 A1 WO2018214491 A1 WO 2018214491A1
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Prior art keywords
thin film
film transistor
electrode
array substrate
source
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PCT/CN2017/117476
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English (en)
French (fr)
Inventor
尚建兴
吴东琨
毛敏
王彦强
刘琨
李晓东
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/073,077 priority Critical patent/US10775659B2/en
Publication of WO2018214491A1 publication Critical patent/WO2018214491A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a display device, and a driving method of the display device.
  • touch has become an indispensable feature of smart display devices. Therefore, the touch screen which can be used for both display and touch operation is widely used in intelligent display devices such as mobile phones, tablets, and notebook computers.
  • touch technology includes different technical directions such as optical, resistive, capacitive, and electromagnetic touch technologies; among many touch technologies, capacitive touch technology relies on its low cost and excellent user experience. Has become the mainstream of touch technology.
  • Capacitive touch calculation can be divided into two types: self-capacitance and mutual capacitance.
  • Embodiments of the present disclosure provide an array substrate, a display device, and a driving method thereof.
  • the array substrate includes a base substrate and a first thin film transistor, a second thin film transistor, a data line, a first electrode, and a second electrode disposed on the base substrate.
  • the first thin film transistor includes a first source and a first drain; the second thin film transistor includes a second source and a second drain; the first source and the second source are respectively connected to the data line, the first drain and The first electrode is connected, the second source is connected to the second electrode, the first electrode is a pixel electrode, and the second electrode is a touch electrode.
  • the array substrate can simultaneously implement display functions and touch functions.
  • At least one embodiment of the present disclosure provides an array substrate including: a substrate substrate; and a first thin film transistor, a second thin film transistor, a data line, a first electrode, and a second electrode disposed on the substrate
  • the first thin film transistor includes a first source and a first drain
  • the second thin film transistor includes a second source and a second drain, and the first source and the second source respectively
  • the data lines are connected, the first drain is connected to the first electrode, and the second drain is connected to the second electrode, the first An extremely pixel electrode, the second electrode being a common electrode.
  • the second electrode is multiplexed into a common electrode.
  • a ratio of the number of the first thin film transistors to the second thin film transistors is greater than or equal to 1:1.
  • the array substrate further includes: a third thin film transistor and a fourth thin film transistor disposed on the base substrate and located in the peripheral region, the third thin film The transistor includes a third source and a third drain, the fourth thin film transistor includes a fourth source and a fourth drain, the third source is configured to be connected to the display driving circuit, the fourth source And being connected to the touch driving circuit, wherein the third drain and the fourth drain are respectively connected to the data line.
  • the data line is configured to load a display data signal, a touch signal, and a common voltage signal.
  • an array substrate provided by an embodiment of the present disclosure further includes a storage electrode disposed in the same layer as the second electrode, an orthographic projection of the storage electrode on the substrate substrate and the first electrode in the lining The orthographic projections on the base substrate at least partially overlap.
  • the first thin film transistor and the second thin film transistor are disposed in the same layer.
  • the first source, the second source, and the data line are formed by one patterning process.
  • an array substrate further includes: a passivation layer disposed on a side of the first thin film transistor and the second thin film transistor away from the base substrate; and an insulating layer disposed at the Between the first electrode and the second electrode, the first electrode is disposed on a side of the passivation layer away from the substrate, and the second electrode is disposed on the insulating layer away from the lining One side of the base substrate.
  • the first electrode is connected to the first drain through a first via in the passivation layer, and the second electrode passes the passivation A second via in the layer is connected to the second via in a third via in the insulating layer.
  • an array substrate provided by an embodiment of the present disclosure further includes: a first gate line; and a second gate line, the first thin film transistor further includes a first gate, and the second thin film transistor further includes a second gate The first gate is connected to the first gate line, and the second gate is connected to the second gate line.
  • the first gate line is disposed in parallel with the second gate line.
  • the first thin film transistor further includes a first active layer, and the first active layer is disposed at the first gate and the first source And the second thin film transistor further includes a second active layer disposed at the second gate and the second source and the first Between the two drains.
  • At least one embodiment of the present disclosure provides a display device including the array substrate of any of the above.
  • a display device further includes: a first driver configured to provide a display data signal, a touch signal, and a common voltage signal for the data line in time series; and a second driver configured to be timed
  • the first thin film transistor and the second thin film transistor are turned on or off.
  • At least one embodiment of the present disclosure provides a driving method of a display device, comprising the array substrate according to any one of the above, the driving method comprising: applying display data to the data line in a first time period Signaling and conducting the first thin film transistor, disconnecting the second thin film transistor, the data line transmitting the display data signal to the first electrode through the first thin film transistor; in a second time period Applying a touch signal to the data line and disconnecting the second thin film transistor to turn on the second thin film transistor, the data line transmitting the touch signal to the a second electrode; and a third time period, applying a common voltage signal to the data line, the data line transmitting the common voltage signal to the second electrode through the second thin film transistor.
  • 1 is a schematic plan view of an array substrate
  • FIG. 2 is a schematic plan view of a touch electrode structure
  • 3A is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • 3B is a schematic plan view of another array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of an array substrate along the AA' direction of FIG. 3A according to an embodiment of the present disclosure. intention;
  • FIG. 5 is a schematic plan view of another array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic plan view of another array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of another display device according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic flow chart of a driving method of a display device according to an embodiment of the present disclosure.
  • the touch screen may include an on-cell touch screen and an in-cell touch screen.
  • the external touch panel is disposed between the color film substrate and the polarizing plate of the liquid crystal panel. Therefore, the external touch screen is relatively heavy, and it is difficult to meet the demand for slimness of the intelligent display device.
  • the in-cell touch panel has a touch sensor disposed inside the liquid crystal panel, and the outer layer can be attached only to a layer of protective glass, thereby having the advantages of high transmittance, high bonding ratio, and lightness and thinness.
  • Figure 1 shows an array substrate.
  • the array substrate includes a thin film transistor 10, a gate line 20, a data line 50, a pixel electrode 30, and a common electrode 40 which are disposed on a base substrate.
  • the thin film transistor 10 includes a gate electrode 12, an active layer 14, a source electrode 16, and a drain electrode 18.
  • the gate 12 is electrically connected to the gate line 20.
  • the gate 12 and the gate line 20 can be patterned by the same conductive layer.
  • the source 16 is electrically connected to the data line 50.
  • the source 16 and the data line 50 can also be electrically conductive. Layer patterning is obtained. Thereby, the array substrate can load the display signal to the pixel electrode through the data line row by row through the scanning of the gate line No., so that the display function can be realized.
  • the common electrode 40 is a slit electrode
  • the pixel electrode 30 is a plate-mounted electrode or a slit electrode
  • the common electrode 40 is located on a side of the pixel electrode 30 opposite to the substrate, that is, the pixel electrode 30 is away from the substrate. One side.
  • FIG. 2 shows a touch electrode structure.
  • the touch electrode structure includes a plurality of touch electrodes 45 disposed in an array, and the plurality of touch electrodes 45 are respectively connected to the plurality of signal transmission lines 46 .
  • the principle of the touch electrode structure is that a plurality of touch electrodes 45 are disposed in the same layer and insulated from each other; each touch electrode 45 can be connected to the touch detection chip through the signal transmission line 46.
  • the capacitance of the respective capacitor electrodes is a fixed value; when a touch occurs, the capacitance of the touch electrode 45 corresponding to the touch position is a fixed value superimposed on the human body capacitance, and the touch detection chip detects each touch electrode by detecting The change in the capacitance value of 45 can determine the touch position.
  • Embodiments of the present disclosure provide an array substrate, a display device, and a driving method thereof.
  • the array substrate includes a base substrate and a first thin film transistor, a second thin film transistor, a data line, a first electrode, and a second electrode disposed on the base substrate.
  • the first thin film transistor includes a first source and a first drain; the second thin film transistor includes a second source and a second drain; the first source and the second source are respectively connected to the data line, the first drain and The first electrode is connected, the second drain is connected to the second electrode, the first electrode is a pixel electrode, and the second electrode is a touch electrode.
  • the array substrate can load the signal on the data line to the first electrode and the second electrode in a time-sharing manner through the first thin film transistor and the second thin film transistor, thereby simultaneously implementing the display function and the touch function. Moreover, the array substrate does not need to additionally provide a touch metal layer and a touch signal line, thereby reducing the number of mask processes of the array substrate, thereby reducing the cost of the array substrate.
  • FIG. 3A shows an array substrate according to the present embodiment.
  • the array substrate includes a base substrate 101 including a display area 1010 and a peripheral area 1011 surrounding the display area 1010, and a first film disposed on the base substrate 101 and located in the display area 1010.
  • the transistor 110, the second thin film transistor 120, the data line 150, the first electrode 130, and the second electrode 140 are included in the display area 1010.
  • the first thin film transistor 110 includes a first source 116 and a first drain 118; the second thin film transistor 120 includes a second source 126 and a second drain 128; the first source 116 and the second source 126 are respectively associated with data
  • the lines 150 are connected, the first drain 118 is connected to the first electrode 130, and the second source 128 is connected to the second electrode 140.
  • the first source 116 of the first thin film transistor 110 and the second source 126 of the second thin film transistor 120 disposed adjacently in the extending direction of the data line 150 are connected to the same data line 150.
  • the first source 116 and the second source 126 are respectively connected to the data line 150, the first drain 118 is connected to the first electrode 130, and the second drain 128 and the first The two electrodes 140 are connected, the first electrode 130 is a pixel electrode, and the second electrode 140 is a touch electrode.
  • the array substrate can load the signal on the data line to the first electrode and the second electrode through the first thin film transistor and the second thin film transistor, thereby simultaneously implementing the display function and the touch.
  • the signal on the data line can be loaded to the first electrode, and the data line can be loaded by displaying the display data signal, thereby realizing the display function;
  • the signal on the data line can be loaded to the second electrode.
  • the touch signal and the common voltage signal can be loaded by the time division on the data line, thereby realizing the display function. Simultaneously implement the touch function.
  • the array substrate does not need to additionally provide a touch metal layer and a touch signal line, thereby reducing the number of mask processes of the array substrate, thereby reducing the cost of the array substrate.
  • the second electrode is multiplexed into a common electrode. That is to say, in the embodiment of the present disclosure, the second electrode can serve as a common electrode for forming an electric field with the pixel electrode when used for display, or a touch electrode for performing touch.
  • the array substrate further includes a storage electrode 145 disposed in the same layer as the second electrode 140, and an orthographic projection of the storage electrode 145 on the substrate 101.
  • the orthographic projections of the first electrodes 130 on the substrate substrate 101 at least partially overlap.
  • the storage electrode 145 and the first electrode 130 may constitute a storage capacitor to store a display data signal on the first electrode.
  • the storage electrode 145 may be disposed in parallel with the data line 150 and disposed between adjacent sub-pixels.
  • each storage electrode can be connected to a common voltage signal.
  • the embodiments of the present disclosure include, but are not limited to, the storage electrodes may also be disposed in parallel with the gate lines, as long as the storage electrodes and the first electrodes can form a storage capacitor.
  • the data line can be loaded with a display data signal, a touch signal, and a common voltage signal.
  • the data lines are sequentially loaded with the display data signal, the touch signal, and the common voltage signal. Therefore, when the array substrate provided in this embodiment performs display and touch, the data line is loaded with the display data signal during the first time period, and at this time, the thin film transistor connected to the pixel electrode (the first thin film transistor or a second thin film transistor), the pixel electrode is charged, and in the second period, the data line is loaded with the touch signal, and at this time, the thin film transistor (the first thin film transistor or the second thin film transistor) connected to the common electrode can be turned on, common The electrode can be used as a touch electrode. In the third time period, the data line is loaded with a common voltage signal, and the common electrode is charged, thereby being electrically connected to the pixel. The pole forms an electric field to drive the liquid crystal molecules to deflect, thereby achieving display.
  • the first electrode and/or the second electrode may be a transparent conductive material, such as a transparent oxide conductive material such as indium tin oxide (ITO).
  • a transparent conductive material such as a transparent oxide conductive material such as indium tin oxide (ITO).
  • the first source, the second source, and the data line are integrally formed, which can be formed by one patterning process.
  • the first source, the second source and the data line can be obtained by patterning the same conductive layer, thereby saving the mask process.
  • the array substrate further includes a first gate line 171 and a second gate line 172.
  • the first thin film transistor 110 includes a first gate electrode 112
  • the second thin film transistor 120 includes a second gate electrode 122.
  • the first gate electrode 112 is connected to the first gate line 171, and the second gate electrode 122 is connected to the second gate line 172.
  • the first thin film transistor and the second thin film transistor can be driven by the first gate line and the second gate line, respectively.
  • the first gate electrode 112 and the first gate line 171 may be integrally formed, that is, formed by one patterning process.
  • the first gate and the first gate line can be obtained by patterning the same conductive layer.
  • the second gate electrode 122 and the second gate line 172 may be integrally formed, that is, formed by one patterning process.
  • the second gate and the second gate line can be obtained by patterning the same conductive layer.
  • the first gate line 171 and the second gate line 172 are disposed in parallel.
  • the first thin film transistor 110 further includes a first active layer 114, and the first active layer 114 is disposed at the first gate 112 and the first Between the source 116 and the first drain 118 (source/drain electrode layer), the second thin film transistor 120 further includes a second active layer 124, and the second active layer 124 is disposed at the second gate 122 and the second source Between 126 and the second drain 128 (source drain electrode layer).
  • the first thin film transistor and the second thin film transistor also include other necessary layer structures.
  • the first thin film transistor and the second thin film transistor provided by the embodiments of the present disclosure may adopt a top gate type structure or a bottom gate type structure.
  • the array substrate further includes a first connection electrode 181 and a second connection electrode 182.
  • the first connection electrode 181 connects the first drain 118 and the first electrode 130; the second connection electrode 182 connects the second drain 128 and the second electrode 140.
  • the first connection electrode and the first electrode may be integrally formed, that is, formed by one patterning process.
  • the conductive layer may be connected to the first drain through, for example, a via, and then patterning the conductive layer may obtain the first connection electrode and the first electrode.
  • embodiments of the present disclosure include but are not limited thereto.
  • the second connecting electrode and the second electrode may be integrally formed, that is, formed by one patterning process.
  • FIG. 3B shows another array substrate according to the present embodiment.
  • the array substrate further includes: a third thin film transistor 230 and a fourth thin film transistor 240 disposed on the base substrate 101 and located in the peripheral region 1011, and the third thin film transistor 230 includes a third source 231 and a third The third drain 232, the fourth thin film transistor 240 includes a fourth source 241 and a fourth drain 242.
  • the third source 231 is connected to the display driving circuit 510
  • the fourth source 241 is connected to the touch driving circuit 520.
  • the drain 232 and the fourth drain 242 are connected to the data line 150, respectively.
  • the fourth thin film transistor can be turned off by turning on the third thin film transistor so that the display driving circuit can load a signal to the data line, for example, displaying the data signal and the common voltage signal; the third thin film transistor can be turned off by turning on the fourth thin film transistor
  • the touch driving circuit can load the touch signal to the data line.
  • Fig. 4 is a cross-sectional view showing the array substrate in the AA' direction of Fig. 3A according to the present embodiment.
  • the first thin film transistor 110 and the second thin film transistor 120 are disposed in the same layer.
  • the first thin film transistor and the second thin film transistor can be simultaneously formed without increasing the mask process; and the thickness of the array substrate can also be reduced.
  • the same layer arrangement of the first thin film transistor and the second thin film transistor means that the functional layers (gate, active layer, source/drain electrode layer, etc.) in the first thin film transistor and the second thin film transistor are respectively the same Layer settings. For example, as shown in FIG.
  • the gate 112 of the first thin film transistor 110 and the gate 122 of the second thin film transistor 120 are disposed in the same layer; the active layer 114 of the first thin film transistor 110 and the second thin film transistor 120 are active.
  • the layer 124 is disposed in the same layer; the source 116 and the drain 118 of the first thin film transistor 110 and the source 126 and the drain 128 of the second thin film transistor 120 are disposed in the same layer.
  • the array substrate further includes a passivation layer 117 and an insulating layer 119; the passivation layer 117 is disposed on the first thin film transistor 110 and the second thin film transistor. 120 is away from one side of the base substrate 101; an insulating layer 119 is disposed between the first electrode 130 and the second electrode 140.
  • the first electrode 130 is disposed on a side of the passivation layer 117 away from the base substrate 101, and the second electrode 140 is disposed on a side of the insulating layer 119 away from the base substrate 101.
  • the first electrode 130 is connected to the first drain 118 through the first via 1171 in the passivation layer 117, for example, as shown in FIG. Show,
  • the first electrode 130 is connected to the first drain 118 through the first connection electrode 181 and the first via 1171; the second electrode 140 passes through the second via 1172 in the passivation layer 117 and the third via in the insulating layer 119 1191 is connected to the second drain 128.
  • the second electrode 140 is connected to the second drain 128 through the second connection electrode 182 and the second via 1172 and the third via 1191.
  • FIG. 5 shows an array substrate according to the present embodiment.
  • the first electrode 130 is a pixel electrode
  • the second electrode 140 is a common electrode
  • the ratio of the number of the first thin film transistor 110 to the second thin film transistor 120 is 1:1. Since one common electrode can correspond to a plurality of pixel electrodes, for example, as shown in FIG. 5, one second electrode 140 corresponds to three first electrodes 130, and at this time, the second electrode 140 is connected to the data line 150 through three thin film transistors 120.
  • Fig. 6 shows another array substrate according to the present embodiment. As shown in FIG.
  • the ratio of the number of the first thin film transistors 110 to the second thin film transistors 120 is 3:1. Since one common electrode can be disposed opposite to the plurality of pixel electrodes, the number of second thin film transistors can be less than the number of first thin film transistors. The ratio of the number of the first thin film transistor to the second thin film transistor can be adjusted according to actual conditions as long as each common electrode is connected to at least one drain of one second thin film transistor.
  • the array substrate further includes a storage electrode 145 disposed in the same layer as the second electrode 140, and the storage electrode 145 is positive on the substrate substrate 101.
  • the projection at least partially overlaps the orthographic projection of the first electrode 130 on the base substrate 101.
  • the storage electrode 145 and the first electrode 130 may constitute a storage capacitor to store a display data signal on the first electrode.
  • the storage electrode 145 may be disposed in parallel with the first gate line 171 or the second gate line 172.
  • each storage electrode can be connected to a common voltage signal.
  • a plurality of second electrodes may be combined to form one touch electrode.
  • a plurality of second electrodes are combined by an algorithm of a driving circuit.
  • the number of the first electrodes ie, the pixel electrodes
  • the number of second electrodes common electrode and touch electrode
  • the ratio of the number of the first thin film transistor to the second thin film transistor ranges from 4050:1 to 1:1.
  • the ratio of the number of the first thin film transistor to the second thin film transistor is greater than 1:1 and less than 4050:1, so that the number of second thin film transistors can be reduced without affecting the touch precision.
  • the ratio of the number of the first gate lines to the second gate lines is greater than or equal to 1:1. That is, the number of first gate lines may be greater than or equal to the number of second gate lines.
  • the common electrode is disposed opposite to the plurality of pixel electrodes belonging to the plurality of rows, the number of the first gate lines may be greater than the number of the second gate lines.
  • FIG. 7 shows a display device according to the present embodiment.
  • the display device includes the array substrate 100 described in accordance with any of the above embodiments.
  • the display device can load the signal on the data line to the first electrode and the second electrode in a time-sharing manner through the first thin film transistor and the second thin film transistor, thereby simultaneously implementing the display function and the touch function.
  • the display device does not need to additionally set the touch metal layer and the touch signal line, thereby reducing the number of mask processes of the array substrate, thereby reducing the cost of the array substrate.
  • the display device further includes a first driver 500 and a second driver 600, and the first driver 500 is configured to provide a display data signal for the data line in time series. And a touch signal and a common voltage signal, the second driver 600 is configured to turn on or off the first thin film transistor and the second thin film transistor in time series.
  • the first driver and the second driver can respectively drive the data lines and the first thin film transistor and the second thin film transistor to perform time division, thereby implementing display and touch functions.
  • the first driver 500 may include the display driving circuit 510 and the touch driving circuit 520 described above.
  • the first driver and the second driver can be integrated into one driver.
  • Fig. 8 shows a display device according to the present embodiment.
  • the display device further includes a counter substrate 200 and a liquid crystal layer 300.
  • the opposite substrate 200 is disposed opposite to the array substrate 100.
  • the liquid crystal layer 300 is disposed between the array substrate 100 and the opposite substrate 200.
  • the first electrode 130 and the second electrode 140 can generate an electric field when the voltage is applied to drive the liquid crystal layer 300. Liquid crystal molecules.
  • FIG. 9 is a flow chart showing a driving method of a display device according to the embodiment. As shown in FIG. 9, the driving method includes the following steps S401-S403.
  • Step S401 Apply a display data signal to the data line and turn on the first thin film transistor in the first period of time, and turn off the second thin film transistor, and the data line transmits the display data signal to the first electrode through the first thin film transistor.
  • Step S402 Apply a touch signal to the data line and disconnect the first thin film transistor, turn on the second thin film transistor, and transmit the touch signal to the second power through the second thin film transistor in the second time period. pole.
  • Step S403 In the third time period, a common voltage signal is applied to the data line, and the data line transmits the common voltage signal to the second electrode through the second thin film transistor.
  • the signal on the data line can be time-divisionally loaded to the first electrode and the second electrode through the first thin film transistor and the second thin film transistor, thereby simultaneously realizing the display function and the touch.
  • the first period of time applying a display data signal to the data line and turning on the first thin film transistor, disconnecting the second thin film transistor, the data line transmitting the display data signal to the first electrode through the first thin film transistor, and charging the first electrode
  • the formation of an electric field drives the deflection of liquid crystal molecules in the liquid crystal layer

Abstract

一种阵列基板、显示装置及其驱动方法。该阵列基板包括衬底基板(101)包括显示区(1010)和围绕显示区(1010)的周边区(1011)；以及设置在衬底基板(101)上且位于显示区(1010)的第一薄膜晶体管(110)、第二薄膜晶体管(120)、数据线(150)、第一电极(130)和第二电极(140)。第一薄膜晶体管(110)包括第一源极(116)和第一漏极(118)；第二薄膜晶体管(120)包括第二源极(126)和第二漏极(128)；第一源极(116)和第二源极(126)分别与数据线(150)相连，第一漏极(118)和第一电极(130)相连，第二漏极(128)和第二电极(140)相连。该阵列基板可同时实现显示功能和触控功能。并且，该阵列基板无需额外设置触控金属层和触控信号线，从而可降低该阵列基板的掩膜工艺次数，从而降低该阵列基板的成本。

Description

阵列基板、显示装置及其驱动方法
交叉引用
本申请要求于2017年05月25日递交的中国专利申请第201710378364.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板、显示装置以及显示装置的驱动方法。
背景技术
随着智能显示设备的不断发展，触控已经成为了智能显示设备不可或缺的一个功能。因此，既可用于显示又可用于实现触控操作的触控屏在手机、平板、笔记本电脑等智能显示设备中的应用日益广泛。
通常，触控技术包括光学式、电阻式、电容式、电磁式触控技术等不同的技术方向；在众多的触控技术中，电容式触控技术凭借其较低的成本和优异的用户体验已成为触控技术的主流。电容式触控计算出又可分为自电容式和互电容式两种方式。
发明内容
本公开实施例提供一种阵列基板、显示装置及其驱动方法。该阵列基板包括衬底基板以及设置在衬底基板上的第一薄膜晶体管、第二薄膜晶体管、数据线、第一电极和第二电极。第一薄膜晶体管包括第一源极和第一漏极；第二薄膜晶体管包括第二源极和第二漏极；第一源极和第二源极分别与数据线相连，第一漏极和第一电极相连，第二源极和第二电极相连，第一电极为像素电极，第二电极为触控电极。该阵列基板可同时实现显示功能和触控功能。本公开至少一个实施例提供一种阵列基板，其包括：衬底基板；以及设置在所述衬底基板上的第一薄膜晶体管、第二薄膜晶体管、数据线、第一电极和第二电极，所述第一薄膜晶体管包括第一源极和第一漏极，所述第二薄膜晶体管包括第二源极和第二漏极，所述第一源极和所述第二源极分别与所述数据线相连，所述第一漏极与所述第一电极相连，所述第二漏极与所述第二电极相连，所述第一电 极为像素电极，所述第二电极为公共电极。
例如，在本公开一实施例提供的阵列基板中，所述第二电极复用为公共电极。
例如，在本公开一实施例提供的阵列基板中，所述第一薄膜晶体管与所述第二薄膜晶体管的数量之比大于等于1:1。
例如，在本公开一实施例提供的阵列基板中，该阵列基板还包括：设置在所述衬底基板上且位于所述周边区的第三薄膜晶体管和第四薄膜晶体管，所述第三薄膜晶体管包括第三源极和第三漏极，所述第四薄膜晶体管包括第四源极和第四漏极，所述第三源极被配置为与显示驱动电路相连，所述第四源极被配置为与触控驱动电路相连，所述第三漏极和所述第四漏极分别与所述数据线相连。
例如，在本公开一实施例提供的阵列基板中，所述数据线被配置为加载显示数据信号、触控信号以及公共电压信号。
例如，本公开一实施例提供的阵列基板还包括存储电极，与所述第二电极同层设置，所述存储电极在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的阵列基板中，所述第一薄膜晶体管和所述第二薄膜晶体管同层设置。
例如，在本公开一实施例提供的阵列基板中，所述第一源极、所述第二源极以及所述数据线通过一次构图工艺形成。
例如，本公开一实施例提供的阵列基板还包括：钝化层，设置在所述第一薄膜晶体管和所述第二薄膜晶体管远离所述衬底基板的一侧；以及绝缘层，设置在所述第一电极和所述第二电极之间，所述第一电极设置在所述钝化层远离所述衬底基板的一侧，所述第二电极设置在所述绝缘层远离所述衬底基板的一侧。
例如，在本公开一实施例提供的阵列基板中，所述第一电极通过所述钝化层中的第一过孔与所述第一漏极相连，所述第二电极通过所述钝化层中的第二过孔与所述绝缘层中的第三过孔与所述第二漏极相连。
例如，本公开一实施例提供的阵列基板还包括：第一栅线；以及第二栅线，所述第一薄膜晶体管还包括第一栅极，所述第二薄膜晶体管还包括第二栅极，所述第一栅极与所述第一栅线相连，所述第二栅极与所述第二栅线相连。
例如，在本公开一实施例提供的阵列基板中，所述第一栅线与所述第二栅线平行设置。
例如，在本公开一实施例提供的阵列基板中，所述第一薄膜晶体管还包括第一有源层，所述第一有源层设置在所述第一栅极与所述第一源极和所述第一漏极之间，所述第二薄膜晶体管还包括第二有源层，所述第二有源层设置在所述第二栅极与所述第二源极和所述第二漏极之间。
本公开至少一个实施例提供一种显示装置，其包括上述任一项所述的阵列基板。
例如，本公开一实施例提供的显示装置还包括：第一驱动器，被配置为按时序为所述数据线提供显示数据信号、触控信号以及公共电压信号；以及第二驱动器，被配置为按时序导通或断开所述第一薄膜晶体管和所述第二薄膜晶体管。
本公开至少一个实施例提供一种显示装置的驱动方法，所述显示装置包括上述任一项所述的阵列基板，所述驱动方法包括：在第一时间段，向所述数据线施加显示数据信号并导通所述第一薄膜晶体管，断开所述第二薄膜晶体管，所述数据线将所述显示数据信号通过所述第一薄膜晶体管传输至所述第一电极；在第二时间段，向所述数据线施加触控信号并断开所述第二薄膜晶体管，导通所述第二薄膜晶体管，所述数据线将所述触控信号通过所述第二薄膜晶体管传输至所述第二电极；以及在第三时间段，向所述数据线施加公共电压信号，所述数据线将所述公共电压信号通过所述第二薄膜晶体管传输至所述第二电极。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板的平面示意图；
图2为一种触控电极结构的平面示意图；
图3A为本公开一实施例提供的一种阵列基板的平面示意图；
图3B为本公开一实施例提供的另一种阵列基板的平面示意图；
图4为本公开一实施例提供的一种阵列基板沿图3A中AA’方向的截面示 意图；
图5为本公开一实施例提供的另一种阵列基板的平面示意图；
图6为本公开一实施例提供的另一种阵列基板的平面示意图；
图7为本公开一实施例提供的一种显示装置的示意图；
图8为本公开一实施例提供的另一种显示装置的示意图；以及
图9为本公开一实施例提供的一种显示装置的驱动方法的流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
目前，触控屏可以包括外挂式(On-cell)触控屏和内嵌式(In-cell)触控屏等。外挂式触控屏例如将触控面板设置在液晶面板的彩膜基板和偏振片之间，因此外挂式触控屏比较厚重，难以满足智能显示设备轻薄化的需求。而内嵌式触控屏将触控传感器设置在液晶面板内部，而外部可仅贴合一层保护玻璃，因而具有高透光度、高贴合率以及轻薄化等优点。
图1示出了一种阵列基板。如图1所示，该阵列基板包括设置在衬底基板上的薄膜晶体管10、栅线20、数据线50、像素电极30以及公共电极40。薄膜晶体管10包括栅极12、有源层14、源极16和漏极18。栅极12与栅线20电性相连，例如栅极12和栅线20可由同一导电层图案化得到；源极16与数据线50电性相连，例如源极16和数据线50也可由同一导电层图案化得到。由此，该阵列基板可通过栅线的扫描逐行通过数据线向像素电极加载显示信 号，从而可实现显示功能。
在一些示例中，公共电极40为狭缝电极，像素电极30为板装电极或狭缝电极，公共电极40位于像素电极30的与衬底基板相反的一侧，即像素电极30远离衬底基板的一侧。
图2示出了一种触控电极结构。如图2所示，该触控电极结构包括阵列设置的多个触控电极45，多个触控电极45分别与多条信号传输线46相连。该触控电极结构的原理为：多个触控电极45同层设置且相互绝缘；每个触控电极45可通过信号传输线46连接到触控侦测芯片。当人体未触摸屏幕时，各自电容电极的电容为一固定值；当发生触摸时，触摸位置对应的触控电极45的电容为固定值叠加人体电容，触控侦测芯片通过检测各触控电极45的电容值的变化情况可以判断出触摸位置。
本公开实施例提供一种阵列基板、显示装置及其驱动方法。该阵列基板包括衬底基板以及设置在衬底基板上的第一薄膜晶体管、第二薄膜晶体管、数据线、第一电极和第二电极。第一薄膜晶体管包括第一源极和第一漏极；第二薄膜晶体管包括第二源极和第二漏极；第一源极和第二源极分别与数据线相连，第一漏极和第一电极相连，第二漏极和第二电极相连，第一电极为像素电极，第二电极为触控电极。该阵列基板可通过第一薄膜晶体管和第二薄膜晶体管将数据线上的信号分时加载给第一电极和第二电极，从而同时实现显示功能和触控功能。并且，该阵列基板无需额外设置触控金属层和触控信号线，从而可降低该阵列基板的掩膜工艺次数，从而降低该阵列基板的成本。
本公开一实施例提供一种阵列基板。图3A示出了根据本实施例的一种阵列基板。如图3A所示，该阵列基板包括衬底基板101，衬底基板101包括显示区1010和围绕显示区1010的周边区1011；以及设置在衬底基板101上且位于显示区1010的第一薄膜晶体管110、第二薄膜晶体管120、数据线150、第一电极130和第二电极140。第一薄膜晶体管110包括第一源极116和第一漏极118；第二薄膜晶体管120包括第二源极126和第二漏极128；第一源极116和第二源极126分别与数据线150相连，第一漏极118和第一电极130相连，第二源极128和第二电极140相连。例如，如图3A所示，在数据线150的延伸方向上相邻设置的第一薄膜晶体管110的第一源极116和第二薄膜晶体管120的第二源极126与同一数据线150相连，第一源极116和第二源极126分别与数据线150相连，第一漏极118和第一电极130相连，第二漏极128和第 二电极140相连，第一电极130为像素电极，第二电极140为触控电极。
在本实施例提供的阵列基板中，该阵列基板可通过第一薄膜晶体管和第二薄膜晶体管将数据线上的信号分时加载给第一电极和第二电极，从而同时实现显示功能和触控功能。例如，当第一薄膜晶体管导通，第二薄膜晶体管断开时，数据线上的信号可加载到第一电极，此时数据线上可通过加载显示数据信号，从而可实现显示功能；当第一薄膜晶体管断开，第二薄膜晶体管导通时，数据线上的信号可加载到第二电极，此时数据线上可通过分时加载触控信号和公共电压信号，从而在实现显示功能的同时实现触控功能。另外，该阵列基板无需额外设置触控金属层和触控信号线，从而可降低该阵列基板的掩膜工艺次数，从而降低该阵列基板的成本。
例如，在本实施例一示例提供的阵列基板中，第二电极复用为公共电极。也就是说，在本公开实施例中，第二电极既可在用于进行显示时作为与像素电极形成电场的公共电极，也可在用于进行触控时的触控电极。
例如，在本实施例一示例提供的阵列基板中，如图3A所示，该阵列基板还包括存储电极145与第二电极140同层设置，存储电极145在衬底基板101上的正投影与第一电极130在衬底基板101上的正投影至少部分重叠。由此，存储电极145和第一电极130可构成存储电容，从而存储在第一电极上的显示数据信号。
例如，如图3A所示，存储电极145可与数据线150平行设置，并且设置在相邻的子像素之间。例如，各存储电极可与公共电压信号相连。当然，本公开实施例包括但不限于此，各存储电极也可与栅线平行设置，只要存储电极与第一电极可形成存储电容即可。
例如，在本实施例一示例提供的阵列基板中，数据线可加载显示数据信号，触控信号以及公共电压信号。
例如，在本实施例一示例提供的阵列基板中，数据线依次加载显示数据信号、触控信号以及公共电压信号。由此，当本实施例提供的阵列基板进行显示和触控时，在第一时间段，数据线加载显示数据信号，此时，可导通与像素电极相连的薄膜晶体管(第一薄膜晶体管或第二薄膜晶体管)，像素电极完成充电，在第二时间段，数据线加载触控信号，此时，可导通与公共电极相连的薄膜晶体管(第一薄膜晶体管或第二薄膜晶体管)，公共电极可作为触控电极，在第三时间段，数据线加载公共电压信号，公共电极完成充电，从而与像素电 极形成电场以驱动液晶分子偏转，从而实现显示。
例如，在本实施例一示例提供的阵列基板中，第一电极和/或第二电极可采用透明导电材料，例如氧化铟锡(ITO)等透明氧化物导电材料。
例如，在本实施例一示例提供的阵列基板中，如图3A所示，第一源极、第二源极以及数据线一体成型，即可通过一次构图工艺形成。由此，第一源极、第二源极和数据线可通过图案化同一导电层得到，从而节省掩膜工艺。
例如，在本实施例一示例提供的阵列基板中，如图3A所示，该阵列基板还包括第一栅线171和第二栅线172。第一薄膜晶体管110包括第一栅极112，第二薄膜晶体管120包括第二栅极122，第一栅极112与第一栅线171相连，第二栅极122与第二栅线172相连。由此，可通过第一栅线和第二栅线分别驱动第一薄膜晶体管和第二薄膜晶体管。
例如，如图3A所示，第一栅极112和第一栅线171可一体成型，即可通过一次构图工艺形成。由此，第一栅极和第一栅线可通过图案化同一导电层得到。
例如，如图3A所示，第二栅极122和第二栅线172可一体成型，即可通过一次构图工艺形成。由此，第二栅极和第二栅线可通过图案化同一导电层得到。
例如，如图3A所示，第一栅线171和第二栅线172平行设置。
例如，在本实施例一示例提供的阵列基板中，如图3A所示，第一薄膜晶体管110还包括第一有源层114，第一有源层114设置在第一栅极112与第一源极116和第一漏极118(源漏电极层)之间，第二薄膜晶体管120还包括第二有源层124，第二有源层124设置在第二栅极122与第二源极126和第二漏极128(源漏电极层)之间。当然，第一薄膜晶体管和第二薄膜晶体管还包括其他必需的层结构，具体可参见现有设计，本公开实施例在此不作限制。需要说明的是，本公开实施例提供的第一薄膜晶体管和第二薄膜晶体管可采用顶栅型结构也可在底栅型结构。
例如，在本实施例一示例提供的阵列基板中，如图3A所示，该阵列基板还包括第一连接电极181和第二连接电极182。第一连接电极181将第一漏极118和第一电极130相连；第二连接电极182将第二漏极128和第二电极140相连。
例如，第一连接电极和第一电极可一体成型，即可通过一次构图工艺形成。 例如，通过在第一薄膜晶体管远离衬底基板的一侧形成导电层，导电层可通过例如过孔与第一漏极相连，然后图案化导电层可得到第一连接电极和第一电极。当然，本公开实施例包括但不限于此。
例如，类似地，第二连接电极和第二电极可一体成型，即可通过一次构图工艺形成。
图3B示出了根据本实施例的另一种阵列基板。如图3B所示，该阵列基板还包括：设置在衬底基板101上且位于周边区1011的第三薄膜晶体管230和第四薄膜晶体管240，第三薄膜晶体管230包括第三源极231和第三漏极232，第四薄膜晶体管240包括第四源极241和第四漏极242，第三源极231与显示驱动电路510相连，第四源极241与触控驱动电路520相连，第三漏极232和第四漏极242分别与数据线150相连。由此，可通过打开第三薄膜晶体管，关闭第四薄膜晶体管使得显示驱动电路可向数据线加载信号，例如，显示数据信号和公共电压信号；可通过打开第四薄膜晶体管，关闭第三薄膜晶体管使得触控驱动电路可向数据线加载触控信号。
图4示出了根据本实施例的一种阵列基板沿图3A中AA’方向的截面示意图。如图4所示，第一薄膜晶体管110和第二薄膜晶体管120同层设置。由此，可同时形成第一薄膜晶体管和第二薄膜晶体管，不会增加掩膜工艺；并且还可减少该阵列基板的厚度。需要说明的是，上述的第一薄膜晶体管和第二薄膜晶体管同层设置是指第一薄膜晶体管和第二薄膜晶体管中的功能层(栅极、有源层、源漏电极层等)分别同层设置。例如，如图4所示，第一薄膜晶体管110的栅极112和第二薄膜晶体管120的栅极122同层设置；第一薄膜晶体管110的有源层114和第二薄膜晶体管120的有源层124同层设置；第一薄膜晶体管110的源极116和漏极118和第二薄膜晶体管120的源极126和漏极128同层设置。
例如，在本实施例一示例提供的阵列基板中，如图4所示，该阵列基板还包括钝化层117和绝缘层119；钝化层117设置在第一薄膜晶体管110和第二薄膜晶体管120远离衬底基板101的一侧；绝缘层119设置在第一电极130和第二电极140之间。第一电极130设置在钝化层117远离衬底基板101的一侧，第二电极140设置在绝缘层119远离衬底基板101的一侧。
例如，在本实施例一示例提供的阵列基板中，如图4所示，第一电极130通过钝化层117中的第一过孔1171与第一漏极118相连，例如，如图4所示， 第一电极130通过第一连接电极181和第一过孔1171与第一漏极118相连；第二电极140通过钝化层117中的第二过孔1172与绝缘层119中的第三过孔1191与第二漏极128相连，例如，如图4所示，第二电极140通过第二连接电极182和第二过孔1172和第三过孔1191与第二漏极128相连。
本公开另一实施例提供一种阵列基板。在该阵列基板中，第一薄膜晶体管110与第二薄膜晶体管120的数量之比大于等于1:1。图5示出了根据本实施例的一种阵列基板。如图5所示，第一电极130为像素电极，第二电极140为公共电极，第一薄膜晶体管110与第二薄膜晶体管120的数量之比为1:1。由于一个公共电极可对应多个像素电极，例如，如图5所示，一个第二电极140对应三个第一电极130，此时第二电极140通过三个薄膜晶体管120与数据线150连接。图6示出了根据本实施例的另一种阵列基板。如图6所示，第一薄膜晶体管110与第二薄膜晶体管120的数量之比为3:1。由于一个公共电极可与多个像素电极相对设置，因此第二薄膜晶体管的数量可少于第一薄膜晶体管的数量。第一薄膜晶体管与第二薄膜晶体管的数量之比可根据实际情况进行调节，只要保证每个公共电极至少与一个第二薄膜晶体管的漏极相连。
例如，在本实施例示例提供的阵列基板中，如图5和图6所示，该阵列基板还包括存储电极145与第二电极140同层设置，存储电极145在衬底基板101上的正投影与第一电极130在衬底基板101上的正投影至少部分重叠。由此，存储电极145和第一电极130可构成存储电容，从而存储在第一电极上的显示数据信号。
例如，如图5和图6所示，存储电极145可与第一栅线171或第二栅线172平行设置。例如，各存储电极可与公共电压信号相连。需要说明的是，当第二电极作为触控电极时，可通过将多个第二电极进行组合以形成一个触控电极。例如，通过驱动电路的算法将多个第二电极进行组合。
例如，在本实施例的一示例提供的阵列基板中，第一电极(即像素电极)的数量为720*3*1080＝2332800个(720*1080个像素)，则第一薄膜晶体管的数量也为2332800个；第二电极(公共电极和触控电极)的数量为32*18＝576个。因此，为保证每个公共电极至少与一个第二薄膜晶体管的漏极相连，第一薄膜晶体管与第二薄膜晶体管的数量之比的范围为4050:1-1:1。例如，第一薄膜晶体管与第二薄膜晶体管的数量之比的范围大于1:1且小于4050:1，这样，在不影响触摸精度的情况下可以减少第二薄膜晶体管的数量。
例如，在本实施例一示例提供的阵列基板中，第一栅线与第二栅线的数量比大于或等于1:1。也就是说，第一栅线的数量可大于等于第二栅线的数量。当公共电极可与属于多行的多个像素电极相对设置，因此第一栅线的数量可大于第二栅线的数量。
本公开一实施例提供一种显示装置。图7示出了根据本实施例的一种显示装置。如图6所示，该显示装置包括根据上述实施例中任一项所描述的阵列基板100。由此，该显示装置可通过第一薄膜晶体管和第二薄膜晶体管将数据线上的信号分时加载给第一电极和第二电极，从而同时实现显示功能和触控功能。另外，该显示装置无需额外设置触控金属层和触控信号线，从而可降低该阵列基板的掩膜工艺次数，从而降低该阵列基板的成本。
例如，在本实施例一示例提供的显示装置中，如图7所示，该显示装置还包括第一驱动器500和第二驱动器600，第一驱动器500用于按时序为数据线提供显示数据信号、触控信号以及公共电压信号，第二驱动器600用于按时序导通或断开第一薄膜晶体管和第二薄膜晶体管。由此，第一驱动器和第二驱动器可分别对数据线与第一薄膜晶体管和第二薄膜晶体管进行分时驱动，从而实现显示和触控功能。
例如，第一驱动器500可包括上述的显示驱动电路510和触控驱动电路520。
例如，第一驱动器和第二驱动器可集成为一个驱动器。
图8示出了根据本实施例的一种显示装置。如图8所示，该显示装置还包括对置基板200和液晶层300。对置基板200与阵列基板100相对设置，液晶层300设置在阵列基板100和对置基板200之间，第一电极130和第二电极140可在施加有电压时产生电场以驱动液晶层300中的液晶分子。
本公开一实施例提供一种显示装置的驱动方法。图9为根据本实施例的一种显示装置的驱动方法的流程示意图。如图9所示，该驱动方法包括以下步骤S401-S403。
步骤S401：在第一时间段，向数据线施加显示数据信号并导通第一薄膜晶体管，断开第二薄膜晶体管，数据线将显示数据信号通过第一薄膜晶体管传输至第一电极。
步骤S402：在第二时间段，向数据线施加触控信号并断开第一薄膜晶体管，导通第二薄膜晶体管，数据线将触控信号通过第二薄膜晶体管传输至第二电 极。
步骤S403：在第三时间段，向数据线施加公共电压信号，数据线将公共电压信号通过第二薄膜晶体管传输至第二电极。
在本实施例提供的显示装置的驱动方法中，可通过第一薄膜晶体管和第二薄膜晶体管将数据线上的信号分时加载给第一电极和第二电极，从而同时实现显示功能和触控功能。在第一时间段，向数据线施加显示数据信号并导通第一薄膜晶体管，断开第二薄膜晶体管，数据线将显示数据信号通过第一薄膜晶体管传输至第一电极，第一电极进行充电；在第二时间段，向数据线施加触控信号并断开第二薄膜晶体管，导通第二薄膜晶体管，数据线将触控信号通过第二薄膜晶体管传输至第二电极，第二电极作为触控电极以进行触控；在第三时间段，向数据线施加公共电压信号，数据线将公共电压信号通过第二薄膜晶体管传输至第二电极，第二电极进行充电并与第一电极之间形成电场驱动液晶层中的液晶分子偏转。需要说明的是，上述第一时间段、第二时间段以及第三时间段的顺序可根据实际情况进行设置，本公开实施例在此不作限制。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种阵列基板，包括：
    衬底基板，包括显示区和围绕所述显示区的周边区；以及
    设置在所述衬底基板上且位于所述显示区的第一薄膜晶体管、第二薄膜晶体管、数据线、第一电极和第二电极，
    其中，所述第一薄膜晶体管包括第一源极和第一漏极，所述第二薄膜晶体管包括第二源极和第二漏极，所述第一源极和所述第二源极分别与所述数据线相连，所述第一漏极与所述第一电极相连，所述第二漏极与所述第二电极相连，所述第一电极为像素电极，所述第二电极为触控电极。
  2. 根据权利要求1所述的阵列基板，其中，所述第二电极复用为公共电极。
  3. 根据权利要求2所述的阵列基板，其中，所述第一薄膜晶体管与所述第二薄膜晶体管的数量之比大于等于1:1。
  4. 根据权利要求1所述的阵列基板，还包括：
    设置在所述衬底基板上且位于所述周边区的第三薄膜晶体管和第四薄膜晶体管，
    其中，所述第三薄膜晶体管包括第三源极和第三漏极，所述第四薄膜晶体管包括第四源极和第四漏极，所述第三源极被配置为与显示驱动电路相连，所述第四源极被配置为与触控驱动电路相连，所述第三漏极和所述第四漏极分别与所述数据线相连。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，所述数据线被配置为加载显示数据信号、触控信号以及公共电压信号。
  6. 根据权利要求1-4中任一项所述的阵列基板，还包括：
    存储电极，与所述第二电极同层设置，
    其中，所述存储电极在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影至少部分重叠。
  7. 根据权利要求1-4中任一项所述的阵列基板，其中，所述第一薄膜晶体管和所述第二薄膜晶体管同层设置。
  8. 根据权利要求1-4中任一项所述的阵列基板，其中，所述第一源极、所述第二源极以及所述数据线通过一次构图工艺形成。
  9. 根据权利要求1-4中任一项所述的阵列基板，还包括：
    钝化层，设置在所述第一薄膜晶体管和所述第二薄膜晶体管远离所述衬底基板的一侧；以及
    绝缘层，设置在所述第一电极和所述第二电极之间，
    其中，所述第一电极设置在所述钝化层远离所述衬底基板的一侧，所述第二电极设置在所述绝缘层远离所述衬底基板的一侧。
  10. 根据权利要求8所述的阵列基板，其中，所述第一电极通过所述钝化层中的第一过孔与所述第一漏极相连，所述第二电极通过所述钝化层中的第二过孔与所述绝缘层中的第三过孔与所述第二漏极相连。
  11. 根据权利要求1-4中任一项所述的阵列基板，还包括：
    第一栅线；以及
    第二栅线，
    其中，所述第一薄膜晶体管还包括第一栅极，所述第二薄膜晶体管还包括第二栅极，所述第一栅极与所述第一栅线相连，所述第二栅极与所述第二栅线相连。
  12. 根据权利要求11所述的阵列基板，其中，所述第一栅线与所述第二栅线的数量比大于或等于1:1。
  13. 根据权利要求11所述的阵列基板，其中，所述第一薄膜晶体管还包括第一有源层，所述第一有源层设置在所述第一栅极与所述第一源极和所述第一漏极之间，所述第二薄膜晶体管还包括第二有源层，所述第二有源层设置在所述第二栅极与所述第二源极和所述第二漏极之间。
  14. 一种显示装置，包括根据权利要求1-13中任一项所述的阵列基板。
  15. 根据权利要求14所述的显示装置，还包括：
    第一驱动器，被配置为按时序为所述数据线提供显示数据信号、触控信号以及公共电压信号；以及
    第二驱动器，被配置为按时序导通或断开所述第一薄膜晶体管和所述第二薄膜晶体管。
  16. 一种根据权利要求14或15所述的显示装置的驱动方法，包括：
    向所述数据线施加显示数据信号并导通所述第一薄膜晶体管，断开所述第二薄膜晶体管，所述数据线将所述显示数据信号通过所述第一薄膜晶体管传输至所述第一电极；
    向所述数据线施加触控信号并断开所述第一薄膜晶体管，导通所述第二薄膜晶体管，所述数据线将所述触控信号通过所述第二薄膜晶体管传输至所述第二电极；以及
    向所述数据线施加公共电压信号并断开所述第一薄膜晶体管，导通所述第二薄膜晶体管，所述数据线将所述公共电压信号通过所述第二薄膜晶体管传输至所述第二电极。
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Publication number Priority date Publication date Assignee Title
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CN113655919B (zh) * 2021-08-18 2023-06-30 深圳市华星光电半导体显示技术有限公司 内嵌式的oled触控显示面板
CN114721553B (zh) * 2022-06-06 2022-12-13 惠科股份有限公司 触控结构、oled触控显示面板及制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110043466A1 (en) * 2009-08-19 2011-02-24 Silicon Works Co., Ltd Touch screen liquid crystal display device
CN104820321A (zh) * 2015-05-08 2015-08-05 厦门天马微电子有限公司 一种阵列基板和显示面板
CN104882092A (zh) * 2015-06-29 2015-09-02 京东方科技集团股份有限公司 一种内嵌式触控显示屏及其驱动方法、显示装置
CN104991678A (zh) * 2015-07-28 2015-10-21 京东方科技集团股份有限公司 阵列基板及其驱动方法、制作方法、显示装置
CN105094431A (zh) * 2015-08-11 2015-11-25 厦门天马微电子有限公司 一种阵列基板及制作方法、触控显示面板及触控显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103500747B (zh) * 2013-09-30 2017-01-25 京东方科技集团股份有限公司 阵列基板、阵列基板驱动方法和显示装置
CN103955309B (zh) * 2014-04-14 2017-08-25 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN104716144B (zh) * 2015-03-06 2018-02-16 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104898892B (zh) * 2015-07-09 2017-11-17 京东方科技集团股份有限公司 一种触控显示面板及其制作方法、触控显示装置
US10310667B2 (en) * 2015-09-21 2019-06-04 Apple Inc. Multi-bar capacitive sense electrode

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110043466A1 (en) * 2009-08-19 2011-02-24 Silicon Works Co., Ltd Touch screen liquid crystal display device
CN104820321A (zh) * 2015-05-08 2015-08-05 厦门天马微电子有限公司 一种阵列基板和显示面板
CN104882092A (zh) * 2015-06-29 2015-09-02 京东方科技集团股份有限公司 一种内嵌式触控显示屏及其驱动方法、显示装置
CN104991678A (zh) * 2015-07-28 2015-10-21 京东方科技集团股份有限公司 阵列基板及其驱动方法、制作方法、显示装置
CN105094431A (zh) * 2015-08-11 2015-11-25 厦门天马微电子有限公司 一种阵列基板及制作方法、触控显示面板及触控显示装置

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