WO2018209787A1

WO2018209787A1 - Balancing protection circuit and battery balancing system

Info

Publication number: WO2018209787A1
Application number: PCT/CN2017/093373
Authority: WO
Inventors: 叶伏明; 刘祥
Original assignee: 宁德时代新能源科技股份有限公司
Priority date: 2017-05-18
Filing date: 2017-07-18
Publication date: 2018-11-22
Also published as: CN207039214U

Abstract

A balancing protection circuit and a battery balancing system, related to the field of power batteries. The balancing protection circuit comprises an undervoltage detection module (P1), an overvoltage detection module (P2), a failure signal triggering module (P3), a failure signal holding module (P4), and a protection control module (P5). An output end of the failure signal holding module (P4) is connected to an input end of the protection control module (P5) and to an external signal output end (Vout). The failure signal holding module (P4) is used for receiving a failure triggering signal, generating a failure report signal that is held for a period of time, and outputting the failure report signal to the protection control module (P5) and to the external signal output end (Vout). Because the failure report signal can be held for a period of time, a microcontroller unit can easily capture the failure report signal so as to implement the recording of the time of occurrence of a safety failure, thus implementing the positioning of the safety failure during subsequent servicing of a battery module.

Description

Balanced protection circuit and battery equalization system

Technical field

The present invention relates to the field of power batteries, and in particular, to a balanced protection circuit and a battery equalization system.

Background technique

With the development of power battery technology, in order to meet the requirements of the user's various devices for the battery module power, the capacity of the battery module is also gradually increasing. The battery module includes a plurality of batteries. Due to individual differences or temperature differences of the plurality of cells in the battery module, the consistency of the cells in the battery module is affected, so that the power, voltage or current of each battery cell in the battery module is inconsistent, thereby Reduce the life of the battery module.

In order to ensure the life of the battery module, a balancing strategy is adopted for each battery cell in the battery module. For example, to add electric energy to a cell with a low voltage, increase the voltage of a cell with a low voltage, and make the voltage of the cell reach an equilibrium voltage. Alternatively, the battery with a high voltage is discharged to lower the voltage of the battery with a high voltage, so that the voltage of the battery reaches an equalized voltage. In the equalization strategy, the equalization voltage is required to remain within a certain safe range. However, in the process of equalization, the cell may be overcharged or overdischarged by the equalization strategy due to some unexpected factors, and the equilibrium voltage of the cell exceeds the safe range. In turn, the battery module has a safety failure, which reduces the safety of the battery module.

In order to ensure the safety of the battery module, the equalization voltage is detected by the equalization protection circuit. If the equalization voltage exceeds the safe range, a fault signal is generated, and the control equalization control chip stops working immediately. When the equalization control chip stops working, the equalization voltage disappears and the fault signal disappears. In other words, the fault signal exists for a very short time and is difficult to capture. As a result, it is difficult to record the time when the safety fault occurs, and thus the safety fault cannot be located according to the time when the battery module is maintained in the later stage.

Summary of the invention

The embodiment of the invention provides a balance protection circuit and a battery module system, which can record the time when the safety fault occurs, thereby realizing the positioning of the safety fault when the battery module is maintained in the later stage.

In one aspect, an embodiment of the present invention provides an equalization protection circuit, including:

An undervoltage detection module, wherein the input end of the undervoltage detection module is connected to the equalization voltage sampling end and the first voltage supply end, and the output end of the undervoltage detection module is connected to the input end of the fault signal triggering module, the undervoltage The detecting module is configured to convert the voltage of the first voltage supply end into a reference lower limit voltage, and if the equalization voltage of the equalization voltage sampling end is less than the reference lower limit voltage, output an undervoltage trigger signal to the fault signal triggering module;

An overvoltage detection module, wherein an input end of the overvoltage detection module is connected to the equalization voltage sampling end and a second voltage supply end, and an output end of the overvoltage detection module is connected to an input end of the fault signal triggering module, The overvoltage detection module is configured to convert the voltage of the second voltage supply terminal into a reference upper limit voltage, and if the equalization voltage of the equalization voltage sampling end is greater than the reference upper limit voltage, output an overvoltage trigger signal to the fault signal trigger module. ;

The fault signal triggering module, the output end of the fault signal triggering module is connected to the input end of the fault signal holding module, and the fault signal triggering module is configured to receive the undervoltage triggering signal or the overvoltage triggering signal, The fault signal holding module outputs a fault trigger signal;

The fault signal holding module, the output end of the fault signal holding module is connected to the input end of the protection control module and the external signal output end, and the fault signal holding module is configured to receive the fault trigger signal and generate the hold for a period of time. a fault reporting signal and outputting the fault report signal to the protection control module and the external signal output;

The protection control module, the output end of the protection control module is connected to the equalization control chip, the protection control module is configured to receive the fault report signal, output a work stop signal to the equalization control chip, and control the equalization control The chip stopped working.

In another aspect, an embodiment of the present invention provides a battery equalization system including the equalization protection circuit in the above embodiment.

The embodiment of the invention provides an equalization protection circuit and a battery equalization system, and the equalization protection circuit comprises an undervoltage detection module, an overvoltage detection module, a fault signal triggering module, a fault signal holding module and a protection control module. Fault signal when receiving undervoltage trigger signal or overvoltage trigger signal The trigger module outputs a fault trigger signal to the fault signal holding module. The fault signal holding module receives the fault trigger signal, generates a fault report signal that is kept for a period of time, and outputs a fault report signal to the protection control module and the external signal output end. The external signal output can be connected to the micro control unit. Since the fault report signal can be kept for a period of time, the micro control unit can easily capture the fault report signal. In turn, it is possible to record the time when the safety fault occurs, and to locate the safety fault when the battery module is maintained in the later stage.

DRAWINGS

The invention may be better understood from the following description of the embodiments of the invention, in which the same or similar reference numerals indicate the same or similar features.

1 is a schematic structural diagram of an equalization protection circuit according to an embodiment of the present invention;

2 is a schematic structural diagram of an equalization protection circuit according to an example of an embodiment of the present invention;

3 is a schematic structural diagram of an equalization protection circuit according to another embodiment of the present invention;

4 is a schematic structural diagram of an equalization protection circuit in an example of another embodiment of the present invention;

FIG. 5 is a schematic structural diagram of an equalization protection circuit according to still another embodiment of the present invention; FIG.

FIG. 6 is a schematic structural diagram of an equalization protection circuit in an example of another embodiment of the present invention.

detailed description

Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth However, it will be apparent to those skilled in the art that the present invention may be practiced without some of the details. The following description of the embodiments is merely provided to provide a better understanding of the invention. The present invention is in no way limited to any specific configurations and algorithms set forth below, but without departing from the spirit and scope of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary obscuring the invention.

FIG. 1 is a schematic structural diagram of an equalization protection circuit according to an embodiment of the present invention. As shown in FIG. 1, the equalization protection circuit includes an undervoltage detection module P1, an overvoltage detection module P2, a fault signal triggering module P3, a fault signal holding module P4, and a protection control module P5.

The input end of the undervoltage detection module P1 is connected to the equalization voltage sampling terminal Vin and the first voltage supply terminal V1, and the output terminal of the undervoltage detection module P1 is connected to the input terminal of the fault signal triggering module P3. The undervoltage detection module P1 is configured to convert the voltage of the first voltage supply terminal V1 into a reference lower limit voltage. If the equalization voltage of the equalization voltage sampling terminal Vin is less than the reference lower limit voltage, the undervoltage trigger signal is output to the fault signal triggering module P3.

The equalization voltage sampling terminal Vin can provide the collected equalization voltage. The undervoltage trigger signal indicates that the equalization voltage is undervoltage.

The input end of the overvoltage detecting module P2 is connected to the equalization voltage sampling terminal Vin and the second voltage supply terminal V2, and the output end of the overvoltage detecting module P2 is connected to the input terminal of the fault signal triggering module P3. The overvoltage detection module P2 is configured to convert the voltage of the second voltage supply terminal V2 into a reference upper limit voltage. If the equalization voltage of the equalization voltage sampling terminal Vin is greater than the reference upper limit voltage, the overvoltage trigger signal is output to the fault signal triggering module P3.

The voltage of the first voltage supply terminal V1 and the voltage of the second voltage supply terminal V2 may be the same or different, but the reference upper limit voltage is greater than the reference lower limit voltage. The overvoltage trigger signal indicates that the equalization voltage has an overvoltage phenomenon.

The output of the fault signal triggering module P3 is connected to the input of the fault signal holding module P4. The fault signal triggering module P3 is configured to receive an undervoltage trigger signal or an overvoltage trigger signal, and output a fault trigger signal to the fault signal holding module P4.

The output of the fault signal holding module P4 is connected to the input of the protection control module P5 and the external signal output terminal Vout. The fault signal holding module P4 is configured to receive the fault trigger signal, generate a fault report signal that is held for a period of time, and output a fault report signal to the protection control module P5 and the external signal output terminal Vout.

Among them, the fault trigger signal lasts for a very short time. When the fault signal holding module P4 receives the fault trigger signal, a fault report signal is generated. The fault report signal can be held for a period of time, which is equivalent to locking the fault trigger signal with a short duration, so that the fault trigger signal can be captured by the fault report signal. And the initial time of the fault report signal that remains for a period of time is the same as the time when the fault trigger signal is received. Therefore, the output fault report signal can be collected from the external signal output terminal Vout, and the initial time of the fault report signal for a period of time can be regarded as the time when the safety fault occurs.

The output of the protection control module P5 is connected to the equalization control chip. The protection control module P5 is configured to receive the fault report signal, output a work stop signal to the equalization control chip, and control the equalization control chip to stop working.

Among them, the equalization control chip stops working, indicating that the battery equalization process is aborted.

The equalization protection circuit and the battery equalization system provided by the embodiments of the present invention include an undervoltage detection module P1, an overvoltage detection module P2, a fault signal triggering module P3, a fault signal holding module P4, and a protection control module P5. When receiving the undervoltage trigger signal or the overvoltage trigger signal, the fault signal triggering module P3 outputs a fault trigger signal to the fault signal holding module P4. The fault signal holding module P4 receives the fault trigger signal, generates a fault report signal that is held for a period of time, and outputs a fault report signal to the protection control module P5 and the external signal output terminal Vout. The external signal output terminal Vout can be connected to the micro control unit. Since the fault report signal can be maintained for a period of time, the micro control unit can easily capture the fault report signal. In turn, it is possible to record the time when the safety fault occurs, and to locate the safety fault when the battery module is maintained in the later stage.

FIG. 2 is a schematic structural diagram of an equalization protection circuit according to an example of an embodiment of the present invention. As shown in FIG. 2, the undervoltage detection module P1, the overvoltage detection module P2, the fault signal triggering module P3, the fault signal holding module P4, and the protection control module P5 in FIG. 1 may each be composed of components. The specific structure of the undervoltage detecting module P1, the overvoltage detecting module P2, the fault signal triggering module P3, the fault signal holding module P4, and the protection control module P5 will be described below.

The undervoltage detecting module P1 includes a first resistor combination, a second resistor combination, and a first comparator M1.

Wherein, one end of the first resistor combination is connected to the first voltage supply terminal V1, the other end of the first resistor combination is connected to one end of the second resistor combination, and the other end of the second resistor combination is grounded to GND1.

The non-inverting input terminal of the first comparator M1 is connected to the equalization voltage sampling terminal Vin, and the inverting input terminal of the first comparator M1 is connected to the other end of the first resistor combination and the second resistor combination, and the first comparator is connected. The output of M1 is connected to the fault signal triggering module P3.

As shown in FIG. 2, the first resistor combination includes resistors R3 and R4, and the second resistor combination includes resistor R2. The first resistor combination and the second resistor combination are in a series relationship, and the reference lower limit voltage received by the inverting input terminal of the first comparator M1 is the voltage of one end of the second resistor combination. So can In the circuit design, according to the working scene or the work requirement, the resistance of the first resistor combination and the resistance of the second resistor combination are adjusted, so that the voltage provided by the first voltage supply terminal V1 is converted into the reference lower limit voltage. It should be noted that the first resistor combination includes at least one resistor, and the second resistor combination includes at least one resistor. The combination of the resistors in the first resistor combination and the resistor combination in the second resistor combination are not limited herein. It is also possible to provide a protection resistor in the undervoltage detection module P1 to ensure that the current flowing through the undervoltage detection module P1 is not excessively large, for example, the resistor R1 in FIG. 2 is a protection resistor.

As shown in FIG. 2, the first comparator M1 is further connected to the seventh voltage supply terminal V7 and the ground terminal GND2, and the seventh voltage supply terminal V7 can supply the operating voltage to the first comparator M1.

In order to improve the accuracy of the undervoltage detection module P1, a capacitor C1 for filtering may be provided in the undervoltage detection module P1. One end of the capacitor C1 is connected to the non-inverting input terminal of the first comparator M1, and the capacitor C1 is further connected. One end is grounded.

The overvoltage detecting module P2 includes a third resistor combination, a fourth resistor combination, and a second comparator M2.

Wherein, one end of the third resistor combination is connected to the second voltage supply terminal V2, the other end of the third resistor combination is connected to one end of the fourth resistor combination, and the other end of the fourth resistor combination is grounded to GND3.

The non-inverting input terminal of the second comparator M2 is connected to the other end of the combination of the third resistor and the fourth resistor, and the inverting input terminal of the second comparator M2 is connected to the equalization voltage sampling terminal Vin, and the second comparator The output of M2 is connected to the fault signal triggering module P3.

As shown in FIG. 2, the third resistor combination includes a resistor R8, and the fourth resistor combination includes resistors R6 and R7. The third resistor combination and the fourth resistor combination are in a series relationship, and the reference upper limit voltage received by the non-inverting input terminal of the second comparator M2 is the voltage of one end of the fourth resistor combination. Therefore, in the circuit design, according to the working scene or the work requirement, the resistance value of the third resistor combination and the resistance of the fourth resistor combination can be adjusted, so that the voltage provided by the second voltage supply terminal V2 is converted into the reference upper limit voltage. The reference lower limit voltage and the reference upper limit voltage can be set more precisely, reducing the protection range of the equalization voltage, making the protection of the equalization voltage more precise. It should be noted that the third resistor combination includes at least one resistor, the fourth resistor combination includes at least one resistor, and the combination of the resistors in the third resistor combination and the resistor combination in the fourth resistor combination are not limited herein. Still A protection resistor can be provided in the overvoltage detection module P2 to ensure that the current flowing through the voltage detection module P2 is not excessive. For example, the resistor R5 in FIG. 2 is a protection resistor.

As shown in FIG. 2, the second comparator M2 is also connected to the eighth voltage supply terminal V8 and the ground terminal GND4, and the fourth voltage supply terminal V4 can provide an operating voltage for the eighth comparator.

In order to improve the accuracy of the overvoltage detection module P2, a capacitor C2 for filtering may be disposed in the overvoltage detection module P2. One end of the capacitor C2 is connected to the inverting input terminal of the second comparator M2, and the capacitor C2 is further connected. One end is grounded.

The fault signal triggering module P3 includes a first optical coupler OC1. The first photocoupler OC1 includes a first light emitting diode L1 and a first photosensitive semiconductor tube T1.

The anode of the first LED L1 is connected to the third voltage supply terminal V3, and the cathode of the first LED L1 is connected to the output of the undervoltage detection module P1 and the output of the overvoltage detection module P2.

One end of the first photosensitive semiconductor tube T1 is connected to the input terminal of the fault signal holding module P4, and the other end of the first photosensitive semiconductor tube T1 is grounded to GND5.

It is also possible to set a protection resistor in the fault signal triggering module P3 to ensure that the current flowing through the fault signal triggering module P3 is not excessively large, for example, the resistor R9 in FIG. 2 is a protection resistor.

The fault signal holding module P4 includes a first transistor Q1 and a second transistor Q2.

The control terminal of the first transistor Q1 is connected to the output terminal of the fault signal triggering module P3, the first terminal of the first transistor Q1 is connected to the fourth voltage supply terminal V4, and the second terminal of the first transistor Q1 is connected to the external signal output terminal. Vout connection. In one example, the external signal output terminal Vout can be externally connected to a Micro Control Unit (MCU), and the micro control unit records the time when the safety fault occurs.

The control terminal of the second transistor Q2 is connected to the second terminal of the first transistor Q1 and the input terminal of the protection control module P5. The first terminal of the second transistor Q2 is grounded to GND6, and the second terminal of the second transistor Q2 is triggered by a fault signal. The output of module P3 is connected.

It is also possible to provide a protection resistor in the fault signal holding module P4 to ensure that the current flowing through the fault signal holding module P4 is not excessively large, and to prevent the transistor from being burnt out, such as the resistors R10, R11, R12, R13 in FIG. Both R14 and R15 are protective resistors.

The protection control module P5 includes a third transistor Q3 and a second photocoupler OC2. Second optocoupler The combiner OC2 includes a second light emitting diode L2 and a second photosensitive semiconductor tube T2.

The control terminal of the third transistor Q3 is connected to the output terminal of the fault signal holding module P4, the first terminal of the third transistor Q3 is connected to the ground GND7, and the second terminal of the third transistor Q3 is connected to the cathode of the second light emitting diode L2.

The anode of the second light emitting diode L2 is connected to the fifth voltage supply terminal V5.

One end of the second photosensitive semiconductor tube T2 is connected to the equalization control chip, and the other end of the second photosensitive semiconductor tube T2 is grounded to GND8. In one example, one end of the second photosensitive semiconductor tube T2 can be coupled to an enable pin of the equalization control chip.

It is also possible to provide a protection resistor in the protection control module P5 to ensure that the current flowing through the protection control module P5 is not excessively large, and to prevent the transistor from being burnt out. For example, the resistors R16, R17 and R18 in FIG. 2 are protection resistors.

The first transistor Q1 is a PNP transistor, the second transistor Q2 and the third transistor Q3 are both NPN transistors, the control terminal is a base, the first end is an emitter, and the second end is a collector. The working principle of the equalization protection circuit shown in 2:

The non-inverting input terminal of the first comparator M1 receives the equalization voltage of the input of the equalization voltage sampling terminal Vin, and the inverting input terminal of the first comparator M1 receives the reference lower limit voltage. If the equalization voltage is less than the reference lower limit voltage, the output of the first comparator M1 outputs a low level signal (ie, an undervoltage trigger signal).

The inverting input of the second comparator M2 receives the equalized voltage of the input of the equalized voltage sampling terminal Vin, and the non-inverting input of the second comparator M2 receives the reference upper limit voltage. If the equalization voltage is greater than the reference upper limit voltage, the output of the second comparator M2 outputs a low level signal (ie, an overvoltage trigger signal).

If the negative electrode of the first light emitting diode L1 in the first photocoupler OC1 receives the low level signal, the first light emitting diode L1 is turned on and emits light. The first photosensitive semiconductor tube T1 in the first photocoupler OC1 receives the light emitted from the first light emitting diode L1 and is turned on, pulling the signal of one end of the first photosensitive semiconductor tube T1 low.

The control terminal of the first transistor Q1 receives a low level signal (ie, a fault trigger signal) at one end of the first photosensitive semiconductor tube T1, and the first transistor Q1 is turned on. The first transistor Q1 transmits a high level signal provided by the fourth voltage supply terminal V4 of the first terminal to the control terminal of the second transistor Q2 and The control terminal of the three transistor Q3. The second transistor Q2 is turned on to pull the signal of the control terminal of the first transistor Q1 to a low level signal. The first transistor Q1 will continue to be in an on state, and the external signal output terminal Vout outputs a high level signal (ie, a fault report signal) for a period of time until the fault signal holding module P4 is reset.

The control terminal of the third transistor Q3 receives a high level signal, and the third transistor Q3 is turned on. The cathode of the second light-emitting transistor in the second photocoupler OC2 is in communication with the ground, and the second light-emitting transistor is turned on and emits light. The second photosensitive semiconductor tube T2 in the second photocoupler OC2 is turned on to output a low level signal (ie, a work stop signal) to the equalization control chip. The equalization control chip receives the low level signal and stops working to protect the battery module.

FIG. 3 is a schematic structural diagram of an equalization protection circuit according to another embodiment of the present invention. 3 is different from FIG. 1 in that the equalization protection circuit of FIG. 3 further includes a reset module P6.

The input end of the reset module P6 is connected to the external signal input terminal Vr, and the output end of the reset module P6 is connected to the input end of the fault signal holding module P4 for receiving the control signal of the external signal input terminal Vr, and outputting to the fault signal holding module P4. The reset signal controls the fault signal holding module P4 to reset.

The reset module P6 can control the reset of the fault signal holding module P4 to start a new round of equalization voltage detection.

FIG. 4 is a schematic structural diagram of an equalization protection circuit in an example of another embodiment of the present invention. 4 is different from FIG. 2 in that the new reset module P6 in FIG. 4 can be composed of components. The specific structure of the reset module P6 will be described below.

The reset module P6 includes a fourth transistor Q4. The control terminal of the fourth transistor Q4 is connected to the external signal input terminal Vr, the first terminal of the fourth transistor Q4 is connected to the sixth voltage supply terminal V6, and the second terminal of the fourth transistor Q4 is connected to the input terminal of the fault signal holding module P4. . The external signal input terminal Vr can be connected to the micro control unit, and the micro control unit sends a signal to control the reset module P6.

As shown in FIG. 4, the resistors R19 and R20 are protection resistors to prevent the current flowing through the reset module P6 from being excessively large, and to prevent the transistor from being burned out.

Hereinafter, the fourth transistor Q4 will be described as an example of a PNP transistor. The signal of the external signal input terminal Vr is initially a high level signal, and the fourth transistor Q4 is turned off. When the micro control unit monitors When the battery voltage in the battery module is normal and the communication of the battery module is normal, the low-level signal is input through the external signal input terminal Vr. The control terminal of the fourth transistor Q4 receives the low level signal, and the fourth transistor Q4 is turned on to transmit the high level signal to the control terminal of the first transistor Q1. The control terminal of the first transistor Q1 receives a high-level signal (ie, a reset signal), the first transistor Q1 is turned off, the control terminal of the second transistor Q2 has no high-level signal input, and the external signal output terminal Vout has no signal output, thereby achieving a fault. Reset of signal hold module P4.

The control terminal of the third transistor Q3 has no high level signal input, and the third transistor Q3 is turned off. The second photocoupler OC2 is turned off, and the low level signal (ie, the operation stop signal) cannot be supplied to the equalization control chip. The equalization control chip can continue to work.

FIG. 5 is a schematic structural diagram of an equalization protection circuit according to still another embodiment of the present invention. 5 is different from FIG. 3 in that the equalization protection circuit of FIG. 5 further includes an operation signal providing module P7.

The input end of the working signal providing module P7 is connected to the working signal providing end, and the output end of the working signal providing module P7 is connected to the equalization control chip. The working signal providing module P7 is configured to provide a working signal for the equalization control chip when the protection control module P5 does not receive the fault report signal.

FIG. 6 is a schematic structural diagram of an equalization protection circuit in an example of another embodiment of the present invention. 6 is different from FIG. 4 in that the new work signal providing module P7 in FIG. 6 can be composed of components. The specific structure of the operation signal providing module P7 will be described below.

The operational signal supply module P7 includes an equivalent resistance combination and a diode. Among them, the diodes may be one or more than one.

The first end of the equivalent resistance combination is connected to the equalization control chip, the second end of the equivalent resistance combination is grounded, and the third end of the equivalent resistance combination is connected to the negative pole of the diode. The anode of the diode is connected to the working signal supply terminal.

As shown in FIG. 6, the equivalent resistance combination may include resistors R21 and R22. There are three diodes, D1, D2 and D3. The positive electrode of the diode D1, the positive electrode of D2, and the positive electrode of D3 are connected to the operation signal supply terminals Vw1, Vw2, and Vw3, respectively. One end of the resistor R21 is connected to the equalization control chip, and the other end of the resistor R21 is connected to one end of the resistor R22, the cathode of the diode D1, the cathode of D2, and the cathode of D3. The other end of the resistor R22 is grounded.

If the third transistor Q3 does not receive a high level signal (ie, a fault report signal), the working signal supply terminals Vw1, Vw2, and/or Vw3 provide a high level signal to the equalization control chip (ie, Signaling), so that the equalization control chip works normally.

It should be noted that the first voltage supply terminal V1, the second voltage supply terminal V2, the third voltage supply terminal V3, the fourth voltage supply terminal V4, the fifth voltage supply terminal V5, and the sixth voltage supply terminal in the above embodiment V6, the seventh voltage supply terminal V7, and the eighth voltage supply terminal V8 each provide a voltage higher than 0V. The first voltage supply terminal V1, the second voltage supply terminal V2, the third voltage supply terminal V3, the fourth voltage supply terminal V4, the fifth voltage supply terminal V5, the sixth voltage supply terminal V6, the seventh voltage supply terminal V7, and the first The voltage of the eight voltage supply terminals V8 may be the same or different, and may be adjusted according to the working requirements of the equalization protection circuit.

The embodiment of the invention further provides a battery equalization system, which includes the equalization protection circuit in the above embodiment. The battery equalization system may further include an equalization control chip, a battery module or other functional chips and functional modules, which are not limited herein.

The features, structures, or characteristics described in the above embodiments may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are set forth However, those skilled in the art will appreciate that the technical solution of the present invention may be practiced without one or more of the specific details, or other components or the like may be employed. In other instances, well-known structures, materials, etc. are not shown or described in detail to avoid obscuring the invention.

Claims

An equalization protection circuit, comprising:

An undervoltage detection module, wherein the input end of the undervoltage detection module is connected to the equalization voltage sampling end and the first voltage supply end, and the output end of the undervoltage detection module is connected to the input end of the fault signal triggering module, the undervoltage The detecting module is configured to convert the voltage of the first voltage supply end into a reference lower limit voltage, and if the equalization voltage of the equalization voltage sampling end is less than the reference lower limit voltage, output an undervoltage trigger signal to the fault signal triggering module;

An overvoltage detection module, wherein an input end of the overvoltage detection module is connected to the equalization voltage sampling end and a second voltage supply end, and an output end of the overvoltage detection module is connected to an input end of the fault signal triggering module, The overvoltage detection module is configured to convert the voltage of the second voltage supply terminal into a reference upper limit voltage, and if the equalization voltage of the equalization voltage sampling end is greater than the reference upper limit voltage, output an overvoltage trigger signal to the fault signal trigger module. ;

The fault signal triggering module, the output end of the fault signal triggering module is connected to the input end of the fault signal holding module, and the fault signal triggering module is configured to receive the undervoltage triggering signal or the overvoltage triggering signal, The fault signal holding module outputs a fault trigger signal;

The fault signal holding module, the output end of the fault signal holding module is connected to the input end of the protection control module and the external signal output end, and the fault signal holding module is configured to receive the fault trigger signal and generate the hold for a period of time. a fault reporting signal and outputting the fault report signal to the protection control module and the external signal output;

The protection control module, the output end of the protection control module is connected to the equalization control chip, the protection control module is configured to receive the fault report signal, output a work stop signal to the equalization control chip, and control the equalization control The chip stopped working.
The equalization protection circuit according to claim 1, further comprising a reset module, wherein an input end of the reset module is connected to an external signal input end, an output end of the reset module and an input of the fault signal holding module The terminal module is configured to receive a control signal of the external signal input terminal, output a reset signal to the fault signal holding module, and control the fault signal holding module to reset.
The equalization protection circuit according to claim 1, wherein said undervoltage check The measurement module includes a first resistance combination, a second resistance combination, and a first comparator;

Wherein, one end of the first resistor combination is connected to the first voltage supply end, the other end of the first resistor combination is connected to one end of the second resistor combination, and the other end of the second resistor combination is grounded;

a non-inverting input end of the first comparator is connected to the equalization voltage sampling end, and an inverting input end of the first comparator is combined with one end of the first resistor and one end of the second resistor Connected to each other, the output of the first comparator is connected to the fault signal triggering module.
The equalization protection circuit according to claim 1, wherein the overvoltage detection module comprises a third resistor combination, a fourth resistor combination and a second comparator;

Wherein, one end of the third resistor combination is connected to a second voltage supply end, the other end of the third resistor combination is connected to one end of the fourth resistor combination, and the other end of the fourth resistor combination is grounded;

The non-inverting input terminal of the second comparator is connected to the other end of the third resistor combination and the fourth resistor combination, and the inverting input terminal of the second comparator is sampled with the equalization voltage The terminal is connected, and the output of the second comparator is connected to the fault signal triggering module.
The equalization protection circuit of claim 1 , wherein the fault signal triggering module comprises a first optical coupler, the first optical coupler comprising a first light emitting diode and a first photosensitive semiconductor tube;

The anode of the first LED is connected to the third voltage supply end, and the cathode of the first LED is connected to the output of the undervoltage detection module and the output of the overvoltage detection module.

One end of the first photosensitive semiconductor tube is connected to an input end of the fault signal holding module, and the other end of the first photosensitive semiconductor tube is grounded.
The equalization protection circuit according to claim 1, wherein the fault signal holding module comprises a first transistor and a second transistor;

The control end of the first transistor is connected to the output end of the fault signal triggering module, the first end of the first transistor is connected to the fourth voltage supply end, and the second end of the first transistor is Connecting the external signal output terminal;

a control end of the second transistor and a second end of the first transistor and the protection control The input ends of the module are connected, the first end of the second transistor is grounded, and the second end of the second transistor is connected to the output end of the fault signal triggering module.
The equalization protection circuit of claim 1 , wherein the protection control module comprises a third transistor and a second optical coupler, the second optical coupler comprising a second light emitting diode and a second photosensitive semiconductor tube;

a control end of the third transistor is connected to an output end of the fault signal holding module, a first end of the third transistor is grounded, and a second end of the third transistor is connected to a negative end of the second light emitting diode ;

The positive electrode of the second light emitting diode is connected to the fifth voltage supply end;

One end of the second photosensitive semiconductor tube is connected to the equalization control chip, and the other end of the second photosensitive semiconductor tube is grounded.
The equalization protection circuit according to claim 2, wherein the reset module comprises a fourth transistor;

a control end of the fourth transistor is connected to the external signal input end, a first end of the fourth transistor is connected to a sixth voltage supply end, and a second end of the fourth transistor is connected to the fault signal holding module The input is connected.
The equalization protection circuit according to claim 1, further comprising an operation signal providing module, wherein an input end of the working signal providing module is connected to the working signal providing end, and an output end of the working signal providing module is The equalization control chip is connected, and the working signal providing module is configured to provide a working signal for the equalization control chip when the protection control module does not receive the fault report signal.
The equalization protection circuit according to claim 9, wherein the operation signal providing module comprises an equivalent resistance combination and a diode;

The first end of the equivalent resistance combination is connected to the equalization control chip, the second end of the equivalent resistance combination is grounded, and the third end of the equivalent resistance combination is connected to the negative pole of the diode;

The anode of the diode is coupled to the operational signal supply terminal.
A battery equalization system, comprising the equalization protection circuit of any one of claims 1-10.