CN112186279B - Power management system with dormancy activation function - Google Patents
Power management system with dormancy activation function Download PDFInfo
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- CN112186279B CN112186279B CN202011059483.4A CN202011059483A CN112186279B CN 112186279 B CN112186279 B CN 112186279B CN 202011059483 A CN202011059483 A CN 202011059483A CN 112186279 B CN112186279 B CN 112186279B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/0036—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using connection detecting circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
- H02J7/0071—Regulation of charging or discharging current or voltage with a programmable schedule
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M2010/4271—Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Abstract
The invention discloses a power management system with a dormancy activation function, which comprises: the current acquisition module is used for being connected in series on a main loop of the power supply to form lower voltage drop and transmitting the voltage drop subjected to isolation protection and filtering to a current measurement input end of the front-end module; the front-end module is used for digitizing the analog output acquired by the current acquisition module, transmitting the digitized analog output to the main control module, and outputting a first switch control signal and a second switch control signal to the switch module according to the control of the main control module; the main control module is used for receiving the sampling data, determining whether to start the sleep mode according to the sampling data, and controlling the front-end module to output a first switch control signal and a second switch control signal to the switch module to close an NMOS switch tube of the switch module when determining to start the sleep mode; the switch module is used for opening or closing a current path by opening or closing the NMOS switch tube under the control of the first switch control signal and the second switch control signal output by the front-end module; and the battery pack is used for supplying power to the system.
Description
Technical Field
The invention relates to the technical field of BMS (Battery Management System), in particular to a power Management System of a marine lithium Battery with a dormancy activation function.
Background
The lithium ion battery has become an ideal energy source for development in the 21 st century because of its advantages of high working voltage, small size, light weight, high energy, no memory effect, no pollution, small self-discharge, long cycle life and the like. With the development of the lithium battery industry, large lithium battery packs are gradually expanded and are gradually applied to various power driving fields such as electric vehicles and electric ships, and the lithium battery packs are also commonly adopted in power driving systems on fishing boats at present.
However, during the working process of the fishing boat, the fishing boat has a fishing break period of several months every year, the fishing boat is in a harbor state during the fishing break period, and most of power systems of the fishing boat are in a stop state. However, most lithium battery protection boards on the current market do not have a dormancy system, and are normally opened passively, so the battery has self-consumption throughout the year, wherein self-consumption current is about tens of milliamperes, which can lead to the loss increase of the battery, if there is long-time nonuse, can lead to the voltage of battery too low, the life-span reduces, can not charge, even scrap the circumstances such as etc., therefore it is very important to increase the function of dormancy in the battery system.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a power management system with a sleep activation function, which reduces the self-power consumption current of a battery system from milliampere level to microampere level by adding the sleep function, almost ignores the self-power consumption, recovers the power supply of a battery pack by adopting a charging activation and discharging activation mode, and avoids inconvenience caused by sleep while reducing the self-power consumption.
To achieve the above and other objects, the present invention provides a power management system with sleep activation function, comprising:
the current acquisition module is used for being connected in series on a main loop of the power supply to form lower voltage drop and transmitting the voltage drop subjected to isolation protection and filtering to a current measurement input end (RS1, RS2) of the front-end module;
the front-end module is used for digitizing the analog output acquired by the current acquisition module, transmitting the digitized analog output to the main control module, and outputting a first switch control signal and a second switch control signal to the switch module according to the control of the main control module;
the main control module is used for receiving the sampling data of the current acquisition module after the front-end module is digitalized, determining whether to start the sleep mode according to the sampling data, and controlling the front-end module to output corresponding first and second switch control signals to the switch module to close an NMOS switch tube of the switch module when the sleep mode is determined to be started;
the switch module is used for opening or closing a current path by opening or closing the NMOS switch tube under the control of the first switch control signal and the second switch control signal output by the front-end module;
and the battery pack is used for supplying power to the system.
Preferably, the system further comprises a discharge activation module, configured to generate a load detection signal and a charge completion signal by detecting whether a negative electrode P-of the control board is at a high level, and transmit the load detection signal and the charge completion signal to the main control module and the front end module, respectively.
Preferably, the system further comprises a charging activation module for outputting a charging activation trigger signal by detecting whether the control board negative pole P-is at a low level.
Preferably, the front-end module further outputs the first and second switch control signals to the switch module according to the received activation signal.
Preferably, when the main control module receives a load detection signal, a charge completion signal, or/and a charge activation trigger signal of the charge activation module of the discharge activation module, the main control module is controlled to exit from the sleep mode, and meanwhile, the front end module outputs corresponding first and second switch control signals to the switch module to turn on an NMOS switch tube of the switch module.
Preferably, the discharge activation module comprises an NPN triode (Q1), an NMOS (Q22), a bias resistor (R13-R14), a protection diode (D3), a charging capacitor (C3), a zener diode (D7), a protection diode (D8), a bias resistor (R36-R37) and a voltage dividing resistor (R16, R18, R23, R35), a control board negative electrode P-is connected to an anode of the protection diode (D3), one end of the voltage dividing resistor (R16), a cathode of the protection diode (D3) is connected to one end of the bias resistor (R14), the other end of the bias resistor (R14) is connected to a base of the NPN triode (Q14) and one end of the bias resistor (R14), an emitter of the NPN triode (Q14) and the other end of the bias resistor (R14) are grounded, a collector of the NPN triode (Q14), i.e. a load detection signal is connected to the master control module, the other end of the voltage dividing resistor (R14) is connected to one end of the charging capacitor (R14), the other end of the charging capacitor (C3) is connected with one end of a voltage dividing resistor (R23), the other end of the voltage dividing resistor (R23) is connected with one end of the voltage dividing resistor (R35), the cathode of the voltage stabilizing diode (D7) and the anode of the protection diode (D8), the cathode of the protection diode (D8) is connected with one end of a bias resistor (R36), the other end of the bias resistor (R36) is connected with one end of a bias resistor (R37) and the grid of the NMOS tube (Q22), the other end of the voltage dividing resistor (R18), the other end of the voltage dividing resistor (R35), the anode of the protection diode (D8) and the source of the NMOS tube (Q22) are grounded, and the drain of the NMOS tube (Q22), namely the charging completion signal, is connected to the front-end module.
Preferably, when the negative electrode P-of the control board is at a high level, the base of the NPN triode (Q1) is triggered, the triode is turned on, so that the load detection signal terminal generates a low level, and the load detection signal is connected to the main control module, so as to ensure that the main control module is activated to work by a signal generated during discharging.
Preferably, when the negative pole P-of the control board is changed from low level to high level, the jump is coupled to the zener diode (D7) through the charging capacitor (C3) for stabilizing voltage, the gate of the NMOS transistor (Q22) is triggered through the series-connected protection diode (D8) and the bias resistor (R36), the NMOS transistor (Q22) is turned on to change the charging completion signal to low level, the charging completion signal is connected to the corresponding input pin of the front-end module, and the preset high level is pulled down to low level, so that the front-end module receives the discharging activation signal to generate the first and second switch control signals, and the sleep is ended.
Preferably, the charging activation module comprises an NPN triode (Q31), a PNP triode (Q32), a bias resistor (R82), an NPN triode (Q34) and a load resistor (R79), the battery pack comprises a load resistor (R71), a current-limiting resistor (R74), a voltage stabilizing diode (D18), a protection diode (D15) and bias resistors (R58, R72 and R78), wherein the positive pole B + of the battery pack is connected with the emitter of the PNP triode (Q32) and one end of the bias resistor (R72), the other end of the bias resistor (R72) is connected with the base of the PNP triode (Q32) and one end of the load resistor (R71), the other end of the load resistor (R71) is connected with the NPN collector of the NPN triode (Q31), the base of the NPN triode (Q31) is grounded through the bias resistor (R58), the emitter of the NPN triode (Q31) is connected with the anode of the protection diode (D15), and the cathode of the protection diode (D15) is connected with a negative control board P-; the collector of the PNP triode (Q32) is connected to the cathode of the zener diode (D18) and one end of the bias resistor (R78) through the current limiting resistor (R74), the other end of the bias resistor (R78) is connected to one end of the bias resistor (R82) and the base of the NPN triode (Q34), the main control power supply VDD is connected to the collector of the NPN triode (Q34) through the load resistor (R79), namely the charging activation trigger signal, the anode of the zener diode (D18), the other end of the bias resistor (R82) and the emitter of the NPN triode (Q34) are grounded.
Preferably, if it is detected that the negative electrode P-of the control board is a negative level, the NPN transistor (Q31) is turned on, a connection point between a collector of the NPN transistor (Q31) and the load resistor (R71) is a low level, the low level triggers the PNP transistor (Q32) to be turned on, the positive electrode B + of the battery pack is transmitted to the voltage regulator diode (D18) through the PNP transistor (Q32) and the current limiting resistor (R74), the regulated voltage is divided by the bias resistors (R78, R82) and then the NPN transistor (Q34) is turned on, at this time, the collector of the NPN transistor (Q34), i.e., the charging activation trigger signal, is pulled down from the high level to the low level, and the charging activation trigger signal is connected to a corresponding input pin of the main control module, so that generation of the charging activation trigger signal is realized, and the sleep mode is released.
Compared with the prior art, the power management system with the sleep activation function is added with the sleep function through the BMS, when no current is generated in a certain time, the system is started in the sleep mode, the self-power consumption current of the marine battery system is reduced from milliampere level to microampere level, the self-power consumption can be almost ignored, meanwhile, when the current is generated outside, the battery pack is recovered by adopting a charging activation and discharging activation mode, and inconvenience caused by sleep is avoided while the self-power consumption is reduced.
Drawings
FIG. 1 is a circuit diagram of a power management system with sleep activation according to the present invention;
FIG. 2 is a detailed circuit diagram of the current collection module 10 in an embodiment of the present invention;
FIG. 3 is a detailed circuit diagram of the switch module 40 according to one embodiment of the present invention;
FIG. 4 is a detailed circuit diagram of the discharge enable module 85 according to one embodiment of the present invention;
FIG. 5 is a detailed circuit diagram of the charge activation module 95 according to one embodiment of the present invention;
fig. 6 is a detailed circuit diagram of the main control module 70 according to an embodiment of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 1 is a circuit diagram of a power management system with sleep activation function according to the present invention. As shown in fig. 1, a power management system with sleep activation function of the present invention includes: the battery pack comprises a current collection module 10, a switch module 40, a main control module 70, a front end module 80, a discharge activation module 85, a charge activation module 95 and a battery pack 100.
The current acquisition module 10 is composed of a plurality of high-precision low-resistance sampling resistors, current measurement filter capacitors C32-C34, and protection isolation resistors R87 and R98, and is used for being connected in series on a main power circuit to form a lower voltage drop and transmitting the voltage drop subjected to isolation protection and filtering to current measurement input ends RS1 and RS2 of the front-end module 80 as shown in fig. 2;
the switch module 40 is composed of a plurality of parallel sub-switch arrays connected in series, the present embodiment is composed of a first parallel sub-switch array (bias resistors R4-R12 and MOS switch transistors Q2-Q10) connected in series with a second parallel sub-switch array (bias resistors R26-R34 and NMOS switch transistors Q12-Q20), each parallel self-switch array is composed of 9 MOS switch transistors (WSD75100 micro), as shown in fig. 3, and is configured to open or close a current path by opening or closing the NMOS switch transistors under the control of a switch control signal P3-P4 output by the front-end module 80;
the front-end module 80 is configured to digitize the analog output collected by the current collecting module 10 and transmit the digitized analog output to the main control module 70, and output first and second switch control signals P3 and P4 to the switch module 40 according to a control or activation signal of the main control module 70;
the main control module 70 is composed of a microprocessor MCU (U4, SH79F6441), a reset switch S1, isolation resistors R41 and R51, protection diodes D12 and D14, a filter capacitor C14, a reset capacitor C12, serial isolation resistors R94-R95, a serial protection diode D20-D21, a serial socket JP3, and a programming socket JP1, as shown in fig. 4, and is configured to receive sampling data of the current collection module 10 after digitization by the front-end module 80, determine whether to start the sleep mode according to the sampling data, control the front-end module 80 to output corresponding first and second switch control signals P3 and P4 to the switch module 40 to turn off an NMOS switch tube of the switch module 40 when determining to start the sleep mode, thereby reduce power consumption of an external LOAD, and, when the main control module 70 receives a LOAD detection signal LOAD of the discharge activation module 85, a charge completion signal CHGD or/or a charge activation signal Charger of the charge activation module 95, the main control module 70 is controlled to exit the sleep mode, and meanwhile, the front end module 80 outputs the corresponding first and second switch control signals P3, P4 to the switch module 40 to turn on the NMOS switch of the switch module 40.
The discharge activation module 85 is configured to generate a LOAD detection signal LOAD and a charge completion signal CHGD by detecting whether an output B-of the battery pack 100, which is simply a P-negative electrode P-through the current collection module 10 and the switch module 40, is at a high level or not, and transmit the LOAD detection signal LOAD and the charge completion signal CHGD to the main control module 70 and the front end module 80, respectively;
the charging activation module 95 is configured to output a charging activation trigger signal, charge, by detecting whether the negative electrode P "of the control board is at a low level;
the battery pack 100 is composed of a plurality of single batteries connected in series and used for supplying power to the marine system, and in the embodiment, the battery pack 100 is composed of 8 batteries connected in series.
Specifically, 8 single batteries of the battery pack 100 are sequentially connected in series, the positive electrode B8 of the 8 th battery is connected in series with a positive electrode protection resistor R149(0R) to form a positive electrode B + of the battery pack, the negative electrode B0 of the 1 st battery is connected in series with a negative electrode protection resistor R147-R148(0R) to form a negative electrode B-of the battery pack, and the common end of the isolation resistors R147-R148(0R) is grounded; the negative pole P-of the control board is connected to the input end of the switch module 40, and the output negative pole P2 of the switch module 40 is connected to the input end of the current acquisition module 10; the current collection module 10 is connected in series with the main loop of the load power supply, namely the current input end of the current collection module is connected with the main loop of the load, namely the output cathode P2 of the switch module 40, and the current output end of the current collection module 10 is connected with the cathode B-of the battery pack; the front-end module 80 passes through a communication port (serial UART or two-wire I)2Protocol C, etc.) is connected to the main control module 70; the negative electrode P-of the control board is connected to the input terminals of the discharging activation module 85 and the charging activation module 95, the output LOAD detection signal LOAD of the discharging activation module 85 is connected to the main control module 70, the charging completion signal CHGD is connected to the front-end module 80, and the output charging permission signal charge of the charging activation module 95 is connected to the main control module 70.
Fig. 2 is a detailed circuit diagram of the current collection module 10 according to an embodiment of the present invention. In the embodiment of the invention, the current collecting module 10 is composed of four high-precision low-resistance sampling resistors, current measuring filter capacitors C32-C34 and protection isolation resistors R87 and R98, the four high-precision low-resistance sampling resistors adopt 4 3mR (3 milliohm) high-precision constantan wires R90-R93, the 4 chip resistors are connected in parallel and then connected in series on the negative circuit of the control board, the current is sampled by using the voltage drop formed by the current flowing through the sampling resistors, the voltage values at two ends of the 4 sampling resistors are measured, two protection isolation resistors (R87 and R98) are respectively connected in series on the measuring circuit to realize the protection function, the three current measuring filter capacitors C32-C34 are connected in parallel between two ends of the measuring circuit and the ground to realize the filtering to stabilize the measured voltage value, the stability and correctness of the measurement are ensured, the two filtered measuring voltages RS1 and RS2 are connected to the current sampling input end of the front end chip of the front end module, and then the front-end chip is used for quantizing the measurement voltage at the two ends of the sampling resistor and the MCU is used for calculating so as to obtain the current magnitude.
Fig. 3 is a detailed circuit diagram of the switch module 40 according to an embodiment of the present invention. In the embodiment of the present invention, the switch module 40 is composed of a first parallel sub-switch array (bias resistors R4-R12 and NMOS switch transistors Q2-Q10) connected in series with a second parallel sub-switch array (bias resistors R26-R34 and NMOS switch transistors Q12-Q20), the MOS switch transistor is an important part of the whole circuit switch and is an actuating device of the whole protection board (referring to the circuit board including all the circuits of the present invention), wherein 18 WSD75100 (micro-large) NMOS switch transistors are connected in parallel to form a switch capable of bearing peak current and large current, specifically, the first switch control signal P3 is connected to the gates of the NMOS switch transistors Q2-Q10 through bias resistors R4-R12 respectively, the second switch control signal P4 is connected to the gates of the NMOS switch transistors Q12-Q20 through bias resistors R26-R34 respectively, the negative electrode P-Q-switch control board is connected to the drains Q2-Q10 of the NMOS switch transistors Q2-Q352, the sources of the NMOS switching tubes Q2-Q10 are connected to the drains of the NMOS switching tubes Q12-Q20, and the sources of the NMOS switching tubes Q2-Q10 are connected to form the output cathode P2 of the switching module 40.
Fig. 4 is a detailed circuit diagram of the discharge activation circuit 85 according to an embodiment of the present invention. In the specific embodiment of the present invention, the discharge activation module 85 is composed of an NPN triode Q1, an NMOS transistor Q22, bias resistors R13-R14, a protection diode D3, a charging capacitor C3, a zener diode D7, a protection diode D8, bias resistors R36-R37, voltage dividing resistors R16, R18, R23, and R35, a control board negative electrode P-is connected to an anode of the protection diode D3 and one end of the voltage dividing resistor R16, a cathode of the protection diode D3 is connected to one end of the bias resistor R14, the other end of the bias resistor R14 is connected to a base of the NPN triode Q1 and one end of the bias resistor R13, an emitter of the NPN triode Q1 and the other end of the bias resistor R13 are grounded, and a collector of the NPN triode Q1, that is, i.e., a LOAD detection signal LOAD, is connected to the main control module 70; the other end of the voltage dividing resistor R16 is connected to one end of the voltage dividing resistor R18 and one end of the charging capacitor C3, the other end of the charging capacitor C3 is connected to one end of the voltage dividing resistor R23, the other end of the voltage dividing resistor R23 is connected to one end of the voltage dividing resistor R35, the cathode of the zener diode D7 and the anode of the protection diode D8, the cathode of the protection diode D8 is connected to one end of the bias resistor R36, the other end of the bias resistor R36 is connected to one end of the bias resistor R37 and the gate of the NMOS transistor Q22, the other end of the voltage dividing resistor R18, the other end of the voltage dividing resistor R35, the anode of the protection diode D8 and the source of the NMOS transistor Q22 are grounded, and the drain of the NMOS transistor Q22, that is, i.e., the charging completion signal CHGD, is connected to the front-end module 80.
When the negative pole P-of the control panel is high level (the main loop is temporarily switched on through a mechanical switch at the moment of discharging), the base electrode of the triode Q1 is triggered, the triode is switched on, the LOAD detection signal LOAD end generates low level, the LOAD is connected to the MCU pin, and it is guaranteed that the MCU works by generating signals when discharging. When the P-level is changed from low level to high level, the jump is coupled to a voltage stabilizing diode D7 for voltage stabilization through a capacitor C3, the grid of an NMOS tube Q22 is triggered through a protective diode D8 and a bias resistor R36 which are connected in series, a Q22 is turned on to enable a charging completion signal CHGD to become low level, the end of the charging completion signal CHGD is connected to a corresponding input pin of the front-end module 80, the preset high level is pulled down to be low level, the front-end chip receives a discharging activation signal to generate, and the dormancy stopping is finished
Fig. 5 is a detailed circuit diagram of the charge activation module 95 according to an embodiment of the present invention. In the specific embodiment of the present invention, the charging activation module 95 is composed of an NPN triode Q31, a PNP triode Q32, R82, an NPN triode Q34, a load resistor R79, a load resistor R71, a current limiting resistor R74, a zener diode D18, a protection diode D15, a bias resistor R58, R72, and R78, wherein a positive electrode B + of the battery pack is connected to an emitter of the PNP triode Q32 and one end of the bias resistor R72, the other end of the bias resistor R72 is connected to a base of the PNP triode Q32 and one end of the load resistor R71, the other end of the load resistor R71 is connected to a collector of the NPN triode Q31, a base of the NPN triode Q31 is grounded through the bias resistor R58, an emitter of the NPN triode Q31 is connected to an anode of the protection diode D15, and a cathode of the protection diode D15 is connected to a negative electrode P-; the collector of the PNP triode Q32 is connected to the cathode of the zener diode D18 and one end of the bias resistor R78 through the current limiting resistor R74, the other end of the bias resistor R78 is connected to one end of the bias resistor R82 and the base of the NPN triode Q34, the main control power supply VDD is connected to the collector of the NPN triode Q34, i.e., the charge activation trigger signal, through the load resistor R79, and the anode of the diode D18, the other end of the bias resistor R82, and the emitter of the NPN triode Q34 are grounded.
In the invention, the charging activation circuit triggers the voltage on a load resistor R71 of an NPN triode Q31 to be high or low by detecting whether the voltage at the negative electrode P-end of a control panel is changed, if the negative electrode P-end of the control panel is detected to be a negative level (the external voltage is higher than the battery voltage during charging, the mcu of a main control module 70 judges the voltage, a MOS tube of a control switch module is switched on or off to switch on or switch off a current path, after the current path is switched on, the P-is a lower level and is negative to the ground), the NPN triode Q31 is switched on, the connection point of the collector of the NPN triode Q31 and the load resistor R71 is a low level, the low level triggers the PNP triode Q32 to be switched on, the positive electrode B + of a battery pack is transmitted to a voltage stabilizing diode D18 through the PNP triode Q32 and a current limiting resistor R74, the voltage after the voltage is divided by bias resistors R78 and R82 to trigger a triode Q34 to be switched on, at this time, the collector of the NPN triode Q34, namely a charging activation signal charge is pulled from a high level to a low level, the charging activation trigger signal, charge, is connected to a corresponding input pin of the main control module 70, so that generation of the charging activation trigger signal is realized, and the sleep mode is released;
on the contrary, when P-is not low, Q31 and Q32 are both off, R74 and R78 resistors are both low, Q34 cannot be turned on, and the charge end is pulled up by the resistor R79, so the charge end always keeps high.
Fig. 6 is a detailed structural diagram of the main control module 70 according to an embodiment of the present invention. As shown in fig. 6, the main control module 70 is composed of a microprocessor MCU (U4, SH79F6441), a test switch S1, isolation resistors R41 and R51, protection diodes D12 and D14, a filter capacitor C14, a reset resistor R76, a reset capacitor C12, a serial isolation resistor R94-R94, a serial protection diode D94-D94, a serial socket JP 94, and a programming socket JP 94, the microprocessor MCU (U94, SH79F6441) is a minimum system configuration, a serial receiving RXD, a serial transmitting TXD are respectively connected to the serial socket JP 94 through the serial isolation resistors R94 and R94, and the parallel serial protection diodes D94-D94 bottom, a CHGD signal is connected to the anode of the protection diode D94 through the isolation resistor R94, the cathode of the protection diode D94 is grounded through the test switch S94, a KEY-M of one port of the microprocessor U94 is connected to the anode of the protection diode D94 through the isolation resistor R94, and the cathode of the protection diode D94 is connected to the ground through the test switch S94, the programming socket JP1 is connected to the power supply voltage VDD and ground and to the programming ports TCK, TDI, TMS, TDO of the microprocessor U4, the filter capacitor C14 is connected across the power supply terminal of the microprocessor U4 and ground, and the RESET capacitor C12 is connected across the RESET terminal RESET of the microprocessor U4 and ground (the RESET resistor is in the front end block 80).
In the invention, the sleep mode is realized by detecting whether current is generated currently according to the current acquisition module, the sleep mode is always kept normally when the current acquisition module detects that current is generated all the time, when the current acquisition module detects that no current is generated for a certain time, such as several preset hours, a Microprocessor (MCU) of the main control module starts the sleep mode, and the front-end module generates a first switch control signal P3 and a second switch control signal P3 to close an NMOS switch tube of the switch module, thereby reducing the self-consumption of external loads.
When current is generated outside, the dormant microprocessor of the main control module can be awakened through signals collected by the charging activation circuit and the discharging activation circuit, namely, when charging or external load is generated under an activation condition, normal work of an MCU chip of the main control module can be triggered, when an activation signal is generated, an NMOS switch of a switch module can be controlled to be turned on through a front-end chip IC of the front-end module, the speed of the switch is very quick, and the whole power supply delay only exists for a few microseconds.
In summary, the power management system with the sleep activation function of the present invention adds the sleep function to the BMS system, and when no current is generated within a certain time, the system starts the sleep mode, so that the self-consumption current of the marine battery system is reduced from milliampere level to microampere level, and the self-consumption can be almost ignored, and when a current is generated outside, the battery pack is restored by using the charging activation and discharging activation, so that inconvenience due to sleep is avoided while the self-consumption is reduced.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (7)
1. A power management system with sleep activation functionality, comprising:
the current acquisition module is used for being connected in series on a main loop of the power supply to form lower voltage drop and transmitting the voltage drop subjected to isolation protection and filtering to a current measurement input end of the front-end module;
the front-end module is used for digitizing the analog output acquired by the current acquisition module, transmitting the digitized analog output to the main control module, and outputting a first switch control signal and a second switch control signal to the switch module according to the control of the main control module;
the main control module is used for receiving the sampling data of the current acquisition module after the front-end module is digitalized, determining whether to start the sleep mode according to the sampling data, and controlling the front-end module to output corresponding first and second switch control signals to the switch module to close an NMOS switch tube of the switch module when the sleep mode is determined to be started;
the switch module is used for opening or closing a current path by opening or closing the NMOS switch tube under the control of the first switch control signal and the second switch control signal output by the front-end module;
the battery pack is used for supplying power to the system;
the discharging activation module is used for generating a load detection signal and a charging completion signal by detecting whether a control board negative pole P & lt- & gt is high level and transmitting the load detection signal and the charging completion signal to the main control module and the front end module respectively, the discharging activation module comprises an NPN triode (Q1), an NMOS (Q22), biasing resistors (R13-R14), a protection diode (D3), a charging capacitor (C3), a voltage stabilizing diode (D7), a protection diode (D8), biasing resistors (R36-R37 and voltage dividing resistors (R16, R18, R23 and R35), the control board negative pole P & lt- & gt is connected to an anode of the protection diode (D3) and one end of the voltage dividing resistor (R16), a cathode of the protection diode (D3) is connected to one end of the biasing resistor (R14), the other end of the biasing resistor (R14) is connected to a base of the NPN triode (Q1) and one end of the biasing resistor (R13), and the other end of the emitter of the transistor (Q1) is grounded, the collector of the NPN triode (Q1), namely a load detection signal, is connected to the main control module; the other end of the voltage dividing resistor (R16) is connected with one end of a voltage dividing resistor R18 and one end of a charging capacitor (C3), the other end of the charging capacitor (C3) is connected with one end of a voltage dividing resistor (R23), the other end of the voltage dividing resistor (R23) is connected with one end of a voltage dividing resistor (R35), the cathode of a voltage stabilizing diode (D7) and the anode of a protection diode (D8), the cathode of a protection diode (D8) is connected with one end of a bias resistor (R36), the other end of a bias resistor (R36) is connected with one end of a bias resistor (R37) and the gate of an NMOS tube (Q22), the other end of the voltage dividing resistor (R18), the other end of the voltage dividing resistor (R35), the anode of the protection diode (D8), the source of the NMOS tube (Q22) is grounded, and the drain of the NMOS tube (Q22), namely the charging completion signal is connected to the front-end module;
and the charging activation module is used for outputting a charging activation trigger signal by detecting whether the negative pole P-of the control panel is at a low level.
2. A power management system with sleep activation as claimed in claim 1, wherein: the front-end module also outputs the first and second switch control signals to the switch module according to the received activation signal.
3. A power management system with sleep activation as claimed in claim 2, wherein: when the main control module receives a load detection signal, a charging completion signal or/and a charging activation trigger signal of the charging activation module, the main control module is controlled to exit from a sleep mode, and meanwhile, the front-end module outputs corresponding first and second switch control signals to the switch module to start an NMOS switch tube of the switch module.
4. A power management system with sleep activation as claimed in claim 3, wherein: when the negative pole P-of the control panel is high level, the base electrode of the NPN triode (Q1) is triggered, the triode is turned on, the load detection signal end generates low level, the load detection signal is connected to the main control module, and it is guaranteed that a signal is generated during discharging to activate the main control module to work.
5. A power management system with sleep activation as claimed in claim 4, wherein: when the negative pole P-of the control panel is changed from low level to high level, the jump is coupled to a voltage stabilizing diode (D7) for voltage stabilization through the charging capacitor (C3), the grid electrode of an NMOS (Q22) is triggered through a protection diode (D8) and a bias resistor (R36) which are connected in series, the NMOS (Q22) is turned on to enable the charging completion signal to be changed into low level, the charging completion signal is connected to the corresponding input pin of the front-end module and pulls down the preset high level to be low level, so that the front-end module receives the discharging activation signal to generate a first switch control signal and a second switch control signal, and the dormancy is ended.
6. A power management system with sleep activation as claimed in claim 5, wherein: the charging activation module comprises an NPN triode (Q31), a PNP triode (Q32), a bias resistor (R82), an NPN triode (Q34), a load resistor (R79), a load resistor (R71), a current limiting resistor (R74), a voltage stabilizing diode (D18), a protection diode (D15) and bias resistors (R58, R72 and R78), the positive pole B + of the battery pack is connected with the emitter of the PNP triode (Q32) and one end of a bias resistor (R72), the other end of the bias resistor (R72) is connected with the base of the PNP triode (Q32) and one end of a load resistor (R71), the other end of the load resistor (R71) is connected with the collector of the NPN triode (Q31), the base of the NPN triode (Q31) is grounded through the bias resistor (R58), the emitter of the NPN triode (Q31) is connected with the anode of a protection diode (D15), and the cathode of the protection diode (D15) is connected with the negative pole P-of a control board; the collector of the PNP triode (Q32) is connected to the cathode of the zener diode (D18) and one end of the bias resistor (R78) through the current limiting resistor (R74), the other end of the bias resistor (R78) is connected to one end of the bias resistor (R82) and the base of the NPN triode (Q34), the main control power supply VDD is connected to the collector of the NPN triode (Q34) through the load resistor (R79), namely the charging activation trigger signal, the anode of the zener diode (D18), the other end of the bias resistor (R82) and the emitter of the NPN triode (Q34) are grounded.
7. A power management system with sleep activation as claimed in claim 6, wherein: if the negative electrode P-of the control panel is detected to be a negative level, the NPN triode (Q31) is conducted, the connection point of the collector of the NPN triode (Q31) and the load resistor (R71) is a low level, the low level triggers the conduction of the PNP triode (Q32), the positive electrode B + of the battery pack is transmitted to the voltage stabilizing diode (D18) through the PNP triode (Q32) and the current limiting resistor (R74), the stabilized voltage is divided by the bias resistors (R78 and R82) and then triggers the conduction of the NPN triode (Q34), at the moment, the collector of the NPN triode (Q34), namely the charging activation trigger signal, is pulled down to be the low level from the high level, the charging activation trigger signal is connected to the corresponding input pin of the main control module, the generation of the charging activation trigger signal is realized, and the sleep mode is released.
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