WO2018207831A1 - Programmable logic circuit and semiconductor device using same - Google Patents

Abstract

In order to output two potential values of a power supply voltage and a ground voltage and provide a reconfigurable logic integrated circuit having a small circuit area, this programmable logic circuit is provided with: a first switch; a second switch; a pair of transistors, which is a P-type transistor and an N-type trans each having a gate connected to an input terminal, the P-type transistor having a source connected to the power supply voltage directly or via the first switch, and the N-type transistor having a drain connected to the ground voltage directly or via the second switch; and a third switch which is linked with the first switch and the second switch and outputs, to an output terminal, a drain voltage of the P-type transistor, which is in an on-state and the source of which is connected to the power supply voltage, or a source voltage of the N-type transistor, which is in an on-stae and the drain of which is connected to the ground voltage.

Description

Programmable logic circuit and semiconductor device using the same

The present invention relates to a programmable logic integrated circuit using resistance change elements and a semiconductor device using the same.

A programmable logic circuit is an integrated circuit in which various logic circuits can be reconfigured by rewriting setting information in the circuit. As shown in FIG. 10, a reconfigurable circuit using a programmable logic circuit includes a programmable logic circuit having a lookup table (hereinafter abbreviated as LUT) and a flip-flop, and selection of input / output signals to the programmable logic circuit. And a routing circuit that switches signal paths between programmable logic circuits. The reconfigurable circuit is currently widely used in fields such as image processing and communication, and is also used for circuit trials at the development stage.

The routing circuit performs signal path switching such as switching between input [k] and input [k + 1] and outputting to output [n] with a switch as shown in FIG. As an example of this switch, FIG. 12 shows an SRAM switch composed of SRAM (Static Random Access Memory), a pass transistor having PMOS (P-type Metal-Oxide-Semiconductor) and NMOS (N-type MOS). The path to the output [n] of the input “k” can be switched by turning on and off the pass transistor with a signal from the SRAM.

Patent Documents 1 and 2 disclose techniques for reducing the circuit area and power consumption by replacing the SRAM of the routing circuit with a resistance change element. Japanese Patent Application No. 2017-78050 proposes a technique for replacing an SRAM used as a memory of an LUT in a programmable logic circuit with a resistance change element.

As disclosed in Patent Document 1 and Patent Document 2, the resistance change element uses precipitation of metal bridges in an ion conductive layer through which metal ions are conducted. The variable resistance element has a structure in which an active electrode that supplies metal ions to an ion conductive layer and an inactive electrode that does not supply metal ions sandwich an ion conductive layer. The variable resistance element is turned on and off by forming and dissolving a metal bridge that connects the two electrodes in the ion conductive layer. In the resistance change element, the resistance ratio between the low resistance state (on state) and the high resistance state (off state) is 10 to the fifth power or higher.

When a resistance change element is used as a switch in a reconfigurable circuit, since a voltage is always applied to all elements on the circuit, it is more reliable than a memory in which voltage or current is applied only during reading. Sex is required. In order to realize this high reliability, Patent Document 3 and Patent Document 4 disclose complementary switch elements including two pairs of resistance change elements and one transistor. Further, Patent Document 5 discloses a complementary switching element in which a transistor is replaced with a varistor (Variable Resistor) element formed in a wiring layer in order to suppress an increase in element area due to the transistor and to reduce the element size. It is disclosed. A varistor element is an element that has two terminals and changes from an insulated state to a conductive state when a voltage difference between the terminals exceeds a threshold value.

JP 2005-101535 A International Publication No. 2012/043502 International Publication No. 2013/190742 International Publication No. 2014/030393 International Publication No. 2016/163120

The LUT of the programmable logic circuit can be divided into a memory and a selection circuit as shown in FIG. The memory is composed of an SRAM, a switch element provided in a wiring layer as shown in FIG. Further, for example, as shown in FIG. 15, in the case of a two-input LUT, three selection circuits are required to form a one-input multiplexer in two stages. As shown in FIG. 16A, the multiplexer uses a CMOS (Complementary MOS) switch for signal switching, so that the number of transistors is 4 for NMOS and PMOS in a single multiplexer and 12 in total for 3 units. .

On the other hand, the existing two-input logic circuit of NAND (NAND) and NOR (NOR) can be composed of four transistors. That is, there is a problem that when a logical operation is performed by an LUT using a selection circuit by a multiplexer using a CMOS switch, a circuit area increases because a large number of transistors are required.

Further, according to the circuit for selecting a signal with one NMOS and one PMOS as shown in FIG. 16B instead of CMOS, the number of transistors can be reduced to six with three multiplexers. However, in this case, as shown in FIG. 17, the output voltage from the LUT is smaller than the difference between the ground (GND) and the power supply voltage (V _DD ) by the threshold voltage of each NMOS and PMOS transistor. Become. For this reason, when the output voltage from the LUT is introduced into the subsequent circuit, a sufficient voltage cannot be obtained at the CMOS gate, or the leakage current increases due to the intermediate potential. As a result, in a reconfigurable circuit in which a plurality of programmable logic circuits are combined, reduction in operating frequency and increase in power consumption are problems.

In Patent Documents 1 to 5, a logic that can be reconfigured without causing an increase in circuit area or a decrease in output voltage by using the variable resistance element disclosed in Patent Documents 1 to 5 as a switch. A technique for realizing an integrated circuit is not disclosed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a logic integrated circuit that outputs a binary potential of a power supply voltage and a ground and that can be reconfigured with a small circuit area. It is in.

The programmable logic circuit of the present invention includes a first switch, a second switch, a P-type transistor having a gate connected to an input terminal and a source connected to the power supply voltage via the first switch or directly. The source is connected to the power supply voltage in conjunction with two sets of N-type transistors whose drains are grounded via the second switch or directly to the ground, and the first and second switches; And a third switch that outputs to the output terminal the voltage of the drain of the P-type transistor that is turned on, or the voltage of the source of the N-type transistor that is grounded and turned on.

The semiconductor device of the present invention has the programmable logic circuit of the present invention.

According to the present invention, it is possible to provide a logic integrated circuit that outputs a binary potential of a power supply voltage and a ground and that can be reconfigured with a small circuit area.

It is a figure which shows the structure of the programmable logic circuit of the 1st Embodiment of this invention. It is a figure which shows the structure of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure for demonstrating operation | movement of the switch of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure for demonstrating the magnitude | size of the output signal of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure which shows the structure of the switch of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure for demonstrating the connection with the wiring of the switch of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure which shows the structure of the variable resistance element of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure which shows the variable resistance element of the programmable logic circuit of the 2nd Embodiment of this invention symbolically. It is a figure for demonstrating operation | movement of the resistance change element of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure for demonstrating a response | compatibility with the switch and logic operation of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure for demonstrating a response | compatibility with the switch of the programmable logic circuit of the 2nd Embodiment of this invention, and logic operation (negative). It is a figure for demonstrating a response | compatibility with the switch of the programmable logic circuit of the 2nd Embodiment of this invention, and a logical operation (negative logical product). It is a figure for demonstrating the response | compatibility with the switch of the programmable logic circuit of the 2nd Embodiment of this invention, and logic operation (negative OR). It is a figure for demonstrating a response | compatibility with the switch and programmable logic (clamp) of the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor device using the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor device using the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor device using the programmable logic circuit of the 2nd Embodiment of this invention. It is a figure which shows the structure of a known reconstruction circuit. It is a figure for demonstrating the switch of the routing circuit of a known reconstruction circuit. It is a figure which shows the structure of the SRAM switch of the routing circuit of a known reconstruction circuit. It is a block diagram which shows the structure of a known LUT. It is a figure which shows the structure of the switch of a known LUT. It is a block diagram which shows the structure of a known LUT. It is a figure which shows the structure of the multiplexer of a known LUT. It is a figure which shows another structure of the multiplexer of a known LUT. It is a figure for demonstrating the magnitude | size of the output signal of a known LUT.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the preferred embodiments described below are technically preferable for carrying out the present invention, but the scope of the invention is not limited to the following.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a programmable logic circuit according to the first embodiment of the present invention. The programmable logic circuit 1 according to this embodiment includes a first switch 11 and a second switch 12. Furthermore, a P-type transistor 14 whose gate is connected to the input terminal and whose source is connected to the power supply voltage (V _DD ) via the first switch 11 or directly, and whose drain is connected via the second switch 12 or directly. And two sets 16 of N-type transistors 15 to be grounded. Further, in conjunction with the first switch 11 and the second switch 12, the drain voltage of the P-type transistor 14 whose source is connected to the power supply voltage and turned on, or the drain is grounded and turned on. A third switch 13 is provided for outputting the source voltage of the N-type transistor 15 to the output terminal.

According to the programmable logic circuit 1, a logical operation can be reconfigured by a combination of on / off of the first to third switches, and the output of the logical operation can be a binary value of a power supply voltage and ground. Furthermore, since the programmable logic circuit 1 can be configured by four transistors, the circuit area can be reduced.

As described above, according to the present embodiment, it is possible to provide a logic integrated circuit that outputs a binary potential of a power supply voltage and a ground and that can be reconfigured with a small circuit area.

(Second Embodiment)
FIG. 2 is a diagram showing a configuration of the programmable logic circuit 2 according to the second embodiment of the present invention. The programmable logic circuit 2 includes a set of a P-type transistor PMOS [0] and an N-type transistor NMOS [0], and a set of a P-type transistor PMOS [1] and an N-type transistor NMOS [1]. Further, as four kinds of change-over switches, a switch SW _1-1 as a first switch, a switch SW _2-1 as a second switch, switches SW _3-1 , SW _3-2 as third switches, SW _3-3 and SW _3-4 and switches SW _4-1 and SW _4-2 as fourth switches are provided.

As shown in FIG. 3, the above four types of changeover switches exist at the intersections of the intersecting wirings, and switch between electrical connection (on) and non-connection (off) between the intersecting wirings.

SW _1-1 switches between electrical connection and non-connection between the source of PMOS [1] and the power supply voltage (V _DD ) via wiring node [1] to which the source of PMOS [1] is connected. On the other hand, the source of PMOS [0] is connected to V _DD .

The SW _2-1 switches between electrical connection and non-connection between the drain of the NMOS [1] and the ground (GND) via the wiring node [0] to which the drain of the NMOS [1] is connected. On the other hand, the drain of NMOS [0] is connected to GND.

SW _3-1 exists in a node to which the drains of both PMOS [0] and PMOS [1] are connected, and switches between electrical connection and non-connection between the node and the wiring node [0]. SW _3-2 exists at a node to which the sources of both NMOS [0] and NMOS [1] are connected, and switches between electrical connection and non-connection between the node and the wiring node [1]. SW _3-3 and SW _3-4 exist in the wiring node [0] and the wiring node [1], respectively, and are electrically connected and disconnected between the wiring node [0] and the output terminal OUT, respectively. The electrical connection and disconnection between the node [1] and the output terminal OUT are switched.

SW _4-1 and SW _4-2 perform switching to input the input signal Di [1] of the input terminal IN [1] or the power supply voltage to the gates of both PMOS [1] and NMOS [1], respectively. . On the other hand, the input signal Di [0] of the input terminal IN [0] is input to the gates of both PMOS [0] and NMOS [0]. Note that a switch for switching between electrical connection and non-connection may be provided between the gates of the PMOS [0] and NMOS [0] and the input terminal IN [0].

The input signals Di [0] and Di [1] have a high signal or a low signal. In High, NMOS is turned on and PMOS is not turned on. On the other hand, at Low, PMOS is turned on and NMOS is not turned on.

In the wiring node [0], either SW _2-1 or SW _3-1 is interlocked and one of them is turned on, so that pull-up to the power supply voltage via the PMOS or via the NMOS is performed. Pulled down to GND. Also, the wiring node [1] is connected to SW _1-1 and SW _3-2 and either one is turned on, so that pull-up to the power supply voltage via PMOS or via NMOS is performed. Pull down to all GND. As described above, the potentials of the wiring node [0] and the wiring node [1] are binary values of the power supply voltage and GND. That is, the magnitude of the output signal can be the difference between the power supply voltage and GND, as shown in FIG.

Strictly speaking, the wiring node [0] [1] is connected between the wiring node [0] [1] and the on-resistance of the PMOS or NMOS, the wiring resistance of the wiring, etc. existing between the power supply voltage and GND. The potential output to the voltage drops below the power supply voltage and rises above GND. However, such a potential drop or rise is sufficiently smaller than the potential drop or rise due to the threshold voltage of the PMOS or NMOS described in FIG. Furthermore, such potential drops or rises in electronic circuits using normal PMOS, NMOS, or interconnects can be used to sufficiently increase the gate voltage to lower the on-resistance, or to control the cross-sectional area and length of the interconnects. This can be dealt with by reducing the wiring resistance. Therefore, in the present embodiment and the entirety of this specification, the outputs of the wiring node [0] and the wiring node [1] are included in order to briefly explain the effects, including such potential drops and increases. It is assumed that the binary value of the power supply voltage and GND.

The above four types of change-over switches (first to fourth switches) are preferably switched on / off by a switch element formed in the wiring layer without including a transistor. The four-terminal switch 20 shown in FIG. can do. The four-terminal switch 20 has two terminals each and is connected in series. The first resistance change element 21 and the first varistor element 23, the second resistance change element 22, and the second varistor element 24 are connected. Are connected at the terminals connected in series.

The first resistance change element 21 and the second resistance change element 22 have a bipolar characteristic that has a polarity in the direction of application of a voltage for resistance change. The first variable resistance element 21 and the second variable resistance element 22 are connected with the same polarity. The first varistor element 23 and the second varistor element 24 are bipolar, and change from an insulated state to a conductive state when the potential difference between the terminals exceeds a threshold value.

FIG. 5B is a diagram for explaining the connection between the four-terminal switch 20 and the wiring. Terminals other than the terminal to which the first resistance change element 21 and the second resistance change element 22 are connected in series are connected to the first signal line and the second signal line, respectively. In addition, terminals different from the terminal to which the first varistor element 23 and the second varistor element 24 are connected in series are connected to the first control line and the second control line, respectively. The four-terminal switch 20 enables signal transmission between the first signal line and the second signal line when both the first resistance change element 21 and the second resistance change element 22 are turned on. . The first control line and the second control line turn on and off the first resistance change element 21 and the second resistance change element 22 together with the first signal line and the second signal line. In FIG. 2, the control lines are omitted.

First, when switching the first resistance change element 21, a predetermined voltage is applied between the first signal line and the second control line. For the second variable resistance element 22 that is not switched at this time, the voltage between the second signal line and the first control line is the voltage at which the first varistor element 23 changes from the insulated state to the conductive state. Do not exceed the threshold.

Next, when switching the second variable resistance element 22, a predetermined voltage is applied between the second signal line and the first control line. For the first variable resistance element 21 that is not switched at this time, the voltage between the first signal line and the second control line is prevented from exceeding the threshold value of the second varistor element 24.

The first resistance change element 21 and the second resistance change element 22 are resistance change elements that change the resistance state by applying a predetermined voltage for a predetermined time and maintain the changed resistance state. Good. Also, the first resistance change element 21 and the second resistance change element 22 have a polarity in the direction in which the resistance change voltage is applied from the viewpoint of increasing the disturbance resistance when the signal is continuously passed and used. It is desirable to have some bipolar characteristics.

As the resistance change element, a ReRAM (Resistance Random Access Memory) element using a transition metal oxide, a NanoBridge (registered trademark) element using an ion conductor, or the like can be used.

6A shows the structure of the resistance change element, FIG. 6B shows a symbolic representation of the resistance change element, and FIG. 6C shows a method of switching the resistance state of the resistance change element. As illustrated in FIG. 6A, the resistance change element includes a resistance change layer, and a first electrode and a second electrode provided on opposite surfaces in contact with the resistance change layer.

When an ion conductor is used for the resistance change layer, metal ions are supplied from the first electrode to the resistance change layer, and metal ions are not supplied from the second electrode. Thereby, the variable resistance element can have bipolar characteristics. Examples of the ion conductor include oxides containing Al, Ti, Ta, Si, Hf, Zr, chalcogenide compounds containing Ge, As, TeS, etc., organic polymer films containing carbon, oxygen, and silicon. Can be used. For example, copper can be used as the first electrode, and ruthenium can be used as the second electrode.

As shown in FIG. 6C, by changing the polarity of the voltage applied to the resistance change layer between the first electrode and the second electrode, the resistance value of the resistance change element can be changed to control the conduction state between the electrodes. it can. That is, by controlling the voltage applied between both electrodes, a metal bridge is formed and connected between both electrodes in the ionic conductor, and the metal bridge is dissolved and cut. Thereby, the resistance between both electrodes can be changed between a low resistance state (referred to as an on state) and a high resistance state (referred to as an off state). Since the resistance ratio between the low resistance state and the high resistance state can be set to, for example, 10 5 or higher, the resistance change element functions as a switch that is electrically connected or disconnected. Further, the low resistance state and the high resistance state are non-volatile, and the on and off states are maintained even when no voltage is applied.

The varistor element can have a laminated structure in which a rectifying layer is sandwiched between opposing electrode layers. For example, silicon nitride can be used as the rectifying layer, and nitride of titanium or tantalum can be used as the electrode layer. Further, for example, amorphous silicon may be inserted as a buffer layer between the rectifying layer and the electrode layer.

The varistor element has an insulation state with a large impedance (for example, 100 MΩ or more) when no voltage is applied between the electrodes, and when a voltage higher than a threshold value is applied, the impedance decreases and becomes conductive. In the conductive state, a large current of 100 μA or more can be passed.

The varistor element suppresses inflow of current to a resistance change element other than the resistance change element to be turned on / off when the resistance change element is turned on / off. Also, current limiting is performed when the resistance change element is turned on and off. Also, the resistance value when the variable resistance element is on is adjusted. Furthermore, a sneak current (sneak current) through the four-terminal switch in the on state is suppressed during signal transmission through the signal line.

FIG. 7 is a diagram for explaining the correspondence between the switches of the programmable logic circuit 2 and the logical operations. In FIG. 7, a switch that is turned on is indicated by a circle. The input signals Di [0] and Di [1] input from the input terminals IN [0] and IN [1] are negated (NOT) and NANDed (NAND) according to the switch setting of the programmable logic circuit 2. ), NOR (NOR), and clamping. The processing result is output to the wiring nodes [0] and [1] as a binary value of the power supply voltage (V _DD ) and GND. The processing results output to the wiring nodes [0] and [1] are taken out to the output terminal OUT as appropriate by _{turning on} and off the switches SW _3-3 and SW _3-4 .

In FIG. 7, the settings of SW _3-3 and SW _3-4 are omitted. Also, in FIG. 7 and subsequent FIGS. 8A to 8D, the negation of the input signal is represented as “˜”, the product as “&”, and the sum as “|”.

8A to 8D are diagrams showing correspondence between the switches of the programmable logic circuit 2 shown in FIG. 7 and logical operations (negative, negative logical product, negative logical sum, and clamp) using FIG.

FIG. 8A shows a case where the programmable logic circuit 2 performs a negative (NOT) process. In this _{case, SW 3-1, SW 3-2, SW} 3-3, turns on the SW _4-1. By turning on SW _4-1 , V _DD is input to the gates of PMOS [1] and NMOS [1]. On the other hand, the input signal Di [0] is input to the gates of PMOS [0] and NMOS [0].

In PMOS [1] and NMOS [1] to which V _DD is input, PMOS [1] is off and NMOS [1] is on. When the input signal Di [0] is High, PMOS [0] is off and NMOS [0] is on. As a result, both the wiring node [1] and the wiring node [0] become GND through the NMOS [0] connected to the GND and the NMOS [1] connected to the NMOS [0], and the input signal Di [0] The negative GND is output.

When the input signal Di [0] is Low, PMOS [0] is on and NMOS [0] is off. As a result, both the wiring node [0] and the wiring node [1] are connected via the PMOS [0] connected to V _DD and the NMOS [1] connected to the PMOS [0] via the wiring node [0]. V _DD is output, and V _DD which is the negative of the input signal Di [0] is output.

In the case of FIG. 8A, since a negative processing result is output to both the wiring node [0] and the wiring node [1], in order to output a negative processing result to the output terminal OUT, SW _3-3 Any one of SW _3-4 may be turned on. FIG. 8A shows a case where SW _3-3 is turned on.

FIG. 8B shows a case where the programmable logic circuit 2 performs a NAND operation. In this _{case, SW 1-1, SW 3-1, SW} 3-3, turns on the SW _4-2. By turning on SW _4-2 , the input signal Di [1] is input to the gates of PMOS [1] and NMOS [1]. On the other hand, the input signal Di [0] is input to the gates of PMOS [0] and NMOS [0]. Further, the wiring node [1] always becomes V _DD via SW _1-1 .

When the input signal Di [0] is High and the input signal Di [1] is High, PMOS [0] is off, NMOS [0] is on, PMOS [1] is off, and NMOS [1] is on. As a result, the wiring node [0] becomes GND through the NMOS [0] connected to the GND and the NMOS [1] connected to the NMOS [0], and outputs the GND that is the NAND of the input signal.

When the input signal Di [0] is High and the input signal Di [1] is Low, PMOS [0] is off, NMOS [0] is on, PMOS [1] is on, and NMOS [1] is off. As a result, the wiring node [0] becomes V _DD via the PMOS [1] connected to the power supply voltage, and outputs V _DD which is the NAND of the input signal.

When the input signal Di [0] is Low and the input signal Di [1] is High, PMOS [0] is on, NMOS [0] is off, PMOS [1] is off, and NMOS [1] is on. As a result, the wiring node [0], V _DD next through the PMOS [0] to be connected to V _DD, and outputs the V _DD is a NAND of the input signal.

When the input signal Di [0] is Low and the input signal Di [1] is Low, PMOS [0] is on, NMOS [0] is off, PMOS [1] is on, and NMOS [1] is off. As a result, the wiring node [0], V _DD next through the PMOS [0] to be connected to V _DD, and outputs the V _DD is a NAND of the input signal.

Or interconnection node outputting the NAND as [0] via the SW _3-3 is connected to the output terminal OUT. The output terminal OUT outputs the NAND processing result.

FIG. 8C shows a case where the programmable logic circuit 2 performs a negative OR (NOR) process. In this _{case, SW 2-1, SW 3-2, SW} 3-4, turns on the SW _4-2. By turning on SW _4-2 , the input signal Di [1] is input to the gates of PMOS [1] and NMOS [1]. On the other hand, the input signal Di [0] is input to the gates of PMOS [0] and NMOS [0]. Further, the wiring node [0] always becomes GND via the SW _2-1 .

When the input signal Di [0] is High and the input signal Di [1] is High, PMOS [0] is off, NMOS [0] is on, PMOS [1] is off, and NMOS [1] is on. As a result, the wiring node [1] becomes GND through the NMOS [0] connected to the GND, and outputs GND that is the NOR of the input signal.

When the input signal Di [0] is High and the input signal Di [1] is Low, PMOS [0] is off, NMOS [0] is on, PMOS [1] is on, and NMOS [1] is off. As a result, the wiring node [1] becomes GND through the NMOS [0] connected to the GND, and outputs GND that is the NOR of the input signal.

When the input signal Di [0] is Low and the input signal Di [1] is High, PMOS [0] is on, NMOS [0] is off, PMOS [1] is off, and NMOS [1] is on. As a result, the wiring node [1] becomes GND via the NMOS [1] connected to the GND, and outputs GND that is the NOR of the input signal.

When the input signal Di [0] is Low and the input signal Di [1] is Low, PMOS [0] is on, NMOS [0] is off, PMOS [1] is on, and NMOS [1] is off. As a result, the wiring node [1], V _DD becomes via the PMOS [1] to connect to the PMOS [0] and PMOS [0] to be connected to V _DD, and outputs the V _DD is a NOR of the input signal .

The wiring node [1] that outputs NOR as described above is connected to the output terminal OUT via the SW _3-4 . The output terminal OUT outputs a NOR processing result.

FIG. 8D shows a case where the programmable logic circuit 2 performs the clamping process. In this case, SW _1-1 and SW _2-1 are turned on. By turning on SW _1-1 , the wiring node [1] is clamped to V _DD . Further, by turning on the SW _2-1, interconnection node [0] is clamped to GND. Further, when either SW _3-3 or SW _3-4 is turned on, the output terminal OUT outputs GND or V _DD .

As described above, the programmable logic circuit 2 outputs the result of logical operation of the input signal as binary values of V _DD and GND.

The element areas of the N-type transistor (NMOS) and the P-type transistor (PMOS) are about 16 F ² , where F is the minimum design dimension in semiconductor design. The element area of the switch provided in the wiring layer is 4F ² . Here, in the known lookup table shown in FIG. 15, it is assumed that the memory is formed by an in-wiring layer switch and the selection circuit is formed by a CMOS switch shown in FIG. 16A. In this case, the exclusive area of the memory in the wiring layer is 4F ² × 8 = 32F ² because eight switches twice are required to form four memories. Further, the area occupied by the selection circuit on the silicon substrate is 16F ² × 12 = 192F ² . Since the exclusive area of the lookup table is the larger area in the wiring layer and on the silicon substrate, the exclusive area in this case is 192F ² .

On the other hand, in the programmable logic circuit 2 of the present embodiment, the exclusive area in the wiring layer is 4F ² × 8 = 32F ² , and the exclusive area on the silicon substrate is 16F ² × 4 = 64F ² . Compared to 192F ² which is the exclusive area of the lookup table, the exclusive area of the programmable logic circuit 2 is reduced to 1/3.

When the area occupied by the circuit is reduced, the wiring length between the circuit blocks can be shortened, so that the operating power is reduced. Further, in the programmable logic circuit 2, since the output signal is a binary value of the power supply voltage and GND, when this output signal is used as an input signal for the circuit in the subsequent stage, an increase in leakage current due to the intermediate potential can be suppressed. it can.

FIG. 9A is a diagram showing a configuration of the semiconductor device 3 using the programmable logic circuit 2 of the present embodiment. The semiconductor device 3 has a multilayer copper wiring layer, and the switch of the programmable logic circuit 2 can be incorporated in the multilayer copper wiring layer. Further, a flip-flop circuit may be provided at the subsequent stage of the programmable logic circuit 2 so that the output signal of the programmable logic circuit 2 is output in synchronization with the clock via the flip-flop circuit.

The semiconductor device 3 can have an integrated circuit such as a memory circuit having a CMOS transistor or a bipolar transistor, a logic circuit such as a microprocessor, or a circuit on which these are simultaneously mounted. The semiconductor device 3 may also be packaged with resin, metal, ceramic, or the like. Further, an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, a MEMS (Micro Electro Mechanical Systems), or the like can be connected to the semiconductor device 3.

FIG. 9B is a diagram showing a configuration of the semiconductor device 3 using the programmable logic circuit 2 of the present embodiment. As shown in FIG. 9B, by using the output signal of the programmable logic circuit 2 as an input signal of another programmable logic circuit 2, it is possible to configure a logic circuit in which the programmable logic circuit 2 has a multi-stage configuration.

FIG. 9C is a diagram showing a configuration of the semiconductor device 3 using the programmable logic circuit 2 of the present embodiment. As shown in FIG. 9C, a circuit that executes a large-scale logical operation is realized by connecting the programmable logic circuit 2 and a multiplication circuit, a memory, and the like to each other via a routing circuit.

The logic of register transfer level RTL (Register Transfer Level) can be used for designing logical operations using the programmable logic circuit 2. A logic operation described in RTL is converted into a circuit (net list) described by a combination of basic gates of logic operations such as NAND and NOR using a logic synthesis tool. By assigning each basic gate to the programmable logic circuit 2 and connecting the basic gates with a routing circuit, a circuit that executes a large-scale logic operation is realized.

As described above, according to the programmable logic circuit 2 of the present embodiment, the logic operation can be reconfigured by combining the first to fourth switches on and off, and the output of the logic operation is supplied between the power supply voltage and the ground. It can be binary. Furthermore, since the programmable logic circuit 2 can be configured with four transistors, the circuit area can be reduced.

As described above, according to the present embodiment, it is possible to provide a logic integrated circuit that outputs a binary potential of a power supply voltage and a ground and that can be reconfigured with a small circuit area.

The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

A part or all of the above embodiment can be described as follows, but is not limited to the following configuration.
(Appendix 1)
A first switch, a second switch,
A P-type transistor whose gate is connected to the input terminal and whose source is connected to the power supply voltage via the first switch or directly; and an N-type transistor whose drain is connected to the ground via the second switch or directly; , And two pairs,
In conjunction with the first and second switches, the source voltage is connected to the source voltage and the drain voltage of the P-type transistor that is turned on, or the drain is grounded and turned on. And a third switch that outputs the voltage of the source of the transistor to the output terminal.
(Appendix 2)
The input terminal supplies a first input signal to the gate of one of the two P-type transistors and the N-type transistor in the two sets, and the other P-type transistor and the N-type of the two sets. The programmable logic circuit according to appendix 1, wherein a second input signal is input to each gate of the type transistor.
(Appendix 3)
The source of the P-type transistor of one of the two sets is directly connected to the power supply voltage, the drain of the N-type transistor is directly grounded,
The other of the two sets, the source of the P-type transistor is connected to the power supply voltage via the first switch, and the drain of the N-type transistor is grounded via the second switch. The programmable logic circuit according to appendix 1 or 2.
(Appendix 4)
4. The programmable logic circuit according to claim 1, further comprising a fourth switch that switches between connection and non-connection of the input terminal or the power supply voltage and the gate.
(Appendix 5)
The programmable logic circuit according to appendix 4, wherein the first to fourth switches have resistance change elements.
(Appendix 6)
The programmable logic circuit according to appendix 5, wherein the first to fourth switches have two of the variable resistance elements, and the variable resistance elements have bipolar characteristics and are connected in series at the same pole.
(Appendix 7)
The first to fourth switches include two varistor elements, and the two varistor elements are respectively connected to nodes where the variable resistance elements are connected in series at the same pole. Programmable logic circuit.
(Appendix 8)
8. The programmable logic circuit according to one of appendices 5 to 7, wherein the resistance change element changes its resistance by forming and dissolving a metal bridge.
(Appendix 9)
9. A semiconductor device having the programmable logic circuit according to one of appendices 1 to 8.
(Appendix 10)
The semiconductor device according to appendix 9, wherein the semiconductor device has a multilayer copper wiring layer, and the first, second, and third switches of the programmable logic circuit are formed in the multilayer copper wiring layer.
(Appendix 11)
The semiconductor device according to appendix 9 or 10, wherein the output terminal of the programmable logic circuit is connected to the input terminal of another programmable logic circuit.
(Appendix 12)
12. The semiconductor device according to one of appendices 9 to 11, wherein the plurality of programmable logic circuits are connected to each other via a routing circuit.
(Appendix 13)
13. The semiconductor device according to one of appendices 9 to 12, wherein the programmable logic circuit is connected to another integrated circuit via a routing circuit.

This application claims priority based on Japanese Patent Application No. 2017-94507 filed on May 11, 2017, the entire disclosure of which is incorporated herein.

DESCRIPTION OF SYMBOLS 1, 2 Programmable logic circuit 11 1st switch 12 2nd switch 13 3rd switch 14 P-type transistor 15 N-type transistor 16 set 20 4 terminal switch 21 1st resistance change element 22 2nd resistance change element 23 First varistor element 24 Second varistor element 3 Semiconductor device

Claims (13)

A first switch, a second switch,
A P-type transistor whose gate is connected to the input terminal and whose source is connected to the power supply voltage via the first switch or directly; and an N-type transistor whose drain is connected to the ground via the second switch or directly; , And two pairs,
In conjunction with the first switch and the second switch, the drain voltage of the P-type transistor whose source is connected to the power supply voltage and turned on, or the drain is grounded and turned on A programmable logic circuit comprising: a third switch that outputs a voltage of a source of the N-type transistor to an output terminal. The input terminal supplies a first input signal to the gate of one of the two P-type transistors and the N-type transistor in the two sets, and the other P-type transistor and the N-type of the two sets. The programmable logic circuit according to claim 1, wherein a second input signal is input to each gate of the type transistor. The source of the P-type transistor of one of the two sets is directly connected to the power supply voltage, the drain of the N-type transistor is directly grounded,
The other of the two sets, the source of the P-type transistor is connected to the power supply voltage via the first switch, and the drain of the N-type transistor is grounded via the second switch. The programmable logic circuit according to claim 1 or 2. 4. The programmable logic circuit according to claim 1, further comprising a fourth switch for switching between connection and non-connection of the input terminal or the power supply voltage and the gate. The programmable logic circuit according to claim 4, wherein the first to fourth switches include a resistance change element. 6. The programmable logic circuit according to claim 5, wherein the first to fourth switches have two of the variable resistance elements, and the variable resistance elements have bipolar characteristics and are connected in series at the same pole. The first to fourth switches have two varistor elements, and the two varistor elements are respectively connected to nodes where the resistance change elements are connected in series at the same pole. Programmable logic circuit. 8. The programmable logic circuit according to claim 5, wherein the resistance change element changes its resistance by forming and dissolving a metal bridge. A semiconductor device comprising the programmable logic circuit according to claim 1. The semiconductor device according to claim 9, further comprising a multilayer copper wiring layer, wherein the first to third switches of the programmable logic circuit are formed in the multilayer copper wiring layer. 11. The semiconductor device according to claim 9, wherein the output terminal of the programmable logic circuit is connected to the input terminal of another programmable logic circuit. The semiconductor device according to claim 9, wherein the plurality of programmable logic circuits are connected to each other via a routing circuit. 13. The semiconductor device according to claim 9, wherein the programmable logic circuit is connected to another integrated circuit via a routing circuit.

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