WO2019049980A1 - Reconfiguration circuit - Google Patents

Abstract

In order to achieve both high-density implementation of applications in the form a reconfiguration circuit without a redundancy bit and the capability to continuously run applications with redundancy, the present invention is a reconfiguration circuit provided with: a first lookup table composed of a crossbar memory formed in a crossbar switching circuit having a plurality of switch cells including a complementary element and a multiplexer for selecting and outputting at least one of a plurality of signals input from the crossbar memory; a second lookup table composed of a crossbar memory and a multiplexer; and a switch that is connected to an output node of the first lookup table and to an output node of the second lookup table and that switches the output node of the first lookup table and the output node of the second lookup table to an electrically conductive state or a non-conductive state.

Description

Reconstruction circuit

The present invention relates to a reconfiguration circuit whose logic circuit can be reconfigured.

The programmable logic integrated circuit (also referred to as a reconfiguration circuit) can reconfigure various logic circuits by rewriting internal setting information. FIG. 29 is a circuit diagram of a general reconstruction circuit 100. As shown in FIG. The reconfiguration circuit 100 includes a plurality of reconfiguration circuits 101 (hereinafter, referred to as LB: Logic Block) and a plurality of routing units 102 (hereinafter, referred to as RB: Routing Block). The LB includes a look-up table (hereinafter referred to as LUT) and a flip-flop FF. The RB switches input / output signals to / from the LB and switches signal paths between the LBs.

The number of configurable logics (the circuit scale of the reconfiguration circuit) can be adjusted by designing a logic block (hereinafter, CLB: Configurable Logic Block) having LBs and RBs of a certain size. And, by adjusting the number of CLBs arranged to interconnect, it is possible to manufacture a semiconductor chip including reconfiguration circuits of different circuit sizes in accordance with customer needs. In the fields of image processing and communication, various semiconductor chips including reconstruction circuits have been developed.

So far, SRAM switches including pass transistors and static random access memories (SRAMs) have been developed as reconfiguration circuits or CLBs. However, in a general SRAM, since the transistor and the memory are formed in the same layer, there is a problem that the chip area becomes large.

Patent Document 1 discloses a programmable logic integrated circuit having a crossbar switch including a variable resistance element and a logic circuit logically configured by the crossbar switch. According to the circuit of Patent Document 1, since the transistor and the memory can be formed in different layers by using the resistance change element, the chip area can be reduced.

In addition, there is a technique for improving the reliability of the device by configuring a plurality of arithmetic units in the device and obtaining redundancy instead of the resistance change element itself.

Patent Document 2 discloses an arithmetic processing unit having two identical arithmetic units in an arithmetic processing unit and capable of performing arithmetic processing on different operand input data at the same time.

In Patent Document 3, image values from an image signal source are sequentially stored in a frame memory, and image values stored in a frame memory are sequentially read at a speed faster than the writing speed to the frame memory and displayed on a display device. An image processing apparatus is disclosed.

International Publication No. 2017/038095 Japanese Patent Application Laid-Open No. 09-305423 Unexamined-Japanese-Patent No. 01-017096

As in Patent Document 1, in a reconfiguration circuit using a resistance change element, transition from a set state (low resistance state) to an off state (high resistance state) with the passage of time as shown in FIG. Poor retention may occur. For example, it is assumed that a chip in which an application pattern is mounted on a reconfiguration circuit by rewriting a switch state is incorporated into a product and shipped. In such a case, if a holding failure occurs in the switch elements constituting the crossbar switch used as the LUT memory in the chip, the data as the LUT memory disappears and the logical operation can not be performed. As a result, there is a possibility that the chip does not operate as an application.

The devices of Patent Document 2 and Patent Document 3 can detect a defect caused by the aged deterioration of the element. However, in the devices of Patent Document 2 and Patent Document 3, since the circuit block in which the fault occurs does not operate normally, the application is interrupted due to the switching process to the alternative process in another circuit block, and the chip before and after the fault occurs. Performance degradation may occur. In order to ensure continuous operation without causing performance degradation, it is necessary to simultaneously operate at least triple redundant circuits in parallel, which increases the overhead of the circuit area.

The object of the present invention is to solve the above-mentioned problems, and while implementing an application at a high density as a reconfiguration circuit without redundant bits, provide redundancy with a small circuit overhead to enable continuous application operation. An object of the present invention is to provide a reconstruction circuit.

A reconfiguration circuit according to an aspect of the present invention includes a crossbar memory configured of a crossbar switch circuit including a plurality of switch cells including complementary elements, and at least one of a plurality of signals input from the crossbar memory. A first lookup table configured by a multiplexer that selects and outputs the second lookup table configured by the crossbar memory and the multiplexer; an output node of the first lookup table; And a switch connected to the output node of the second look-up table and electrically switching the output node of the first look-up table and the output node of the second look-up table to a conductive or non-conductive state.

According to the present invention, there is provided a reconfiguration circuit which enables continuous application operation by providing redundancy with a small amount of circuit overhead while mounting an application at high density as a reconfiguration circuit without redundant bits. Becomes possible.

FIG. 1 is a block diagram showing a configuration of a reconfiguration circuit according to a first embodiment of the present invention. It is a block diagram which shows the structure of the look-up table (LUT: Lookup Table) comprised by the reconstruction circuit which concerns on the 1st Embodiment of this invention. FIG. 6 is a conceptual diagram showing a configuration of a resistance change element included in a switch cell of a crossbar switch circuit for configuring a crossbar memory of a LUT included in the reconfiguration circuit according to the first embodiment of the present invention. It is a symbolic expression of the resistance change element contained in the switch cell of the crossbar switch circuit which comprises the crossbar memory of LUT contained in the reconfiguration | reconstruction circuit which concerns on the 1st Embodiment of this invention. It is a table regarding the change of the resistance state of the variable resistance element contained in the switch cell of the crossbar switch circuit which comprises the crossbar memory of LUT contained in the reconfiguration | reconstruction circuit which concerns on the 1st Embodiment of this invention. It is a symbolic representation of the switch cell of the crossbar switch circuit which comprises the crossbar memory of LUT contained in the reconfiguration | reconstruction circuit which concerns on the 1st Embodiment of this invention. It is a circuit diagram showing connection of switch cells of a crossbar switch circuit which constitutes a crossbar memory of a LUT included in the reconfiguration circuit according to the first embodiment of the present invention. It is a conceptual diagram which shows the structure of the switch cell of the crossbar switch circuit which comprises the crossbar memory of LUT contained in the reconfiguration | reconstruction circuit which concerns on the 1st Embodiment of this invention. FIG. 3 is a circuit diagram showing a connection state of a crossbar switch circuit and a switching control circuit included in the reconfiguration circuit according to the first embodiment of the present invention. It is a conceptual diagram which shows the structure of the interface of the crossbar switch circuit which comprises the crossbar memory of LUT comprised by the reconfiguration | reconstruction circuit which concerns on the 1st Embodiment of this invention. It is a conceptual diagram which shows the structure of the interface of the crossbar switch circuit which comprises the crossbar memory of LUT comprised by the reconfiguration | reconstruction circuit which concerns on the 1st Embodiment of this invention. It is a conceptual diagram which shows the structure of LUT comprised by the reconstruction circuit which concerns on the 1st Embodiment of this invention. It is a conceptual diagram which shows the structure of the reconfiguration | reconstruction circuit which concerns on the 1st Embodiment of this invention. It is a conceptual diagram regarding operation (normal mode) of a reconfiguration circuit concerning a 1st embodiment of the present invention. It is a conceptual diagram regarding operation (reliable mode) of a reconfiguration circuit concerning a 1st embodiment of the present invention. FIG. 7 is a circuit diagram for describing a switch cell redundant in an operation (reliable mode) of the reconfiguration circuit according to the first embodiment of the present invention. FIG. 2 is a conceptual view of a large scale logic integrated circuit in which logic cells (hereinafter, CLB: Configurable Logic Block) including LUTs included in the reconfiguration circuit according to the first embodiment of the present invention are arranged. It is a conceptual diagram which shows LUT using the crossbar switch circuit which made the switch cell redundant. FIG. 6 is a conceptual diagram showing an example of making a LUT highly reliable using a crossbar switch circuit in which switch cells are made redundant. FIG. 6 is a conceptual diagram showing a LUT in which two crossbar switch circuits are connected to make them redundant. It is a block diagram which shows the structure of the reconfiguration | reconstruction circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the look-up table (LUT: Lookup Table) comprised by the reconstruction circuit which concerns on the 2nd Embodiment of this invention. FIG. 6 is a circuit diagram showing a connection state of a crossbar switch circuit and a switching control circuit included in a reconfiguration circuit according to a second embodiment of the present invention. It is a conceptual diagram which shows the structure of LUT comprised by the reconstruction circuit which concerns on the 2nd Embodiment of this invention. It is a conceptual diagram which shows the structure of the reconfiguration | reconstruction circuit which concerns on the 2nd Embodiment of this invention. It is a conceptual diagram regarding operation (normal mode) of a reconfiguration circuit concerning a 2nd embodiment of the present invention. It is a conceptual diagram regarding operation (reliable mode) of the reconfiguration circuit according to the second embodiment of the present invention. It is a circuit diagram for demonstrating the switch cell made redundant in operation (reliable mode) of the reconfiguration circuit concerning a 2nd embodiment of the present invention. It is a circuit diagram which shows the structure of a general reconstruction circuit. It is a conceptual diagram which shows the example which a holding failure generate | occur | produces in a general crossbar switch circuit, and a part of memory data for LUT lose | disappears.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are technically preferable limitations for carrying out the present invention, but the scope of the invention is not limited to the following. In all the drawings used in the following description of the embodiment, the same reference numerals are given to the same parts unless there is a particular reason. In the following embodiments, the same configuration and operation may not be repeatedly described. Further, the direction of the arrow in the drawing indicates an example of the direction of the signal, and does not limit the direction of the signal.

First Embodiment
First, a reconfiguration circuit according to a first embodiment of the present invention will be described with reference to the drawings. In the reconstruction circuit of this embodiment, at least two look-up tables (hereinafter referred to as LUTs) are configured.

(Constitution)
FIG. 1 is a block diagram showing a configuration of a reconfiguration circuit 1 configured in the reconfiguration circuit of the present embodiment. As shown in FIG. 1, the reconstruction circuit 1 includes a first LUT 10-1, a second LUT 10-2, and a switch 17. The output node (first output node 15-1) of the first LUT 10-1 and the output node (second output node 15-2) of the second LUT 10-2 are mutually connected via the switch 17 Be done.

In the following, when the first LUT 10-1 and the second LUT 10-2 are not distinguished from one another, they are referred to as the LUT 10. In the reconfiguration circuit of this embodiment, the LUT 10 is configured using a crossbar switch circuit. The switch cells connecting the cross points of the crossbar switch circuit included in the reconfiguration circuit of the present embodiment include a resistance change element.

The first LUT 10-1 outputs a signal via the first output node 15-1. The first LUT 10-1 is connected to the switch 17 via the first output node 15-1. The second LUT 10-2 outputs a signal via the second output node 15-2. The second LUT 10-2 is connected to the switch 17 via the second output node 15-2.

The switch 17 is connected to the first LUT 10-1 via the first output node 15-1, and connected to the second LUT 10-2 via the second output node 15-2. The switch 17 has a configuration of a complementary element in which two semiconductor elements having different polarities are combined. For example, the switch 17 is realized by a selection transistor in which an NMOS (N-type Metal-Oxide-Semiconductor) and a PMOS (P-type Metal-Oxide-Semiconductor) are combined.

In other words, the switch 17 is connected to the first output node 15-1 of the first LUT 10-1 and the second output node 15-2 of the second LUT 10-2. The switch 17 switches the first output node 15-1 of the first LUT 10-1 and the second output node 15-2 of the second LUT 10-2 to the electrically conductive or non-conductive state.

FIG. 2 is a block diagram showing the configuration of the LUT 10. As shown in FIG. 2, the LUT 10 includes a crossbar memory 11 and a multiplexer 13. Although only one crossbar memory 11 and one multiplexer 13 are illustrated in FIG. 2, the LUT 10 can be configured by combining an arbitrary number of crossbar memories 11 and multiplexers 13.

The crossbar memory 11 is a storage circuit configured using a crossbar switch circuit. In other words, the crossbar memory 11 is configured as a crossbar switch circuit having a plurality of switch cells including complementary elements. For example, the crossbar memory 11 is configured by a crossbar switch circuit 12 of 2 inputs and K outputs (K is a natural number).

The multiplexer 13 is a selection circuit that receives a plurality of signals output from the crossbar memory 11 and selects and outputs one of the input signals. In other words, the multiplexer 13 outputs one of the plurality of signals input from the crossbar switch circuit to the output node 15 in response to the selection control signal (not shown). For example, the multiplexer 13 can be configured by combining a plurality of complementary elements in multiple stages. In the present embodiment, a complementary element including a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) is exemplified.

That is, the reconfiguration circuit 1 of the present embodiment is connected to the crossbar switch circuit 12 in which the crossbar memory 11 is configured, the multiplexer 13 connected to the crossbar switch circuit, and the output node 15 of at least two LUTs 10. And the switch 17. The LUT 10 is configured of a crossbar memory 11 configured using a crossbar switch circuit and a multiplexer 13.

When the switch 17 is in the ON state, one node is included in the crossbar memory 11 in which the first LUT 10-1 is configured, and one in the crossbar memory 11 in which the second LUT 10-2 is configured. Electrically connect with the node. When the switch 17 is in the off state, the switch 17 disconnects the electrical connection between the first LUT 10-1 and the second LUT 10-2.

[Resistive change element]
Here, the variable resistance element included in the crossbar switch circuit included in the reconfiguration circuit of the present embodiment will be described. FIG. 3 is a conceptual view showing a configuration of the variable resistance element 50 included in a switch cell configuring the crossbar switch circuit included in the reconfiguration circuit of the present embodiment. FIG. 4 is a symbolic representation of the resistance change element 50.

As shown in FIG. 3, the variable resistance element 50 includes a first wiring layer 51 (also described as T1), a solid electrolyte layer 52 (also described as IC), and a second wiring layer 53 (also described as T2). And. The solid electrolyte layer 52 contains metal ions and is disposed between the first wiring layer 51 and the second wiring layer 53. The resistance change element 50 can change the resistance value by applying a forward bias or a reverse bias to both terminals of the first wiring layer 51 and the second wiring layer 53.

As the variable resistance element 50, one that can change its resistance by applying a predetermined voltage or more for a predetermined time and can hold the changed resistance is used. For example, as the resistance change element 50, ReRAM (Resistance Random Access Memory) using a transition metal oxide, NanoBridge (registered trademark) using an ion conductor, or the like can be used.

The variable resistance element 50 may include two bipolar variable resistance elements having a polarity in the application direction of the voltage for changing the resistance. In this case, it is preferable that the variable resistance element 50 has a configuration in which two bipolar variable resistance elements are opposed and connected in series, and a switch (transistor) is disposed at a connection point of two switches. This is because the variable resistance element 50 having such a configuration has high disturbance resistance when using a signal continuously passing through. Further, the resistance change element 50 may be a resistance change element utilizing movement of metal ions and an electrochemical reaction in a solid (ion conductor) in which ions can freely move by application of an electric field or the like.

The above-described variable resistance element 50 can be used as a switch element that can distinguish whether or not a signal passes between electrodes because the amount of change in resistance is large. The solid electrolyte layer 52 used for the resistance change element 50 receives metal ions from the first wiring layer 51 but does not receive metal ions from the second wiring layer 53. As a result, when the polarity of the voltage applied to both terminals of the variable resistance element 50 changes, the resistance value of the solid electrolyte layer 52 largely changes, and the voltage between the first wiring layer 51 and the second wiring layer 53 is changed. The conduction state can be controlled.

FIG. 5 is a table 500 showing the correspondence between the voltage applied to both terminals of the variable resistance element 50 and the resistance state. When a voltage higher than that of the second wiring layer 53 is applied to the first wiring layer 51 (forward bias), the variable resistance element 50 is in a low resistance state (on). When a voltage higher than that of the first wiring layer 51 is applied to the second wiring layer 53 (reverse bias), the variable resistance element 50 is in a high resistance state (off). For example, the ratio of the resistance value in the low resistance state (on) to the high resistance state (off) is set to be larger than 10 5.

[Switch cell]
FIG. 6 is a symbolic representation of the switch cell 120 disposed at the cross point of the crossbar switch circuit for realizing the reconfiguration circuit of this embodiment. Switch cell 120 includes a first resistance change element 125-1, a second resistance change element 125-2, and a selection transistor 126.

The first resistance change element 125-1 includes the solid electrolyte layer 152-1, and the second resistance change element 125-2 includes the solid electrolyte layer 152-2. Each of the first resistance change element 125-1 and the second resistance change element 125-2 has the structure of the resistance change element 50 of FIG.

That is, the switch cell 120 uses one transistor (selection transistor 126) and two pairs of resistance change elements (first resistance change element 125-1 and second resistance change element 125-2). It is a switch cell of a complementary type (1T2R) structure.

One electrodes of the first resistance change element 125-1 and the second resistance change element 125-2 are connected to each other to form a shared node (hereinafter, common node 127). The common node 127 is connected to one diffusion layer (source or drain) of the selection transistor 126.

The other electrode TR1 of the first resistance change element 125-1 is connected to the first signal line. The resistance value of the first resistance change element 125-1 changes in accordance with the voltage applied to the electrode TR1 and the common node 127. On the other hand, the other electrode TR2 of the second resistance change element 125-2 is connected to the second signal line. The resistance value of second resistance change element 125-2 changes according to the voltage applied to electrode TR 2 and common node 127.

The selection transistor 126 can be configured by a general transistor. One of the diffusion layers (source or drain) of the select transistor 126 is connected to the common node 127. The other (drain or source) electrode TS of the diffusion layer of the selection transistor 126 is connected to a write control line SV described later. The gate electrode TG of the selection transistor 126 is connected to a write control line GH described later.

In summary, the switch cell 120 includes the first resistance change element 125-1 and the second resistance change element 125-2, which can switch the resistance state according to the applied voltage, and at least one selection transistor 126. One terminal of the first resistance change element 125-1 and one terminal of the second resistance change element 125-2 are connected to one of the diffusion layers of the selection transistor 126. For example, the first resistance change element 125-1 and the second resistance change element 125-2 are bipolar type resistance change elements, and are arranged such that the resistance change polarity faces each other. For example, the first resistance change element 125-1 and the second resistance change element 125-2 include an ion conductive solid electrolyte layer.

FIG. 7 is a circuit diagram showing a connection relationship between the switch cell 120 and each wire. The switch cell 120 is used as a switch of the crossbar switch circuit 12. In FIG. 7, the switch cell 120 is a signal line RH [k] which is a wiring along the x direction (also referred to as a first direction) and a signal which is a wiring along ay direction (also referred to as a second direction). It is arranged near the cross point of line RV [j] (j, k: natural number).

The electrode TR1 is connected to the signal line RH [k]. The electrode TR2 of the second resistance change element 125-2 is connected to the signal line RV [j]. That is, the signal line RV [j] and the signal line RH [k] are connected to the electrode not shared by the first resistance change element 125-1 and the second resistance change element 125-2, respectively. Connected

The write control line GH [k] is connected to the gate electrode TG of the selection transistor 126. The write control line SV [j] is connected to the electrode TS of the diffusion layer (drain or source) on the side to which the first resistance change element 125-1 and the second resistance change element 125-2 are not connected. Ru. Although described later, the write control line GH [k] and the write control line SV [j] are wired independently of the signal line RH [k] and the signal line RV [j], and other switches positioned in the wiring direction Shared with.

FIG. 8 is a three-dimensional schematic view of the switch cell 120 shown in FIG. 6 and FIG.

The common node 127 is connected to the solid electrolyte layer 152-1 via the via 128-1, and connected to the solid electrolyte layer 152-2 via the via 128-2. In addition, the common node 127 is connected to one (source or drain) of the diffusion layer of the selection transistor 126 through the via 128-3 and the electrode 129.

The signal line RH [k] is located in the + z direction of the electrode TR1. The signal line RH [k] and the electrode TR1 are electrically connected via the via 128-4. The signal line RV [j] is electrically connected to the electrode TR2 in the same xy plane. The electrode TR1 and the electrode TR2 are located in the same xy plane.

[Crossbar switch circuit]
Next, the crossbar switch circuit 12 for realizing the crossbar memory 11 of the present embodiment will be described with reference to FIG. FIG. 9 is a circuit diagram of the crossbar switch circuit 12.

The crossbar switch circuit 12 shown in FIG. 9 is a crossbar switch circuit for signal switching of J input and K output (J, K: natural number). FIG. 9 is a diagram including a control transistor for controlling a voltage / current source supplied from a writing power source (PS: Power Source) and a control wiring when the resistance change element is rewritten (at the time of writing). It shows. The circuit configuration shown in FIG. 9 conceptually illustrates a part of the configuration of the crossbar switch circuit 12 and does not represent all. Further, the crossbar switch circuit 12 for realizing the reconstruction circuit 1 of the present embodiment is not limited to the number of elements and signal lines shown in FIG.

The crossbar switch circuit 12 includes switch cells 120-1 to 9. Each of switch cells 120-1 to 9 includes a switch element. In the present embodiment, an example in which a pair of resistance change elements are used as switch elements will be described. Further, hereinafter, when the switch cells 120-1 to 9 are not distinguished from one another, the hyphen and the number at the end are omitted and the switch cell 120 is described.

Switch cells 120-1 to 3 have write control line GH [k-1] (also referred to as first write control line) and signal line RH [k-1], which are wirings in the x direction (also referred to as first direction). ] (Also referred to as first wiring). The write control line GH [k−1] and the signal line RH [k−1] are wires independent of each other. The signal line RH [k−1] is connected to one diffusion layer of the first control transistor 121 a connected to the switch cells 120-1 to 3. A power supply line PS [0] (also referred to as a first power supply line) is connected to the other diffusion layer of the first control transistor 121a. A write control line GSH [k−1] (also referred to as a second write control line) is connected to the gate electrode of the first control transistor 121a. The write control line GSH [k−1] is a wiring used to change the resistance of the switch elements included in the switch cells 120-1 to 3.

The switch cells 120-4 to 6 share the write control line GH [k] and the signal line RH [k], which are wirings in the x direction. The write control line GH [k] and the signal line RH [k] are wires independent of each other. The signal line RH [k] is connected to one diffusion layer of the first control transistor 121 b connected to the switch cells 120-4 to 6. The power supply line PS [0] is connected to the other diffusion layer of the first control transistor 121b. The write control line GSH [k] is connected to the gate electrode of the first control transistor 121b. The write control line GSH [k] is a wiring used to change the resistance of the switch elements included in the switch cells 120-4 to 6.

The switch cells 120-7 to 9 share the write control line GH [k + 1] and the signal line RH [k + 1], which are wirings in the x direction. The write control line GH [k + 1] and the signal line RH [k + 1] are wires independent of each other. The signal line RH [k + 1] is connected to one of the diffusion layers of the first control transistor 121c connected to the switch cells 120-7 to 9. The power supply line PS [0] is connected to the other diffusion layer of the first control transistor 121c. The write control line GSH [k + 1] is connected to the gate electrode of the first control transistor 121c. The write control line GSH [k + 1] is a wiring used to change the resistance of the switch elements included in the switch cells 120-7 to 9.

The switch cells 120-1, 4 and 7 have the write control line SV [j-1] (also referred to as a second write control line) and the signal line RV [j], which are wirings in the y direction (also referred to as a second direction). -1] (also referred to as second wiring). The write control line SV [j-1] and the signal line RV [j-1] are wires independent of each other. The write control line SV [j−1] is connected to one diffusion layer of the second control transistor 122 a connected to the switch cells 120-1, 4, 7. A power supply line PS [1] (also referred to as a second power supply line) is connected to the other diffusion layer of the second control transistor 122a. The driver control line PGV [j-1] is connected to the gate electrode of the second control transistor 122a. Further, the signal line RV [j−1] is connected to one diffusion layer of the third control transistor 123 a connected to the switch cells 120-1, 4, 7. A power supply line PS [2] (also referred to as a third power supply line) is connected to the other diffusion layer of the third control transistor 123a. The driver control line PGV [j-1] is connected to the gate electrode of the third control transistor 123a.

The switch cells 120-2, 5, 8 share the write control line SV [j] and the signal line RV [j], which are wirings in the y direction. The write control line SV [j] and the signal line RV [j] are wires independent of each other. The write control line SV [j] is connected to one diffusion layer of the second control transistor 122 b connected to the switch cells 120-2, 5 and 8. The power supply line PS [1] is connected to the other diffusion layer of the second control transistor 122b. The driver control line PGV [j] is connected to the gate electrode of the second control transistor 122b. Further, the signal line RV [j] is connected to one diffusion layer of the third control transistor 123 b connected to the switch cells 120-2, 5, 8. The power supply line PS [2] is connected to the other diffusion layer of the third control transistor 123b. The driver control line PGV [j] is connected to the gate electrode of the third control transistor 123b.

The switch cells 120-3, 6, 9 share the write control line SV [j + 1] and the signal line RV [j + 1], which are wirings in the y direction. The write control line SV [j + 1] and the signal line RV [j + 1] are wires independent of each other. The write control line SV [j + 1] is connected to one diffusion layer of the second control transistor 122 c connected to the switch cells 120-3, 6, 9. The power supply line PS [1] is connected to the other diffusion layer of the second control transistor 122c. The driver control line PGV [j + 1] is connected to the gate electrode of the second control transistor 122c. Further, the signal line RV [j + 1] is connected to one diffusion layer of the third control transistor 123c connected to the switch cells 120-3, 6, 9. The power supply line PS [2] is connected to the other diffusion layer of the third control transistor 123c. The driver control line PGV [j + 1] is connected to the gate electrode of the third control transistor 123c.

FIG. 10 is a conceptual diagram showing an I / O interface, with the J input / K output crossbar switch circuit 12 as one block. As shown in FIG. 10, the signal line RV and the driver control line PGV are arranged on one side corresponding to the x direction. In addition, the write control line GH, the write control line GSH, and the power supply line PS are disposed on one side corresponding to the y direction, and the signal line RH is disposed on the other side. In addition, the conceptual diagram of the cross bar shown in FIG. 10 is an illustration, and does not limit the scope of the present invention.

FIG. 11 is a conceptual diagram showing an input / output interface of a crossbar switch circuit (crossbar memory 11) modified for memory. As shown in FIG. 11, on one side corresponding to the x direction, a signal line RV to which each of the power supply level (VDD) or the ground level (GND) is input and a driver control line PGV are arranged. In addition, the write control line GH, the write control line GSH, and the power supply line PS are disposed on one side corresponding to the y direction, and the signal line RH is disposed on the other side.

The crossbar memory 11 can function as a memory by inputting a power supply level (hereinafter, VDD) and a ground level (hereinafter, GND) to the two RV ports in the crossbar switch configuration. By turning on the switch cell of VDD or GND, the output level of the output node of the crossbar memory 11 can be controlled to VDD or GND.

FIG. 12 is a conceptual diagram showing the configuration of the LUT 10. As shown in FIG. The LUT 10 is implemented by connecting the output from the crossbar memory 11 to the input port of the multiplexer 13. In the example of FIG. 12, the output node (K = 2 ^ N) from the crossbar memory 11 is connected to the N ^ 2 input nodes of the N-input multiplexer 13 to function as one LUT (N, K :Natural number).

The multiplexer 13 has a configuration in which a plurality of complementary elements (switches 130) are combined. FIG. 12 shows an example in which the switches 130-1 to 6 in which a pair of CMOS and NMOS are connected in parallel are combined. Although FIG. 12 shows an example in which six switches 130-1 to 6 are combined and subjected to two inputs, the number of switches 130 and the number of inputs are set according to the scale of the logic circuit to be configured. In FIG. 12 and the subsequent drawings, the gate lines connected to the gate electrodes of the CMOS and NMOS of the switches 130-1 to 6 are omitted.

[Reconstruction circuit]
FIG. 13 is a conceptual diagram showing the configuration of the reconfiguration circuit 1 of the present embodiment. In the present embodiment, an example is shown in which the output node 15 of the LUT 10 of FIG. 11 is connected via a complementary element (switch 17). In FIG. 13 and the subsequent drawings, the gate lines connected to the CMOS and NMOS gate electrodes of the switch 17 are omitted.

The reconfiguration circuit 1 can switch the mode by turning on and off the switch 17. When the switch 17 is off (normal mode), the first output node 15-1 and the second output node 15-2 are not short-circuited. On the other hand, when the switch 17 is on (high reliability mode), the first output node 15-1 and the second output node 15-2 are shorted.

As shown in FIG. 14, when the switch 17 is off (normal mode), the first LUT 10-1 and the second LUT 10-2 execute different logical operations independently of each other. Therefore, the operation result of the first LUT 10-1 is output from the first output node 15-1, and the operation result of the second LUT 10-2 is output from the second output node 15-2.

When the normal mode is used, different logical operations are performed on the first LUT 10-1 and the second LUT 10-2. In this case, desired memory states and input signals are selected for each LUT 10 to operate a desired application. As a result, in the normal mode, the usage efficiency of the LUT is high, and logic can be implemented with high density, so high performance in terms of power and delay can be obtained.

On the other hand, as shown in FIG. 15, when the switch 17 is in the on state (reliable mode), the switch 17 is shorted. The reconfiguration circuit 1 executes the same logical operation as the first LUT 10-1 and the second LUT 10-2. Therefore, the same calculation result calculated by the redundant first LUT 10-1 and the second LUT 10-2 is output from the first output node 15-1 and the second output node 15-2. In other words, in the high reliability mode, a high reliability LUT 110 is formed in which two LUTs performing the same logical operation are redundant.

When the same logical operation is performed on the first LUT 10-1 and the second LUT 10-2 using the high reliability mode, the switch 17 is turned on to connect the two LUTs to each other. At this time, the memory state of the two LUTs 10 and the input signal are made identical and operated as one LUT to operate a desired application. As a result, in the high reliability mode, high reliability can be obtained for the holding failure of the variable resistance element 50.

The on / off of the switch 17 can be controlled by, for example, an IO (Input Output) pin of the chip. Further, the on / off of the switch 17 may be controlled by preparing a memory that holds the on / off state for each switch 17, for example.

As shown in FIG. 16, each node in two different LUTs 10 (FIG. 15) is electrically connected to the corresponding switch cell 120 in crossbar memory 11 via switch 130 constituting multiplexer 13. Be done. One node inside the LUT 10 (FIG. 15) is pulled up to VDD or pulled down to GND through the two switch cells 120 in the on state. For this reason, even if one switch cell corresponding to the same node causes a holding failure and the state transitions, the potential of the node can be kept the same. For example, in the case where the retention failure rate of the variable resistance element when stored for 10 years at a temperature of 150 degrees is 1/6 of 10, the probability that the circuit malfunctions is equal to 10 6 6 before redundancy. In contrast to being 1, it can be improved to one tenth of a factor of 10 by redundancy.

Further, as shown in FIG. 17, a plurality of reconfiguration circuits 1 (hereinafter, CLBs: Configurable Logic Blocks) can be arranged side by side and connected to each other, whereby a larger scale reconfiguration circuit 1000 (also referred to as an integrated circuit) can be configured. . For example, one memory can be configured by sharing on / off states of a plurality of switches 17 included in a plurality of CLBs. The memory configured in this way is redundantly redundant and has high reliability. However, when the reconfiguration circuit 1 is multiplexed as shown in FIG. 17, the write control line of the crossbar memory 11 included in each reconfiguration circuit 1 is shared. If the on / off states are shared by a plurality of switches 17 included in a plurality of CLBs, control can be performed using one memory. When the on / off state is shared by a plurality of switches included in a plurality of CLBs, it is desirable to use a redundant memory.

As described above, in this embodiment, the output nodes of the two LUTs are connected by the switch including the complementary element. In order to efficiently implement an application that prioritizes the logic mounting density, the power characteristic, and the delay characteristic, the switch is turned off and each LUT is used as a different logical operation circuit. On the other hand, when implementing an application that prioritizes reliability, the switch is turned on, and the state of the LUT memory and the input signal to the multiplexer in the LUT are the same between the two LUTs connected by the switch. Do. As a result, even if a holding failure occurs in a switch cell included in one of the LUTs and a transition is made to a high resistance state, the switch cell used in the other LUT is pulled down or pulled up. You can

Also, since two 4-input LUTs require 2 × (16 × 2 + 16 + 4) transistors in the crossbar switch circuit and 2 × (32 + 16 + 8 + 4) transistors in the multiplexer, a total of 224 transistors are used. . The footprint overhead of the footprint resulting from the addition of one switch using PMOS and NMOS each is 1% or less in terms of the number of transistors used for the LUT. Therefore, even if one switch including a complementary element is added, the degradation of performance (power and delay) when the application is installed and operated is 1% or less compared to the case without the switch.
Further, in applications where high reliability is required, it can be coped with by changing the switch pattern (configuration pattern) on the same chip. Furthermore, the circuit area required for the application operation, that is, the product of the number of CLBs necessary for the application operation and the area of the CLB can be doubled.

As described above, the reconfiguration circuit of this embodiment can implement two applications while being a single circuit. One is an application that implements an application at high density as a reconfigurable circuit without redundant bits. The other is an application requiring high reliability that enables continuous application operation even when the resistance change element causes a holding failure. In particular, in applications where high reliability is required, the circuit area required for application operation can be suppressed as compared with high density mounting. That is, according to the present embodiment, it is possible to implement a continuous application operation by providing redundancy with a small amount of circuit overhead while mounting an application at high density as a reconfiguration circuit having no redundant bits. It becomes possible to offer.

(Related technology)
Here, the reconfiguration circuit of the present embodiment will be described in comparison with a reconfiguration circuit using the related art.

For example, three same application patterns are prepared on the reconstruction circuit, the same signal is input to each pattern, and majority decision circuit is inserted to the output node, thereby improving the retention reliability as a chip can do. According to this method using the majority circuit, it is possible to improve the reliability only by changing the switch pattern (configuration pattern) for mounting the application pattern on the reconfiguration circuit, and therefore, it is not necessary to change the circuit of the reconfiguration circuit itself. However, the use of a majority circuit requires three times or more of the circuit area required for the application operation.

Even in reconfiguration circuits using resistance change elements, applications that require high density mounting of applications without redundant bits, and high reliability that applications can operate continuously even if resistance change elements cause retention failure are required. Can be implemented with the same circuit. However, in applications where high reliability is required, it is difficult to reduce the circuit area required for application operation to less than twice that in non-high reliability (dense mounting).

Further, as shown in FIGS. 18 to 20, there is a method of connecting redundantly the number of switches of the crossbar switch circuit constituting the LUT memory to a signal switching point to make it redundant. FIG. 18 and FIG. 19 are examples of multiplexing RV (VDD and GND) and PGV. FIG. 20 shows an example of multiplexing the crossbar memory.

In the case of FIGS. 18 to 20, only the number of switches required for the LUT is doubled, and the number of CLBs required for the application operation is the same, so the circuit area required for the application operation is at most twice as large. It's over. However, in the method shown in FIG. 18 to FIG. 20, the physical layout of the CLB and the reconfiguration circuit itself becomes large, and the possible logic mounting area per unit area decreases. Therefore, in the method shown in FIG. 18 to FIG. 20, for an application where priority is given to logic mounting density, power characteristics, and delay characteristics over retention reliability, a normal reconfiguration circuit without redundant bits is used as shown in FIG. It is necessary to prepare separately. That is, in the method shown in FIGS. 18 to 20, the manufacturing / design cost, the product management cost and the like increase due to the increase in the number of chips.

That is, according to the present embodiment, as compared with the related art described above, while the application is mounted at a high density as a reconfigurable circuit having no redundant bits, continuous holding is possible even when a holding failure occurs in the variable resistance element. It is possible to provide a reconfigurable circuit capable of application operation at low cost.

Second Embodiment
Next, a reconfiguration circuit according to a second embodiment of the present invention will be described with reference to the drawings. The present embodiment and the first embodiment are the same in that the switch cells disposed at the cross points of the crossbar switch circuit include resistance change elements, but the structure of the circuit is different.

(Constitution)
FIG. 21 is a conceptual diagram showing the configuration of the reconfiguration circuit 2 included in the reconfiguration circuit of the present embodiment. As shown in FIG. 21, the reconstruction circuit 2 includes a first LUT 20-1, a second LUT 20-2, and a switch 27. The output node (first output node 25-1) of the first LUT 20-1 and the output node (second output node 25-2) of the second LUT 20-2 are mutually connected via the switch 27. Be done. In the following, when the first LUT 20-1 and the second LUT 20-2 are not distinguished from one another, they are referred to as the LUT 20.

The first LUT 20-1 outputs a signal via the first output node 25-1. The first LUT 20-1 is connected to the switch 27 via the first output node 25-1. The second LUT 20-2 outputs a signal via the second output node 25-2. The second LUT 20-2 is connected to the switch 27 via the second output node 25-2.

The switch 27 is connected to the first LUT 20-1 through the first output node 25-1, and is output to the second LUT 20-2 through the second output node 25-2. The switch 27 is similar to the switch 17 of the first embodiment.

FIG. 22 is a block diagram showing the configuration of the LUT 20. As shown in FIG. As shown in FIG. 22, the LUT 20 includes a first crossbar memory 21A, a second crossbar memory 21B, a first multiplexer 23, and a second multiplexer 24.

The first crossbar memory 21A and the second crossbar memory 21B are storage circuits configured by crossbar switch circuits. The first crossbar memory 21A and the second crossbar memory 21B have nodes at the same signal level or high impedance state as the input signal. For example, the first crossbar memory 21A and the second crossbar memory 21B are realized by a two-input K-output crossbar switch circuit (K is a natural number).

The first multiplexer 23 is a selection circuit which receives a plurality of signals output from the first crossbar memory 21A, selects one of the input signals, and outputs the selected one. For example, the first multiplexer 23 has a configuration in which a plurality of PMOSs are combined in multiple stages, and selects at least one of the plurality of signals input from the first crossbar memory 21A.

The second multiplexer 24 is a selection circuit which receives a plurality of signals output from the second crossbar memory 21B as input, and selects and outputs any one of the input signals. For example, the second multiplexer 24 has a configuration in which a plurality of NMOSs are combined in multiple stages, and selects at least one of the plurality of signals input from the second crossbar memory 21B.

The first multiplexer 23 and the second multiplexer 24 output any one of the plurality of signals input from the crossbar switch circuit to the common output node 25 in response to a selection control signal (not shown).

[Crossbar switch circuit]
FIG. 23 is a circuit diagram showing a circuit configuration of the crossbar switch circuit 22 included in the reconfiguration circuit of the present embodiment. FIG. 23 also includes a control transistor for controlling a voltage / current source supplied from a writing power source (PS: Power Source) and a control wiring when rewriting the resistance change element (during writing). It shows. The circuit configuration shown in FIG. 23 is a conceptual diagram illustrating a part of the configuration of the crossbar switch circuit 22 and does not represent all. Further, the crossbar switch circuit 22 for realizing the reconstruction circuit 2 of the present embodiment is not limited to the number of elements and signal lines shown in FIG.

Crossbar switch circuit 22 includes switch cells 220-1-6. Each of switch cells 220-1 to 6 includes a switch element. In the present embodiment, an example in which a pair of resistance change elements are used as switch elements will be described. Further, hereinafter, when the switch cells 220-1 to 6 are not distinguished from one another, the hyphens and numbers at the end are omitted and described as the switch cell 220.

The output ports of the crossbar switch circuit 22 are provided on the left and right (x direction) of the crossbar switch circuit 22. In addition, the power supply line PS [0] (also referred to as a first power supply line) for writing installed along the y direction shares the switch cells 220-1 to 6 positioned on the left and right of the power supply line PS [0]. Power source.

Switch cells 220-1 to 3 and first control transistors 221-1 to 22-3 are arranged along the y direction between the left output port and the power supply line PS [0].

Switch cells 220-1 to 220-3 are write control lines GH [k-1] to GH [k + 1] (also referred to as first write control lines), which are wirings in the x direction (also referred to as the first direction), and signal lines It is connected to RH1 [k-1] to RH1 [k + 1] (also referred to as first wiring). The write control lines GH [k−1] to GH [k + 1] and the signal lines RH1 [k−1] to RH1 [k + 1] are wires independent of each other. The signal lines RH1 [k−1] to RH1 [k + 1] are connected to one of the diffusion layers of the first control transistors 221a to 221c connected to the switch cells 220-1 to 220-3. A power supply line PS [0] (also referred to as a first power supply line) is connected to the other diffusion layer of the first control transistors 221a to 221c.

Switch cells 220-1 to 220-3 have a write control line SV [1] (also referred to as a second write control line) and a signal line RV [1] (a second line), which are wirings in the y direction (also referred to as a second direction). Share the wiring). The write control line SV [1] and the signal line RV [1] are wires independent of each other. The write control line SV [1] is connected to one diffusion layer of the second control transistor 222 a connected to the switch cells 220-1 to 3. A power supply line PS [1] (also referred to as a second power supply line) is connected to the other diffusion layer of the second control transistor 222a. The driver control line PGV [1] is connected to the gate electrode of the second control transistor 222a. The driver control line PGV [1] is shared by the first control transistors 221a, 221b, and 221c. The driver control line PGV [1] is a second control transistor provided to control the power supply line for writing from the power supply line PS [1] and the power supply line PS [2] (also referred to as a third power supply line). It is shared as a gate line of 222a and the third control transistor 223a. Further, the signal line RV [1] is connected to one diffusion layer of the third control transistor 223a connected to the switch cells 220-1 to 2. The power supply line PS [2] is connected to the other diffusion layer of the third control transistor 223a.

Switch cells 220-4 to 6 and first control transistors 221d, 221e, and 221f are disposed along the y direction between the output port on the right side and PS [0].

The switch cells 220-4 to 6 are connected to write control lines GH [k-1] to GH [k + 1] and signal lines RH2 [k-1] to RH2 [k + 1], which are wirings in the x direction. The write control lines GH [k−1] to GH [k + 1] are shared by the switch cells 220-1 to 3 and the switch cells 220-4 to 6, respectively. The write control lines GH [k−1] to GH [k + 1] and the signal lines RH2 [k−1] to RH2 [k + 1] are wires independent of each other. The signal lines RH2 [k-1] to RH2 [k + 1] are connected to one of the diffusion layers of the first control transistors 221d to 221f connected to the switch cells 220-4 to 6, respectively. The power supply line PS [0] is connected to the other diffusion layer of the first control transistors 221d to 221f.

The switch cells 220-4 to 6 share the write control line SV [2] and the signal line RV [2], which are wirings in the y direction. The write control line SV [2] and the signal line RV [2] are wires independent of each other. The write control line SV [2] is connected to one diffusion layer of the second control transistor 222 b connected to the switch cells 220-4 to 6. The power supply line PS [1] is connected to the other diffusion layer of the second control transistor 222b. The driver control line PGV [2] is connected to the gate electrode of the second control transistor 222b. The driver control line PGV [2] is shared by the first control transistors 221d, 221e, and 221f. The driver control line PGV [2] is a second control transistor 222b and a third control transistor 223b provided to control the power supply line for writing from the power supply line PS [1] and the power supply line PS [2]. Shared as the gate line of Further, the signal line RV [2] is connected to one diffusion layer of the third control transistor 223b connected to the switch cells 220-4 to 6. The power supply line PS [2] is connected to the other diffusion layer of the third control transistor 223b.

FIG. 24 is a conceptual diagram showing an input / output interface of a crossbar switch circuit (crossbar memory 21) modified for memory. As shown in FIG. 24, the signal line RV and the driver control line PGV are arranged on one side corresponding to the x direction. The signal line RH1, the write control line GH, and the power supply line PS are disposed on one side corresponding to the y direction, and the signal line RH2 is disposed on the other side.

The crossbar memory 21 can function as a memory by inputting a power supply level (hereinafter, VDD) or a ground level (hereinafter, GND) to one RV port of the crossbar switch configuration. When the input to the crossbar memory 21 is VDD, the output of the crossbar memory 21 can be controlled by rewriting either the VDD or the high resistance state (High-z) switch cell. When the input to the crossbar switch circuit 22 is GND, the output to the crossbar switch circuit 22 can be controlled by rewriting either the GND or the high resistance state (High-z) switch cell.

[Logic circuit]
FIG. 25 is a conceptual diagram showing a circuit configuration of the reconfiguration circuit 2 (FIG. 21) of the present embodiment. In the present embodiment, the first output node 25-1 of the first LUT 20-1 and the second output node 25-2 of the second LUT 20-2 are connected via the complementary element (switch 27). An example of connecting

The first LUT 20-1 includes a first crossbar memory 21A-1, a second crossbar memory 21B-1, a first multiplexer 23-1, a second multiplexer 24-1, and a first output node 25. It has -1.

The first crossbar memory 21A-1 and the second crossbar memory 21B-1 are, for example, 1-input 2K-output crossbar switch circuits. The first multiplexer 23-1 has a configuration in which a plurality of PMOSs are combined. The second multiplexer 24-1 has a configuration in which a plurality of NMOSs are combined.

As shown in FIG. 25, the first LUT 20-1 has input ports separated and disposed to the left and right across the first output node 25-1. The left input port of the first LUT 20-1 is connected to one output port of the first crossbar memory 21A-1 disposed on the left. The input port on the right side of the first LUT 20-1 is connected to one output port of the second crossbar memory 21B-1 disposed on the right side. The input signals to the first multiplexer 23-1 and the second multiplexer 24-1 included in the first LUT 20-1 are related. One conduction path is selected from each of the first multiplexer 23-1 and the second multiplexer 24-1 for the gate input signal set to the first LUT 20-1.

The second LUT 20-2 includes a first crossbar memory 21A-2, a second crossbar memory 21B-2, a first multiplexer 23-2, a second multiplexer 24-2, and a second output node 25. It has -2.

The first crossbar memory 21A-2 and the second crossbar memory 21B-2 are, for example, 1-input 2K-output crossbar switch circuits. The first multiplexer 23-2 has a configuration in which a plurality of PMOSs are combined. The second multiplexer 24-2 has a configuration in which a plurality of NMOSs are combined.

As shown in FIG. 25, the second LUT 20-2 has input ports separated and disposed to the left and right across the second output node 25-2. The left input port of the second LUT 20-2 is connected to one output port of the first crossbar memory 21A-2 disposed on the left. The input port on the right side of the second LUT 20-2 is connected to one output port of the second crossbar memory 21B-2 disposed on the right side. The input signals to the first multiplexer 23-2 and the second multiplexer 24-2 included in the second LUT 20-2 are related. One conduction path is selected from each of the first multiplexer 23-2 and the second multiplexer 24-2 for the gate input signal set to the second LUT 20-2.

Here, a method of changing the value output from the first output node 25-1 will be described. The method of changing the value output from the second output node 25-2 is the same as that of the first output node 25-1, and thus the description thereof is omitted.

First, the switch cell 220 included in the first crossbar memory 21A-1 connected to the source of the PMOS included in the first multiplexer 23-1 is turned on to start the first crossbar memory 21A-1 The case of outputting VDD will be described. In this case, the switch cell 220 in the second crossbar memory 21B-1 connected to the drain of the NMOS included in the second multiplexer 24-1 is turned off to output High-Z. As a result, the VDD level is output at a node where the internal source and drain of the first multiplexer 23-1 and the second multiplexer 24-1 are connected to each other.

Next, the switch cell 220 included in the first crossbar memory 21A-1 connected to the source of the PMOS included in the first multiplexer 23-1 is turned off, and the first crossbar memory 21A-1 is opened. The case of outputting High-Z from. In this case, the switch cell included in the second crossbar memory 21B-1 connected to the drain of the NMOS included in the second multiplexer 24-1 is turned on to output GND. As a result, the GND level can be output at the node where the sources and drains of the NMOS and PMOS inside the first multiplexer 23-1 and the second multiplexer 24-1 are connected to each other.

Desired logic operation is performed as a LUT by rewriting the switch cell 220 on the conduction path selected for the gate input signal set to the first LUT 20-1 and the second LUT 20-2 while paying attention to the complementarity Be done.

In the present embodiment, as shown in FIG. 25, the first output node 25-1 of the first LUT 20-1 and the second of the second LUT 20-2 are connected via the switch 27 which is a complementary element. And the output node 25-2 of the

When different logical operations are performed on the first LUT 20-1 and the second LUT 20-2 in the circuit configuration of the reconstruction circuit 2 (FIG. 21) shown in FIG. 25, the switch 27 is used as shown in FIG. Turn off. When the switch 27 is turned off, desired memory states and input signals can be selected for each of the first LUT 20-1 and the second LUT 20-2, and a desired application can be operated. In this case, since the use efficiency of the LUT is high and logic can be implemented at high density, performances such as power and delay become high.

On the other hand, when it is desired to give high reliability to the holding failure of the variable resistance element, as shown in FIG. 27, the switch 27 is turned on and the first LUT 20-1 and the second LUT 20-2 are mutually switched. Connect to At this time, the memory states of the first LUT 20-1 and the second LUT 20-2 and the input signals are made identical and operated as one LUT to operate a desired application.

As shown in FIG. 28, each node in the first LUT 20-1 (FIG. 25) and the second LUT 20-2 (FIG. 25) passes through the first multiplexer 23 and the second multiplexer 24, respectively. It is electrically connected to the corresponding switch cell. One node is pulled up to VDD or pulled down to GND through two switch cells in the on state. For this reason, even if one switch cell causes a holding failure and the state transitions, the potential of the node can be kept the same. For example, in the case where the retention failure rate of the variable resistance element when stored for 10 years at a temperature of 150 degrees is 1/6 of 10, the probability that the circuit malfunctions is equal to 10 6 6 before redundancy. In contrast to being 1, it can be improved to 1/12 to the tenth by redundancy.

As described above, according to the logic circuit of this embodiment, the desired logic operation can be performed by rewriting the switch cells on the path selected for each gate input signal set to the LUT while paying attention to the complementarity. An executable LUT can be realized. In the logic circuit of the present embodiment, the operating voltage is alternatively applied to one of the switch cells in the off state. Therefore, according to the present embodiment, the LUT (FIG. 12) using the crossbar switch circuit (FIG. 11) of the first embodiment in which operating voltages are applied to all the switch cells (2 ^ N) Leakage current can be reduced to 1/2 ^ N in comparison with.

Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2017-174182 filed on Sep. 11, 2017, the entire disclosure of which is incorporated herein.

1, 2 Reconstruction circuit 10-1 First LUT
10-2 Second LUT
11 crossbar memory 12 crossbar switch circuit 13 multiplexer 15-1 first output node 15-2 second output node 17 switch 20-1 first LUT
20-2 Second LUT
21A first crossbar memory 21B second crossbar memory 22 crossbar switch circuit 23 first multiplexer 24 second multiplexer 25-1 first output node 25-2 second output node 27 switch 50 resistance change Element 51 first wiring layer 52 solid electrolyte layer 53 second wiring layer 120 switch cell 121a, 121b, 121c first control transistor 122a, 122b, 122c second control transistor 123a, 123b, 123c third control transistor 125-1 First resistance change element 125-2 Second resistance change element 126 Select transistor 127 Common node

Claims (10)

1. A crossbar memory configured in a crossbar switch circuit having a plurality of switch cells including complementary elements, and at least one of a plurality of signals input from the crossbar memory is selected according to a selection control signal A first look-up table configured with an output multiplexer;
   A second lookup table configured by the crossbar memory and the multiplexer;
   An output node of the first look-up table and an output node of the second look-up table, and an output node of the first look-up table and an output node of the second look-up table; And a switch configured to switch to an electrically conductive or non-conductive state.
2. The switch is
   In the ON state, one node included in the crossbar memory in which the first look-up table is configured, and one node included in the crossbar memory in which the second look-up table is configured. Electrically connected,
   The reconfiguration circuit according to claim 1, which disconnects the electrical connection between the first look-up table and the second look-up table in the off state.
3. The crossbar switch circuit is
   A plurality of first wires arranged along the first direction;
   A plurality of first write control lines disposed along the first wiring;
   A plurality of second wires arranged along the second direction;
   A plurality of second write control lines disposed along the second wiring;
   It is disposed at the intersection of the first wiring and the second wiring, one diffusion layer is connected to the first write control line, and the other diffusion layer is connected to the second write control line A plurality of switch cells for switching electrical connection between the first wiring and the second wiring;
   A first control transistor connected to the first wiring and switching an electrical connection between a first power supply line supplying power to the first wiring and the first wiring;
   A second control transistor connected to the first write control line and switching an electrical connection between a second power supply line supplying power to the first write control line and the first write control line;
   3. The device according to claim 1, further comprising: a third control transistor connected to the second wiring and switching an electrical connection between a second power supply line supplying power to the second wiring and the second wiring. Reconstruction circuit as described in.
4. The multiplexer is
   has a configuration in which a plurality of complementary elements including a p-type metal oxide film semiconductor element and an n-type metal oxide film semiconductor element are combined in multiple stages,
   4. The reconstruction circuit according to claim 3, wherein any one of a plurality of signals input from the crossbar switch circuit is output according to the selection control signal.
5. The crossbar switch circuit is
   A plurality of first wires arranged along the first direction;
   A plurality of first write control lines disposed along the first wiring;
   A plurality of second wires arranged along the second direction;
   A plurality of second write control lines disposed along the second wiring;
   A first power supply line disposed along the second direction and connected to the first wiring;
   It is symmetrically disposed at the intersection of the first wiring and the second wiring with the first power supply line interposed between the first wiring and the second wiring. A plurality of the switch cells to switch;
   Electrical connection between a first power supply line, which is connected to the first wiring between the first power supply line and the switch cell, and supplies power to the first wiring, and the first wiring A first control transistor for switching
   Electrically connected between a second power supply line connected to a first write control line connected to one electrode of the switch cell and supplying power to the first write control line and the first write control line A second control transistor that switches the
   3. The device according to claim 1, further comprising: a third control transistor connected to the second wiring and switching an electrical connection between a second power supply line supplying power to the second wiring and the second wiring. Reconstruction circuit as described in.
6. The first and second look-up tables are:
   First and second crossbar memories having nodes at the same signal level or high impedance state as the input signal;
   A first multiplexer configured to combine a plurality of p-type semiconductor elements in multiple stages and selecting at least one of a plurality of signals input from the first crossbar memory;
   A plurality of n-type semiconductor elements combined in multiple stages, and a second multiplexer for selecting at least one of the plurality of signals input from the second crossbar memory;
   The first and second multiplexers
   The reconfiguration circuit according to claim 5, wherein any one of a plurality of signals input from the crossbar switch circuit is output to a common output node according to the selection control signal.
7. The switch cell is
   First and second resistance change elements capable of switching the resistance state in accordance with the applied voltage;
   And at least one transistor,
   7. The device according to claim 1, wherein one terminal of the first variable resistance element and one terminal of the second variable resistance element are connected to one of the diffusion layers of the transistor. Reconstruction circuit.
8. 8. The reconfiguration circuit according to claim 7, wherein the first and second resistance change elements are bipolar type resistance change elements, and are arranged such that resistance change polarities face each other.
9. The reconstruction circuit according to claim 8, wherein the first and second resistance change elements include an ion conductive solid electrolyte layer.
10. An integrated circuit comprising a plurality of the reconfiguration circuits according to any one of claims 1 to 9 and connecting the plurality of reconfiguration circuits to each other.

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