WO2018205633A1 - 循环冗余校验电路及其方法、装置以及芯片、电子设备 - Google Patents

循环冗余校验电路及其方法、装置以及芯片、电子设备 Download PDF

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WO2018205633A1
WO2018205633A1 PCT/CN2017/118622 CN2017118622W WO2018205633A1 WO 2018205633 A1 WO2018205633 A1 WO 2018205633A1 CN 2017118622 W CN2017118622 W CN 2017118622W WO 2018205633 A1 WO2018205633 A1 WO 2018205633A1
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Prior art keywords
crc
generator polynomial
output
power
iterative
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PCT/CN2017/118622
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English (en)
French (fr)
Inventor
杨卫平
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Gree Electric Appliances Inc of Zhuhai
Gree Wuhan Electric Appliances Co Ltd
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Gree Electric Appliances Inc of Zhuhai
Gree Wuhan Electric Appliances Co Ltd
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Priority to US16/612,681 priority Critical patent/US11403166B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/157—Polynomial evaluation, i.e. determination of a polynomial sum at a given value

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a cyclic redundancy check circuit, a method and device thereof, and a chip and an electronic device.
  • Cyclic Redundancy Check (CRC) is used to verify the correctness and integrity of data transmission. CRC operation has strong error detection capability and is easy to implement with encoder or detection circuit.
  • FIG. 1 is a schematic structural diagram of a conventional CRC8 serial shift circuit.
  • An object of the embodiments of the present invention is to provide a cyclic redundancy check circuit, a method, an apparatus, and a chip and an electronic device, which solve the problem that the CRC calculation efficiency is low in the prior art.
  • the embodiment of the present invention provides the following technical solutions:
  • an embodiment of the present invention discloses a cyclic redundancy check circuit, where the circuit includes: a configuration module configured to acquire configuration information and an information field; and a CRC arbitration module configured to determine and generate according to the configuration information.
  • a polynomial configured to acquire configuration information and an information field
  • a CRC arbitration module configured to determine and generate according to the configuration information.
  • a polynomial configured to acquire configuration information and an information field
  • a CRC control module configured to output a clock signal, a coefficient corresponding to each power in the generator polynomial, and an information field in response to the triggering of the CRC arbitration module
  • a parallel iteration module configured to respond to the clock signal, And performing, according to the coefficients corresponding to the powers of the generator polynomial, the iterative processing in parallel to output an iterative result
  • the CRC output module is configured to encapsulate the information field according to the iterative result.
  • the configuration information includes a j-1 bit CRC initial value
  • the parallel iteration module includes i*j iteration units
  • the i-1th row 0 column iteration unit is configured to receive a corresponding bit in the information field.
  • the information value; the 0th column j-1 column iteration unit is set to calculate the 0th row j-1 column iteration according to the CRC initial value and the coefficient corresponding to the power in the generator polynomial in response to the clock signal
  • the output value of the unit; the i-th row and the j-th column iteration unit are set to calculate the number according to the clock signal, according to the output value of the j-1th iteration unit of the i-1th line and the coefficient of the corresponding power in the generator polynomial
  • the output value of the i-th column of the i-th iteration unit, i and j are both positive integers.
  • each of the iteration units includes at least one multiplier and an XOR device; the multiplier of the j-1th column of the i-1th row is set to a coefficient corresponding to the highest power, and an CRC initial value corresponding to the highest bit.
  • the XOR of the 0th column of the i-1th row is set to XOR the multiplication result with the information value of the corresponding bit in the information field, and output The output value of the iteration unit of the 0th column and the 0th column; the XOR of the 0th row and the jth column is set to XOR the multiplication result with the CRC initial value corresponding to the j-1th bit, and output the 0th line jth
  • the output value of the column iteration unit; the XOR of the i-th row and the j-th column is set to XOR the multiplication result with the output value of the j-1th iteration unit of the i-1th line, and output the i-th row and the j-th column iteration The output value of the unit.
  • the configuration information includes a CRC type and a coefficient of a generator polynomial;
  • the CRC arbitration module is configured to determine a generator polynomial according to the configuration information, including: the CRC arbitration module is set according to the CRC type And coefficients of the generator polynomial, determining the type of the generator polynomial and the coefficient corresponding to each power in the generator polynomial.
  • the CRC type includes any one of the following: CRC4, CRC7, CRC8, CRC12, CRC16, CRC32.
  • an embodiment of the present invention provides a cyclic redundancy check method, where the method includes: acquiring configuration information and an information field; and determining, according to the configuration information, a generator polynomial corresponding to each power in the generator polynomial
  • the information field is subjected to parallel iterative processing according to the coefficients corresponding to the powers in the generator polynomial to output an iterative result; and the information field is encapsulated according to the iterative result.
  • the configuration information includes a CRC initial value
  • the information field is subjected to parallel iterative processing according to a coefficient corresponding to each power in the generator polynomial to output an iterative result, including: generating a polynomial according to the generating polynomial
  • the coefficients corresponding to each power in the middle and the initial value of the CRC are processed in parallel by the information field to output an iterative result.
  • the configuration information includes a CRC type and a coefficient of a generator polynomial; and determining, according to the configuration information, a coefficient corresponding to each power of the generator polynomial, including: according to the CRC type And coefficients of the generator polynomial, determining the type of the generator polynomial and the coefficient corresponding to each power in the generator polynomial.
  • an embodiment of the present invention provides a cyclic redundancy check apparatus, where the apparatus includes: an acquisition module configured to acquire configuration information and an information field; and a determining module configured to determine a generator polynomial according to the configuration information. a coefficient corresponding to each power in the generator polynomial; an iterative module, configured to perform parallel iterative processing on the information field according to coefficients corresponding to each power in the generator polynomial to output an iterative result; encapsulating a module, setting The information field is encapsulated according to the iterative result.
  • the configuration information includes an initial value of the CRC, where the iteration module is specifically configured to: perform parallel iterative processing on the information field according to the coefficient corresponding to each power in the generator polynomial and the CRC initial value, to output Iterative results.
  • the configuration information includes a CRC type and a coefficient of a generator polynomial; the determining module is specifically configured to: determine, according to the CRC type and each coefficient of the generator polynomial, a type of the generator polynomial and the generator polynomial The coefficient corresponding to each power.
  • an embodiment of the present invention provides a chip, which includes the cyclic redundancy check circuit of any of the above.
  • an embodiment of the present invention provides a non-transitory computer readable storage medium storing executable instructions of an electronic device, the executable instructions being set such that The electronic device performs a cyclic redundancy check method as described above.
  • an electronic device includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, The instructions are executed by the at least one processor to enable the at least one processor to perform a cyclic redundancy check method as in any of the above.
  • the configuration module acquires configuration information and an information field
  • the CRC arbitration module determines a generator polynomial according to the configuration information
  • the CRC control module responds to the trigger of the CRC arbitration module
  • the output clock signal corresponds to each power in the generator polynomial.
  • the coefficient of the parallel iterative module responds to the clock signal, and performs an iterative process on the information field according to the coefficients corresponding to the powers in the generator polynomial to output the iterative result
  • the CRC output module encapsulates the information field according to the iterative result. Therefore, on the one hand, it only needs one clock signal to complete the parallel iterative processing of the information field, thereby improving the efficiency of the CRC calculation. On the other hand, it can flexibly configure various configuration information to adapt to a variety of CRC computing needs.
  • FIG. 1 is a schematic structural diagram of a CRC8 serial shift circuit according to a conventional art
  • FIG. 2 is a schematic diagram of an application scenario of a CRC check according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a cyclic redundancy check circuit according to an embodiment of the present invention.
  • FIG. 4 is a timing diagram of a CRC check according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a parallel iterative module using a CRC8 type according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a parallel iterative module using a CRC8 type and iterating four-bit information field according to an embodiment of the present invention
  • Figure 7 is an iteration table of Figure 6
  • FIG. 8 is a schematic structural diagram of a cyclic redundancy check apparatus according to an embodiment of the present invention.
  • FIG. 9 is a schematic flowchart diagram of a method for verifying a cyclic redundancy according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
  • N binary check code
  • m(x) is the K-order information polynomial
  • r(x) is the R-1 check polynomial
  • the code corresponding to r(x) is a redundant code, that is, a redundant code is added to the original information field to form a CRC code.
  • the calculation method of r(x) is: adding R zeros after the K-bit information field, and dividing by the code sequence corresponding to g(x), the obtained remainder is the code corresponding to r(x) (should be R- 1 bit; if not, it fills 0 in the high position.
  • the transmitted field is:
  • Receiver Check using the same generated code: Received field/generated code (binary division), correct if it can be divided.
  • the embodiment of the present invention provides an application scenario of the CRC check.
  • the application scenario 200 includes the following elements: an electronic tag 21, a reader/writer 22, and a cloud server 23.
  • the cloud server 23 can be a physical server or a logical server virtualized by multiple physical servers.
  • the cloud server 23 can also be a server group composed of a plurality of servers that can communicate with each other.
  • the electronic tag 21 is composed of a chip and a coupling element, and the built-in antenna communicates with the reader.
  • the reader/writer 22 has a CRC check module embedded therein.
  • the CRC check module uses the preset generator polynomial checksum to encapsulate the communication data, thereby making the transmission communication data more reliable.
  • the electronic tag 21 verifies the communication data using the same generator polynomial, and the verification is successful, the electronic tag 21 returns the verification success information to the reader/writer 22, and the reader/writer 22 verifies the verification.
  • the success information is sent to the cloud server 23 for storage so that the user further develops the verification success information in the cloud server 23.
  • the CRC check module calculates the CRC check code based on the communication data
  • one clock information is required to input one bit of the information code in the communication data, so that the reader/writer 22 cannot respond to the electronic tag 21 quickly to complete the reading and writing process.
  • the CRC check module is not able to flexibly configure the corresponding generator polynomial according to the communication protocol requirements to calculate the CRC check code more quickly or accurately.
  • an embodiment of the present invention provides a cyclic redundancy check circuit.
  • the cyclic redundancy check circuit 300 includes a configuration module 31, a CRC arbitration module 32, a CRC control module 33, a parallel iteration module 34, and a CRC output module 35.
  • the configuration module 31 obtains configuration information and an information field.
  • the configuration information may include a CRC type, a generator polynomial, a CRC initial value, information field rollover processing information, and an iteration result XOR and flip processing information.
  • the configuration information is used to instruct the cyclic redundancy check circuit 300 to select a corresponding configuration information to complete the CRC check. Processing with output data.
  • the CRC type includes any of the following: CRC4, CRC7, CRC8, CRC12, CRC16, CRC32.
  • the generator polynomial includes a generator polynomial type corresponding to each power of the generator polynomial, wherein the generator polynomial type corresponds to the CRC type, and the user can define the generator polynomial type corresponding to each power in the generator polynomial according to the protocol or the product requirement. coefficient.
  • the CRC initial value is used to initialize the parallel iterative module 34, where the CRC initial value can be a protocol defined value or an output value from the last parallel iteration, the number of bits of the CRC initial value being associated with the iteration number of the parallel iteration module 34.
  • the information field inversion processing information is used to instruct the configuration module 31 to invert the respective information codes of the information fields in advance according to the protocol.
  • the iterative result XOR and flip processing information is used to instruct the CRC output module 35 to perform an exclusive OR and flip process on the iterative result.
  • the configuration information includes information field inversion processing information
  • the configuration module 21 inverts the processing information according to the information field, and performs an inversion processing on the information field to conform to the corresponding information field of the protocol output preprocessing.
  • the configuration information includes a CRC type or a generator polynomial.
  • the CRC type is CRC16, the same is available, and the corresponding generator polynomial can be determined for verification.
  • the CRC arbitration module 32 determines, according to the generator polynomial, that the coefficient of the fifth power is 1, the coefficient of the third power is 1, and the coefficients of the power of zero are 1, the power of the first power, the power of the second power, and the coefficient of the fourth power. Is 0.
  • the configuration information includes a CRC initial value.
  • the parallel iteration module 34 simultaneously receives the input of the CRC initial value and the information field for iterative processing.
  • the information field is the communication data sent by the sender to the sender, which is a binary sequence.
  • the CRC arbitration module 32 After determining the generator polynomial according to the configuration information, the CRC arbitration module 32 sends a trigger signal to the CRC control module 33, and the CRC control module 33 sends a clock signal to the parallel iteration module 34 according to the trigger signal, and generates coefficients and information corresponding to each power in the polynomial.
  • the field, parallel iteration module 34 in response to the clock signal, completes the input of the information field in parallel, and performs an iterative parallel processing on the information field according to the coefficients corresponding to the powers in the generator polynomial to output the iterative result.
  • the CRC output module 35 encapsulates the information field based on the iterative result. When the information field is encapsulated and the configuration information includes iterative result XOR and flip processing information, the CRC output module 35 may perform an exclusive OR and flip process on the iterative result.
  • the cyclic redundancy check circuit 300 is used. On the one hand, as shown in FIG. 4, it can complete the parallel iterative processing of the information field by only one clock signal of one cycle, thereby improving the efficiency of the CRC calculation. On the other hand, it can flexibly configure various configuration information to adapt to a variety of CRC computing needs.
  • the configuration information includes a j-1 bit CRC initial value
  • the parallel iteration module 34 includes i*j iteration units.
  • the iteration unit of the 0th column of the i-1th row is set to receive the information value of the corresponding bit in the information field.
  • the 0th column and the j-1th column iteration unit are arranged to calculate the output value of the iteration unit of the 0th row and the j-1th column according to the CRC initial value and the coefficient of the corresponding power in the generator polynomial in response to the clock signal.
  • the i-th row and the j-th column iteration unit are arranged to calculate the i-th row and the j-th column iteration unit according to the clock signal, according to the output value of the j-1th iteration unit of the i-1th line and the coefficient of the corresponding power in the generator polynomial.
  • the output value, i and j are both positive integers.
  • Each iteration unit includes at least one multiplier and an exclusive OR.
  • the multiplier of the j-1th column of the i-1th row is set to multiply the coefficient corresponding to the highest power, the CRC initial value corresponding to the highest bit, and the coefficient of the corresponding power, and output the multiplication result.
  • the XOR of the 0th column of the i-1th row is set to XOR the multiplication result with the information value of the corresponding bit in the information field, and output the output value of the iteration unit of the 0th column of the i-1th row.
  • the XOR of the 0th row and the jth column is set to XOR the multiplication result with the CRC initial value corresponding to the j-1th bit, and output the output value of the 0th column and the jth column iteration unit.
  • the XOR of the i-th row and the j-th column is set to XOR the output value with the output value of the j-1th iteration unit of the i-1th row, and output the output value of the i-th row and the j-th column iteration unit.
  • the 0th row and 0th column iteration unit is set to receive the information value of the corresponding bit in the information fields (d 0 , d 1 . . . d n-2 , d n-1 ).
  • the 0th column and the j-1th column iteration unit are set to be responsive to the clock signal, according to the CRC initial value and the coefficient of the corresponding power in the generator polynomial (g 0 , g 1 , g 2 ... g 6 , g 7 , g 8 ), calculate the output value of the iteration unit in column 0-1 of row 0.
  • the nth row and the jth column iteration unit are arranged to calculate the nth row and jth column iteration unit according to the clock signal, according to the output value of the j-1th iteration unit of the n-1th row and the coefficient of the corresponding power in the generator polynomial.
  • the output value, n and j are both positive integers.
  • Each iteration unit 341 includes at least one multiplier 3411 and an exclusive ORer 3412.
  • the multiplier 3411 of the j-1th column of the i-1th row is set to the coefficient g 8 corresponding to the highest power and the CRC initial value corresponding to the highest bit. And the coefficient of the corresponding power Multiply and output the multiplication result.
  • the exclusive OR unit 3412 of the 0th column of the n-1th row is set to XOR the multiplication result with the information value of the corresponding bit in the information field, and output the output value of the iteration unit 341 of the 0th column of the n-1th row.
  • the XOR device 3412 of the 0th row and the jth column is set to XOR the multiplication result with the j-1th bit corresponding CRC initial value, and output the output value of the 0th column and jth column iteration unit 341.
  • the exclusive OR unit 3412 of the i-th row and the j-th column is set to XOR the output value with the output value of the i-1th row j-1 iteration unit 341, and output the output value of the i-th row j-th column iteration unit 341. .
  • the embodiment of the present invention provides an iterative process of a 4-bit information field.
  • the information fields are d 0 , d 1 , d 2 , and d 3 .
  • CRC initial value They are 01010101, respectively, and the coefficients g 0 , g 1 , g 2 , g 6 , g 7 , and g 8 of the corresponding powers in the generator polynomial are respectively 10001111.
  • the parallel iterative module 34 iterates based on the CRC initial value, the coefficient of the corresponding power in the generator polynomial, and the information field, and iterates the result. They are: 01101111.
  • the configuration information includes the CRC type and the coefficients of the generator polynomial.
  • the CRC arbitration module determines the coefficients of the type of the generator polynomial and the powers of the generator polynomial according to the CRC type and the coefficients of the generator polynomial. Therefore, the CRC arbitration module can determine the coefficients of the generator polynomial according to the CRC type, and can customize the coefficients of the polynomial according to the protocol to determine the coefficients corresponding to the powers, thereby implementing the flexible configuration generation polynomial.
  • an embodiment of the present invention provides a chip including the cyclic redundancy check circuit according to any one of FIGS. 2 to 7.
  • the chip passes the cyclic redundancy check circuit, which can complete the parallel iterative processing of the information field with only one cycle of 1T clock signal, thereby improving the efficiency of the CRC calculation.
  • it can flexibly configure various configuration information to adapt to a variety of CRC computing needs.
  • the chip is a general purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), microcontroller, ARM (Acorn RISC Machine) or other programmable logic device, discrete gate or transistor Logical, discrete hardware components or any combination of these components.
  • embedded device 112 can be any conventional processor, controller, microcontroller or state machine.
  • the processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • an embodiment of the present invention provides a cyclic redundancy check apparatus.
  • the cyclic redundancy check device can implement cyclic redundancy check by means of software plus a general hardware platform.
  • the difference from the foregoing embodiments is that the embodiment of the present invention can also flexibly configure various types of configuration information for indicating CRC check to meet various application requirements. Therefore, as shown in FIG. 8 , the cyclic redundancy check apparatus 800 includes an acquisition module 81 , a determination module 82 , an iteration module 83 , and a packaging module 84 .
  • the obtaining module 81 is configured to obtain configuration information and an information field.
  • the determining module 82 is configured to determine coefficients corresponding to the powers of the generator polynomial from the generator polynomials based on the configuration information.
  • the iteration module 83 is arranged to perform parallel iterative processing on the information fields according to the coefficients corresponding to the powers in the generator polynomial to output the iterative result.
  • Encapsulation module 84 is arranged to encapsulate the information field based on the iterative result.
  • the configuration information may include a CRC type, a generator polynomial, a CRC initial value, information field rollover processing information, and an iteration result XOR and rollover processing information, and the configuration information is used to instruct the cyclic redundancy check apparatus 800 to select a corresponding configuration information to complete the CRC check. Processing with output data.
  • the CRC type includes any of the following: CRC4, CRC7, CRC8, CRC12, CRC16, CRC32.
  • the generator polynomial includes a generator polynomial type corresponding to each power of the generator polynomial, wherein the generator polynomial type corresponds to the CRC type, and the user can define the generator polynomial type corresponding to each power in the generator polynomial according to the protocol or the product requirement. coefficient.
  • the CRC initial value is used for initialization, wherein the CRC initial value may be a protocol definition value or an output value of the last parallel iteration, and the number of bits of the CRC initial value is associated with the number of parallel iteration bits.
  • the information field inversion processing information is used to instruct the obtaining module 81 to invert each information code of the information field in advance according to the protocol.
  • the iterative result XOR and flip processing information is used to instruct the encapsulation module 84 to perform an exclusive OR and flip process on the iterative result.
  • the configuration information includes information field inversion processing information
  • the obtaining module 81 inverts the processing information according to the information field, and performs an inversion processing on the information field in advance so as to conform to the corresponding information field of the protocol output preprocessing.
  • the configuration information includes a CRC type or a generator polynomial.
  • the CRC type is CRC16, the same is available, and the corresponding generator polynomial can be determined for verification.
  • the determining module 82 determines, according to the generator polynomial, that the coefficient of the fifth power is 1, the coefficient of the third power is 1, and the coefficient of the power of zero is 1, the power of the first power, the power of the second power, and the power of the fourth power are 0.
  • the configuration information includes a CRC initial value.
  • the iteration module 83 simultaneously receives the input of the CRC initial value and the information field for iterative processing.
  • the information field is the communication data sent by the sender to the sender, which is a binary sequence.
  • the cyclic redundancy check device 800 is adopted. On the one hand, it only needs one clock signal of 1T to complete the parallel iterative processing of the information field, thereby improving the efficiency of the CRC calculation. On the other hand, it can flexibly configure various configuration information to adapt to a variety of CRC computing needs.
  • the concept of the cyclic redundancy check device 800 is the same as the concept of the CRC check implemented by the cyclic redundancy check circuit described in the above embodiments, the implementation of the cyclic redundancy check device 800 does not conflict with each other.
  • the contents of the above embodiments may be referred to, and details are not described herein.
  • the configuration information includes a CRC initial value. Therefore, the iterative module 83 is specifically configured to perform an iterative process in parallel according to the coefficients corresponding to the powers of the generator polynomial and the CRC initial value to output an iterative result.
  • the configuration information includes the CRC type and the coefficients of the generator polynomial. Therefore, the determining module 84 is specifically configured to: determine the type of the generator polynomial and each of the generator polynomials according to the CRC type and the coefficients of the generator polynomial. The coefficient corresponding to the power.
  • an embodiment of the present invention provides a cyclic redundancy check method.
  • the difference from the foregoing embodiments is that the embodiment of the present invention can also flexibly configure various types of configuration information for indicating CRC check to meet various application requirements.
  • the cyclic redundancy check method 900 includes:
  • Step 91 Obtain configuration information and an information field.
  • Step 92 Determine, according to the configuration information, a coefficient corresponding to each power in the generator polynomial and the generator polynomial;
  • Step 93 Perform parallel iterative processing on the information field according to coefficients corresponding to each power in the generator polynomial to output an iterative result;
  • Step 94 Encapsulate the information field according to the iterative result.
  • the configuration information may include a CRC type, a generator polynomial, a CRC initial value, information field rollover processing information, and an iteration result XOR and rollover processing information, and the configuration information is used to instruct the cyclic redundancy check apparatus 800 to select a corresponding configuration information to complete the CRC check. Processing with output data.
  • the CRC type includes any of the following: CRC4, CRC7, CRC8, CRC12, CRC16, CRC32.
  • the generator polynomial includes a generator polynomial type corresponding to each power of the generator polynomial, wherein the generator polynomial type corresponds to the CRC type, and the user can define the generator polynomial type corresponding to each power in the generator polynomial according to the protocol or the product requirement. coefficient.
  • the CRC initial value is used for initialization, wherein the CRC initial value may be a protocol definition value or an output value of the last parallel iteration, and the number of bits of the CRC initial value is associated with the number of parallel iteration bits.
  • the information field inversion processing information is used to invert each information code of the information field in advance according to the protocol.
  • the iterative result XOR and flip processing information is used to XOR and flip the iterative results.
  • the configuration information includes information field inversion processing information, and the processing information is inverted according to the information field, and the information field is inverted in advance so as to conform to the corresponding information field of the protocol output preprocessing.
  • the configuration information includes a CRC type or a generator polynomial.
  • the CRC type is CRC16, the same is available, and the corresponding generator polynomial can be determined for verification.
  • the coefficient of the fifth power is determined to be 1, the coefficient of the third power is 1, the coefficient of the power of zero is 1, and the coefficient of the power of the first power, the power of the second power, and the power of the fourth power is zero.
  • the configuration information includes a CRC initial value.
  • the initial value of the CRC is 01010101
  • the input of the CRC initial value and the information field are iteratively processed.
  • the information field is the communication data sent by the sender to the sender, which is a binary sequence.
  • the cyclic redundancy check method 900 is adopted. On the one hand, it only needs one clock signal of 1T to complete the parallel iterative processing of the information field, thereby improving the efficiency of the CRC calculation. On the other hand, it can flexibly configure various configuration information to adapt to a variety of CRC computing needs.
  • the configuration information includes a CRC initial value.
  • Step 93 includes: performing parallel iterative processing on the information field according to the coefficient corresponding to each power in the generator polynomial and the CRC initial value, to output an iterative result.
  • the configuration information includes the CRC type and the coefficients of the generator polynomial.
  • Step 92 includes: determining coefficients of the type of the generator polynomial and the powers of the generator polynomial according to the CRC type and the coefficients of the generator polynomial.
  • the embodiments can implement the cyclic redundancy check method by means of software plus a general hardware platform, and can also be implemented by hardware.
  • the concept of the cyclic redundancy check method is the same as the concept of implementing the cyclic redundancy check by the cyclic redundancy check device described in the above embodiments, the implementation of the cyclic redundancy check method is performed without conflicting contents.
  • the contents of the above embodiments may be referred to, and details are not described herein.
  • an embodiment of the present invention provides an electronic device.
  • the electronic device 100 includes a storage medium 11 and a processor 12.
  • the processor 12 and the storage medium 11 may be connected by a bus or other means.
  • a bus connection is taken as an example.
  • the storage medium is a non-volatile computer readable storage medium, and is usable for storing a non-volatile software program, a non-volatile computer executable program, and a module, such as the cyclic redundancy check method in the embodiment of the present invention. Corresponding program instructions/modules.
  • the processor 12 executes various functional applications and data processing of the cyclic redundancy check method by running non-volatile software programs, instructions, and modules stored in the memory 11, that is, implementing the cyclic redundancy check of the above method embodiments The function of each module of the method.
  • the storage medium 11 may include a high speed random access memory, and may also include a nonvolatile memory such as at least one magnetic disk storage device, flash memory device, or other nonvolatile solid state storage device.
  • storage medium 11 may optionally include memory remotely located relative to processor 12, which may be coupled to processor 12 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the program instructions/modules are stored in the memory 11, and when executed by the one or more processors 12, perform a cyclic redundancy check method in any of the above method embodiments, for example, performing each of the above described The function of the steps.
  • Embodiments of the present invention also provide a non-volatile computer readable storage medium storing executable instructions of an electronic device, the executable instructions being executed by one or more processors, such as A processor 12 of 10 may cause the one or more processors to perform the cyclic redundancy check method in any of the above method embodiments, for example, to perform the cyclic redundancy check method in any of the above method embodiments.
  • the apparatus or device embodiments described above are merely illustrative, wherein the unit modules described as separate components may or may not be physically separate, and the components displayed as modular units may or may not be physical units. , can be located in one place, or can be distributed to multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

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Abstract

本发明涉及计算机技术领域，特别是涉及一种循环冗余校验电路及其方法、装置以及芯片、电子设备。其中该循环冗余校验电路包括：配置模块设置为获取配置信息与信息字段；CRC仲裁模块设置为根据配置信息确定生成多项式；CRC控制模块设置为响应于CRC仲裁模块的触发，输出时钟信号、生成多项式中各次幂对应的系数及信息字段；并行迭代模块设置为响应于时钟信号，根据生成多项式中各次幂对应的系数将信息字段进行并行迭代处理以输出迭代结果；CRC输出模块设置为根据迭代结果封装信息字段。

Description

循环冗余校验电路及其方法、装置以及芯片、电子设备 技术领域
本发明涉及计算机技术领域，具体而言，涉及一种循环冗余校验电路及其方法、装置以及芯片、电子设备。
背景技术
循环冗余校验码(Cyclic Redundancy Check，CRC)用于校验数据传输的正确性与完整性，CRC运算具有很强的检错能力，易于用编码器或检测电路实现。
图1是传统技术提供一种CRC8串行移位电路的结构示意图。如图1所示，该电路的生成多项式为：G＝g 8X 8+g 7X 7+...+g 1X 1+1，其能够进行移位以计算出CRC校验码。
发明人在实现本发明的过程中，发现传统技术至少存在以下问题：进行CRC计算时，每输入一位信息码d，便需要一个时钟周期，当输入d 0、d 1......d n-1共n bit信息码,则需要n个时钟周期。因此,进行CRC计算时,需要较多时间输入多位信息码，导致CRC计算时间比较冗长。
发明内容
本发明实施例的一个目的旨在提供一种循环冗余校验电路及其方法、装置以及芯片、电子设备，其解决了现有技术存在着CRC计算效率低下的问题。
为解决上述技术问题，本发明实施例提供以下技术方案：
在第一方面，本发明实施例公开一种循环冗余校验电路，所述电路包括：配置模块，设置为获取配置信息与信息字段；CRC仲裁模块，设置为根据所述配置信息，确定生成多项式；CRC控制模块，设置为响应于所述CRC仲裁模块的触发，输出时钟信号、所述生成多项式中各次幂对应的系数及信息字段；并行迭代模块，设置为响应于所述时钟信号，根据所述生成多项式中各次幂对应的系数，将所述信息字段进行并行迭代处理，以输出迭代结果；CRC输出模块，设置为根据所述迭代结果，封装所述信息字段。
可选的，所述配置信息包括j-1位CRC初始值，所述并行迭代模块包括i*j个迭代单元；第i-1行第0列迭代单元设置为接收所述信息字段中对应位的信息值；第0行第j-1列迭代单元设置为响应于所述时钟信号，根据所述CRC初始值及生成多项式中对应次幂的系数，计算出第0行第j-1列迭代单元的输出值；第i行第j列迭代单元设置为响应于所述时钟信号，根据第i-1行第j-1迭代单元的输出值与生成多项式中对应次幂的系数，计算出第i行第j列迭代单元的输出值，i与j皆为正整数。
可选的，每个所述迭代单元至少包括一个乘法器与异或器；第i-1行第j-1列的乘法器设置为将最高次幂对应的系数、最高位对应的CRC初始值及对应次幂的系数进行相乘，并且输出相乘结果；第i-1行第0列的异或器设置为将相乘结果与所述信息字段中对应位的信息值进行异或，输出第i-1行第0列迭代单元的输出值；第0行第j列的异或器设置为将相乘结果与第j-1位对应CRC初始值进行异或，输出第0行第j列迭代单元的输出值；第i行第j列的异或器设置为将相乘结果与第i-1行第j-1迭代单元的输出值进行异或，输出第i行第j列迭代单元的输出值。
可选的，所述配置信息包括CRC类型与生成多项式的各项系数；所述CRC仲裁模块设置为根据所述配置信息，确定生成多项式，包括：所述CRC仲裁模块设置为根据所述CRC类型与生成多项式的各项系数，确定生成多项式的类型与所述生成多项式中各次幂对应的系数。
可选的，所述CRC类型包括以下任意一种：CRC4、CRC7、CRC8、CRC12、CRC16、CRC32。
在第二方面，本发明实施例提供一种循环冗余校验方法，所述方法包括：获取配置信息与信息字段；根据所述配置信息，确定生成多项式与所述生成多项式中各次幂对应的系数；根据所述生成多项式中各次幂对应的系数，将所述信息字段进行并行迭代处理，以输出迭代结果；根据所述迭代结果，封装所述信息字段。
可选的，所述配置信息包括CRC初始值；所述根据所述生成多项式中各次幂对应的系数，将所述信息字段进行并行迭代处理，以输出迭代结果，包括：根据所述生成多项式中各次幂对应的系数与CRC初始值，将所述信息字段进行并行迭代处理，以输出迭代结果。
可选的，所述配置信息包括CRC类型与生成多项式的各项系数；所述根据所述配置信息，确定生成多项式与所述生成多项式中各次幂对应的系数，包括：根据所述CRC类型与生成多项式的各项系数，确定生成多项式的类型与所述生成多项式中各次幂对应的系数。
在第三方面，本发明实施例提供一种循环冗余校验装置，所述装置包括：获取模块，设置为获取配置信息与信息字段；确定模块，设置为根据所述配置信息，确定生成多项式与所述生成多项式中各次幂对应的系数；迭代模块，设置为根据所述生成多项式中各次幂对应的系数，将所述信息字段进行并行迭代处理，以输出迭代结果；封装模块，设置为根据所述迭代结果，封装所述信息字段。
可选的，所述配置信息包括CRC初始值；所述迭代模块具体设置为：根据所述生成多项式中各次幂对应的系数与CRC初始值，将所述信息字段进行并行迭代处理，以输出迭代结果。
可选的，所述配置信息包括CRC类型与生成多项式的各项系数；所述确定模块具体设置为：根据所述CRC类型与生成多项式的各项系数，确定生成多项式的类型与所述生成多项式中各次幂对应的系数。
在第四方面，本发明实施例提供一种芯片，所述芯片包括如上述任一的循环冗余校验电路。
在第五方面，本发明实施例提供一种非易失性计算机可读存储介质，所述非易失性计算机可读存储介质存储有电子设备的可执行指令，所述可执行指令设置为使所述电子设备执行如上述任一的循环冗余校验方法。
在第六方面，一种电子设备，包括：至少一个处理器；以及与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够用于执行如上述任一的循环冗余校验方法。
在本发明各个实施例中，配置模块获取配置信息与信息字段，CRC仲裁模块根据配置信息，确定生成多项式，CRC控制模块响应于CRC仲裁模块的触发，输出时钟信号与生成多项式中各次幂对应的系数，并行迭代模块响应于时钟信号，根据生成多项式中各次幂对应的系数，将信息字段进行并行迭代处理，以输出迭代结果，CRC输出模块根据迭代结果，封装信息字段。因此，一方面，其只需一个周期的时钟信号便可以完成信息字段的并行迭代处理，从而提高CRC计算的效率。另一方面，其可以灵活配置各类配置信息，以适应多种多样的CRC计算需求。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件， 除非有特别申明，附图中的图不构成比例限制。
图1是传统技术提供一种CRC8串行移位电路的结构示意图；
图2是本发明实施例提供一种CRC校验的应用场景示意图；
图3是本发明实施例提供一种循环冗余校验电路的结构示意图；
图4是本发明实施例提供一种CRC校验的时序图；
图5是本发明实施例提供一种采用CRC8类型的并行迭代模块的结构示意图；
图6是本发明实施例提供一种采用CRC8类型并且迭代四位信息字段的并行迭代模块的结构示意图；
图7是图6的迭代表；
图8是本发明实施例提供一种循环冗余校验装置的结构示意图；
图9是本发明实施例提供一种循环冗余校验方法的流程示意图；
图10是本发明实施例提供一种电子设备的结构示意图；
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
CRC校验原理是在一个K位二进制数据序列之后附加一个(N-R)位二进制校验码(序列)，从而构成一个总长为N＝K+R位的二进制序列。附加在数据序列之后的校验码与数据序列的内容之间存在着某种特定的关系。若因干扰等原因使数据序列中的某一位或某些位发生错误，此种特定关系被破坏，特此，通过CRC校验算法或CRC校验电路校验此类关系，便可以校验数据序列的正确性。
当进行CRC校验时，发送方与接收方需要事先约定一个除数，即生成多项式，一般记作G(x)。生成多项式的最高位与最低位必须是1。常用的CRC码的生成多项式有：
CRC8＝X8+X5+X4+1；
CRC-CCITT＝X16+X12+X5+1；
CRC16＝X16+X15+X5+1；
CRC12＝X12+X11+X3+X2+1；
CRC32＝X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X1+1；
进一步的，如上所述，为了进行差错校验，需要在k位的信息字段后添加的(N-R)位冗余码。
进一步的，在CRC校验过程中，需要用到模2计算方法，所谓的模2计算方法是按位异或(Exclusive OR)运算，即相同为0，相异为1，也就是不考虑进位、借位的二进制加减运算。如：10011011+11001010＝01010001。
CRC校验码的计算原理如下：
设信息字段为K位，校验字段为R位，则码字长度为N(N＝K+R)。设双方事先约定了一个R次多项式g(x)，则CRC码：
V(x)＝A(x)g(x)＝xRm(x)+r(x)
其中：m(x)为K次信息多项式，r(x)为R-1次校验多项式。
r(x)对应的代码即为冗余码，亦即，冗余码加在原信息字段后即形成CRC码。
r(x)的计算方法为：在K位信息字段的后面添加R个0，再除以g(x)对应的代码序列，得到的余数即为r(x)对应的代码(应为R－1位；若不足，而在高位补0)。
例如：
信息字段代码为:1011001；对应m(x)＝x6+x4+x3+1
假设生成多项式为：g(x)＝x4+x3+1；则对应g(x)的代码为:11001
x4m(x)＝x10+x8+x7+x4对应的代码记为：10110010000；
采用多项式除法，得到余数为:1010(即校验字段为：1010)
发送方：发出的传输字段为：
1 0 1 1 0 0 1 1 0 1 0
信息字段 校验字段
接收方：使用相同的生成码进行校验:接收到的字段/生成码(二进制除法)，如果能够除尽，则正确。
为了进一步阐述CRC校验的工作原理，本发明实施例提供一种CRC校验的应用场景。如图2所示，该应用场景200包括以下元素：电子标签21、读写器22及云端服务器23。云端服务器23可以是一个物理服务器或者多个物理服务器虚拟而成的一个逻辑服务器。云端服务器23也可以是多个可互联通信的服务器组成的服务器群。
电子标签21由芯片和耦合元件构成，内置天线与读写器通讯。读写器22内嵌有CRC校验模块，当读写器22向电子标签21发送通信数据时，CRC校验模块使用预设的生成多项式校验与封装该通信数据，从而使传输通信数据更加可靠。电子标签21接收到该通信数据之后，使用同样的生成多项式对该通信数据进行校验，并且校验成功，电子标签21向读写器22返回校验成功信息，读写器22将该校验成功信息发送至云端服务器23进行存储，以便用户在云端服务器23进一步开发该校验成功信息。
CRC校验模块根据该通信数据计算CRC校验码时，需要一个时钟信息方可输入通信数据中一位信息码，导致读写器22未能够迅速响应电子标签21以完成读写过程。并且，CRC校验模块未能够根据通信协议要求灵活配置对应的生成多项式以更加迅速或精确地计算出CRC校验码。
特此，本发明实施例提供一种循环冗余校验电路。如图3所示，该循环冗余校验电路300包括配置模块31、CRC仲裁模块32、CRC控制模块33、并行迭代模块34及CRC输出模块35。
配置模块31获取配置信息与信息字段。配置信息可以包括CRC类型、生成多项式、CRC初始值、信息字段翻转处理信息及迭代结果异或与翻转处理信息，配置信息用于指示循环冗余校验电路300选择对应的配置信息完成CRC校验与输出数据的处理。CRC类型包括以下任意一种：CRC4、CRC7、CRC8、CRC12、CRC16、CRC32。生成多项式包括生成多项式类型与该生成多项式中各次幂对应的系数，其中，生成多项式类型与CRC类型对应，并且用户可以根据协议或者产品需求自行定义生成多项式类型与生成多项式中各次幂对应的系数。CRC初始值用于初始化并行迭代模块34，其中，该CRC初始值可以是协议定义值或上一次并行迭代出的输出值，CRC初始值的位数与并行迭代模块34的迭代位数关联。信息字段翻转处理信息用于指示配置模块31根据协议预先将信息字段的各个信息码进行翻转。迭代结果异或与翻转处理信息用于指示CRC输出模块35对迭代结果进行异或与翻转处理。
例如，配置信息包括信息字段翻转处理信息，配置模块21根据该信息字段翻转处理信息，对信息字段预先进行翻转处理，以便符合协议输出预处理的对应信息字段。
例如，配置信息包括CRC类型或生成多项式。当CRC类型是CRC8(CRC8＝X8+X5+X4+1) 时，则CRC仲裁模块32选择CRC8对应的生成多项式进行校验，并且确定g0＝1，g1＝g2＝g3＝g4＝0，g5＝g6＝1，g7＝0，g8＝1。当CRC类型是CRC16时，同理可得，可以确定对应的生成多项式进行校验。当然，用户可以不选择标准CRC类型，而选择自定义的生成多项式进行校验，例如，g(x)＝x5+x3+1。此时，CRC仲裁模块32根据该生成多项式，确定5次幂的系数为1,3次幂的系数为1,0次幂的系数为1,1次幂、2次幂及4次幂的系数为0。
再例如，配置信息包括CRC初始值。当CRC初始值为01010101时，并行迭代模块34同时接收CRC初始值的输入与信息字段进行迭代处理。
信息字段是发送方向接收方发送的通信数据，其是二进制序列。
CRC仲裁模块32根据配置信息，确定生成多项式之后，向CRC控制模块33发送触发信号，CRC控制模块33根据该触发信号向并行迭代模块34发送时钟信号、生成多项式中各次幂对应的系数及信息字段，并行迭代模块34响应于该时钟信号，并行完成信息字段的输入，并且根据生成多项式中各次幂对应的系数，将信息字段进行并行迭代处理，以输出迭代结果。CRC输出模块35根据迭代结果，封装信息字段。在封装该信息字段，并且配置信息包括迭代结果异或与翻转处理信息时，CRC输出模块35可以对迭代结果进行异或与翻转处理。
综上，采用该循环冗余校验电路300，一方面，如图4所示，其只需一个周期1T的时钟信号便可以完成信息字段的并行迭代处理，从而提高CRC计算的效率。另一方面，其可以灵活配置各类配置信息，以适应多种多样的CRC计算需求。
在一些实施例中，配置信息包括j-1位CRC初始值，并且，并行迭代模块34包括i*j个迭代单元。其中，第i-1行第0列迭代单元设置为接收信息字段中对应位的信息值。第0行第j-1列迭代单元设置为响应于时钟信号，根据CRC初始值及生成多项式中对应次幂的系数，计算出第0行第j-1列迭代单元的输出值。第i行第j列迭代单元设置为响应于时钟信号，根据第i-1行第j-1迭代单元的输出值与生成多项式中对应次幂的系数，计算出第i行第j列迭代单元的输出值，i与j皆为正整数。
每个迭代单元至少包括一个乘法器与异或器。第i-1行第j-1列的乘法器设置为将最高次幂对应的系数、最高位对应的CRC初始值及对应次幂的系数进行相乘，并且输出相乘结果。第i-1行第0列的异或器设置为将相乘结果与信息字段中对应位的信息值进行异或，输出第i-1行第0列迭代单元的输出值。第0行第j列的异或器设置为将相乘结果与第j-1位对应CRC初始值进行异或，输出第0行第j列迭代单元的输出值。第i行第j列的异或器设置为将相乘结果与第i-1行第j-1迭代单元的输出值 进行异或，输出第i行第j列迭代单元的输出值。
为了详细阐述并行迭代模块34，本发明实施例以CRC8为例子，详细阐述并行迭代模块34的工作原理。如图5所示，CRC初始值分别为：
Figure PCTCN2017118622-appb-000001
并行迭代模块34包括n*8个迭代单元341(i＝n，j＝1、2、3、4、5、6、7)，n是正整数。其中，第0行第0列迭代单元设置为接收信息字段(d 0、d 1......d n-2、d n-1)中对应位的信息值。第0行第j-1列迭代单元设置为响应于时钟信号，根据CRC初始值及生成多项式中对应次幂的系数(g 0、g 1、g 2......g 6、g 7、g 8)，计算出第0行第j-1列迭代单元的输出值。第n行第j列迭代单元设置为响应于时钟信号，根据第n-1行第j-1迭代单元的输出值与生成多项式中对应次幂的系数，计算出第n行第j列迭代单元的输出值，n与j皆为正整数。
每个迭代单元341至少包括一个乘法器3411与异或器3412。第i-1行第j-1列的乘法器3411设置为将最高次幂对应的系数g 8、最高位对应的CRC初始值
Figure PCTCN2017118622-appb-000002
及对应次幂的系数
Figure PCTCN2017118622-appb-000003
进行相乘，并且输出相乘结果。第n-1行第0列的异或器3412设置为将相乘结果与信息字段中对应位的信息值进行异或，输出第n-1行第0列迭代单元341的输出值。第0行第j列的异或器3412设置为将相乘结果与第j-1位对应CRC初始值进行异或，输出第0行第j列迭代单元341的输出值。第i行第j列的异或器3412设置为将相乘结果与第i-1行第j-1迭代单元341的输出值进行异或，输出第i行第j列迭代单元341的输出值。
为了进一步详细阐述图5所示实施例的迭代过程，本发明实施例提供4位信息字段的迭代过程，如图6与图7所示，信息字段为d 0、d 1、d 2、d 3分别为0011，CRC初始值
Figure PCTCN2017118622-appb-000004
分别为01010101，生成多项式中对应次幂的系数g 0、g 1、g 2......g 6、g 7、g 8分别为100001111。并行迭代模块34根据CRC初始值、生成多项式中对应次幂的系数与信息字段进行迭代，迭代结果
Figure PCTCN2017118622-appb-000005
分别为：01101111。
在一些实施例中，与上述各个实施例的不同点在于，配置信息包括CRC类型与生成多项式的各项系数。CRC仲裁模块根据CRC类型与生成多项式的各项系数，确定生成多项式的类型与所述生成多项式中各次幂对应的系数。因此，CRC仲裁模块既可以 根据CRC类型便可以确定生成多项式的各项系数，又可以根据协议自定义生成多项式的各项系数以确定各次幂对应的系数，从而实现灵活配置生成多项式。
作为本发明实施例的另一方面，本发明实施例提供一种芯片，其包括如图2至图7任一项所述的循环冗余校验电路。芯片通过该循环冗余校验电路，其只需一个周期1T的时钟信号便可以完成信息字段的并行迭代处理，从而提高CRC计算的效率。另一方面，其可以灵活配置各类配置信息，以适应多种多样的CRC计算需求。
该芯片为通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)、单片机、ARM(Acorn RISC Machine)或其它可编程逻辑器件、分立门或晶体管逻辑、分立的硬件组件或者这些部件的任何组合。还有，嵌入式装置112还可以是任何传统处理器、控制器、微控制器或状态机。处理器也可以被实现为计算设备的组合，例如，DSP和微处理器的组合、多个微处理器、一个或多个微处理器结合DSP核、或任何其它这种配置。
作为本发明实施例的又另一方面，本发明实施例提供一种循环冗余校验装置。该循环冗余校验装置可借助软件加通用硬件平台的方式来实现循环冗余校验。并且，与上述各个实施例的不同点在于，本发明实施例还可以通过灵活配置用于指示CRC校验的各类配置信息以满足各类应用需求。特此，如图8所示，该循环冗余校验装置800包括获取模块81、确定模块82、迭代模块83及封装模块84。
获取模块81设置为获取配置信息与信息字段。确定模块82设置为根据配置信息，确定生成多项式与生成多项式中各次幂对应的系数。迭代模块83设置为根据生成多项式中各次幂对应的系数，将信息字段进行并行迭代处理，以输出迭代结果。封装模块84设置为根据迭代结果，封装信息字段。
配置信息可以包括CRC类型、生成多项式、CRC初始值、信息字段翻转处理信息及迭代结果异或与翻转处理信息，配置信息用于指示循环冗余校验装置800选择对应的配置信息完成CRC校验与输出数据的处理。CRC类型包括以下任意一种：CRC4、CRC7、CRC8、CRC12、CRC16、CRC32。生成多项式包括生成多项式类型与该生成多项式中各次幂对应的系数，其中，生成多项式类型与CRC类型对应，并且用户可以根据协议或者产品需求自行定义生成多项式类型与生成多项式中各次幂对应的系数。CRC初始值用于初始化，其中，该CRC初始值可以是协议定义值或上一次并行迭代出的输出值，CRC初始值的位数与并行迭代位数关联。信息字段翻转处理信息用于指示获取模块81根据协议预先将信息字段的各个信息码进行翻转。迭代结果异或与翻转处理信息用于指示封装模块84对迭代结果进行异或与翻转处理。
例如，配置信息包括信息字段翻转处理信息，获取模块81根据该信息字段翻转处理信息，对信息字段预先进行翻转处理，以便符合协议输出预处理的对应信息字段。
例如，配置信息包括CRC类型或生成多项式。当CRC类型是CRC8(CRC8＝X8+X5+X4+1)时，则CRC仲裁模块32选择CRC8对应的生成多项式进行校验，并且确定g0＝1，g1＝g2＝g3＝g4＝0，g5＝g6＝1，g7＝0，g8＝1。当CRC类型是CRC16时，同理可得，可以确定对应的生成多项式进行校验。当然，用户可以不选择标准CRC类型，而选择自定义的生成多项式进行校验，例如，g(x)＝x5+x3+1。此时，确定模块82根据该生成多项式，确定5次幂的系数为1,3次幂的系数为1,0次幂的系数为1,1次幂、2次幂及4次幂的系数为0。
再例如，配置信息包括CRC初始值。当CRC初始值为01010101时，迭代模块83同时接收CRC初始值的输入与信息字段进行迭代处理。
信息字段是发送方向接收方发送的通信数据，其是二进制序列。
综上，采用该循环冗余校验装置800，一方面，其只需一个周期1T的时钟信号便可以完成信息字段的并行迭代处理，从而提高CRC计算的效率。另一方面，其可以灵活配置各类配置信息，以适应多种多样的CRC计算需求。
并且，由于循环冗余校验装置800的构思与上述各个实施例所述的循环冗余校验电路实现CRC校验的构思一样，在内容不互相冲突下，循环冗余校验装置800的实施例可以引用上述各个实施例的内容，在此不赘述。
在一些实施例中，配置信息包括CRC初始值，因此，迭代模块83具体设置为：根据生成多项式中各次幂对应的系数与CRC初始值，将信息字段进行并行迭代处理，以输出迭代结果。
在一些实施例中，配置信息包括CRC类型与生成多项式的各项系数，因此，确定模块84具体设置为：根据CRC类型与生成多项式的各项系数，确定生成多项式的类型与生成多项式中各次幂对应的系数。
作为本发明实施例的又另一方面，本发明实施例提供一种循环冗余校验方法。与上述各个实施例的不同点在于，本发明实施例还可以通过灵活配置用于指示CRC校验的各类配置信息以满足各类应用需求。如图9所示，该循环冗余校验方法900包括：
步骤91、获取配置信息与信息字段；
步骤92、根据配置信息，确定生成多项式与生成多项式中各次幂对应的系数；
步骤93、根据生成多项式中各次幂对应的系数，将信息字段进行并行迭代处理，以输出迭代结果；
步骤94、根据迭代结果，封装信息字段。
配置信息可以包括CRC类型、生成多项式、CRC初始值、信息字段翻转处理信息及迭代结果异或与翻转处理信息，配置信息用于指示循环冗余校验装置800选择对应的配置信息完成CRC校验与输出数据的处理。CRC类型包括以下任意一种：CRC4、CRC7、CRC8、CRC12、CRC16、CRC32。生成多项式包括生成多项式类型与该生成多项式中各次幂对应的系数，其中，生成多项式类型与CRC类型对应，并且用户可以根据协议或者产品需求自行定义生成多项式类型与生成多项式中各次幂对应的系数。CRC初始值用于初始化，其中，该CRC初始值可以是协议定义值或上一次并行迭代出的输出值，CRC初始值的位数与并行迭代位数关联。信息字段翻转处理信息用于根据协议预先将信息字段的各个信息码进行翻转。迭代结果异或与翻转处理信息用于对迭代结果进行异或与翻转处理。
例如，配置信息包括信息字段翻转处理信息，根据该信息字段翻转处理信息，对信息字段预先进行翻转处理，以便符合协议输出预处理的对应信息字段。
例如，配置信息包括CRC类型或生成多项式。当CRC类型是CRC8(CRC8＝X8+X5+X4+1)时，则CRC仲裁模块32选择CRC8对应的生成多项式进行校验，并且确定g0＝1，g1＝g2＝g3＝g4＝0，g5＝g6＝1，g7＝0，g8＝1。当CRC类型是CRC16时，同理可得，可以确定对应的生成多项式进行校验。当然，用户可以不选择标准CRC类型，而选择自定义的生成多项式进行校验，例如，g(x)＝x5+x3+1。此时，根据该生成多项式，确定5次幂的系数为1,3次幂的系数为1,0次幂的系数为1,1次幂、2次幂及4次幂的系数为0。
再例如，配置信息包括CRC初始值。当CRC初始值为01010101时，同时接收CRC初始值的输入与信息字段进行迭代处理。
信息字段是发送方向接收方发送的通信数据，其是二进制序列。
综上，采用该循环冗余校验方法900，一方面，其只需一个周期1T的时钟信号便可以完成信息字段的并行迭代处理，从而提高CRC计算的效率。另一方面，其可以灵活配置各类配置信息，以适应多种多样的CRC计算需求。
在一些实施例中，配置信息包括CRC初始值。步骤93包括：根据生成多项式中各次幂对应的系数与CRC初始值，将信息字段进行并行迭代处理，以输出迭代结果。
在一些实施例中，配置信息包括CRC类型与生成多项式的各项系数。步骤92包括： 根据CRC类型与生成多项式的各项系数，确定生成多项式的类型与生成多项式中各次幂对应的系数。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加通用硬件平台的方式来实现循环冗余校验方法，当然也可以通过硬件实现。并且，由于循环冗余校验方法的构思与上述各个实施例所述的循环冗余校验装置实现循环冗余校验的构思一样，在内容不互相冲突下，循环冗余校验方法的实施例可以引用上述各个实施例的内容，在此不赘述。
作为本发明实施例的又一方面，本发明实施例提供一种电子设备。如图10所示，该电子设备100包括：存储介质11与处理器12，处理器12和存储介质11可以通过总线或者其他方式连接，图10中以通过总线连接为例。该存储介质作为一种非易失性计算机可读存储介质，可用于存储非易失性软件程序、非易失性计算机可执行程序以及模块，如本发明实施例中的循环冗余校验方法对应的程序指令/模块。处理器12通过运行存储在存储器11中的非易失性软件程序、指令以及模块，从而执行循环冗余校验方法的各种功能应用以及数据处理，即实现上述方法实施例的循环冗余校验方法的各个模块的功能。
存储介质11可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实施例中，存储介质11可选包括相对于处理器12远程设置的存储器，这些远程存储器可以通过网络连接至处理器12。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
所述程序指令/模块存储在所述存储器11中，当被所述一个或者多个处理器12执行时，执行上述任意方法实施例中的循环冗余校验方法，例如，执行以上描述的各个步骤的功能。
本发明实施例还提供了一种非易失性计算机存储介质，非易失性计算机可读存储介质存储有电子设备的可执行指令，该可执行指令被一个或多个处理器执行，例如图10中的一个处理器12，可使得上述一个或多个处理器可执行上述任意方法实施例中的循环冗余校验方法，例如，执行上述任意方法实施例中的循环冗余校验方法。
以上所描述的装置或设备实施例仅仅是示意性的，其中所述作为分离部件说明的单元模块可以是或者也可以不是物理上分开的，作为模块单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络模块单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，上述技术方案本质上或者说对相关技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；在本发明的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，步骤可以以任意顺序实现，并存在如上所述的本发明的不同方面的许多其它变化，为了简明，它们没有在细节中提供；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围

Claims (14)

  1. 一种循环冗余校验电路，包括：
    配置模块，设置为获取配置信息与信息字段；
    CRC仲裁模块，设置为根据所述配置信息，确定生成多项式；
    CRC控制模块，设置为响应于所述CRC仲裁模块的触发，输出时钟信号、所述生成多项式中各次幂对应的系数及信息字段；
    并行迭代模块，设置为响应于所述时钟信号，根据所述生成多项式中各次幂对应的系数，将所述信息字段进行并行迭代处理，以输出迭代结果；
    CRC输出模块，设置为根据所述迭代结果，封装所述信息字段。
  2. 根据权利要求1所述的电路，其中，所述配置信息包括j-1位CRC初始值，所述并行迭代模块包括i*j个迭代单元；
    第i-1行第0列迭代单元设置为接收所述信息字段中对应位的信息值；
    第0行第j-1列迭代单元设置为响应于所述时钟信号，根据所述CRC初始值及生成多项式中对应次幂的系数，计算出第0行第j-1列迭代单元的输出值；
    第i行第j列迭代单元设置为响应于所述时钟信号，根据第i-1行第j-1迭代单元的输出值与生成多项式中对应次幂的系数，计算出第i行第j列迭代单元的输出值，i与j皆为正整数。
  3. 根据权利要求2所述的电路，其中，每个所述迭代单元至少包括一个乘法器与异或器；
    第i-1行第j-1列的乘法器设置为将最高次幂对应的系数、最高位对应的CRC初始值及对应次幂的系数进行相乘，并且输出相乘结果；
    第i-1行第0列的异或器设置为将相乘结果与所述信息字段中对应位的信息值进行异或，输出第i-1行第0列迭代单元的输出值；
    第0行第j列的异或器设置为将相乘结果与第j-1位对应CRC初始值进行异或，输出第0行第j列迭代单元的输出值；
    第i行第j列的异或器设置为将相乘结果与第i-1行第j-1迭代单元的输出值进行异或，输出第i行第j列迭代单元的输出值。
  4. 根据权利要求1至3任一项所述的电路，其中，所述配置信息包括CRC类型与生成多项式的各项系数；
    所述CRC仲裁模块设置为根据所述配置信息，确定生成多项式，包括：
    所述CRC仲裁模块设置为根据所述CRC类型与生成多项式的各项系数，确定生成多项式的类型与所述生成多项式中各次幂对应的系数。
  5. 根据权利要求4所述的电路，其中，所述CRC类型包括以下任意一种：CRC4、CRC7、CRC8、CRC12、CRC16、CRC32。
  6. 一种循环冗余校验方法，包括：
    获取配置信息与信息字段；
    根据所述配置信息，确定生成多项式与所述生成多项式中各次幂对应的系数；
    根据所述生成多项式中各次幂对应的系数，将所述信息字段进行并行迭代处理，以输出迭代结果；
    根据所述迭代结果，封装所述信息字段。
  7. 根据权利要求6所述的方法，其中，所述配置信息包括CRC初始值；
    所述根据所述生成多项式中各次幂对应的系数，将所述信息字段进行并行迭代处理，以输出迭代结果，包括：
    根据所述生成多项式中各次幂对应的系数与CRC初始值，将所述信息字段进行并行迭代处理，以输出迭代结果。
  8. 根据权利要求6或7所述的方法，其中，所述配置信息包括CRC类型与生成多项式的各项系数；
    所述根据所述配置信息，确定生成多项式与所述生成多项式中各次幂对应的系数，包括：
    根据所述CRC类型与生成多项式的各项系数，确定生成多项式的类型与所述生成多项式中各次幂对应的系数。
  9. 一种循环冗余校验装置，包括：
    获取模块，设置为获取配置信息与信息字段；
    确定模块，设置为根据所述配置信息，确定生成多项式与所述生成多项式中 各次幂对应的系数；
    迭代模块，设置为根据所述生成多项式中各次幂对应的系数，将所述信息字段进行并行迭代处理，以输出迭代结果；
    封装模块，设置为根据所述迭代结果，封装所述信息字段。
  10. 根据权利要求9所述的装置，其中，所述配置信息包括CRC初始值；
    所述迭代模块具体设置为：根据所述生成多项式中各次幂对应的系数与CRC初始值，将所述信息字段进行并行迭代处理，以输出迭代结果。
  11. 根据权利要求9或10所述的装置，其中，所述配置信息包括CRC类型与生成多项式的各项系数；
    所述确定模块具体设置为：根据所述CRC类型与生成多项式的各项系数，确定生成多项式的类型与所述生成多项式中各次幂对应的系数。
  12. 一种芯片，包括如权利要求1至5任一项所述的循环冗余校验电路。
  13. 一种非易失性计算机可读存储介质，所述非易失性计算机可读存储介质存储有电子设备的可执行指令，所述可执行指令用于使所述电子设备执行如权利要求6至8任一项所述的循环冗余校验方法。
  14. 一种电子设备，包括：
    至少一个处理器；以及
    与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够用于执行如权利要求6至8任一项所述的循环冗余校验方法。
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