WO2018195830A9

WO2018195830A9 - Field effect device, manufacturing method therefor, and chip using same

Info

Publication number: WO2018195830A9
Application number: PCT/CN2017/082062
Authority: WO
Inventors: 蔡皓程; 徐挽杰; 张臣雄
Original assignee: 华为技术有限公司
Priority date: 2017-04-26
Filing date: 2017-04-26
Publication date: 2019-11-14
Also published as: WO2018195830A1

Abstract

A field effect device, a manufacturing method therefor, and a chip using the same. The method comprises: forming a dummy gate structure (05) and a spindle structure (04) on a substrate baseplate (00), the substrate baseplate (00) comprising a first region (01) for forming a MOSFET and a second region (02) for forming a TFET; forming sidewalls (041, 051) around the dummy gate structure (05) and around the spindle structure (04) respectively; ion doping the source and drain areas (01a, 01b) of the MOSFET and a second electrode area of the TFET; removing the sidewall (041) outside a target area in the second region (02) and the spindle structure (04), the target area comprising an area in the second region (02) for forming a gate; ion doping a first electrode area of the TFET; and forming gates in the first region (01) and the second region (02) respectively. With the method, field effect devices incorporating a MOSFET and a TFET can be manufactured, and chips utilizing the field effect device have good performance and low power consumption.

Description

Field effect device and manufacturing method thereof, chip

Technical field

The present application relates to the field of semiconductor device manufacturing technologies, and in particular, to a field effect device, a method for fabricating the same, and a chip.

Background technique

A field effect transistor is a semiconductor device that utilizes the electric field effect of the control input loop to control the output loop current. The field effect transistor is a voltage-controlled semiconductor device, which has the advantages of high input resistance, low noise, low power consumption, and easy integration, and is a main device constituting a processor chip and a memory chip.

In the related art, commonly used field effect transistors generally include a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a Tunneling Field Effect Transistor (TFET). Wherein, the MOSFET is a gate electric field formed by applying a gate voltage, causing the channel region of the device to change from a depleted state to an inversion state, thereby controlling the device to be turned from off to on. The TFET device is a gate-controlled reverse-biased P-type doped-intrinsic doped-N-type doped junction (referred to as: pin junction) device, which realizes source-side carriers and trenches by gate voltage control pin junction. The channel carrier band is tunneled to control the switching state of the device. Since the structure and manufacturing process of the two FETs are different, generally only one type of FET is used in the same chip.

However, although the chip using the MOSFET has better performance, the power consumption is higher. The chip using the TFET exhibits a good low-power performance in low-frequency operation, but its performance is relatively general.

Summary of the invention

In order to solve the problem of unbalanced performance and energy consumption of a chip using a single FET in the related art, the present application provides a field effect device, a manufacturing method thereof, and a chip. The technical solution is as follows:

In a first aspect, a method of fabricating a field effect device is provided, the method comprising:

A substrate is provided that includes a first region for forming a metal oxide semiconductor field effect transistor MOSFET and a second region for forming a tunneling field effect transistor TFET.

Forming a dummy gate structure and a spindle structure on the base substrate by a patterning process, the dummy gate structure covering a region for forming a gate in the first region, the spindle structure being a strip structure, and the spindle structure Covering the area in the second region for forming the first electrode.

The first electrode may be a source or a drain, and the dummy gate structure and the spindle structure may be made of polysilicon.

A sidewall is formed on the substrate substrate around the dummy gate structure and around the spindle structure, wherein a portion of the sidewall of the spindle structure overlies a region of the second region for forming a gate.

The sidewall is used as a mask, and a region in the first region for forming a source and a drain of the MOSFET, and a region in the second region for forming a second electrode of the TFET are ion doped. Wherein, when the first electrode is a drain, the second electrode is a source; when the first electrode is a source, the second electrode is a drain.

Removing a sidewall in the second region outside the target region and a spindle structure in the second region, the target region including a region in the second region for forming a gate; and then utilizing the remaining portion in the second region The sidewall is a mask for ion doping the region of the second region for forming the first electrode of the TFET.

Finally removing the remaining sidewalls in the second region and the dummy gate structure in the first region, and forming gates respectively in the first region and the second region, for example, a high dielectric constant metal gate can be used A process forms a gate in the first region and in the second region, respectively.

The manufacturing method provided by the present application can fabricate a field effect device including a MOSFET and a TFET on a base substrate, and the field effect device incorporating the MOSFET and the TFET has better performance and lower power consumption.

Optionally, before the sidewalls of the dummy gate structure and the periphery of the spindle structure are respectively formed on the base substrate, the method may further include:

Using a lightly doped drain process, N-type ion doping is performed in a region of the first region for forming a source and a drain of the N-type MOSFET; a lightly doped drain process is used to form in the first region The source and drain regions of the P-type MOSFET are doped with P-type ions.

Optionally, the process of forming sidewalls around the dummy gate structure and the periphery of the spindle structure may specifically include:

First, a sidewall material of a predetermined thickness may be deposited on the surface of the substrate substrate on which the dummy gate structure and the spindle structure are formed by conformal deposition, and the sidewall material may be silicon nitride or amorphous silicon. Secondly, a photoresist is deposited on the surface of the base substrate on which the sidewall material is deposited; then the photoresist covering the first region is removed by using a sidewall mask, and the photoresist is applied according to a predetermined etching thickness. The sidewall material in the first region is anisotropically etched to thin the thickness of the sidewall material in the first region; finally, the photoresist covering the second region is removed, and the sidewall material is removed Sidewall etching is performed to form sidewalls around the dummy gate structure and around the spindle structure, respectively, and the sidewall thickness of the spindle structure is greater than the sidewall thickness of the dummy gate structure. The sidewall of the spindle structure can cover a region for forming a gate of the TFET, so as to block the gate region during subsequent ion doping, so that the ion doping can adopt a self-alignment process, thereby Reduce the difficulty of the process.

Optionally, when the first electrode is a drain and the second electrode is a source, using the sidewall as a mask, a region for forming a source and a drain of the MOSFET in the first region, and the The process of performing ion doping in the region of the second region for forming the second electrode of the TFET may specifically include:

First, a photoresist is deposited on a surface of a base substrate on which the sidewall is formed, and a first source/drain mask is used to remove a photoresist covering a region in the first region for forming an N-type MOSFET. And covering the photoresist in the region of the second region for forming the P-type TOSFET; and then using the sidewall and the remaining photoresist as a mask to form an N-type MOSFET in the first region A region of the source and the drain, and a region of the second region for forming a source of the P-type TFET are doped with N-type ions. The manner of ion doping may include: ion implantation, or etching the region to be doped and then filling the material doped with the corresponding ions.

Further, a photoresist is deposited again on the surface of the ion-doped substrate; and a second source/drain mask is used to remove the lithography in the region of the first region for forming the P-type MOSFET. a glue, and a photoresist covering a region in the second region for forming an N-type MOSFET; and then using the sidewall and the remaining photoresist as a mask to form a P-type in the first region A region of the source and the drain of the MOSFET, and a region of the second region for forming a source of the N-type TFET are subjected to P-type ion doping.

In the above ion doping process, since the sidewall can be utilized as a mask, the source and drain regions of the MOSFET and the region of the second electrode of the TFET can be ion doped by a self-aligned process, which reduces the The difficulty of the manufacturing process.

Optionally, the process of removing the sidewalls in the second area that are outside the target area may include:

Depositing a photoresist on the surface of the ion-doped substrate; then removing the mask by using a sidewall cutout mask The second region covers the photoresist outside the target region; finally, the sidewalls in the region of the second region not covered by the photoresist are etched and removed.

Optionally, the process of removing the spindle structure may include:

Performing an oxide filling and planarization process on the substrate, exposing the material for forming the spindle structure and the sidewall material; depositing a photoresist on a surface of the planarized substrate; and then using a spindle The mask is removed to remove the photoresist overlying the second region; the spindle structure is finally removed by the first solution. Wherein, when the spindle structure is formed by using polysilicon, the first solution may be a solution containing tetramethylammonium hydroxide or a solution containing ammonium hydroxide.

Optionally, when the first electrode is a drain and the second electrode is a source, the remaining sidewalls in the second region are used as a mask, and the first electrode for forming the TFET in the second region is used. The process of ion doping in the region may include:

Depositing a photoresist on a surface of the base substrate; then removing a photoresist covering a region in the second region for forming an N-type TFET by using a first drain mask; and finally utilizing remaining photolithography The glue and the remaining sidewalls in the second region are masks, and N-type ion doping is performed on the region of the second region for forming the drain of the N-type TFET.

Further, a photoresist is deposited again on the surface of the ion-doped substrate, and then a second drain mask is used to remove the lithography in the region of the second region for forming the P-type TFET. Finally, the P-type ion doping is performed on the region of the second region for forming the drain of the P-type TFET by using the remaining photoresist and the remaining sidewalls in the second region as a mask.

Due to the above-described process of ion doping the region for forming the first electrode of the TFET, the sidewall can also be used as a mask, so that the fabrication of the first electrode can also be accomplished by a self-aligned process.

Optionally, the process of removing remaining sidewalls in the second area may include:

Performing an oxide filling and planarization treatment on the base substrate to expose the sidewall material, wherein the oxide may be silicon dioxide; then depositing a photoresist on a surface of the planarized substrate; Then, the mask is removed by using the sidewall to remove the photoresist covering the second region; finally, the remaining sidewalls in the second region may be removed by the second solution. Wherein, when the sidewall material is silicon nitride, the second solution may be a phosphoric acid solution.

Optionally, the process of removing the dummy gate structure may include:

Depositing a photoresist on a surface of the substrate after removing the remaining sidewalls; then removing the mask in the first region by using a dummy gate removal mask; and finally removing the dummy by the first solution Gate structure.

Optionally, after the gate is formed in the first area and the second area, the method may further include:

A dielectric layer is formed on the base substrate on which the gate electrode is formed; contact holes leading to the gate region, the source region, and the drain region are respectively formed in the dielectric layer; and local interconnection of the metal connection lines is performed to complete metallization.

Optionally, the substrate provided by the present application may be covered with an oxide layer, such as an oxide layer formed of silicon dioxide. And forming a plurality of fin structures in the first region and the second region on the base substrate, the fin structure extending along a length direction of a channel of each field effect transistor, and two fin structures The terminals can be used to form the source and drain of the FET, respectively. In addition, a shallow trench isolation region may be formed between the formation regions of any two field effect transistors on the substrate.

In a second aspect, a field effect device is provided, which can be fabricated by the method provided by the first aspect; the field effect device can include: a MOSFET and a TFET.

In a third aspect, a chip is provided, the chip comprising: the field effect device provided by the second aspect.

The beneficial effects of the technical solution provided by the present application are:

In summary, the present application provides a field effect device, a manufacturing method thereof, and a chip, which can be Field effect devices including MOSFETs and TFETs are fabricated on a single substrate. Due to the better performance of the MOSFET and the lower power consumption of the TFET, the performance and power consumption of the field effect device incorporating the MOSFET and the TFET are balanced. When the chip is fabricated by using the field effect device, the power consumption of the chip can be further reduced under the premise of ensuring the performance of the chip.

DRAWINGS

1 is a flow chart of a method for fabricating a field effect device according to an embodiment of the present invention;

2A is a side view of a substrate according to an embodiment of the present invention;

2B is a top view of a substrate according to an embodiment of the present invention;

3A is a side view of a dummy gate structure and a spindle structure according to an embodiment of the present invention;

3B is a top view of a dummy gate structure and a spindle structure according to an embodiment of the present invention;

4A is a side view of an N-type ion doping by a light doping drain process according to an embodiment of the present invention;

4B is a top view of an N-type ion doping by a light doping drain process according to an embodiment of the present invention;

5A is a side view of a P-type ion doping by a light doping drain process according to an embodiment of the present invention;

FIG. 5B is a top view of a P-type ion doping by a light doping drain process according to an embodiment of the invention; FIG.

6A is a flow chart of a method for forming a sidewall according to an embodiment of the present invention;

6B is a side view of a deposition sidewall material according to an embodiment of the present invention;

6C is a top view of the photoresist in the first region after removing the photoresist in the first region;

FIG. 6D is a side view showing an isotropic etching of a sidewall material in a first region according to an embodiment of the present invention; FIG.

6E is a side view of a side wall material after sidewall etching according to an embodiment of the present invention;

6F is a top view of a sidewall material after sidewall etching according to an embodiment of the present invention;

7A is a region of a first region for forming a source and a drain of a MOSFET, and a region for forming a second electrode of the TFET in the second region for ion doping, according to an embodiment of the present invention. Method flow chart;

FIG. 7B is a view showing an area for forming a source and a drain of an N-type MOSFET in a first region, and an N-type region for forming a source of a P-type TFET in a second region according to an embodiment of the present invention. Side view of ion doping;

FIG. 7C is a view showing an area for forming a source and a drain of an N-type MOSFET in a first region, and an N-type region for forming a source of a P-type TFET in a second region according to an embodiment of the present invention. Top view of ion doping;

7D is a P-type region for forming a source and a drain of a P-type MOSFET in a first region and a source for forming an N-type TFET in a second region according to an embodiment of the present invention. Side view of ion doping;

7E is a P-type region for forming a source and a drain of a P-type MOSFET in a first region and a source for forming an N-type TFET in a second region according to an embodiment of the present invention. Top view of ion doping;

FIG. 8A is a side view of removing a sidewall of a second region located outside a target region according to an embodiment of the present invention; FIG.

FIG. 8B is a top view of removing a sidewall of a second region located outside a target region according to an embodiment of the present invention; FIG.

9A is a flowchart of a method for removing a spindle structure according to an embodiment of the present invention;

9B is a side view of a surface of a base substrate filled with an oxide according to an embodiment of the present invention;

9C is a side view showing a planarization process of a surface of a base substrate according to an embodiment of the present invention;

9D is a plan view showing a planarization process on a surface of a base substrate according to an embodiment of the present invention;

9E is a side view of the embodiment of the present invention after removing the spindle structure;

9F is a top view of the spindle structure after removing the spindle structure according to an embodiment of the present invention;

FIG. 10A is a flow chart showing ion doping of a region for forming a first electrode of a TFET in a second region according to an embodiment of the present invention; FIG.

FIG. 10B is a side view showing an N-type ion doping of a region for forming a drain of an N-type TFET in a second region according to an embodiment of the present invention; FIG.

FIG. 10C is a top plan view showing N-type ion doping of a region for forming a drain of an N-type TFET in a second region according to an embodiment of the present invention; FIG.

FIG. 10D is a side view showing P-type ion doping of a region for forming a drain of a P-type TFET in a second region according to an embodiment of the present invention; FIG.

FIG. 10E is a top view showing P-type ion doping of a region for forming a drain of a P-type TFET in a second region according to an embodiment of the present invention; FIG.

FIG. 11A is a flowchart of a method for removing remaining sidewalls in a second region according to an embodiment of the present invention; FIG.

FIG. 11B is a side view showing another surface-filled oxide on a surface of a substrate according to an embodiment of the present invention; FIG.

11C is a side view of another embodiment of the present invention after planarizing the surface of the substrate;

FIG. 11D is a plan view showing another surface of the substrate after planarization treatment according to an embodiment of the present invention; FIG.

FIG. 11E is a side view of the embodiment of the present invention after removing the remaining sidewalls in the second region; FIG.

FIG. 11F is a top view of the embodiment of the present invention after removing the remaining sidewalls in the second region; FIG.

12A is a flowchart of a method for removing a dummy gate structure according to an embodiment of the present invention;

12B is a side view of the embodiment of the present invention after removing a dummy gate structure;

12C is a top view of the embodiment of the present invention after removing the dummy gate structure;

FIG. 13A is a side view of the embodiment of the present invention after forming a gate; FIG.

FIG. 13B is a top view of a gate after forming an embodiment of the present invention; FIG.

14A is a side view of a field effect device according to an embodiment of the present invention;

14B is a top plan view of a field effect device according to an embodiment of the present invention.

detailed description

In order to make the objects, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

FIG. 1 is a flowchart of a method for manufacturing a field effect device according to an embodiment of the present invention. Referring to FIG. 1 , the method may specifically include:

Step 101, providing a substrate including a first region for forming a MOSFET and a second region for forming a TFET.

The base substrate may be made of a material such as silicon (Silicon, Si) or germanium (Geerium, Ge). 2A is a side view of a substrate according to an embodiment of the present invention, and FIG. 2B is a top view of a substrate according to an embodiment of the present invention. Referring to FIG. 2A and FIG. 2B, the substrate 00 may be included. A first region 01 for forming a MOSFET, and a second region 02 for forming a TFET. The first region 01 may be specifically divided into a region 011 for forming an N-type MOSFET and a region 012 for forming a P-type MOSFET; the second region 02 may be specifically divided into a region 021 for forming an N-type TFET and Used in the region 022 for forming a P-type TFET. Each of the regions can be used to form a plurality of FETs, and a shallow trench isolation (STI) region is disposed between the formation regions of any two FETs.

It can also be seen from FIG. 2A and FIG. 2B that a plurality of fin structures 03 are formed in the first region 01 and the second region 02 on the base substrate 00, and each fin structure 03 has a field effect. The channel of the tube extends in the length direction, and both ends of each fin structure 03 can be used to form a source and a drain of a field effect transistor, respectively.

Further, the surface of the base substrate 00 is further covered with an oxide layer 04, which may be formed of silicon dioxide (SiO ₂ ). The oxide layer 04 can serve as an etch stop layer and an interface protective layer for the base substrate.

It is to be noted that, for ease of understanding, FIG. 2A respectively shows a cross section of a region on the base substrate 00 for forming an N-type MOSFET, a P-type MOSFET, an N-type TFET, and a P-type TFET.

Step 102, forming a dummy gate structure and a spindle structure on the base substrate, the dummy gate structure covering a region for forming a gate in the first region, the spindle structure is a strip structure, and the spindle structure covers In the region of the second region for forming the first electrode.

In the embodiment of the present invention, the dummy gate structure and the spindle structure may be formed by a patterning process using a mask. The dummy gate structure and the spindle structure may both be formed of polysilicon. 3A is a side view of a dummy gate structure and a spindle structure according to an embodiment of the present invention, and FIG. 3B is a top view of a dummy gate structure and a spindle structure according to an embodiment of the present invention, and the spindle is combined with FIG. 3A and FIG. 3B. The structure 04 and the dummy gate structure 05 are both strip-shaped structures, and the longitudinal direction of the spindle structure 04 and the dummy gate structure 05 are perpendicular to the fin structure 03. The dummy gate structure 05 covers the region of the first region 01 for forming the gate electrode, and the spindle structure 04 covers the region of the second region 02 for forming the first electrode. The first electrode can be a source or a drain. As can be seen in conjunction with FIGS. 3A and 3B, the gate region for forming the N-type MOSFET in the first region 01 and the gate region for forming the P-type MOSFET are both covered with the dummy gate structure 05; The region for forming the first electrode of the N-type TFET and the region for forming the first electrode of the P-type TFET are covered with the spindle structure 04.

In addition, as can be seen from FIG. 3A, silicon nitride (SiN) is deposited on the side of the upper surface of the main spindle structure 04 and the dummy gate structure 05 (ie, away from the substrate 00), and the SiN is formed into a spindle structure 04. And a hard mask material used in the dummy gate structure 05.

Step 103: Perform ion doping in a region for forming a source and a drain in the first region by using a lightly doped drain process.

Referring to FIGS. 4A and 4B, a lightly doped drain (LDD) process in which a region 01a for forming a source and a drain of an N-type MOSFET is used for N-type ion doping may be employed. . For example, the surface of the base substrate 00 may be covered with a photoresist, and then the photoresist covering the region 011 for forming the N-type MOSFET may be removed by a mask, and finally, the photoresist may be covered. The region enters an N-type ion (eg, arsenic ion) doping.

Further, referring to FIG. 5A and FIG. 5B, a light doping drain process may be employed in which a region 01b for forming a source and a drain of a P-type MOSFET is subjected to P-type ion doping. The process of P-type ion doping is similar to the process of N-type ion doping, and will not be described again here.

It should be noted that the specific manner of the ion doping may be ion implantation directly using an ion implanter, or the region to be doped may be etched and then filled with a material doped with a corresponding ion. Further, the order of execution of the step of N-type ion doping and the step of P-type ion doping may be interchanged.

After the ion doping is completed, it is necessary to peel off the remaining photoresist on the surface of the substrate.

Step 104, forming sidewalls on the substrate substrate around the dummy gate structure and around the spindle structure.

Wherein a portion of the sidewall of the spindle structure covers a region of the second region for forming a gate, the portion of the portion The wall is used to occlude the gate region during subsequent ion doping.

In the embodiment of the present invention, FIG. 6A is a flowchart of a method for forming a sidewall according to an embodiment of the present invention. Referring to FIG. 6A, the process for forming a sidewall may specifically include:

Step 1041: depositing a sidewall material of a predetermined thickness on a surface of the base substrate on which the dummy gate structure and the spindle structure are formed by conformal deposition.

The sidewall material may include silicon nitride or amorphous silicon or the like. A uniform thickness of sidewall material may be deposited on the surface of the substrate by conformal coating. The optional range of the predetermined thickness may be 50 nm to 200 nm; the base substrate on which the sidewall material is deposited may be as shown in FIG. 6B.

Step 1042, depositing a photoresist on a surface of the base substrate on which the sidewall material is deposited.

Step 1043: remove the photoresist covered in the first region by using a sidewall mask, and perform isotropic etching on the sidewall material in the first region according to a predetermined etching thickness.

Referring to FIG. 6C, the opening region of the sidewall mask may be aligned with the first region, and the photoresist performed on the first region may be exposed and developed to remove light covering the first region. Engraved. Thereafter, the sidewall material of the region not covered by the photoresist may be anisotropically etched according to a predetermined etching thickness to make the thickness of the sidewall material in the first region thin. Wherein, the etching thickness can be set according to the thickness of the deposited sidewall material, and generally needs to be greater than one-half of the thickness of the sidewall material. By way of example, if the thickness of the deposited sidewall material ranges from 50 nanometers to 200 nanometers, the corresponding etch thickness can range from 30 nanometers to 150 nanometers.

In addition, it should be noted that the isotropic etching refers to etching the sidewall materials of the surface of the substrate substrate in the horizontal direction and the vertical direction at the same etching rate to ensure the horizontal direction and the vertical direction. The etching thickness of the direction is the same.

As shown in FIG. 6D, after isotropic etching, the thickness of the sidewall material of the first region 01 is thinner than the thickness of the sidewall material in the second region 02.

Step 1044, removing the photoresist covered in the second region.

Step 1045, performing sidewall etching on the sidewall material such that sidewalls of the dummy gate structure and the periphery of the spindle structure respectively form sidewalls, and sidewall thickness of the spindle structure is greater than sidewall thickness of the dummy gate structure.

Further, referring to FIG. 6E and FIG. 6F, the sidewall material may be sidewall etched for sidewall etching by using an anisotropic etching method. The non-isotropic etching refers to etching the sidewall material in a vertical direction and a horizontal direction according to different etching rates. When the sidewall etching is performed by using the anisotropic etching method, it is necessary to ensure that the etching rate in the vertical direction is much larger than the etching rate in the horizontal direction. For example, the ratio of the etching rate in the vertical direction and the horizontal direction may be It is 20:1. Thereby, the side wall 051 can be formed around the dummy gate structure 05, and the side wall 041 can be formed around the spindle structure 04. Moreover, since the thickness of the sidewall material in the first region 01 is thin, and the thickness of the sidewall 041 of the spindle structure 04 is greater than the thickness of the sidewall 051 of the dummy gate structure 05.

Since the size of the gate of the TFET is larger than the size of the gate of the MOSFET, and the sidewall 041 around the spindle structure 04 is used to cover the gate region of the TFET, the thickness of the sidewall 041 around the spindle structure 04 is required. Thicker.

Step 105: using the sidewall as a mask, performing ion doping on a region of the first region for forming a source and a drain of the MOSFET, and a region of the second region for forming a second electrode of the TFET .

When the first electrode is a drain, the second electrode is a source; when the first electrode is a source, the second electrode is a drain. In the embodiment of the present invention, the first electrode is a drain, and the second electrode is a source. The specific implementation process of the step 105 is described in detail. Referring to FIG. 7A, the process may specifically include:

Step 1051, depositing a photoresist on a surface of the base substrate on which the sidewall is formed.

Step 1052: using a first source/drain mask to remove a photoresist covering a region in the first region for forming an N-type MOSFET, and covering a region in the second region for forming a P-type TFET The photoresist inside.

Referring to FIGS. 7B and 7C, an opening region of the first source-drain mask may be aligned with a region 011 for forming an N-type MOSFET in the first region and a region 022 for forming a P-type MOSFET in the second region. After exposure and development, the photoresist in the two

regions

011 and 022 can be removed.

Step 1053, using the sidewall and the remaining photoresist as a mask, a region for forming a source and a drain of the N-type MOSFET in the first region, and a P-type TFET for forming the second region. The source region is doped with N-type ions.

Further, referring to FIG. 7B and FIG. 7C, the remaining photoresist and the sidewalls of the two

regions

011 and 022 can be utilized as a mask for forming a source of the N-type MOSFET in the first region. The region 01a of the drain and the region 02a of the source for forming the P-type TFET in the second region are N-type ion doped. Similarly, the ion doping may be ion implantation, or the region to be doped may be etched, and then a layer of phosphorus silicon (SiP) is deposited in the etched cavity.

As can be seen from FIGS. 7B and 7C, since the sidewall 041 of the spindle structure 04 is thicker, covering the region for forming the gate of the P-type TFET, the spindle structure 04 covers the formation for forming. The region of the drain of the P-type TFET, therefore, the two

regions

011 and 022 can be ion doped by a self-aligned process, which effectively reduces the process difficulty.

Step 1054, depositing a photoresist again on the surface of the ion-doped substrate.

Step 1055, using a second source/drain mask to remove the photoresist covering the region in the first region for forming the P-type MOSFET, and covering the region for forming the N-type MOSFET in the second region. The photoresist inside.

Referring to FIGS. 7D and 7E, an opening region of the second source/drain mask may be aligned with a region 012 for forming a P-type MOSFET in the first region and a region 021 for forming an N-type MOSFET in the second region. After exposure and development, the photoresist in the two

regions

012 and 021 can be removed.

Step 1056, using the sidewall and the remaining photoresist as a mask, a region for forming a source and a drain of the P-type MOSFET in the first region, and a N-type TFET for forming the second region. The source region is doped with P-type ions.

Further, referring to FIG. 7D and FIG. 7E, the remaining photoresist and the sidewalls of the two

regions

012 and 021 can be used as a mask to form a source of the P-type MOSFET in the first region. A region 01b of the drain and a region 02b for forming a source of the N-type TFET in the second region are subjected to P-type ion doping. Similarly, the ion doping may be ion implantation, or etching the region to be doped, and then depositing a boron-containing silicon germanium (SiGe) in the etched cavity. Moreover, the P-type ion doping process can also be performed using a self-aligned process.

Finally, after the ion doping is completed, it is necessary to peel off the remaining photoresist on the surface of the substrate. Through the above steps, the fabrication of the source and drain of the MOSFET and the fabrication of the source of the TFET are completed. To further form the drain of the TFET, it is necessary to first remove the sidewall material and the spindle structure overlying the area used to form the drain of the TFET.

In addition, it should be noted that the

above steps

1055 and 1056 may also be performed before step 1052.

Step 106: Removing a sidewall in the second region that is outside the target region, the target region including a region in the second region for forming a gate.

Specifically, referring to FIG. 8A and FIG. 8B, a photoresist may be deposited on the surface of the ion-doped substrate, and then the sidewall is removed by using a sidewall to remove the second region 02 covering the target region. Photoresist outside; last The sidewall 041 in the region of the second region 02 where the photoresist is not covered is etched away so that a portion of the spindle structure 04 is exposed in the uncovered region of the photoresist.

It should be noted that, referring to FIG. 8B, since the opening of the sidewall cutout mask cannot accurately align the boundary between the target region and the non-target region (that is, the boundary line between the gate region and the drain region), In order to avoid accidental removal of the sidewalls overlying the gate region, the opening of the sidewall cutout mask is typically offset toward the drain region. Therefore, after the sidewall of the region not covered by the photoresist is etched and removed, as shown in FIG. 8B, a sidewall spacer 042 is left at both ends of the spindle structure 04.

Step 107, removing the spindle structure.

After removing the sidewall covering the drain region in the second region, the spindle structure in the second region can be further removed. Referring to FIG. 9A, the process of removing the spindle structure may specifically include:

Step 1071, performing an oxide filling and planarization treatment on the base substrate to expose the material for forming the spindle structure and the sidewall material.

Referring to FIG. 9B, oxide filling, for example, filling of silicon dioxide, may be performed on the surface of the base substrate 00. Then, as shown in FIG. 9C and FIG. 9D, the surface of the base substrate 00 is planarized by a planarization process such as etching and chemical mechanical polishing, so that the materials for forming the spindle structure 04 and the dummy gate 05 are And sidewall material exposure for forming the

sidewalls

041 and 051.

Step 1072: depositing a photoresist on the surface of the planarized substrate.

Step 1073: remove the mask covered by the spindle to remove the photoresist covered in the second region.

Referring to FIGS. 9E and 9F, the open area of the spindle removal mask can be aligned with the second area 02, and the photoresist in the second area 02 can be removed by exposure and development.

Step 1074, removing the spindle structure by the first solution.

Finally, the spindle structure can be removed using a solution that dissolves the spindle structure. For example, when the spindle structure is made of polysilicon, the first solution may be a tetramethylammonium hydroxide solution or an ammonium hydroxide solution.

Step 108: Perform ion doping on a region of the second region for forming a first electrode of the TFET by using a remaining sidewall in the second region as a mask.

In the embodiment of the present invention, the first electrode is a drain, and the second electrode is a source. The specific implementation process of the step 108 is described in detail. Referring to FIG. 10A, the process may specifically include:

Step 1081: depositing a photoresist on a surface of the base substrate.

Step 1082: using a first drain mask to remove photoresist in a region of the second region for forming an N-type TFET.

Referring to FIG. 10B and FIG. 10C, the opening region of the first drain mask may be aligned with the region 021 for forming an N-type TFET in the second region. After exposure and development, the region 021 may be removed. Photoresist.

Step 1083, using the remaining photoresist and the remaining sidewalls in the second region as a mask, performing N-type ion doping on the region of the second region for forming the drain of the N-type TFET.

Further, referring to FIG. 10B and FIG. 10C, the remaining photoresist, and the sidewall 041 in the region 021 for forming the N-type TFET in the second region, and the oxide in the region 021 can be used as a mask. N-type ion doping is performed on the region 02c for forming the drain of the N-type TFET in the second region. Similarly, the ion doping may be ion implantation, or the region to be doped may be etched, and then a layer of phosphorus silicon is deposited in the etched cavity.

Step 1084, depositing a photoresist again on the surface of the ion-doped substrate.

Step 1085, using a second drain mask to remove photoresist in a region of the second region for forming a P-type TFET.

Referring to FIGS. 10D and 10E, the opening region of the second drain mask may be aligned with the region 022 of the second region for forming a P-type TFET. After exposure and development, the region 022 may be removed. Photoresist.

Step 1086: P-type ion doping is performed on the region of the second region for forming the drain of the P-type TFET by using the remaining photoresist and the remaining sidewalls in the second region as a mask.

Further, referring to FIG. 10D and FIG. 10E, the remaining photoresist, and the sidewall 041 in the region 022 of the second region for forming the P-type TFET, and the oxide in the region 022 can be utilized as a mask. P-type ion doping is performed on the region 02d for forming the drain of the P-type TFET in the second region. Similarly, the ion doping may be ion implantation, or the region to be doped may be etched, and then a layer of germanium is deposited in the etched cavity.

After the ion doping is completed, the photoresist on the surface of the base substrate 00 is removed. Thereby, the fabrication of the drain of the TFET in the second region can be completed.

It should be noted that the

above steps

1085 and 1086 may also be performed before step 1082.

Step 109, removing the remaining sidewalls in the second region.

Referring to FIG. 11A, the process of removing the remaining sidewalls in the second area may specifically include:

Step 1091, performing an oxide filling and planarization treatment on the base substrate to expose the sidewall material.

Referring to FIG. 11B, oxide filling, for example, filling of silicon dioxide, may be performed on the surface of the base substrate 00. Then, as shown in FIGS. 11C and 11D, the surface of the base substrate 00 is planarized by a planarization process such as etching and chemical mechanical polishing, so that the sidewall materials for forming the

sidewalls

041 and 051 are And dummy gate material exposure for forming the dummy gate structure 05.

Step 1092, depositing a photoresist on a surface of the planarized substrate.

Step 1093, using a sidewall removal mask to remove the photoresist covering the second region.

Referring to FIGS. 11E and 11F, the open area of the sidewall removal mask can be aligned with the second region 02, and the photoresist in the second region 02 can be removed by exposure and development.

Step 1094, removing the remaining sidewalls in the second region by the second solution.

Finally, the remaining sidewalls can be removed using a solution that is capable of dissolving the sidewall material. For example, when the sidewall material is silicon nitride, the second solution may be a phosphoric acid solution.

Step 110, removing the dummy gate structure.

Referring to FIG. 12A, the process of removing the dummy gate structure may specifically include:

Step 1101, depositing a photoresist on a surface of the base substrate after removing the remaining sidewalls.

Step 1102: Removing the mask by using a dummy gate to remove the photoresist covered in the first region.

Referring to FIG. 12B and FIG. 12C, the open area of the dummy gate removal mask may be aligned with the first area 01, and after the photoresist of the first area 01 is exposed and developed, the cover may be removed. The photoresist in the first region 01.

Step 1103, removing the dummy gate structure by the first solution.

Further, the dummy gate structure may be removed by using a solution capable of dissolving the dummy gate structure. For example, when the dummy gate structure is made of polysilicon, the first solution may be a tetramethylammonium hydroxide solution or an ammonium hydroxide solution. Finally, the photoresist remaining on the surface of the base substrate can be removed.

Step 111: Form a gate in the first region and the second region, respectively.

Further, referring to FIG. 13A and FIG. 13B, a gate 061 and a P-type MOSFET of the N-type MOSFET may be formed in the first region 01 by using a high-k metal gate (HKMG) process, respectively. a gate 062; and a gate 071 of the N-type TFET and a gate 072 of the P-type TFET are formed in the second region 02.

For a specific step of forming a gate by the HKMG process, reference may be made to the related art, which is not described in detail in the embodiment of the present invention.

Further, in the embodiment of the present invention, after the gate is formed on the substrate 00, a dielectric layer may be formed on the substrate formed with the gate, and a gate region is formed in the dielectric layer, Contact holes of the source region and the drain region; local interconnection of metal connection lines is performed to complete metallization of the contact holes. The resulting field effect device can be as shown in Figures 14A and 14B. As can be seen from FIG. 14A and FIG. 14B, the field effect device is integrated with both MOSFET and TFET FETs. It can also be seen from FIG. 14B that the first region 01 includes a plurality of N-type MOSFETs and a plurality of P-type MOSFETs, and the second region 02 includes a plurality of N-type TFETs and a plurality of P-type TFETs.

It should be noted that the sequence of the steps of the method for manufacturing the field effect device according to the embodiment of the present invention may be appropriately adjusted, and the step may also be correspondingly increased or decreased according to the situation. For example, step 110 may be performed before step 109. Any method that can be easily conceived by those skilled in the art within the technical scope of the present application is intended to be included in the scope of the present application and therefore will not be described again.

In summary, the embodiments of the present invention provide a method for fabricating a field effect device, which can fabricate a field effect device including a MOSFET and a TFET on a substrate, which integrates field effects of the MOSFET and the TFET. The device performs better and consumes less power.

The embodiment of the present invention further provides a field effect device. Referring to FIG. 14A and FIG. 14B, the field effect device may include two types of field effect transistors: MOSFET and TFET.

The field effect device can be specifically formed by the method shown in FIG. 1, and the process shown in FIG. 6A, FIG. 7A, FIG. 9A, FIG. 10A, FIG. 11A and FIG. 12A can also be used in the manufacturing process of the field effect device. Process.

The embodiment of the invention further provides a chip, which may include: the field effect device shown in FIG. 14A and FIG. 14B. Since the field effect device used in the chip integrates both MOSFET and TFET type FETs, the power consumption of the chip can be further reduced while ensuring the performance of the chip.

The above description is only an optional embodiment of the present application, and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the protection of the present application. Within the scope.

Claims

A method of fabricating a field effect device, the method comprising:

Providing a base substrate including a first region for forming a metal oxide semiconductor field effect transistor MOSFET, and a second region for forming a tunneling field effect transistor TFET;

Forming a dummy gate structure over a surface of the first region for forming a gate on the base substrate, the spindle structure being a strip structure, and the spindle a structure covering the region in the second region for forming the first electrode;

Forming sidewalls around the dummy gate structure and around the spindle structure on the base substrate, wherein a portion of the sidewall of the spindle structure covers a region in the second region for forming a gate on;

Using the sidewall as a mask, performing ion doping on a region of the first region for forming a source and a drain of the MOSFET, and a region of the second region for forming a second electrode of the TFET The first electrode is a drain, the second electrode is a source, or the first electrode is a source, and the second electrode is a drain;

Removing a sidewall of the second region that is outside the target region, the target region including a region of the second region for forming a gate;

Removing the spindle structure;

Ion doping the region of the second region for forming the first electrode of the TFET by using the remaining sidewalls in the second region as a mask;

Removing the remaining sidewalls in the second region;

Removing the dummy gate structure;

Gates are formed in the first region and in the second region, respectively.
The method according to claim 1, wherein the sidewalls of the dummy gate structure and the periphery of the spindle structure are respectively formed on the base substrate, and the method comprises:

Depositing a sidewall material of a predetermined thickness on a surface of the base substrate on which the dummy gate structure and the spindle structure are formed by conformal deposition;

Depositing a photoresist on a surface of the base substrate on which the sidewall material is deposited;

Removing the photoresist covered in the first region by using a sidewall mask, and performing isotropic etching on the sidewall material in the first region according to a preset etching thickness;

Removing the photoresist covered in the second region;

Performing sidewall etching on the sidewall material such that sidewalls of the dummy gate structure and the periphery of the spindle structure respectively form sidewalls, and sidewall thickness of the spindle structure is greater than sidewalls of the dummy gate structure thickness.
The method according to claim 1, wherein the first electrode is a drain, the second electrode is a source, and the sidewall is used as a mask, and is used in the first region. The ion doping is performed on a region forming a source and a drain of the MOSFET, and a region in the second region for forming a second electrode of the TFET, including:

Depositing a photoresist on a surface of the base substrate on which the sidewall is formed;

Using a first source drain mask to remove photoresist in a region of the first region for forming an N-type MOSFET, and covering a region in the second region for forming a P-type TOSFET Photoresist

Using the sidewall and the remaining photoresist as a mask, a region for forming a source and a drain of the N-type MOSFET in the first region, and a P-type TFET for forming the second region The source region is doped with N-type ions;

Re-depositing the photoresist on the surface of the ion-doped substrate;

Using a second source/drain mask to remove photoresist in a region of the first region for forming a P-type MOSFET, and covering an area in the second region for forming an N-type MOSFET Photoresist

Using the sidewall and the remaining photoresist as a mask, a region for forming a source and a drain of the P-type MOSFET in the first region, and a N-type TFET for forming the second region The source region is doped with P-type ions.
The method according to claim 1, wherein the removing the sidewalls of the second region that are outside the target region comprises:

Depositing a photoresist on a surface of the ion-doped substrate;

Removing a photoresist covering the target region from the second region by using a sidewall cutout mask;

The sidewalls in the region of the second region that are not covered by the photoresist are etched away.
The method of claim 1 wherein said removing said spindle structure comprises:

Performing an oxide filling and planarization treatment on the base substrate such that a material for forming the spindle structure and the sidewall material are exposed;

Depositing a photoresist on a surface of the planarized substrate;

Removing the mask by using a spindle to remove the photoresist covering the second region;

The spindle structure is removed by a first solution.
The method according to claim 1, wherein the first electrode is a drain, the second electrode is a source, and the remaining sidewalls in the second region are used as a mask, The region of the second region for forming the first electrode of the TFET is ion doped, including:

Depositing a photoresist on a surface of the base substrate;

Using a first drain mask to remove photoresist in a region of the second region for forming an N-type TFET;

Performing N-type ion doping on a region of the second region for forming a drain of the N-type TFET by using a remaining photoresist and remaining sidewalls in the second region as a mask;

Re-depositing the photoresist on the surface of the ion-doped substrate;

Using a second drain mask to remove photoresist in a region of the second region for forming a P-type TFET;

P-type ion doping is performed on a region of the second region for forming a drain of the P-type TFET using the remaining photoresist and the remaining sidewalls in the second region as a mask.
The method according to claim 1, wherein the removing the remaining sidewalls in the second region comprises:

Performing an oxide filling and planarization treatment on the base substrate to expose the sidewall material;

Depositing a photoresist on a surface of the planarized substrate;

Removing the mask from the second region by using a sidewall removal mask;

The remaining sidewalls in the second region are removed by a second solution.
The method of claim 1 wherein said removing said dummy gate structure comprises:

Depositing a photoresist on a surface of the substrate after removing the remaining sidewalls;

Removing the mask by using a dummy gate to remove the photoresist covering the first region;

The dummy gate structure is removed by a first solution.
The method according to claim 1, wherein the forming the gates in the first region and the second region respectively comprises:

A gate is formed in the first region and in the second region, respectively, using a high dielectric constant metal gate process.
The method according to any one of claims 1 to 9, wherein before the sidewalls of the dummy gate structure and the periphery of the spindle structure are respectively formed on the base substrate, the method further comprises:

Using a lightly doped drain process, N-type ion doping is performed in a region of the first region for forming a source and a drain of the N-type MOSFET;

A P-type ion doping is performed in a region of the first region for forming a source and a drain of the P-type MOSFET using a lightly doped drain process.
The method according to any one of claims 1 to 9, wherein after the gate is formed in the first region and in the second region, the method further comprises:

Forming a dielectric layer on the base substrate on which the gate is formed;

Forming contact holes to the gate region, the source region, and the drain region, respectively, in the dielectric layer;

Localizing the metal vias to complete the metallization of the contact holes.
A method according to any one of claims 1 to 9, wherein

The substrate substrate is provided with an oxide layer, and a plurality of fin structures are respectively formed in the first region and the second region on the substrate.
The method according to any one of claims 1 to 9, wherein the manner of ion doping comprises:

Ion implantation, or etching the region to be doped, is followed by filling with a material doped with the corresponding ions.
Field effect device characterized in that the field effect device is manufactured by the method according to any one of claims 1 to 13;

The field effect device includes: a metal oxide semiconductor field effect transistor MOSFET and a tunneling field effect transistor TFET.
A chip, characterized in that the chip comprises:

The field effect device of claim 14.