WO2018193405A1

WO2018193405A1 - Phase angle tunable fractional-order capacitors including poly (vinylidene fluoride)-based polymers and blends and methods of manufacture thereof

Info

Publication number: WO2018193405A1
Application number: PCT/IB2018/052737
Authority: WO
Inventors: Khaled Nabil Salama; Agamyrat AGAMBAYEV; Shashikant Patole; Hakan BAGCI; Mohamed Farhat
Original assignee: Sabic Global Technologies, B.V.
Priority date: 2017-04-19
Filing date: 2018-04-19
Publication date: 2018-10-25

Abstract

Fractional-order capacitors are fabricated from components including metallic and dielectric layers, the combination of which produces a desired operation of the fractional-order capacitor. The fractional-order capacitors discussed herein are fabricated to tune the constant phase angle using one or more components of the structure. The dielectric layers employed in the fractional-order capacitors may be formed from a single ferroelectric poly(vinylidene fluoride (P(VDF))-based material, or may be formed as a blend or two or more of those materials in a predetermined ratio based on a desired for a targeted constant phase angle.

Description

PHASE ANGLE TUNABLE FRACTIONAL-ORDER CAPACITORS INCLUDING POLY (VINYLIDENE FLUORIDE)-BASED POLYMERS AND BLENDS AND METHODS OF

MANUFACTURE THEREOF

BACKGROUND

[0001] Fractional order capacitors (FOC) have impedance Ζ(ω) = ^-_ω^_α where

C is a constant that represents a pseudo-capacitance, ω represents an angular frequency (ω = 2π/), and a is a number in the range 0 < a < 1. Conventional capacitors have an a-value that is approximately 1 . Such conventional capacitors may be referred to as "integer order" capacitors. It is understood, notwithstanding, that such conventional capacitors commonly exhibit an a-value of less than 1 , but even low- quality conventional capacitors commonly exhibit an a-value > 0.95. As such, conventional capacitors are often modeled as ideal integer order devices. The a-value of a capacitor may be sensitive to an operating frequency. Said in other words, FOCs may exhibit an a-value of approximately integer order, except in a predefined frequency band.

[0002] FOCs have applications in a variety of different fields that may be said to provide solutions to fractional order calculus problems. Some of these applications include solving nonlinear problems in such real-world domains as pattern recognition, automated control, signal processing, and modeling various processes. As one specific example, FOCs have application in proportional-integral-differential (PID) controllers. While fractional order calculus and FOCs have been studied theoretically, in practice it has been difficult to realize practical FOCs. Previous FOC realization approaches have involved liquid-electrode based (LEB) type FOCs, fractal-type (FT) FOCs, and ladder network approximation FOCs composed of conventional resistors and capacitors (e.g., integer order capacitors). These previous FOC realization techniques have suffered from one or more significant drawbacks. One commonly encountered significant drawback of previous techniques of realizing FOCs has been undesirable restriction on the operational frequency range of FOC behavior and/or undesirable ripple in the a - value of the FOC over the operational frequency range.

SUMMARY

[0003] In an embodiment, a fractional-order capacitor comprising: a first metallic layer formed on a S1O2 layer; and a dielectric layer formed on the first metallic layer, wherein the dielectric layer comprises at least one of ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF- TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP"). In an embodiment, the fractional-order capacitor further comprises a second metallic layer formed on the dielectric layer.

[0004] In an alternate embodiment, a fractional-order capacitor comprising: a substrate; an S1O2 layer formed on the substrate; a metallic layer formed on the S1O2 layer; and a dielectric layer formed on the metallic layer, wherein the dielectric layer comprises at least two of ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE- CFE) ("TP").

[0005] In an embodiment, a method of fabricating a fractional-order capacitor, comprising: forming a first metallic layer on an S1O2 layer; forming a dielectric layer on the first metallic layer, wherein the dielectric layer comprises forming a blend of a solvent and at least two of: ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE- CFE) ("TP"). In an embodiment, the method further comprises forming a second metallic layer on the dielectric layer.

[0006] These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0008] FIGS. 1A-1 F are partial schematic cross-sections of a plurality of fractional order capacitor (FOC) designs comprising a polymer blend dielectric layer fabricated according to certain embodiments of the disclosure.

[0009] FIGS. 2A-2F are schematic illustrations of arrays used in fractional order capacitors (FOC) comprising polymer blend dielectric layer fabricated according to certain embodiments of the disclosure.

[0010] FIG. 3 illustrates an embodiment of a method of fabricating a fractional order capacitor (FOC) comprising a polymer blend dielectric layer fabricated according to certain embodiments of the disclosure. [0011] FIGS. 4A and 4B are graphs of the phase angle, φ, and the impedance, Z of the individual capacitors fabricated according to certain embodiments of the present disclosure.

[0012] FIGS. 5A-5F shows the measured phase angle, φ, and the measured impedance, Z, for P-TP, P-CP and P-TP blends in the constant phase zone (CPZ) according to certain embodiments of the present disclosure.

[0013] FIGS. 6A-6C are graphs of the constant phase angle (CPA) v. the composition of the polymer blend used for the dielectric layer according to certain embodiments of the present disclosure.

[0014] FIGS. 7A and 7B are graphs of Fourier Transform Infrared Spectroscopy (FTIR) (FIG. 7A) and x-ray diffraction (XRD) (FIG. 7B) studies of P-TP blends according to certain embodiments of the present disclosure.

[0015] FIGS. 8A and 8B are schematic illustrations of polymers and polymer blends fabricated and employed in FOCs according to embodiments of the present disclosure.

DETAILED DESCRIPTION

[0016] It should be understood at the outset that although illustrative implementations of one or more embodiments are illustrated below, the disclosed systems and methods may be implemented using any number of techniques, whether currently known or not yet in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0017] Fractional order capacitors (FOC) may be employed to accurately model the physical behavior of nature and to provide at least one additional degree of freedom in the design of advanced electrical systems, which is not possible using conventionally employed ideal circuit elements. For instance, to build an oscillator with a high order (>2) and with a desired frequency, the FOCs employed may each have different constant phase angles (CPAs). Currently employed technology has multiple challenges such as that it lacks portability and may use power at an undesirable rate. Additionally, currently-employed FOC designs may have other disadvantages such as (1 ) a lack of PCB (printed circuit board) compatibility, e.g., the difficulty of integration of designed fractional order capacitors to the electrical circuit; (2) difficulty controlling tunability in a constant phase angle during design and resultant fabrication; (3) the phase angle ripple and excessive (undesirable) variation in the constant phase angle; and (4) difficulty in low-cost, commercially-viable production.

[0018] Currently employed materials used in FOCs may be oxides and/or silicates with filler materials. In contrast, the FOCs discussed herein can be designed and fabricated with a tuned (targeted) CPA using ferroelectric polymers. For example, using the combinations of layered ferroelectric polymers including but not limited to poly(vinylidene fluoride)-based materials such as P(VDF) (hereinafter "P"), P(VDF-CFE) (hereinafter "TP") and P(VDF-CFE-TrFE) (hereafter "CP"). Thus, the dielectric layers discussed herein that comprise interlayer structures of poly(vinylidene fluoride)-based materials are employed to design and fabricate FOCs with targeted properties, including a target (tuned) CPA. The terms "targeted" and "tuned" as well as variations thereof may be employed herein to mean a property value or a range of property values that are desired from an FOC such that the FOC contains elements including the dielectric layer that are designed to produce a property value, e.g., a CPA, of a particular number or within a desired range.

[0019] Electrical circuit elements can be classified as either a passive or active element. Inductors, resistors, and capacitors are ubiquitous passive circuit elements whose cyclic frequency-dependent (ω) impedance (Z) can be given as follows:

Ζ(ω) = A(jo)-^a (1 )

where A is a coefficient, / represents the imaginary unit, and a is the exponent of the element which is a constant that determines the phase angle of impedance, Z, and ω represents an angular frequency (ω = 2π/), In the ideal case, a takes one of the following values: -1 (pure inductor), 0 (pure resistor), or 1 (pure capacitor). However, if a takes non-integer values, then the element is called a fractional-order element, an additional circuit element with the phase angle as shown in equation (2) below:

. , χπ

Φ = ±— (2)

[0020] The concept of a fractional-order element gives an additional degree of freedom in modeling, characterizing, and implementing novel circuit components in a wide spectrum of disciplines: viz. energy-storage and energy-generation devices, neural-system modeling, neurovascular coupling model, characterizing bio-impedance, control-system design, heat diffusion control, electromagnetics, and advanced electronics. [0021] Currently employed materials used in FOCs may be oxides and/or silicates with filler materials. In contrast, the FOCs discussed herein can be designed and fabricated with a tuned (targeted) CPA using ferroelectric polymers. For example, using the combinations of layered ferroelectric polymers including but not limited to poly(vinylidene fluoride)-based materials such as P(VDF) (hereinafter "P"), P(VDF-CFE) (hereinafter "CP") and P(VDF-CFE-TrFE) (hereafter "TP"). Thus, the dielectric layers discussed herein that comprise interlayer structures of poly(vinylidene fluoride)-based materials are employed to design and fabricate FOCs with targeted properties, including a target (tuned) CPA. The terms "targeted" and "tuned" as well as variations thereof may be employed herein to mean a property value or a range of property values that are desired from an FOC such that the FOC contains elements including the dielectric layer that are designed to produce a property value, e.g., a CPA, of a particular number or within a desired range.

[0022] In particular, a fractional-order element with 0<α<1 (-90°<φ<0°) is called a fractional-order capacitor (FOC). An FOC facilitates circuit configurations that would be impractical or impossible to implement with conventional capacitors. For example, replacing an integer-order capacitor with an FOC in a temperature controller virtually eliminates the overshoot and windup effect due to the time spent in actuator saturation and drastically reduces the time required to stabilize the temperature. In general, it is highly desirable to have an FOC that is dielectric-based and printed-circuit-board (PCB) compatible, and that could operate over wide frequency bands with a constant phase angle (CPA) that may be tuned during design by adjusting design parameters such as volume fractions of dielectric materials and/or ratios of thickness of different layers of dielectric materials, and minimum-phase-angle ripples. The structures herein may be said to be "electrically coupled" to PCB boards. When two or more components are said to be "electrically coupled," this may mean that a completed circuit is formed by the assembly of the two or more components.

[0023] Realizations of FOCs may be classified into five categories: 1 ) liquid electrode-based (LEB) FOCs, 2) geometry-related fractal (FT) FOCs, 3) resistor- capacitor (RC) ladders FOCs, 4) CMOS-based emulator FOCs, and 5) composite FOCs. LEB FOCs are constructed by dipping capacitive, parallel-plate electrodes coated with a porous film of polymers into an ionic medium. The operating principle of LEB FOCs is anomalous diffusion of ions through a porous surface at the electrode- electrolyte interface. The CPA is based on the depth of immersion of the electrodes into the ionic medium, the thickness of the polymer film, and the conductivity of the ionic medium. The large dimension, lack of portability and liquid ionic medium prevent the LEB FOC's integration in microelectronic circuits. FT FOCs use fractal structures created with metal traces onto silicon wafers, which makes FT FOCs integrate-able with microelectronic circuits.

[0024] The CPA of a circuit comprising an FT FOC depends on the fractal shape and number of iterations. RC ladder FOCs may be fabricated using a combination of different value resistors and capacitors to approximate the term, (ίω)^_α, in Equation (1 ) with non-integer-order transfer functions. Disadvantages of using network approximations may be that a designer needs a large number of components to obtain the fractional behavior accurately, the design may call for elements with impractical values (e.g., 1 farad capacitors, 1 ohm resistors), and the frequency band may be narrower than desirable for the end applications. CMOS-based emulator FOCs may use a differentiator and a voltage-to-current converter for emulation of the constant phase element. CMOS-based emulator FOCs may employ an operational transconductance amplifier and grounded capacitors for tuning the equivalent CPA, and may use external power for operation. Furthermore, for at least some of the previously employed, the FOC is obtained by the resultant circuit impedance rather than by a physical capacitor. It is important to mention that none of the above offer a FOC that is dielectric based and printed-circuit-board (PCB) compatible with a CPA tunable (targetable) during fabrication, a wide frequency band for CPA, and minimum variations in CPA.

[0025] Previously employed FOCs may comprise a dielectric-based, PCB- compatible, microscale electrostatic FOC with a broadband CPA that may be obtained by using a reduced graphene oxide (rGO) reinforced polymer composite. As a result, the capacitance of a network FOC behaves like an FOC that can have different phase angles by varying the rGO loading. However, at least the difficulty in controlling the volume ratio of rGO in the composite, which plays a key role in tuning the phase angle, made the resulting FOCs undesirable to implement in commercial electronics.

[0026] Systems and methods discussed herein are associated with embodiments of FOCs comprising at least one dielectric layer of poly(vinylidene fluoride)-based polymers and blends of two or more poly(vinylidene fluoride)-based polymers formed using a solvent such as dimethylformamide (DMF), dimethylacetamide (DMAC), N- methyl-2-pyrrolidone (NMP), triethyl phosphate (TEP), dimethyl sulfoxide (DMSO), or combinations and/or derivatives thereof. In an embodiment, there is no water content in the solutions formed as discussed herein. The concentration of polymer to solvent in each solution formed prior to forming the blended solutions discussed herein may be from 1 ml_ solvent: 50mg polymer to 1 ml_ solvent: 200mg polymer.

[0027] In alternate embodiments, the dielectric layer may comprise poly(vinylidene fluoride- trifluoroethylene- chlorotrifluoroethylene) (PVDF-TrFE-CTFE), polyvinyl alcohol (PVA), Ppoly(butylene succinate) (PBS), polyvinyl chloride (PVC), poly(c/^'s-1 ,4- isoprene), and/or glycol phthalate resin.

[0028] In other embodiments, the dielectric layer may comprise ceramics such as polyaniline - (PAN I), Barium Titanate - BaTiO_3: PbTiO_3: SrTiO_3: and BiFe0₃ and/or oxides with a high dielectric constant such as La₀.9i Zr₀.o9 O₂, Ce0₂, CaCu3Ti012, and/or Pbi-_3x/2Ndx (Zr_0.65Ti₀.₃5)O_3.

[0029] As discussed herein, this dielectric layer may be used to fabricate electrical components including printed-circuit-board compatible FOCs. The material which comprises the dielectric layer formed from the DMF and the blends of poly(vinylidene fluoride)-based polymers may be referred to as "polymer blends" or "poly blends," depending upon the embodiment. As discussed herein, a solution-mixing approach was employed to form the blends to facilitate targeting of the dielectric properties. The methods discussed herein may be employed to control and/or target the constant phase angle (CPA) in the FOC. As discussed herein, an empirical relation was derived between blend constituents and the CPA that gives freedom to the design of an FOC for a targeted (tunable during fabrication) CPA. The structural composition of the blends was confirmed using Fourier transform infrared spectroscopy (FTIR) and x-ray diffraction (XRD). In an embodiment, using this solution-mixing approach, a separate aqueous solution may be formed using each of the polymers that may go into the blend, and then the solutions blended according to a desired volume percent ratio ("vol. %" or "volume %" herein).

[0030] Not wishing to be bound by theory, ferroelectric polymers such as P, CP, and TP contain permanent dipole moments and when a time-dependent electrical field is applied, the permanent or induced dipoles tend to align with the direction of the applied external electric field. The frequency of an applied electric field determines the motion of dipoles: if the frequency is small, the dipoles could be easily polarized where the material behaves as close to the ideal capacitor (φ ~ -90°). At a high frequency, however, the dipoles would lack time enough to respond to the electrical field and therefore stay relaxed (φ«-90°). At intermediate frequencies, friction accompanies the polarization. It also produces an electrical current, resulting in imaginary permittivity and phase difference (-90<φ<0°). This phenomenon is called orientation (or dipolar) relaxation. It is expected that P(VDF)-based polymers could be the potential candidate for the FOC.

[0031] As discussed herein, ferroelectric poly(vinylidene fluoride) P(VDF) and P(VDF)-based polymer blends are employed herein and exhibit a dielectric constant (1 1 at 100 Hz), a dissipation factor (0.01 1 at 100 Hz) and a dielectric loss (0.12 at 100 Hz) that may, in combination with other components and/or polymers, make a functional, commercially viable FOC. The control over polar and nonpolar molecular structures, for example, by the addition of other components, contributes to the tenability of the dielectric properties of P(VDF) and its compounds. In one example, the addition of trifluoroethylene (TrFE) molecules to P(VDF) yields a copolymer P(VDF-TrFE) with improved dielectric properties such as desired phase angles and/or a broader bandwidth of operation. In another example, the addition of cholorfluroethylene (CFE) molecules in P(VDF-TrFE) yields a trifluoroethylene chlorofluoroethylene P(VDF-TrFE- CFE) that also comprises desirable dielectric properties. In various discussions herein, the polymers that may be used alone or in combination to form the dielectric layer discussed herein may be referred to as follows: P(VDF) (hereinafter "P"), P(VDF-CFE) (hereinafter "CP"), and P(VDF-CFE-TrFE) (hereafter "TP").

[0032] In various embodiments discussed herein, P(VDF)-based polymers and polymer blends are used to fabricate PCB-compatible FOCs. A solution-mixing approach to form the blends facilitates manipulation of the dielectric properties. Solution mixing may be employed to control the dielectric layer's composition CPA in FOC in the range of -79° to -65° for predefined 150 kHz to 10 MHz constant phase zone (herein after "CPZ"). As used herein, a CPZ is a frequency band in which the phase angle, φ, varies within, for example, ±2°, or another predefined range of tolerance for variance, and a "constant phase angle" (CPA) is an average of maximum and minimum phase angles, φ, in the CPZ. The dielectric layer discussed herein is formed from P, TP, CP, and combinations thereof may be referred to while in solution as comprising the stated polymer or polymers in a blend as well as dimethylformamide (DMF) used as a solvent. Thus, in embodiments where the dielectric layer "consists essentially of" P, TP, and CP, there may be some residual solvent remaining. Furthermore, an empirical relation between blend constituents and phase angles is derived that gives immense freedom to designing FOCs with desired CPAs. FTIR and XRD results (see below in FIGS. 7A and 7B) confirm that the blends contain P and TP in their pristine forms. That is, the polymer blends discussed herein are formed without forming any additional complex molecular structures in the blends. Discussed below are systems and methods for fabrication a PCB-compatible FOC using P(VDF)-based polymers. These polymer-based dielectrics enable FOC fabrication with at least PCB compatibility, a wide range of CPAs, fine-tuning (targeting) of CPAs during the FOC fabrication process (e.g., by changing the design or 'recipe' that is used in fabrication), a wide range of operational frequency bands, and a low cost of fabrication, such that the use of these polymer blends is commercially viable and scalable for FOC production.

[0033] FIGS. 1A-1 F are partial schematic cross-sections of a plurality of fractional order capacitor (FOC) designs 100A-100F that may be fabricated according to certain embodiments of the present disclosure. FIG. 1A is a schematic of a partial cross- section of a structure 100A that comprises a substrate 102. In an embodiment, a layer 104 comprising a dielectric to isolate the substrate 102 from the first metallic layer 106 is formed on the substrate 102, and the first metallic layer 106 is formed on the layer 104. In this example structure 100A, the substrate 102 may be silicon and the layer 104 may comprise SiO₂the first metallic layer 106 is formed as a contiguous layer, e.g., formed as a sheet without holes or vias. In an embodiment the first metallic layer 106 may be of varying thicknesses, for example, from about 50 nm to about 350 nm, and may be formed from platinum, gold, or other elements or combinations of elements suitable for the intended function of the FOC. In some embodiments, the first metallic layer 106 comprises multiple interlayers (not shown) of different materials. In one example, the metallic layer 106 comprises an interlayer of titanium (Ti) formed on the first layer 104 and a second layer of gold (Au) formed on the first interlayer of Ti.

[0034] In an embodiment, dielectric layer 108 comprising the polymer blends discussed herein is formed on the first metallic layer 106, this dielectric layer 108 may be from 10 pm to about 35 pm thick, and in some embodiments the dielectric layer 108 may be about 25 pm thick. In some embodiments, the dielectric layer 108 may comprise 100% P, 100% TP, or 100% CP. In alternate embodiments, the dielectric layer 108 may comprise a volume ratio of 75% P: 25% CP; or 50% P: 50% CP; or 25% P: 75% CP. In other examples, the dielectric layer 108 may comprise a volume ratio of 75% TP: 25% CP; or 50% TP: 50% CP; or 25% TP: 75% CP. While example volume ratios are given herein, other ratios are possible depending upon the desired end properties and performance of the FOC as long as the total % of polymers, when totaled, is equal to 100%.

[0035] In an embodiment, a second metallic layer 1 10 is formed on the first layer 104. In the structure 100A, in contrast to the contiguous first metallic layer 106, the second metallic layer 1 10 is formed as a plurality of discreet sections 1 10a that may be referred to as a plurality of contacts 1 10a. While the cross-section of 1 10a shows 3 discreet contacts 1 10a, the total number of contacts (e.g., as visible from a top-view as discussed in FIGS. 2A-2F below) may be from 1 - 16, or more, depending upon the size of the FOC fabricated.

[0036] In an embodiment, depending upon the composition and thickness of the dielectric layer 108, the plurality of contacts 1 10a of the second metallic layer 1 10 may be employed in order to apply less stress to the dielectric layer 108, as opposed to the amount of stress created using a contiguous metallic layer. The use of the plurality of contacts 1 10a may aid in preserving the integrity (shape/size) of the dielectric layer 108 during the assembly and operation of the structure 100A. Each contact 1 10a that comprises the second metallic layer 1 10 may be referred to as a capacitor.

[0037] FIG. 1 B is a schematic of a partial cross-section of a structure 100B that comprises a substrate 102, a first layer 104 that may comprise S1O2 is formed on the substrate 102. In an embodiment, a first metallic layer 106 is formed on the first layer 104, and a dielectric layer 108 comprising at least one of P, CP, or TP is formed on the first metallic layer 106. In an embodiment, a second metallic layer 1 12 is formed on the dielectric layer 108. In the structure 100B, the second metallic layer 1 12 is formed as a contiguous layer, similarly to that of the first metallic layer 106. It is appreciated that the first 106 and second 1 12 metallic layers discussed in FIG. 1 B and otherwise herein may comprise the same or differing materials, and one or more metallic layer may comprise two or more interlayers as discussed herein. FIG. 1 B illustrates a single FOC formed using the two metallic layers 106 and 1 12 with the dielectric layer 108 disposed therebetween.

[0038] FIG. 1 C is a schematic of a partial cross-section of a structure 100C that comprises a substrate 102, a first layer 104 that may comprise S1O2 is formed on the substrate 102, and a first metallic layer 1 14 formed on the first layer 104. Similarly to the second metallic layer 1 10 discussed in FIG. 1A, the first metallic layer 1 14 in FIG. 1 C comprises a plurality of discreet sections 1 14A referred to as contacts 1 14A. The plurality of contacts 1 14A may be arranged in various manners as discussed herein. A dielectric layer 108 comprising the polymer(s) or polymer blends discussed herein is formed on the first metallic layer 1 14. In some examples, masking or another process may be used to fabricate the dielectric layer 108 such that it is not in contact with the first layer 104 when the second layer 108 is formed on the first metallic layer 1 14.

[0039] In an embodiment in the structure 100C, a second metallic layer 1 10 is formed on the first layer 104. In the structure 100C, the second metallic layer 1 10 is formed as a plurality of discreet sections 1 10a that may be referred to as a plurality of contacts 1 10a. These contacts 1 10a may be formed in a plurality of different arrangements, including arrays of contacts 1 10a where each contact 1 10a is not in contact with (touching) any other contacts 1 10a. In one example, an array of contacts 1 10a that comprises the second metallic layer 1 10 may be formed wherein each contact 1 10a is spaced about equidistant from each adjacent contact. Each contact 1 10a that comprises the second metallic layer 1 10 may be referred to as a capacitor, and each contact 1 10a is aligned with each contact 1 14a.

[0040] FIG. 1 D is a schematic of a partial cross-section of a structure 100D that comprises a substrate 102, a first layer 104 formed on the substrate 102, and a first metallic layer 1 14 formed on the first layer 104. In this example, the first metallic layer 1 14 comprises a plurality of discreet sections 1 14a referred to as contacts 1 14a. The plurality of contacts 1 14a may be arranged in a similar manner to the contacts 1 10a, discussed above. A dielectric layer 108 that may comprise one or more of P, CP, and TP is formed on the first metallic layer 106. In an embodiment, a second metallic layer 1 12 is formed on the first layer 104 as a contiguous layer, similarly to what is discussed herein with respect to FIG. 1 B.

[0041] FIG. 1 E is a schematic of a partial cross-section of an structure 100E that comprises a substrate 102, a first layer 104 formed on the substrate 102, a first metallic layer 1 14 is formed on the first 104, and comprises a plurality of discreet sections 1 14A referred to as contacts 1 14A. The plurality of contacts 1 14A may be arranged in a similar manner to the contacts 1 1 OA, discussed above. In FIG. 1 E, the example first metallic layer 1 14 comprises 5 contacts 1 14a, in contrast to the other examples of the layer 1 10 in FIGS. 1A, 1 C, and 1 D, each of which illustrate 3 contacts in the respective cross-sectional views. A dielectric layer 108 comprising the polymer blends discussed herein is formed on the first metallic layer 106. In an embodiment, a second metallic layer 1 12 is formed on the dielectric layer 108 as a contiguous layer, similarly to what is discussed herein with respect to FIG. 1 B. [0042] FIG. 1 F is a schematic of a partial cross-section of an structure 100F that comprises the first metallic layer 106 and the second metallic layer 1 12 with the dielectric layer 108 disposed in between the first 106 and the second 1 12 metallic layers. The dielectric layer 108, similarly to those discussed above, may comprise one or more of P, TP, and CP in various combinations. While varying thicknesses and relative thicknesses are illustrated in the figures herein, including FIGS. 1A-1 E, it is to be appreciated that both the metallic layer and dielectric layer discussed herein may comprise varying thicknesses among and between embodiments, and that the first and second metallic layers in a single capacitor may comprise the same or different materials, and may be of the same or differing thicknesses, depending upon the embodiment.

[0043] FIGS. 2A-2F are schematic illustrations of a partial top view of an FOC fabricated according to certain embodiments of the present disclosure. While what may be referred to herein as a second metallic layer is discussed in FIGS. 2A-2F and thus illustrated, it is to be appreciated that the first metallic layer may comprise a substantially similar structure such that each contact 1 10a discussed in FIGS. 2A-2F of the second metallic layer aligns with each contact of the first metallic layer (e.g., 1 14a in FIGS. 1 C, 1 D, and 1 E above) when the structure is fabricated. Each contact 1 10a may be said to form an FOC, such that, for example in FIG. 2A, there are 16 FOCs formed, one for each of the contacts 1 10a. In alternate embodiments, a single FOC may be formed, and/or different numbers of FOCs may be formed.

[0044] As discussed in detail below, the metallic layers may take various forms including ordered and random (disordered) arrays. In an embodiment, the plurality of contacts 1 10a may be formed in a plurality of different arrangements, including ordered and random arrays of contacts 1 10a. An ordered array may be an array where each contact 1 10a is spaced about equidistant from each adjacent contact 1 10a (see at least FIGS. 2A-2C below). A random (non-ordered) array may be an array where at least some of the contacts 1 10a are separated from adjacent contacts 1 10a by distances that are not equivalent across the array (see at least FIGS. 2D and 2E below). In either a random or an ordered array, each contact 1 10a is not in contact with (touching) any other contacts 1 10a in the same metallic layer 1 10.

[0045] In one example, the array of contacts 1 10a may be formed wherein each contact 1 10a is substantially the same size and/or shape as each of the other contacts 1 10a in the array of the second metallic layer 1 10. In another example, the array of contacts 1 10a may be formed wherein each contact 1 10a is spaced such that it is not equidistant from each adjacent contact. In another example, the array of contacts 1 10a that comprises the second metallic layer 1 10 may be formed wherein at least some contacts 1 10a are a different size and/or shape as compared to each of the other contacts 1 10a in the array of the second metallic layer 1 10. While the plurality of contacts 1 10 illustrated above in FIGS. 1A-1 F and FIG. 3 exhibit a dome-shaped cross section and may comprise a circular or elliptical shape when viewed perpendicular to the surface of the capacitor, this is one illustrative example. As discussed further below, in alternate embodiments, the cross-sectional shapes may comprise polygons including squares and rectangles. In other embodiments, the second metallic layer 1 10 may comprise shapes, viewed perpendicular to the surface of the capacitor, including triangles, irregular shapes, polygons, circles, ellipses, or combinations thereof.

[0046] For example, FIGS. 2A-2C are schematic illustrations of ordered arrays of contacts 1 10a in FOCs comprising a polymer blend dielectric layer fabricated according to certain embodiments of the disclosure. FIG. 2A illustrates an embodiment of an ordered array 200A of polygon-shaped contacts 1 10a. In this example array 200A taken from a top view as discussed herein, each contact 1 10a comprises a substantially similar shape and size is spaced about equidistant from an adjacent contact 1 10a, such that a distance 202 between a first contact 1 10a and a second contact 1 10a along the X-axis is the same as a distance 204 between a first contact 1 10a and a second contact 1 10a along the Y-axis. The directions of the X and Y axes discussed herein are illustrated in the legend 226.

[0047] FIG. 2B illustrates an embodiment of an ordered array 200B of elliptically- shaped contacts 1 10b. As used herein, an elliptically-shaped contact includes circular and oval shapes. In this example array 200B taken from a top view as discussed herein, each contact 1 10b is spaced about equidistant from an adjacent contact 1 10b, such that a distance 206 between a first contact 1 10b and a second contact 1 10b along the X-axis is the same as a distance 208 between a first contact 1 10b and a second contact 1 10b along the Y-axis. FIG. 2B comprises 16 contacts 1 10b, and thus 16 FOCs.

[0048] FIG. 2C illustrates an embodiment of an ordered array 200C of both polygon- shaped and elliptically contacts 1 10a and 1 10b. In this example array 200C taken from a top view as discussed herein, each contact 1 10a and 1 10b is spaced about equidistant from an adjacent contact 1 10a and/or 1 10b, such that a distance 210 between two adjacent contacts along the X-axis is the same as a distance 212 between the same contact and a different adjacent along the Y-axis. It is to be appreciated that, while various numbers of contacts 1 10a and 1 10b are used for illustrative purposes in at least FIGS. 2A-2F, this number may differ depending upon the embodiment, 16 FOCs are formed by the arrangement in FIG. 2C.

[0049] FIGS. 2D-2F are schematic illustrations non-ordered arrays of contacts 1 10a. FIG. 2D illustrates an embodiment of an array 200D of polygon-shaped contacts 1 10a. In this example array 200D taken from a top view as discussed herein, each contact 1 10a comprises substantially similar shapes and sizes spaced from each adjacent contact 1 10a at a distance that's not equal. For example, such that a distance 214 between two adjacent contacts 1 10a along the X-axis is not the same as a distance 216 between the same contact and a different contact along the Y-axis.

[0050] FIG. 2E illustrates an embodiment of an array 200E of polygon and elliptically-shaped contacts 1 10a and 1 10b. In this example array 200E taken from a top view as discussed herein, each contact 1 10a and 1 10b is spaced from each adjacent contact 1 10a at a distance that's not equal. For example, such that a distance 218 between two adjacent contacts 1 10a and/or 1 10b along the X-axis is not equivalent to a distance 220 between the same contact 1 10a/1 10b and a different contact 1 10a/1 10b along the Y-axis.

[0051] FIG. 2F illustrates an embodiment of an array 200F of polygon-shaped contacts 1 10a of varying sizes. While the contact 1 10a shapes are shown in FIGS. 2A- 2E to be of substantially similar diameter, this may not always be the case. In this example array 200F taken from a top view as discussed herein, each contact 1 10a is spaced from each adjacent contact 1 10c at a distance that's not equal, and may be of a differing size (and shape, though not shown in FIG. 2F). For example, such that a distance 222 between two adjacent contacts 1 10a and/or 1 10c along the X-axis is not the same as a distance 224 between the same contact and a different contact along the Y-axis. It is to be appreciated that differently-sized and/or differently shaped contacts 1 10a and/or 1 10c may also be arranged in an ordered array, similarly to those shown in FIGS. 2A-2C. It is appreciated that the contacts 1 10a, 1 10b, 1 10c discussed herein may differ in size, shape, material, or other properties and characteristics depending upon the embodiment.

[0052] FIG. 3 illustrates an embodiment of a method 300 of fabricating a capacitor according to certain embodiments of the present disclosure. In the method 300, at block A, a first layer 304 which may comprise Si0₂ is formed on a silicon (Si) substrate 302. At block B, a first metallic layer 306 is formed on the first layer 304. In one example, the first metallic layer 306 comprises gold, and in another example, the first metallic layer 306 may comprise platinum. In other examples, the metallic layer 306 comprises multiple interlayers of different materials including gold, titanium, and platinum. In one example, the metallic layer 306 comprises an interlayer of titanium (Ti) formed on the first layer 304 and a second layer of gold (Au) formed on the first interlayer of Ti. In an embodiment, the metallic layer 306 may comprise a total thickness from 50 nm to 250 nm. In the example where more than one metallic layer is combined to form the layer 306, a first interlayer may from 1 nm to 25nm thick.

[0053] In an embodiment, at block C, a dielectric layer 308 is formed. The dielectric layer 308 may be formed from a polymer blend according to various embodiments of the present disclosure. In one example, the polymer blend is fabricated such that two or more materials are combined to form a homogenous mixture. In some examples, three polymers may be used in various combinations such that each polymer comprises at least 1 volume % of the polymer blend. In an embodiment, the polymer blend used to form the dielectric layer 308 may comprise P, CP, and/or TP, according to various volume ratios.

[0054] In some embodiments, the dielectric layer 308 may comprise 100% P, 100% TP, or 100% CP. In alternate embodiments, the dielectric layer 108 may comprise a volume ratio of 75% P: 25% CP; or 50% P: 50% CP; or 25% P: 75% CP. In other examples, the dielectric layer 108 may comprise a volume ratio of 75% TP: 25% CP; or 50% TP: 50% CP; or 25% TP: 75% CP. While example volume ratios are given herein, other ratios are possible depending upon the desired end properties and performance of the FOC as long as the total % of polymers, when totaled, is equal to 100%. It is appreciated that the volume percentages discussed herein refer to when the polymers are in solution, and that, as substantially all of the solvent is removed during the formation of the dielectric layer 308, the ratio of components is the same in the dried dielectric layer as it is in solution.

[0055] Turning back to FIG. 3, in some embodiments, the dielectric layer 308 formed at block C may be formed via a drop-casting process. Drop casting comprises forming a bubble of a material, e.g., the aqueous polymer or polymer blend solutions discussed herein, on top of a surface to be coated, such as the surface of the first metallic layer 306. The substrate 302 that comprises the first metallic layer 306 may then be spun or otherwise rotated/moved to spread the material of the bubble, and/or it may be held stationary to dry. The formation of the dielectric layer 308 at block C may comprise forming the bubble as well as drying and/or rinsing, depending upon the embodiment. At block D, a second metallic layer 310 may be formed on the dielectric layer 308. As discussed in FIGS. 1A, 1 B, 1 D, 1 E, and 1 F the first metallic layer and/or second metallic layers (e.g., 106, 1 12, respectively in the various figures) may be each be formed as a single, contiguous layer or, as shown in FIGS. 1A and 1 C-E a plurality of individual contacts (1 10a or 1 14a, respectively) may be employed.

[0056] In one example, the structure formed at blocks A through D of FIG. 3 may be rotated at block E to be bonded via flip-chip bonding to a PCB board 312 at block F. The flip-chip bonding discussed herein may comprise disposing a plurality of solder balls (not shown) on the second metallic layer 210 and rotating the structure 180 degrees a block E. At block F, the solder balls are re-melted to bond the structure formed at blocks A-D to a PCB board 212. In some embodiments, an electrically- insulating adhesive material may be employed to fill in any voids left by the soldering portion of the flip-bonding.

[0057] FIGS. 4A and 4B are graphs of the phase angle, φ versus frequency (FIG. 4A), and the impedance, Z (FIG. 4B) of the individual FOCs fabricated according to certain embodiments of the present disclosure. FIG. 4A illustrates the phase angle, φ, and FIG. 3B illustrates the impedance, Z dispersion against frequency for P, CP, and TP. The insets inside the plots represent example chemical structures of P, CP and TP. As shown, PVDF is present in all P, CP, TP, the TrFE molecule is present only in CP and TP, and CFE is present only in the TP.

[0058] As shown in FIG. 4A, the phase angle, φ, increases with frequency and saturates in the MHz range, which further decreases in the high-frequency range (the high-frequency range is not covered completely in the figure). The CPZ is observed in the range between 150 KHz to 10 MHz. In the defined CPZ, the observed CPAs are - 79°, -76°, and -65° for P, CP, and TP, respectively. FIG. 4B shows impedance and Z versus frequency in log scale. The slope in the line equations represents the exponent of the element constant, a. Explicitly, the values of a are 0.90, 0.85 and 0.69, which gives a CPA of -81 °, -77°, and -63° for P, CP, and TP, respectively.

[0059] Exemplary polymers and polymer blends used for the dielectric layer discussed herein may be found below in Table 1 . These blends may be adjusted in various embodiments to tune the properties of the FOC as discussed herein for various applications.

EXAMPLE Device Fabrication and results:

[0060] Initially, 200 mg each of P, TP, and CP, were each dissolved in 2 ml of DMF under constant stirring at room temperature to obtain 0.1 mg/ml solution of individual polymers. These solutions were further used to obtain various volume-ratio blends to fabricate the polymer films, as shown below in Table 1. Au-deposited, 2 cm χ 2 cm Si/Si0₂ wafers were used to fabricate the fractional-order capacitors (FOC) by drop casting the polymer blend solutions. A metallic layer comprising a metallic layer comprising a first interlay of 10 nm of Ti and a second interlayer of 190 nm of Au was deposited on Si/SiO₂ wafers via DC sputter to define one of the electrodes. The polymer solutions were drop-casted, leveled and dried for 12 hours at 80 °C under a vacuum. The other Au electrode of defined geometry was deposited in similar fashion using a shadow mask. The electrode is defined in a 3 mm circular form, which gives us freedom to fabricate nine individual FOCs on a 2 cm by 2 cm sample area. The sample was further flip-bonded on a PCB board (Block F of FIG. 3). The PCB board was designed in such a way that an individual capacitor gives a separate connection for the electrical measurements.

[0061] An Agilent 4294A precision impedance analyzer was used for the electrical measurements. Individual FOCs were characterized as illustrated herein for the impedance, Z, and phase angle, φ, in the 50 kHz to 10 MHz frequency range at 0.5 V. Fourier-transform, infrared-attenuated, total-reflection (FTIR-ATR) spectroscopy (Thermo Scientific NICOLET iSIO) was used to characterize the dielectric films with a wave number range of 4000 cm^"1 to 550 cm^"1 and with a spectral resolution of 0.2 cm^"1. Crystallographic analysis of samples was performed using a powder X-ray diffractometer (XRD; Bruker D8 Advance) with Cu Ka (1.5418 A) radiation. The instrument was operated at 40 kV voltage and 40 mA current. The dielectric films were analyzed from 10 to 60 2Θ degrees at 0.01 increments and 0.1 s/step scan speed. All spectra were normalized for the Au (1 1 1 ) peak to obtain the relative crystallinity of the polymers in the samples.

Table 1 : Exemplary polymer blends for dielectric layer of FOC

M1 75% - 25%

P-TP M2 50% - 50%

M3 25% - 75%

TP 100%

P 100% - -

M4 25% 75% -

P-CP M5 50% 50% -

M6 75% 25% -

CP - 100% -

M7 - 75% 25%

CP-TP M8 - 50% 50%

M9 - 25% 75%

TP 100%

[0062] FIGS. 5A-5F shows the measured phase angle, φ, and the measured impedance, Z, dispersion against frequency for P-TP, P-CP and P-TP blends in CPZ. The results of unblended P, CP, and TP are also provided in the respective graphs for comparison. FIG. 5A illustrates the φ for P, M1 , M2, M3, and TP, and FIG. 5B illustrates the Z for the same, P, M1 , M2, M3, and TP. FIG. 5C illustrates the φ for P, M4, M5, M6, and CP, and FIG. 5D illustrates the Z for the same, P, M4, M5, M6, and CP. FIG. 5E illustrates the phase angle φ for CP, M7, M8, M9, and TP, and FIG. 5F illustrates the Zfor the same, CP, M7, M8, M9, and TP.

[0063] Note that the CPAs for the blends (FIGS. 5A, 5C, 5E) are different than the CPAs of the P, CP, and TP. Overall, the CPA for the blends lies in between that of their two constituent polymers. For example, the blend M3 contains 75 vol% of TP and 25 vol% of P, whose CPA is -70.45°. Thus, this supports that, through proper fabrication, a CPA can be tuned by simply changing the blend composition. FIGS. 5B, 5D, and 5F show impedance, Z, versus frequency in log scale for P-TP, P-CP and P-TP blends in CPZ. Concomitant with FIG. 5B, the slope in the line equations represents the exponent of the element constant, a.

[0064] Table 2 shows the exponent of the element constant, a, obtained from the slope in the line equations given in FIGS. 5B, 5D, and 5F for the samples in Table 1 . A comparison of the CPAs derived from the line equations in FIGS. 5B, 5D, and 5F with the experimentally obtained values in FIGS. 5A, 5C, 5E. The a values in FIGS. 5B, 5D, and 5F confirm the measured CPA values in FIGS. 5A, 5C, 5E and Table 2. As shown in FIGS. 5B, 5D, and 5F, the change in CPA and impedance, Z, with the change in composition implies that the dielectric properties of P, TP and CP are modifying in the blend.

Table 2

[0065] FIGS. 6A-6C are graphs of the CPA versus the composition of the polymer blends used for the dielectric layer. FIG. 6A is a graph that shows the P-TP blend with an average of 4° of CPA change for every 25 vol% change of TP in P-TP composition. FIG. 6B is a graph that shows the P-CP polymer blends with an average of 1° CPA change for every 25 vol% change of CP in P-CP composition. FIG. 6C is a graph that shows the CP-TP blend shows an average of 3° CPA change for every 25 vol% change of CP in CP-TP composition.

[0066] FIGS. 7A and 7B are graphs of FTIR (FIG. 7A) and XRD (FIG. 7B) studies of P-TP series blends to investigate the effects of blend formation on the structural changes. As shown in FIG. 7A, the FTIR spectra of P, TP and its blends show that the blends contain signature peaks of P and TP per their volume percentage in the blend. No additional peak arises due to the blending of two polymers; rather, individual polymers retain their characteristic molecular structures. The observed peaks in P are 835 cm^"1 (CF stretching vibration of PVDF), 880 cm^"1 (C-C-C asymmetrical stretching vibration), 1096 cm^"1, 1 183 cm^"1 (C-C bond of P(VDF)), and 1403 cm^"1 (CH₂ wagging vibrations). TP shows a higher intensity of peaks confirming, thus the higher freedom for molecular vibrations due to the presence of CFE monomers in CP, which gives chemical confinement to the VDF-TrFE sequence and meanwhile expands the lattice spacing to cause local distortion.

[0067] FIG. 7B shows the XRD spectra of P, TP, and the blends discussed herein. P shows a single broad peak at 20.5° that corresponds to (200) and (1 10) crystal planes, whereas TP shows intense peaks at 18.2° followed by a 16.5° peak corresponding to (1 1 1 ) and (100) planes. The higher d spacing in TP is due to the incorporation of TrFE-CFE molecules in P(VDF) chains. The XRD peaks follow the P to TP trend as per the TP contained in the blend. FTIR and XRD confirm that the blends contain P and TP in their pristine forms, without additional complex molecular structure in the blend. Nonetheless, the change in the microstructures in the blend, which are responsible for the change in dielectric properties such as polar conformation, could not be discarded.

[0068] FIGS. 8A-8C are schematic illustrations of polymers and polymer blends fabricated and employed in FOCs according to embodiments of the present disclosure. FIG. 8A illustrates 802, a schematic shows an FOC with P(VDF)-based polymer dielectric disposed between two plates, fabricated according to embodiments of the present disclosure. A P(VDF) molecular structure is shown in FIG. 8B as 804 and arrows indicating polarization vectors of the P and TP components are indicated in 806. The arrows in 808 are employed herein to show the random nature of polarization in the polymer films comprising P, TP, and P+TP.

[0069] FIG. 8C illustrates a graph 810 of permittivity (real and imaginary) and ψ plotted against frequency. The inset in the graph 810 shows ψ against frequency in CPZ. The color bands show three regions in the frequency dispersion. The dipole response to the frequency in the three regions of the graph 810 are illustrated in 812, and the visualization of ψ between current (I) and voltage (V) in the three regions of the graph 810 are shown at 814.

[0070] Table 3 compares aspects of examples of P(VDF)-based FOCs with the other typed of FOCs previously fabricated ("reference" samples). Thus, the P(VDF)- based FOCs fabricated as discussed herein have improved properties and functionalities over the other FOCs at least in terms of CPA, CPZ, phase error and tunability of the CPA during FOC fabrication.

[0071] Table 3

[0072] Having described various devices and processes herein, specific aspects can include, but are not limited to:

[0073] In a first aspect, a fractional-order capacitor comprises: a first metallic layer formed on a S1O₂ layer; and a dielectric layer formed on the first metallic layer, wherein the dielectric layer comprises at least one of ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP"); and a second metallic layer formed on the dielectric layer.

[0074] A second aspect can include the fractional order capacitor of the first aspect, wherein at least one of the first metallic layer or the second metallic layer comprises a plurality of interlayers.

[0075] A third aspect can include the fractional order capacitor of any of the first to second aspects, wherein the first metallic layer comprises a first interlayer of titanium (Ti) formed on the S1O2 layer and a second interlayer of gold (Au) formed on the interlayer of Ti, wherein the dielectric layer is in contact with the second interlayer of Au.

[0076] A fourth aspect can include the fractional order capacitor of any of the first to third aspects, wherein each metallic contact of the array is spaced about equidistant from at least one adjacent metallic contact.

[0077] A fifth aspect can include the fractional order capacitor of the fourth aspects, wherein each metallic contact of the array is spaced about equidistant from at least one adjacent metallic contact.

[0078] A sixth aspect can include the fractional order capacitor of any of the first to fifth aspects, further comprising a printed-circuit-board (PCB) board electrically coupled to the second metallic layer.

[0079] In a seventh aspect, a fractional-order capacitor comprises: a substrate; an Si0₂ layer formed on the substrate; a metallic layer formed on the Si0₂layer; and a dielectric layer formed on the metallic layer, wherein the dielectric layer comprises at least two of ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP").

[0080] An eighth aspect can include the method of the seventh aspect, wherein the dielectric layer is selected from the group consisting essentially of: P and TP, CP and P, or TP and CP.

[0081] A ninth aspect can include the method of any of the seventh to eighth aspects, wherein the second metal layer is electrically coupled to a printed-circuit-board (PCB).

[0082] A tenth aspect can include the method of the ninth aspect, wherein the capacitor comprises a predetermined phase angle constant a from 0.69 to 0.90 and a CPA, φ from -65.0 to -79.0. [0083] An eleventh aspect can include the method of any of the seventh to tenth aspects, wherein the dielectric layer consists essentially of P, CP, and TP, in equal volume percentages.

[0084] A twelfth aspect can include the method of any of the seventh to eleventh aspects, wherein the dielectric layer consists essentially of P, CP, and TP, and at least one of P, CP, and TP comprises a volume percentage of greater than 33.4%.

[0085] In a thirteenth aspect, a method of fabricating a fractional-order capacitor, comprises: forming a first metallic layer on an S1O2 layer; forming a dielectric layer on the first metallic layer, wherein the dielectric layer comprises forming a blend of a solvent and at least two of: ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE- CFE) ("TP"); and forming a second metallic layer on the dielectric layer.

[0086] A fourteenth aspect can include a method of the thirteenth aspect, wherein forming the dielectric layer comprises forming an aqueous solution of dimethylformamide (DMF) and the at least two of P, TP, or CP.

[0087] A fifteenth aspect can include a method of the fourteenth aspect, further comprising, subsequent to forming the second metallic layer, electrically coupling the structure to a printed-circuit board (PCB).

[0088] A sixteenth aspect can include a method of any of the thirteenth to fifteenth aspects, further comprising, wherein forming the second metallic layer comprises forming an array of discreet metallic contacts.

[0089] A seventeenth aspect can include a method of the sixteenth aspect, wherein the array comprises an ordered array of a plurality of uniform shapes, wherein each uniform shape of the plurality of uniform shapes is spaced about equidistant from at least one adjacent uniform shape.

[0090] An eighteenth aspect can include a method of the sixteenth aspect, wherein the array comprises a plurality of shapes of at least two different geometries.

[0091] A nineteenth aspect can include a method of the sixteenth aspect, wherein the array comprises a non-ordered distribution of a plurality of shapes of at least two different geometries.

[0092] A twentieth aspect can include a method of any of the thirteenth to nineteenth aspects, further comprising forming the dielectric layer via drop-casting. [0093] While several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted or not implemented.

[0094] For further information about fractional order capacitors, see U.S. Provisional Patent Application 62/487,466, filed this same day April 19, 2017, entitled "Numerical Design of Fractional Order Capacitors," by Khaled Nabil Salama, et al.; U.S. Provisional Patent Application 62/487,467, filed this same day April 19, 2017, entitled "Modeling a Fractional Order Capacitor Design," by Khaled Nabil Salama, et al., and U.S. Provisional Patent Application 62/487,463, filed this same day April 19, 2017, entitled "Phase Angle Tunable Fractional-order Capacitors Including Multi-layer Dielectric Layers Methods of Manufacture Thereof," by Khaled Nabil Salama, et al., which are hereby incorporated by reference, each in its entirety.

[0095] Where numerical ranges or limitations are expressly stated, such express ranges or limitations should be understood to include iterative ranges or limitations of like magnitude falling within the expressly stated ranges or limitations (e.g., from about 1 to about 10 includes, 2, 3, 4, etc.; greater than 0.10 includes 0.1 1 , 0.12, 0.13, etc.). For example, whenever a numerical range with a lower limit, F¾, and an upper limit, R_u, is disclosed, any number falling within the range is specifically disclosed. In particular, the following numbers within the range are specifically disclosed: R=Ri+k^*(R_u-Ri), wherein k is a variable expressed as a percent, for example, a weight or volume percent ranging from 1 percent to 100 percent with a 1 percent increment, i.e., k is 1 percent, 2 percent, 3 percent, 4 percent, 5 percent, . . ., 50 percent, 51 percent, 52 percent, . . ., 95 percent, 96 percent, 97 percent, 98 percent, 99 percent, or 100 percent. Moreover, any numerical range defined by two R numbers as defined in the above is also specifically disclosed.

[0096] Also, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component, whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.

Claims

CLAIMS What is claimed is:

1. A fractional-order capacitor comprising:

a first metallic layer formed on a S1O2 layer; and

a dielectric layer formed on the first metallic layer, wherein the dielectric layer comprises at least one of ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP"); and

a second metallic layer formed on the dielectric layer.

2. The capacitor of claim 1 , wherein at least one of the first metallic layer or the second metallic layer comprises a plurality of interlayers.

3. The capacitor of claim 1 , wherein the first metallic layer comprises a first interlayer of titanium (Ti) formed on the Si0₂ layer and a second interlayer of gold (Au) formed on the interlayer of Ti, wherein the dielectric layer is in contact with the second interlayer of Au.

4. The capacitor of claim 1 , wherein forming the second metallic layer comprises forming an array of discreet metallic contacts.

5. The capacitor of claim 4, wherein each metallic contact of the array is spaced about equidistant from at least one adjacent metallic contact.

6. The capacitor of claim 1 , further comprising a printed-circuit-board (PCB) board electrically coupled to the second metallic layer.

7. A fractional-order capacitor comprising:

a substrate;

an Si0₂ layer formed on the substrate;

a metallic layer formed on the Si0₂layer; and

a dielectric layer formed on the metallic layer, wherein the dielectric layer comprises at least two of ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP").

8. The capacitor of claim 7, wherein the dielectric layer is selected from the group consisting essentially of: P and TP, CP and P, or TP and CP.

9. The capacitor of claim 7, wherein the second metal layer is electrically coupled to a printed-circuit-board (PCB).

10. The capacitor of claim 9, wherein the capacitor comprises a predetermined phase angle constant a from 0.69 to 0.90 and a CPA, φ from -65.0 to -79.0.

1 1 . The capacitor of claim 7, wherein the dielectric layer consists essentially of P, CP, and TP, in equal volume percentages.

12. The capacitor of claim 7, wherein the dielectric layer consists essentially of P, CP, and TP, and at least one of P, CP, and TP comprises a volume percentage of greater than 33.4%.

13. A method of fabricating a fractional-order capacitor, comprising:

forming a first metallic layer on an S1O2 layer;

forming a dielectric layer on the first metallic layer, wherein the dielectric layer comprises forming a blend of a solvent and at least two of: ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF- TrFE-CFE) ("TP"); and

forming a second metallic layer on the dielectric layer.

14. The capacitor of claim 13, wherein forming the dielectric layer comprises forming an aqueous solution of dimethylformamide (DMF) and the at least two of P, TP, or CP.

15. The method of claim 14, further comprising, subsequent to forming the second metallic layer, electrically coupling the structure to a printed-circuit board (PCB).

16. The method of claim 13, wherein forming the second metallic layer comprises forming an array of discreet metallic contacts.

17. The method of claim 16, wherein the array comprises an ordered array of a plurality of uniform shapes, wherein each uniform shape of the plurality of uniform shapes is spaced about equidistant from at least one adjacent uniform shape.

18. The method of claim 16, wherein the array comprises a plurality of shapes of at least two different geometries.

19. The method of claim 16, wherein the array comprises a non-ordered distribution of a plurality of shapes of at least two different geometries.

20. The method of claim 13, further comprising forming the dielectric layer via drop- casting.