WO2018193402A1

WO2018193402A1 - Phase angle tunable fractional-order capacitors including multi-layer ferroelectric polymer dielectric and methods of manufacture thereof

Info

Publication number: WO2018193402A1
Application number: PCT/IB2018/052733
Authority: WO
Inventors: Khaled Nabil Salama; Agamyrat AGAMBAYEV; Hakan BAGCI; Mohamed Farhat; Shashikant Patole
Original assignee: Sabic Global Technologies, B.V.
Priority date: 2017-04-19
Filing date: 2018-04-19
Publication date: 2018-10-25

Abstract

Discussed herein are embodiments of fractional-order capacitors (FOC) and methods of manufacture thereof such that the FOC is tuned to a value or to fall within a predetermined value such as a phase angle. The FOCs are designed and fabricate with dielectric layers of an interlayer structure of two or more individual layers of poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride terpolymer P(VDF-TrFE-CFE) ("TP"). Each layer of an interlayer structure of a dielectric layer may differ from at least one other layer in one of material, composition of solution used to form the layer, and/or thickness.

Description

PHASE ANGLE TUNABLE FRACTIONAL-ORDER CAPACITORS INCLUDING MULTI-LAYER

FERROELECTRIC POLYMER DIELECTRIC AND METHODS OF MANUFACTURE THEREOF

BACKGROUND

[0001] Fractional order capacitors (FOC) have impedance Ζ(ω) = , ^_a where

C is a constant that represents a capacitance, ω represents an angular frequency (ω = 2π/), and a is a number in the range 0 < a < 1. Conventional capacitors have an a-value that is approximately 1 . Such conventional capacitors may be referred to as "integer order" capacitors. It is understood, notwithstanding, that such conventional capacitors commonly exhibit an a-value of less than 1 , but even low- quality conventional capacitors commonly exhibit an a-value > 0.95. As such, conventional capacitors are often modeled as ideal integer order devices. The a-value of a capacitor may be sensitive to an operating frequency. Said in other words, FOCs may exhibit an a-value of approximately integer order, except in a predefined frequency band.

[0002] FOCs have applications in a variety of different fields that may be said to provide solutions to fractional order calculus problems. Some of these applications include solving nonlinear problems in such real-world domains as pattern recognition, automated control, signal processing, and modeling various processes. As one specific example, FOCs have application in proportional-integral-differential (PID) controllers. While fractional order calculus and FOCs have been studied theoretically, in practice it has been difficult to realize practical FOCs. Previous FOC realization approaches have involved liquid-electrode based (LEB) type FOCs, fractal-type (FT) FOCs, and ladder network approximation FOCs composed of conventional resistors and capacitors (e.g., integer order capacitors). These previous FOC realization techniques have suffered from one or more significant drawbacks. One commonly encountered significant drawback of previous techniques of realizing FOCs has been undesirable restriction on the operational frequency range of FOC behavior and/or undesirable ripple in the a- value of the FOC over the operational frequency range.

SUMMARY

[0003] In an embodiment, a fractional-order capacitor comprising: a first metallic layer formed on a S1O2 layer; a dielectric layer formed on the metallic layer, wherein the dielectric layer comprises an interlayer structure of at least two layers; and a second metallic layer formed on the dielectric layer. [0004] In an alternate embodiment, fractional-order capacitor comprising: a substrate; an S1O2 layer formed on the substrate; a metallic layer formed on the S1O2 layer; and a dielectric layer formed on the metallic layer and comprising an interlayer structure of at least two of ferroelectric poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE- CFE) ("TP").

[0005] In an embodiment, a method of fabricating a fractional-order capacitor, comprising: forming a first metallic layer on an S1O2 layer; forming a dielectric layer on the first metallic layer, wherein forming the dielectric layer comprises forming an interlayer structure of at least two layers, wherein each layer is selected from the group consisting of: poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride terpolymer P(VDF-TrFE-CFE) ("TP"); and forming a second metallic layer on the dielectric layer.

[0006] These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0008] FIGS. 1A-1 F are partial schematic cross-sections of a plurality of fractional order capacitor (FOC) designs comprising the dielectric layers fabricated according to certain embodiments of the disclosure.

[0009] FIGS. 2A-2F are schematic illustrations of a partial top-down view of structures comprising at least one FOC each and fabricated according to certain embodiments of the present disclosure.

[0010] FIG. 3 illustrates an embodiment of a method of fabricating a fractional order capacitor (FOC) comprising the dielectric layers fabricated according to certain embodiments of the disclosure.

[0011] FIGS.4A-4D are partial schematic illustrations of example embodiments of dielectric layers comprising interlayer structures according to certain embodiments of the present disclosure. [0012] FIG. 5 shows the normalized XRD spectra of P, TP, and TP-P bilayer films with different thickness ratios.

[0013] FIG. 6A is a graph of the calculated and measured, φ, against frequency interlayer structures of TP-P, CP-P, and TP-CP comprising equal layer thickness fabricated according to certain embodiments of the present disclosure.

[0014] FIG. 6B is a graph of the measured Z against frequency for P, CP, and TP and interlayer structures of TP-P, CP-P, and TP-CP comprising equal layer thickness fabricated according to certain embodiments of the present disclosure.

[0015] FIG. 7 A shows the φ calculated using equation 2 as well as the measured φ against frequency for TP-P interlayer structures with different thickness ratios of TR=0,

TR=0.33, TR=0.5, TR=0.66, and TR=1 .0 fabricated according to certain embodiments of the present disclosure.

[0016] FIG. 7B shows the measured Z versus frequency for TP-P interlayer structures with different thickness ratios of TR=0, TR=0.33, TR=0.5, TR=0.66, and TR=1.0 fabricated according to certain embodiments of the present disclosure.

[0017] FIG. 8 is a graph illustrating the CPA v. the thickness ratio for a P-TP interlayer structure fabricated according to certain embodiments of the present disclosure.

DETAILED DESCRIPTION

[0018] It should be understood at the outset that although illustrative implementations of one or more embodiments are illustrated below, the disclosed systems and methods may be implemented using any number of techniques, whether currently known or not yet in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0019] Fractional order capacitors (FOC) may be employed to accurately model the physical behavior of nature and to provide at least one additional degree of freedom in the design of advanced electrical systems, which is not possible using conventionally employed ideal circuit elements. For instance, to build an oscillator with a high order (>2) and with a desired frequency, the FOCs employed may each have different CPAs. Currently employed technology has multiple challenges such as that it lacks portability and may use power at an undesirable rate. Additionally, currently-employed FOC designs may have other disadvantages such as (1 ) a lack of PCB (Printed circuit board) compatibility, e.g., the difficulty of integration of designed fractional order capacitors to the electrical circuit; (2) difficulty controlling tunability in a constant phase angle during design and resultant fabrication; (3) the phase angle ripple and excessive (undesirable) variation in the constant phase angle; and (4) difficulty in low-cost, commercially-viable production.

[0020] Currently employed materials used in FOCs may be oxides and/or silicates with filler materials. In contrast, the FOCs discussed herein can be designed and fabricated with a tuned (targeted) CPA using ferroelectric polymers. For example, using the combinations of layered ferroelectric polymers including but not limited to poly(vinylidene fluoride)-based materials such as P(VDF) (hereinafter "P"), P(VDF-CFE) (hereinafter "CP" since it it's a copolymer) and P(VDF-CFE-TrFE) (hereafter "TP" since it is a terpolymer). Thus, the dielectric layers discussed herein that comprise interlayer structures of poly(vinylidene fluoride)-based materials are employed to design and fabricate FOCs with targeted properties, including a target (tuned) CPA. The terms "targeted" and "tuned" as well as variations thereof may be employed herein to mean a property value or a range of property values that are desired from an FOC such that the FOC contains elements including the dielectric layer that are designed to produce a property value, e.g., a CPA, of a particular number or within a desired range.

[0021] In alternate embodiments, the dielectric layer may comprise poly(vinylidene fluoride- trifluoroethylene- chlorotrifluoroethylene) (PVDF-TrFE-CTFE), polyvinyl alcohol (PVA), Ppoly(butylene succinate) (PBS), polyvinyl chloride (PVC), poly(c/^'s-1 ,4- isoprene), and/or glycol phthalate resin.

[0022] In other embodiments, the dielectric layer may comprise ceramics such as polyaniline - ( PANI), Barium Titanate - BaTiO_3: PbTiO_3: SrTiO_3: and BiFeO₃ and/or oxides with a high dielectric constant such as La₀.9i Zr₀.o9 O2_, CeO2_, CaCu3TiO12, and/or Pbi-_3x/2Ndx (Zr_0.65Ti₀.₃5)O_3.

[0023] Inductors, resistors, and capacitors are ubiquitous passive circuit elements whose cyclic frequency-dependent (ω) impedance (Z) can be given as follows:

Ζ(ω) = A(ja))-^a (2)

where A is a coefficient, j represents the imaginary unit, and Of is the exponent of the element which is constant that determines the phase angle φ of impedance Z, and CO represents an angular frequency (ω = 2π/), In the ideal case, a takes one of the following values: -1 (pure inductor), 0 (pure resistor), or 1 (pure capacitor). However, if a takes non-integer values, then the element is called a fractional-order element, an additional circuit element with the phase angle as shown in equation (3) below:

. . αχπ

Φ = ±— (3)

[0024] The concept of a fractional-order element provides additional degrees of freedom in modeling, characterizing, and implementing novel circuit components in a wide spectrum of disciplines: viz. energy-storage and energy-generation devices, neural-system modeling, neurovascular coupling model, characterizing bio-impedance, control-system design, heat diffusion control, electromagnetics, and advanced electronics.

[0025] In particular, a fractional-order element with 0 < a < 1 (-90° < φ < 0°) is called a fractional-order capacitor (FOC). An FOC facilitates circuit configurations that would be impractical or impossible to implement with conventional capacitors. For example, replacing an integer-order capacitor with an FOC in a temperature controller virtually eliminates the overshoot and windup effect due to the time spent in actuator saturation and drastically reduces the time required to stabilize the temperature. In general, it is highly desirable to have an FOC that is dielectric-based and printed-circuit-board (PCB) compatible, and that could operate over wide frequency bands with a constant phase angle (CPA) that may be tuned during fabrication, and with minimum-phase-angle ripples. The structures herein may be said to be "electrically coupled" to PCB boards. When two or more components are said to be "electrically coupled," this may mean that a completed circuit is formed by the assembly of the two or more components.

[0026] Previously employed FOCs may be classified into at least five categories: 1 ) liquid electrode-based (LEB) FOCs, 2) geometry-related fractal (FT) FOCs, 3) resistor- capacitor (RC) ladders FOCs, 4) CMOS-based emulator FOCs, and 5) composite FOCs. LEB FOCs are constructed by dipping capacitive, parallel-plate electrodes coated with a porous film of polymers into an ionic medium. The operating principle of LEB FOCs is anomalous diffusion of ions through a porous surface at the electrode- electrolyte interface. The CPA is based on the depth of immersion of the electrodes into the ionic medium, the thickness of the polymer film, and the conductivity of the ionic medium. The large dimension, lack of portability and liquid ionic medium prevent the LEB FOCs integration in microelectronic circuits. FT FOCs use fractal structures created with metal traces onto silicon wafers, which makes FT FOCs integrate-able with microelectronic circuits. [0027] The CPA of a circuit comprising an FT FOC depends on the fractal shape and number of iterations. RC ladder FOCs may be fabricated using a combination of different value resistors and capacitors to approximate the term, (/ω)^_α, in Equation (1 ) with non-integer-order transfer functions. One of the disadvantages of using network approximations is that a designer needs a large number of components to obtain the fractional behavior accurately and that it may drop demand elements with impractical values such that the frequency band is narrower than desirable for the end applications. CMOS-based emulator FOCs may use a differentiator and a voltage-to-current converter for emulation of the constant phase element. CMOS-based emulator FOCs may employ an operational transconductance amplifier and grounded capacitors for tuning the equivalent CPA, and may use external power for operation. Furthermore, for at least some of the previously employed, the FOC is obtained by the resultant circuit impedance rather than by a physical capacitor. It is important to mention that none of the above offer a FOC that is dielectric based and printed-circu it-board (PCB) compatible with a CPA tunable (targetable) during fabrication, a wide frequency band for CPA, and minimum variations in CPA.

[0028] Previously employed FOCs may comprise a dielectric-based, PCB- compatible, microscale electrostatic FOC with a broadband CPA that may be obtained by using a reduced graphene oxide (rGO) reinforced polymer composite. As a result, the capacitance of a network FOC behaves like an FOC that can have different phase angles by varying the rGO loading. However, at least the difficulty in controlling the volume ratio of rGO in the composite, which plays a key role in tuning the phase angle, made the resulting FOCs undesirable to implement in commercial electronics.

[0029] Discussed herein are PCB-compatible FOC with a CPA that is tunable during the design fabrication of the dielectric layer from ferroelectric materials including polymers. The tunability of one or more properties of an FOC is the ability to target a desired value or range of that property, such as the CPA, and design the FOC to have that value or to operate within the range of values based upon the properties and design of one or more aspects of the FOC. For example, a target CPA for an FOC may be determined by a design team or by a software analysis, and a composition, thickness, material, or other properties of the dielectric layer used in the FOC may be determined such that the design of the FOC is "tuned" to produce the desired CPA. The poly(vinylidene fluoride)-based polymers are used to fabricate PCB-compatible fractional-order capacitors (FOCs). A solution drop cast approach to form the layers facilitates the manipulation of the effective dielectric properties to control the constant phase angle (CPA) of the FOC between -65° to -83°. In various examples, an empirical relation may be drawn between a layer thickness ratio and a CPA that promotes the feasibility of the design and fabrication of FOCs with the desired CPA. FOCs were fabricated with different CPAs from ferroelectric polymers utilizing the orientation relaxation of dipoles. The dielectric layers discussed herein may be formed as an interlayer structure. As used herein, the term "interlayer structure" may be used to refer to a portion of an FOC that is formed from two or more layers of P, CP, and/or TP. A "bilayer" may be the term used herein to refer to an interlayer structure that comprises two layers of different materials, concentrations of material in solution during application/formation, and/or thicknesses. By creating the interlayer structures from those polymers with different configurations of layers in the interlayer structure, the shifts in effective CPA were observed. In one example, by changing thickness ratio of layers, the CPA was tuned to the desired value by using different thicknesses of layers within an interlayer structure. Thus, during FOC manufacture, a CPA value may be tuned by taking the simple equivalent value of serially connected layers.

[0030] A double drop-casting method is used to form a dielectric layer of P(VDF)- based polymers. Drop casting comprises forming a bubble of a material, e.g., the aqueous polymer solutions discussed herein, on top of a surface to be coated, such as the surface of a metallic layer. The substrate that comprises the first metallic layer may then be spun or otherwise rotated/moved to spread the material of the bubble, and/or it may be held stationary to dry. Discussed herein are the phase angle, φ, and the impedance, Z of the individual capacitor, resulting from dielectric layers comprising interlay structures of two or more of P, CP, and/or TP. As discussed herein, an interlayer structure may be used to form a dielectric layer for one or more FOCs.

[0031] The interlayer structures discussed herein comprise at least two layers, each of which is associated with a thickness. The thickness ratio of the layers of an interlayer, for example, when two layers are used to form the interlayer may be determined as follows.

[0032] As used herein, the "thickness ratio" for an interlayer structure comprising two layers such as P and TP (e.g., a single bilayer) is defined as: where d_p is the thickness of the first (P) layer and d_TP is the thickness of the second (TP) layer. In other examples, the thickness ratio may be expressed as TR = cfsingie/cftotai, where cftotai is ^tne total thickness of the dielectric layer, e.g., the sum of the individual thicknesses of layers used to form the interlayer structure, and d_Singie is the thickness of a single layer within the dielectric layer's interlayer structure.

[0033] Systems and methods discussed herein are associated with embodiments of FOCs having a dielectric layer of poly(vinylidene fluoride)-based polymers formed using a solvent such as dimethylformamide (DMF). In alternate embodiments, in addition to or instead of DMF, solvents including dimethylacetamide (DMAC), N-methyl-2- pyrrolidone (NMP), triethyl phosphate (TEP), and/or dimethyl sulfoxide (DMSO). It is to be appreciated that the aqueous solutions employed to form the interlayer structure herein do not contain water, and may be formed with concentration levels (ratios) from 1 ml_ solvent : 50 mg polymer to 1 ml_ solvent : 200mg polymer.

[0034] As discussed herein, this dielectric layer comprises an interlayer structure of at least a bilayer, where each layer of the bilayer comprises a different material, concentrations of material in solution during application/formation, and/or thicknesses from the other layer of the bilayer. As discussed herein, the concentration of a layer may refer to the percentage (e.g., volume %) of ferroelectric polymer in solution as compared to the solvent for the aqueous solution formed and applied, and the thickness may refer to a measurement of the layer perpendicular to the substrate. The dielectric layers discussed herein are fabricated as interlayer structures that may be used to fabricate electrical components including printed-circuit-board compatible FOCs to tune various properties of the FOCs during the fabrication process. As discussed herein, a solution-mixing approach was employed to form aqueous solutions to facilitate targeting of the dielectric properties. The methods discussed herein may be employed to control and/or target the constant phase angle (CPA) in the FOC during fabrication. In an embodiment, using this solution-mixing approach, a separate aqueous solution may be formed using each of the polymers employed.

[0035] Notwithstanding any limiting theory, ferroelectric polymers such as P, CP, and TP contain permanent dipole moments and when a time-dependent electrical field is applied, the permanent or induced dipoles tend to align with the direction of the applied external electric field. The frequency of an applied electric field determines the motion of dipoles: if the frequency is small, the dipoles could be easily polarized where the material behaves as close to the ideal capacitor (φ ~ -90°). At a high frequency, however, the dipoles would lack time enough to respond to the electrical field and therefore stay relaxed (φ«-90°). At intermediate frequencies, friction accompanies the polarization. It also produces an electrical current, resulting in imaginary permittivity and phase difference (-90° > φ < 0°). This phenomenon is called orientation (or dipolar) relaxation. It is expected that P(VDF)-based polymers could be the potential candidate for the FOC.

[0036] FIGS. 1A-1 F are partial schematic cross-sections of a plurality of fractional order capacitor (FOC) designs 100A-100F that may be fabricated according to certain embodiments of the present disclosure. FIG. 1A is a schematic of a partial cross- section of a structure 100a that comprises a substrate 102, a layer 104 comprising a dielectric to isolate the substrate 102 from the first metallic layer 106 is formed on the substrate 102, and the first metallic layer 106 is formed on the layer 104. In this example structure 100a, the substrate 102 may be silicon and the layer 104 may comprise SiO_2, the first metallic layer 106 is formed as a contiguous layer, e.g., formed as a sheet without holes or vias. In an embodiment the first metallic layer 106 may be of varying thicknesses, for example, from about 50nm to about 350 nm, and may be formed from platinum, gold, or other elements or combinations of elements suitable for the intended function of the FOC. In some embodiments, the first metallic layer 106 comprises multiple interlayers (not shown) of different materials. In one example, the first metallic layer 106 comprises an interlayer of titanium (Ti) formed on the layer 104 and a second layer of gold (Au) formed on the first interlayer of Ti. In an embodiment, dielectric layer 108 comprising the polymer interlayer structures discussed herein is formed on the first metallic layer 106, this dielectric layer may be from about 50nm thick to about 350nm thick.

[0037] In an embodiment, a second metallic layer 1 10 is formed on the dielectric layer 108. In the structure 100a, in contrast to the contiguous first metallic layer 106, the second metallic layer 1 10 is formed as a plurality of discreet sections 1 10a that may be referred to as a plurality of contacts 1 10a. While the cross-section of 1 10a shows 3 discreet contacts 1 10a, the total number of contacts (e.g., as visible from a top-view as discussed in FIGS. 2A-2F below) may vary depending upon the embodiment. Each contact 1 10a forms a capacitor such that a single structure may comprise from 1 - 24 capacitors, or more, depending upon the size (surface area) of the second metallic layer 1 10 and chip. [0038] In an embodiment, depending upon the material and thickness of the second dielectric layer 108, the plurality of contacts 1 10a of the second metallic layer 1 10 may be employed in order to apply less stress to the second dielectric layer 108, as opposed to the amount of stress created using a contiguous metallic layer. The use of the plurality of contacts 1 10a may aid in preserving the integrity (shape/size) of the second dielectric layer 108 during the assembly and operation of the structure 100a. Each contact 1 10a that comprises the second metallic layer 1 10 may be referred to as a capacitor.

[0039] FIG. 1 B is a schematic of a partial cross-section of a structure 100b that comprises a substrate 102 and an Si0₂ layer 104 formed on the substrate 102. In an embodiment, a first metallic layer 106 is formed on the S1O2 layer 104, and a second dielectric layer 108 comprising at least one of P, CP, or TP is formed on the first metallic layer 106. In an embodiment, a second metallic layer 1 12 is formed on the second dielectric layer 108. In the structure 100b, the second metallic layer 1 12 is formed as a contiguous layer, similarly to that of the first metallic layer 106. It is appreciated that the first 106 and second 1 12 metallic layers discussed in FIG. 1 B and otherwise herein may comprise the same or differing materials, and one or more metallic layer may comprise two or more interlayers as discussed herein.

[0040] The FIG. 1 B inset shows a magnified view of a portion of the example dielectric layer 108 comprising an interlayer structure of first layer 108a and second layer 108b. While the first layer 108a and second layer 108b are shown in the Inset as being of substantially similar thickness, in different embodiments, different thicknesses and numbers of layers may be used to form this interlayer structure, as discussed in more detail in FIGS. 4A-4D. In an embodiment, the dielectric layer 108 comprises a thickness from 2 pm to about 50 pm thick.

[0041] FIG. 1 C is a schematic of a partial cross-section of a structure 100c that comprises a substrate 102 and a S1O2 layer 104 formed on the substrate 102, and a first metallic layer 1 14 formed on the S1O2 layer 104. Similarly to the second metallic layer 1 10 discussed in FIG. 1A, the first metallic layer 1 14 in FIG. 1 C comprises a plurality of discreet sections 1 14A referred to as contacts 1 14A. The plurality of contacts 1 14A may be arranged in various manners as discussed herein. A second dielectric layer 108 comprising the interlayer structures of two or more polymers as discussed herein is formed on the first metallic layer 1 14. In some examples, masking or another process may be used to fabricate the dielectric layer 108 such that it is not in contact with the Si0₂ layer 104 when the second layer 108 is formed on the first metallic layer 1 14.

[0042] In an embodiment in the structure 100c, a second metallic layer 1 10 is formed on the S1O2 layer 104. In the structure 100c, the second metallic layer 1 10 is formed as a plurality of discreet sections 1 10a that may be referred to as a plurality of contacts 1 10a. These contacts 1 10a may be formed in a plurality of different arrangements, including arrays of contacts 1 10a where each contact 1 10a is not touching any other contacts 1 10a. In one example, an array of contacts 1 10a that comprises the second metallic layer 1 10 may be formed wherein each contact 1 10a is spaced equidistant from each adjacent contact. Each contact 1 10a that comprises the second metallic layer 1 10 may be referred to as a capacitor, and each contact 1 10a is aligned with each contact 1 14a.

[0043] FIG. 1 D is a schematic of a partial cross-section of a structure 100d that comprises a substrate 102, a Si0₂ layer 104 formed on the substrate 102, and a first metallic layer 1 14 formed on the Si0₂ layer 104. In this example, the first metallic layer 1 14 comprises a plurality of discreet sections 1 14a referred to as contacts 1 14a. The plurality of contacts 1 14a may be arranged in a similar manner to the contacts 1 10a, discussed above. A dielectric layer 108 that may comprise an interlayer structure formed from one or more layers of P, CP, and/or TP is formed on the first metallic layer 106. In an embodiment, a second metallic layer 1 12 is formed on the Si0₂ layer 104 as a contiguous layer, similarly to what is discussed herein with respect to FIG. 1 B.

[0044] FIG. 1 E is a schematic of a partial cross-section of a structure 100e that comprises a substrate 102, an S1O2 layer 104 formed on the substrate 102, a first metallic layer 1 14 is formed on the S1O2 layer 104, and comprises a plurality of discreet sections 1 14A referred to as contacts 1 14A. The plurality of contacts 1 14A may be arranged in a similar manner to the contacts 1 1 OA, discussed above. In FIG. 1 E, the example first metallic layer 1 14 comprises 5 contacts 1 14a, in contrast to the other examples of the layer 1 10 in FIGS. 1A, 1 C, and 1 D, each of which illustrate 3 contacts in the respective cross-sectional views. A dielectric layer 108 comprising the polymer interlayer structure discussed herein is formed on the first metallic layer 106. In an embodiment, a second metallic layer 1 12 is formed on the dielectric layer 104 as a contiguous layer, similarly to what is discussed herein with respect to FIG. 1 B.

[0045] FIG. 1 F is a schematic of a partial cross-section of a structure 10Of that comprises the first metallic layer 106 and the second metallic layer 1 12 with the dielectric layer 108 disposed in between the first 106 and the second 1 12 metallic layers. The dielectric layer 108, similarly to those discussed above, may comprise an interlayer structure of one or more of P, TP, and/or CP in various combinations. While varying thicknesses and relative thicknesses are illustrated in the figures herein, including FIGS. 1A-1 E, it is to be appreciated that both the metallic and dielectric layers discussed herein may comprise varying thicknesses among and between embodiments and that the first and second metallic layers in a single capacitor may comprise the same or different materials, and may be of the same or differing thicknesses, depending upon the embodiment.

[0046] FIGS. 2A-2F are schematic illustrations of a partial top-down view of structures comprising at least one FOC each and fabricated according to certain embodiments of the present disclosure. While what may be referred to herein as a second metallic layer is discussed in FIGS. 2A-2F and thus illustrated, it is to be appreciated that the first metallic layer may comprise a substantially similar structure such that each contact 1 10a discussed in FIGS. 2A-2F of the second metallic layer aligns with each contact of the first metallic layer (e.g., 1 14a in FIGS. 1 C, 1 D, and 1 E above) when the structure is fabricated.

[0047] As discussed in detail below, the metallic layers may take various forms including ordered and random (disordered) arrays. In an embodiment, the plurality of contacts 1 10a may be formed in a plurality of different arrangements, including ordered and random arrays of contacts 1 10a. An ordered array may be an array where each contact 1 10a is spaced equidistant from each adjacent contact 1 10a (see at least FIGS. 2A-2C below). A random (non-ordered) array may be an array where at least some of the contacts 1 10a are separated from adjacent contacts 1 10a by distances that are not equivalent across the array (see at least FIGS. 2D and 2E below). In either a random or an ordered array, each contact 1 10a is not in contact with (touching) any other contacts 1 10a in the same metallic layer 1 10.

[0048] In one example, the array of contacts 1 10a may be formed wherein each contact 1 10a is substantially the same size and/or shape as each of the other contacts 1 10a in the array of the second metallic layer 1 10. In another example, the array of contacts 1 10a may be formed wherein each contact 1 10a is spaced such that it is not equidistant from each adjacent contact. In another example, the array of contacts 1 10a that comprises the second metallic layer 1 10 may be formed wherein at least some contacts 1 10a are a different size and/or shape as compared to each of the other contacts 1 10a in the array of the second metallic layer 1 10. While the plurality of contacts 1 10 illustrated above in FIGS. 1A-1 F and FIG. 3 exhibit a dome-shaped cross section and may comprise a circular or elliptical shape when viewed perpendicular to the surface of the capacitor 1 10A, this is one illustrative example. As discussed further below, in alternate embodiments, the cross-sectional shapes may comprise polygons including squares and rectangles. In other embodiments, the second metallic layer 1 10 may comprise shapes, viewed perpendicular to the surface of the capacitor 1 1 OA, including triangles, irregular shapes, polygons, circles, ellipses, or combinations thereof.

[0049] For example, FIGS. 2A-2C are schematic illustrations of ordered arrays of contacts 1 10a in structures comprising the dielectric layers fabricated according to certain embodiments of the present disclosure. FIG. 2A illustrates an embodiment of an ordered array 200A of polygon-shaped contacts 1 10a. In this example array 200a taken from a top view as discussed herein, each contact 1 10a comprises a substantially similar shape and size and is spaced equidistant from an adjacent contact 1 10a, such that a distance 202 between a first contact 1 10a and a second contact 1 10a along the X-axis is the same as a distance 204 between a first contact 1 10a and a second contact 1 10a along the Y-axis. The directions of the X and Y axes discussed herein are illustrated in the legend 226.

[0050] FIG. 2B illustrates an embodiment of an ordered array 200b of elliptically- shaped contacts 1 10b. As used herein, an elliptically-shaped contact includes circular and oval shapes. In this example array 200B taken from a top view as discussed herein, each contact 1 10b is spaced about equidistant from an adjacent contact 1 10b, such that a distance 206 between a first contact 1 10b and a second contact 1 10b along the X-axis is the same as a distance 208 between a first contact 1 10b and a second contact 1 10b along the Y-axis. FIG. 2B comprises 16 contacts 1 10b, and thus 16 FOCs.

[0051] FIG. 2C illustrates an embodiment of an ordered array 200c of both elliptically and polygon-shaped contacts 1 10a and 1 10b. In this example array 200c taken from a top view as discussed herein, each contact 1 10a and 1 10b is spaced about equidistant from an adjacent contact 1 10a and/or 1 10b, such that a distance 210 between two adjacent contacts along the X-axis is the same as a distance 212 between the same contact and a different adjacent along the Y-axis. It is to be appreciated that, while various numbers of contacts 1 10a and 1 10b are used for illustrative purposes in at least FIGS. 2A-2F, this number may differ depending upon the embodiment, 16 FOCs are formed by the arrangement in FIG. 2C.

[0052] FIGS. 2D-2F are schematic illustrations of non-ordered arrays of contacts 1 10a. FIG. 2D illustrates an embodiment of an array 200d of polygon-shaped contacts 1 10a. In this example array 200d taken from a top view as discussed herein, each contact 1 10a comprises substantially similar shapes and sizes spaced from each adjacent contact 1 10a at a distance that's not equal. For example, such that a distance 214 between two adjacent contacts 1 10a along the X-axis is not the same as a distance 216 between the same contact and a different contact along the Y-axis.

[0053] FIG. 2E illustrates an embodiment of an array 200e of polygon and elliptically-shaped contacts 1 10a and 1 10b. In this example array 200e taken from a top view as discussed herein, each contact 1 10a and 1 10b is spaced from each adjacent contact 1 10a at a distance that's not equal. For example, such that a distance 218 between two adjacent contacts 1 10a and/or 1 10b along the X-axis is not equivalent to a distance 220 between the same contact 1 10a/1 10b and a different contact 1 10a/1 10b along the Y-axis.

[0054] FIG. 2F illustrates an embodiment of an array 200f of polygon-shaped contacts 1 10a of varying sizes. While the contact 1 10a shapes are shown in FIGS. 2A- 2E to be of substantially similar diameter, this may not always be the case. In this example array 200f taken from a top view as discussed herein, each contact 1 10a is spaced from each adjacent contact 1 10c at a distance that's not equal, and may be of a differing size (and shape, though not shown in FIG. 2F). For example, such that a distance 222 between two adjacent contacts 1 10a and/or 1 10c along the X-axis is not the same as a distance 224 between the same contact and a different contact along the Y-axis. It is to be appreciated that differently-sized and/or differently shaped contacts 1 10a and/or 1 10c may also be arranged in an ordered array, similarly to those shown in FIGS. 2A-2C. It is appreciated that the contacts 1 10a, 1 10b, 1 10c discussed herein may differ in size, shape, material, or other properties and characteristics depending upon the embodiment.

[0055] FIG. 3 illustrates an embodiment of a method 300 of fabricating a capacitor according to certain embodiments of the present disclosure. In the method 300, at block A, an S1O2 layer 304 is formed on a silicon (Si) substrate 302. At block B, a first metallic layer 306 is formed on the S1O2 layer 304. In one example, the first metallic layer 306 comprises gold, and in another example, the first metallic layer 306 may comprise platinum. In other examples, the metallic layer 306 comprises multiple interlayers of different materials including gold, titanium, and platinum. In one example, the metallic layer 306 comprises an interlayer of titanium (Ti) formed on the S1O2 layer 304 and a second layer of gold (Au) formed on the first interlayer of Ti. In an embodiment, the metallic layer 306 may comprise a total thickness from 50 nm to 250 nm. In the example where more than one metallic layer is combined to form the layer 306, a first interlayer may from 1 nm to 25nm thick.

[0056] In an embodiment, at blocks C1 and C2, a dielectric layer 308 is formed. At block C1 , a first layer 308a of an interlayer structure is formed on the metallic layer 306. The first layer 308a may be formed using drop-casting such that when the second layer 308b is formed at block C2 on the first layer 308a, the layers maintain their integrity as discreet and separate structures, e.g., there is no blending, mixing, or diffusion between the layers of the interlayer structures of the dielectric layers discussed herein. The first and second layers 308a and 308b may comprise substantially similar materials, concentrations, or thicknesses. In an alternate embodiment, the first and second layers 308a and 308b may differ in at least one of a thickness, a material, or a concentration (volume %) of the material in solution (solvent).

[0057] In some embodiments, the dielectric layer 308 formed at blocks C1 and C2 may be formed via a drop-casting process. Drop casting comprises forming a bubble of a material, e.g., the aqueous polymer solutions discussed herein, on top of a surface to be coated, such as the surface of the first metallic layer 306. The substrate 302 that comprises the first metallic layer 306 may then be spun or otherwise rotated/moved to spread the material of the bubble, and/or it may be held stationary to dry. The formation of the dielectric layer 308 at block C1 and C2 may comprise forming a bubble for each layer 308a and 308b of the interlayer structure of 308 as well as drying and/or rinsing, depending upon the embodiment. The first layer 308a is formed at block C1 and dried sufficiently as to not bleed into or mix with the second layer 308b. At block D, a second metallic layer 310 may be formed on the dielectric layer 308. As discussed in FIGS. 1A, 1 B, 1 D, 1 E, and 1 F the first metallic layer and/or second metallic layers (e.g., 106, 1 12, respectively in the various figures) may be each be formed as a single, contiguous layer or, as shown in FIGS. 1A and 1 C-1 E a plurality of individual contacts (1 10a or 1 14a, respectively) may be employed.

[0058] In one example, the structure formed at blocks A through D of FIG. 3 may be rotated at block E to be bonded via flip-chip bonding to a PCB board 312 at block F. The flip-chip bonding at blocks may comprise disposing a plurality of solder balls (not shown) on the second metallic layer 210 and rotating the structure 180 degrees a block E. At block F, the solder balls are re-melted to bond the structure formed at blocks A-D to a PCB board 212. In some embodiments, an electrically-insulating adhesive material may be employed to fill in any voids left by the soldering portion of the flip-bonding.

[0059] FIGS. 4A-4D are partial schematic cross-sections of FOCs fabricated according to embodiments of the present disclosure with varying thicknesses of the layers of the interlayer structure. In FIG. 4A, the structure 400a comprises a first metallic layer 402 and a second metallic layer 404. Formed in between the first 402 and second 404 metallic layers is a dielectric layer 412 that comprises a first interlayer 406 and a second interlayer 408. The first interlayer 406 is formed on the first metallic layer 402 and comprises a thickness T₄₀6, and the second interlayer 408 is formed on the first interlayer 406 and comprises a thickness T₄₀8- The dielectric layer 412 has a thickness T_{4 2} which is equal to the total of the sum of T₄₀6 and T₄₀8- In the example in FIG. 4A, the thickness T₄₀6 is less than the thickness T₄₀8. In various embodiments, the first layer 406 may comprise a different thickness, material, and/or concentration than the second layer 408, and in alternate embodiments, the layers 406 and 408 may comprise substantial similarities in at least one of thickness, material, or concentration. In this example, the interlayers 408 and 406 are illustrated as having thicknesses T₄₀6 and T₄₀8 such that the thickness ratio TR₄₀6 = T₄₀6 /( ₄₀6 + T₄₀8) is about 0.33. It is to be understood that this may be re-written as TR₄₀6 = T₄o6 / ( 412) It is appreciated that T₄₀6 + T₄o8 may also be expressed as c/₄i2, and that a thickness ratio may be defined in terms of a first or a second layer of an interlayer structure, and, in the example in FIG. 4A, the thickness ratio of the first layer 406 to the dielectric layer 412 is thus 0.33. Conversely, if the equation is revised to calculate the thickness ratio TR₄₀8 of the second layer 408 to the layer 412, the thickness ratio TR₄₀8 of the second layer 408 to the dielectric layer 412 is thus 0.67.

[0060] Alternate embodiments of the structure 400a are illustrated in FIGS. 4B-4C. In FIG. 4B, the interlayers 408 and 406 of the interlayer structure 400b are illustrated as having substantially similar thicknesses c/₄06 and cf₄08 such that the thickness ratio TR = T₄o6 / (T₄o6 and Τ₄₀δ) is about 0.50. In FIG. 4C, the interlayer structure 400c the interlayers 408 and 406 of the interlayer structure 400b are illustrated as having thicknesses T₄₀6 and T₄₀8 such that the thickness ratio TR₄₀6 = T₄₀6 / ( ₄₀6 + T₄₀8) is about 0.60. Conversely, if the equation is revised to calculate the thickness ratio of the second layer 408 to the layer 412, the thickness ratio TR₄₀8 of the second layer 408 to the dielectric layer 412 is thus 0.40. Depending upon the embodiment and desired end application, the thickness ratio of a layer of an interlayer structure to the thickness of the entire interlayer structure may range from about 0.05 to about 0.9. In various embodiments, the first layer 406 of the interlayer structure may be the thickest layer of the interlayer structure of the dielectric layer 412 and may be formed directly on the first metallic layer 402. The first layer 406 may be referred to as the "innermost" layer of interlayer structure of 412 since it is formed directly on the first metallic layer 402. Similarly, the second layer 408 may be referred to as the "outermost" layer of interlayer structure of 412 since it is the furthest layer of 406 and 408 from the first metallic layer 402. In alternate embodiments, the first layer 406 of the interlayer structure may be the thinnest layer of the interlayer structure of the dielectric layer 412 and may be formed directly on the first metallic layer 402.

[0061 ] In still other embodiments, more than two layers may be used to form the interlayer structure of the dielectric layer 412. FIG. 4D is an example of this structure. In FIG. 4, the dielectric layer 412 comprises a thickness T₄i₂ and is made up of a first layer 406 formed on the first metallic layer, a second layer 408 formed on the first layer 406, and a third layer 410 formed on the second layer 408. This trilayer structure is an example of a more-than-two-layer interlayer structure. As illustrated, each of the first (406), second (408), and third (410) layers of the dielectric layer 412 interlayer structure is associated with a thickness T₄₀6, T₄₀8, and T₄-i o, respectively. The thickness ratio of each layer may be determined by TR_Si_ngie = T_Singie/Tt₀tai, as discussed above, where TRsingie is the thickness ratio of a single layer to the entire structure, e.g., T_Si_ngie is a thickness of a single layer and d_totai is the thickness of the dielectric layer e.g., 412. While the example in FIG. 4D illustrates T₄₀6 > T₄₀8 > T_{4 0,} in other example, the layers of an interlayer structure that comprises more than 2 layers may be arranged in varying thicknesses and relative thicknesses such as to produce a desired property from the FOC or FOCs formed from the structure 400d. The first layer 406 may be referred to as the "innermost" layer of interlayer structure of 412 since it is formed directly on the first metallic layer 402. Similarly, the third layer 410 may be referred to as the "outermost" layer of interlayer structure of 412 since it is the furthest layer of 406 and 408 from the first metallic layer 402.

EXAMPLE Experimental Results: [0062] To fabricate the films, 200 mg each of polymers P, CP, and TP (CAS No. 24937-79-9) were mixed with the solvent Ν,Ν-Dimethylformamide (DMF) (CAS No. 68- 12-2), purchased from Sigma Aldrich. In an embodiment, a copolymer (CP), P(VDF- TrFE) (composition of 70/30 % mol) and terpolymer (TP), P(VDF-TrFE-CFE) (composition 60/30/10 % mol) were purchased from PiezoTech, France) was dissolved in the 2 ml DMF by constant stirring at room temperature to obtain 0.1 mg/ml solution of individual polymers. In this example, 200 mg was mixed with 2ml of DMF, but in other embodiments the ratio of dielectric material to solvent may be from 50 mg: 1 ml to 200 mg: 1 ml. A 10 nm Ti followed by a 190 nm-thick Au layer (first metallic layer) was deposited on Si/Si0₂ wafers via DC sputter to define bottom of the electrodes. To form the interlayer structure of the dielectric layer, a first polymer solution for a first layer of the interlayer structure was drop casted onto the Au-deposited, 2 cm χ 2 cm Si/Si0₂ wafers and dried for 12 hours at 80 °C under a vacuum. Subsequently, a second layer of the interlayer structure was also deposited directly onto first layer by following the similar method. The amount of polymer cast in the deposition of each layer of the interlayer structures is directly proportional to the thickness of the resulting films. For example, if a 250ml solution is cast, a film thickness resulting from that casting is about 25 micrometers thick, and if a 350ml solution is case, a film thickness resulting from that casting is about 35 ml thick.

[0063] The top Au electrode (second metallic layer) was formed comprising a plurality of contacts, each of which was a circle-shape with a diameter of about 3mm. The second metallic layer was deposited using a shadow mask, such that nine separated electrodes (contacts) were fabricated in the 2 cm χ 2 cm area. The sample was further flip-bonded on a PCB board with a design that an individual capacitor gives a separate connection for the electrical measurements.

[0064] FIG. 5 shows the normalized x-ray diffraction (XRD) spectra of P, TP, and TP- P bilayer films with different thickness ratios. In FIG. 5, P shows a single broad peak at 20.5° that corresponds to (200) and (1 10) crystal planes, whereas TP shows intense peaks at 18.2° followed by a 16.5° peak corresponding to (1 1 1 ) and (100) planes. The higher d spacing in TP may be due to the incorporation of TrFE-CFE molecules in P(VDF) chains. XRD confirmed that the peak intentisties of P and TP are proportional to thickness ratio of layers. No additional peaks are observed such that without forming any additional complex molecular structure in the interface. Nonetheless, the change in the microstructures in the interface, which are responsible for the change in dielectric properties such as polar conformation, could not be discarded.

[0065] In particular, FIG. 5 shows the normalized XRD spectra for P, TP, P-TP layers with thickness ratio: TR=0.5, TR=1 , and TR=2. XRD spectra are normalized with the main Au (1 1 1 ) peak at 38.3° as shown with star. The inset XRD patterns in FIG. 5 show 2Θ from 15 ⁰ to the 25° range, it is to be appreciated that there are inset shown here in order to more clearly illustrate the patterns for the samples tested.

[0066] Table 1 below shows the same identifiers as compared to the composition of the interlayer structures.

Table 1

[0067] FIG. 6A is a graph of the calculated and measured, φ, against frequency for P, CP, and TP and interlayer structures of TP-P, CP-P, and TP-CP where each layer of the respective interlayer (bilayer) structures has the same layer thickness ( d = 25 μιη ) as the other layer. FIG. 6B is a graph of the measured Z against frequency for P, CP, and TP and interlayer structures of TP-P, CP-P, and TP-CP where each layer of the respective interlayer (bilayer) structures has the same layer thickness ( d = 25 μτη ) as the other layer.

[0068] The effective phase angle of the bilayer is calculated by given equation

arg( _e ) = arg(Z_x + Z₂) (5)

where, Z, = - and Z, = - impedance values for the 1^st and the 2^nd layers of the interlayer structure, respectively.

[0069] An Agilent 4294A precision impedance analyzer was used to characterize the fabricated capacitors between 50 KHz and 10 MHz. The phase angle, φ, and the impedance, Z of the individual capacitors using P, CP, and TP and different configurations were measured. As shown in FIG. 6B, the constant phase zone (CPZ) is observed in the range between 150 kHz to 10 MHz. Within a defined CPZ, the observed CPAs are -83°, -77°, and -65° for P, CP, and TP, respectively. FIG. 3A illustrates that the measured φ, of bilayers for TP-P, TP-CP and CP-P are -77°,-74°, and -82°, are in agreement with the values calculated using equation (2) above. In particular, FIG. 6B shows the impedance Z versus frequency in logarithmic (log) scale. The slope in the line equations represents the exponent of the element constant, a. Explicitly, the values of a are 0.91 , 0.85 and 0.69, which gives a CPA of -82 °, -77°, and -65° for P, CP, and TP, respectively. Similarly the a values for bilayers; TP-P, TP-CP, and CP-P, 0.84, 0.79 and 0.88, which gives a CPA of -76, -72 and -78. The values of a from FIG. 2B confirm the measured CPA values given in FIG. 2A. Overall, the CPA for the bilayers lies in between that of their two constituent polymers. These results clearly show that a bilayer PVDF based polymer can be used for tuning the CPA during the FOC manufacturing process. While FIGS. 6A and 6B are associated with interlayer structures of a bilayer where each layer of the bilayer is of substantially similar thickness, interlayer structures with different thickness ratios are discussed below.

[0070] FIG. 7A shows the φ calculated using equation 2 as well as the measured φ against frequency for TP-P interlayer structures with different thickness ratios of TR=0, TR=0.33, TR=0.5, TR=0.66, and TR=1 .0. FIG. 7B shows the measured Z versus frequency for TP-P interlayer structures with different thickness ratios of TR=0, TR=0.33, TR=0.5, TR=0.66, and TR=1.0. Thus, the impedanceZ of each layer of an interlayer structure depends on the thickness layer oft/ and the overall impedance Z will also change with changing the thickness of layers.

[0071] In examples where other types of ferroelectric polymers are used, these indications may be any two different layers in an interlayer structure, respectively. As shown in FIG. 7A, the CPA values are increased from -83° to -81 °, -77°, -74°, -65° with increasing the thickness ratio of P from TR=0, TR=0.33, TR=0.5, TR=0.66 and TR=1.0 respectively. As shown in FIG. 7A, the calculated and measured CPA are well matched. Concomitant with FIG. 6B, the slope in the line equations represents the exponent of the element constant, a. The values of a in FIG. 7B confirm the measured CPA values in FIG. 7A.

[0072] FIG. 8 is a graph illustrating the CPA v. the thickness ratio for a P-TP interlayer structure. The slope of the line is indicated by a formula that indicates an example relationship between CPA and TR. Thus, the relationship between two or more layers in an interlayer structure, e.g., the thickness ratio, may be derived and used to tune an FOC during fabrication.

[0073] In another example, an FOC comprises a substrate; an S1O2 layer formed on the substrate; a metallic layer formed on the S1O2 layer; and a dielectric layer formed on the metallic layer and comprising an interlayer structure of at least two of ferroelectric poly(vinylidene fluoride) (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene) P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP"). In this example, the interlayer structure comprises at least two layers, wherein a first layer of the interlayer structure comprises a first composition, a first concentration, and a first thickness, and wherein a second layer of the interlayer structure comprises a second material, a second concentration, and a second thickness, and the first layer and the second layer differ in at least one of material, concentration, or thickness. The dielectric layer is selected from the group consisting essentially of: P and TP, CP and P, or TP and CP. In this example, the second metal layer may be electrically coupled to a printed-circuit board (PCB). The FOC comprises a predetermined phase angle a from -0.69 to -0.90 and a CPA Φ from 65.0 to 79.0.

[0074] In an embodiment method of fabricating a fractional-order capacitor, comprising: forming a first metallic layer on an S1O2 layer; forming a dielectric layer on the first metallic layer, wherein forming the dielectric layer comprises forming an interlayer structure of at least two layers, wherein each layer is selected from the group consisting of: poly(vinylidene fluoride) (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene) P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP"); and forming a second metallic layer on the dielectric layer. In an embodiment, forming the the dielectric layer comprises drop-casting. In this example, subsequent to forming the second metallic layer, electrically coupling the structure to a printed-circuit board (PCB). In an embodiment, forming the second metallic layer comprises forming an array of discreet metallic contacts, and the array comprises an ordered array of a plurality of uniform shapes, wherein each uniform shape of the plurality of uniform shapes is spaced about equidistant from at least one adjacent uniform shape. In some examples, the array comprises a plurality of shapes of at least two different geometries. In another example, the array comprises a non-ordered distribution of a plurality of shapes of at least two different geometries. [0075] In an embodiment method of fabricating a fractional-order capacitor, comprising: forming a first metallic layer on an S1O2 layer; forming a dielectric layer on the first metallic layer, wherein forming the dielectric layer comprises forming an interlayer structure of at least two layers, wherein each layer is selected from the group consisting of: poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride terpolymer P(VDF-TrFE-CFE) ("TP"); and forming a second metallic layer on the dielectric layer. In an embodiment, forming the the dielectric layer comprises drop- casting. In this example, subsequent to forming the second metallic layer, electrically coupling the structure to a printed-circuit board (PCB). In an embodiment, forming the second metallic layer comprises forming an array of discreet metallic contacts, and the array comprises an ordered array of a plurality of uniform shapes, wherein each uniform shape of the plurality of uniform shapes is spaced about equidistant from at least one adjacent uniform shape. In some examples, the array comprises a plurality of shapes of at least two different geometries. In another example, the array comprises a non- ordered distribution of a plurality of shapes of at least two different geometries.

[0076] Having described various devices and processes herein, specific aspects can include, but are not limited to:

[0077] In a first aspect, a fractional-order capacitor comprises: a first metallic layer formed on a Si0₂ layer; a dielectric layer formed on the first metallic layer, wherein the dielectric layer comprises an interlayer structure of at least two layers; and a second metallic layer formed on the dielectric layer.

[0078] A second aspect can include the fractional order capacitor of the first aspect, wherein the interlayer structure comprises at least two layers, wherein a first layer of the interlayer structure comprises a first material, a first concentration, and a first thickness, and wherein a second layer of the interlayer structure comprises a second material, a second concentration, and a second thickness, wherein the first layer and the second layer differ in at least one of material, concentration, or thickness.

[0079] A third aspect can include the fractional order capacitor of any of the first to second aspects, wherein the interlayer structure comprises at least two of ferroelectric poly(vinylidene fluoride) (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene) P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP"). [0080] A fourth aspect can include the fractional order capacitor of any of the first to third aspects, wherein at least one of the first metallic layer or the second metallic layer comprises a plurality of interlayers.

[0081] A fifth aspect can include the fractional order capacitor of any of the first to fourth aspects, wherein the first metallic layer comprises a first interlayer of titanium (Ti) formed on the S1O2 layer and a second interlayer of gold (Au) formed on the interlayer of Ti, wherein the dielectric layer is in contact with the second interlayer of Au.

[0082] A sixth aspect can include the fractional order capacitor of any of the first to fifth aspects, wherein forming the second metallic layer comprises forming an array of discreet metallic contacts.

[0083] A seventh aspect can include the fractional order capacitor of the sixth aspect, wherein each metallic contact of the array is spaced about equidistant from at least one adjacent metallic contact.

[0084] In an eighth aspect, a fractional-order capacitor comprises: a substrate; an Si0₂ layer formed on the substrate; a metallic layer formed on the Si0₂ layer; and a dielectric layer formed on the metallic layer and comprising an interlayer structure of at least two of ferroelectric poly(vinylidene fluoride) (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene) P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP").

[0085] A ninth aspect can include the method of the eighth aspect, wherein the interlayer structure comprises at least two layers, wherein a first layer of the interlayer structure comprises a first material, a first concentration, and a first thickness, and wherein a second layer of the interlayer structure comprises a second material, a second concentration, and a second thickness.

[0086] A tenth aspect can include the method of the ninth aspect, wherein the interlayer structure comprises at least two layers, wherein a first layer of the interlayer structure comprises a first material, a first concentration, and a first thickness, and wherein a second layer of the interlayer structure comprises a second material, a second concentration, and a second thickness.

[0087] An eleventh aspect can include the method of any of the eighth to tenth aspects, wherein the first layer and the second layer differ in at least one of material, concentration, or thickness. [0088] A twelfth aspect can include the method of any of the eighth to eleventh aspects, wherein the second metal layer is electrically coupled to a printed-circuit board (PCB).

[0089] A thirteenth aspect can include the method of any of the eighth to twelfth aspects, wherein the capacitor comprises a predetermined phase angle constant a from 0.69 to 0.90 and a CPA Φ from- 65.0 to -79.0.

[0090] In a fourteenth aspect, a method of fabricating a fractional-order capacitor, comprises: forming a first metallic layer on an S1O2 layer; forming a dielectric layer on the first metallic layer, wherein forming the dielectric layer comprises forming an interlayer structure of at least two layers, wherein each layer is selected from the group consisting of: poly(vinylidene fluoride) (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene) P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP"); and forming a second metallic layer on the dielectric layer.

[0091] A fifteenth aspect can include a method of the fourteenth aspect, further comprising, subsequent to forming the second metallic layer, electrically coupling the structure to a printed-circuit board (PCB).

[0092] A sixteenth aspect can include a method of any of the fourteenth to fifteenth aspects, wherein forming the second metallic layer comprises forming an array of discreet metallic contacts.

[0093] A seventeenth aspect can include a method of the sixteenth aspect, wherein the array comprises an ordered array of a plurality of uniform shapes, wherein each uniform shape of the plurality of uniform shapes is spaced about equidistant from at least one adjacent uniform shape.

[0094] An eighteenth aspect can include a method of the seventeenth aspect, wherein the array comprises a plurality of shapes of at least two different geometries.

[0095] A nineteenth aspect can include a method of the seventeenth aspect, wherein the array comprises a non-ordered distribution of a plurality of shapes of at least two different geometries.

[0096] A twentieth aspect can include a method of any of the fourteenth to nineteenth aspects, further comprising forming the dielectric layer via drop-casting.

[0097] For further details about fractional order capacitors, see U.S. Provisional Patent Application 62/487,466, filed this same day April 19, 2017, entitled, "Numerical Design of Fractional Order Capacitors," by Khaled Nabil Salama, et al.; U.S. Provisional Patent Application 62/487,467, filed this same day April 19, 2017, entitled, "Modeling a Fractional Order Capacitor Design," by Khaled Nabil Salama, et al., and U.S. Provisional Patent Application 62/487,468, filed this same day April 19, 2017, entitled, "Phase Angle Tunable Fractional-order Capacitors Including Poly (Vinylidene Fluoride)- based Polymers and Blends and Methods of Manufacture Thereof," by Khaled Nabil Salama, et al., which are hereby incorporated by reference, each in its entirety.

[0098] While several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted or not implemented.

[0099] Where numerical ranges or limitations are expressly stated, such express ranges or limitations should be understood to include iterative ranges or limitations of like magnitude falling within the expressly stated ranges or limitations (e.g., from about 1 to about 10 includes, 2, 3, 4, etc.; greater than 0.10 includes 0.1 1 , 0.12, 0.13, etc.). For example, whenever a numerical range with a lower limit, R|, and an upper limit, R_u, is disclosed, any number falling within the range is specifically disclosed. In particular, the following numbers within the range are specifically disclosed: R=Ri+k^*(R_u-Ri), wherein k is a variable expressed as a percent, for example, a weight or volume percent ranging from 1 percent to 100 percent with a 1 percent increment, i.e., k is 1 percent, 2 percent, 3 percent, 4 percent, 5 percent, 50 percent, 51 percent, 52 percent, 95 percent, 96 percent, 97 percent, 98 percent, 99 percent, or 100 percent. Moreover, any numerical range defined by two R numbers as defined in the above is also specifically disclosed

[00100] Also, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component, whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.

Claims

CLAIMS What is claimed is:

1. A fractional-order capacitor comprising:

a first metallic layer formed on a Si0₂ layer;

a dielectric layer formed on the first metallic layer, wherein the dielectric layer comprises an interlayer structure of at least two layers; and a second metallic layer formed on the dielectric layer.

2. The capacitor of claim 1 , wherein the interlayer structure comprises at least two layers, wherein a first layer of the interlayer structure comprises a first material, a first concentration, and a first thickness, and wherein a second layer of the interlayer structure comprises a second material, a second concentration, and a second thickness, wherein the first layer and the second layer differ in at least one of material, concentration, or thickness.

3. The capacitor of claim 1 , wherein the interlayer structure comprises at least two of ferroelectric poly(vinylidene fluoride) (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene) P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP").

4. The capacitor of claim 1 , wherein at least one of the first metallic layer or the second metallic layer comprises a plurality of interlayers.

5. The capacitor of claim 1 , wherein the first metallic layer comprises a first interlayer of titanium (Ti) formed on the S1O2 layer and a second interlayer of gold (Au) formed on the interlayer of Ti, wherein the dielectric layer is in contact with the second interlayer of Au.

6. The capacitor of claim 1 , wherein forming the second metallic layer comprises forming an array of discreet metallic contacts.

7. The capacitor of claim 6, wherein each metallic contact of the array is spaced about equidistant from at least one adjacent metallic contact.

8. A fractional-order capacitor comprising:

a substrate;

an S1O2 layer formed on the substrate;

a metallic layer formed on the S1O2 layer; and a dielectric layer formed on the metallic layer and comprising an interlayer structure of at least two of ferroelectric poly(vinylidene fluoride) (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene) P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF-TrFE-CFE) ("TP").

9. The capacitor of claim 8, wherein the interlayer structure comprises at least two layers, wherein a first layer of the interlayer structure comprises a first material, a first concentration, and a first thickness, and wherein a second layer of the interlayer structure comprises a second material, a second concentration, and a second thickness.

10. The capacitor of claim 9, wherein the first layer and the second layer differ in at least one of material, concentration, or thickness.

1 1 . The capacitor of claim 8, wherein the dielectric layer is selected from A group consisting essentially of: P and CP, TP and P, or TP and CP.

12. The capacitor of claim 8, wherein the second metal layer is electrically coupled to a printed-circuit board (PCB).

13. The capacitor of claim 8, wherein the capacitor comprises a predetermined phase angle constant a from 0.69 to 0.90 and a CPA Φ from- 65.0 to -79.0.

14. A method of fabricating a fractional-order capacitor, comprising:

forming a first metallic layer on an S1O2 layer;

forming a dielectric layer on the first metallic layer, wherein forming the dielectric layer comprises forming an interlayer structure of at least two layers, wherein each layer is selected from the group consisting of: poly(vinylidene fluoride) (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene) P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride trifluoroethylene chlorofluoroethylene P(VDF- TrFE-CFE) ("TP"); and

forming a second metallic layer on the dielectric layer.

15. The method of claim 14, further comprising, subsequent to forming the second metallic layer, electrically coupling the structure to a printed-circuit board (PCB).

16. The method of claim 14, wherein forming the second metallic layer comprises forming an array of discreet metallic contacts.

17. The method of claim 16, wherein the array comprises an ordered array of a plurality of uniform shapes, wherein each uniform shape of the plurality of uniform shapes is spaced about equidistant from at least one adjacent uniform shape.

18. The method of claim 17, wherein the array comprises a plurality of shapes of at least two different geometries.

19. The method of claim 17, wherein the array comprises a non-ordered distribution of a plurality of shapes of at least two different geometries.

20. The method of claim 14, further comprising forming the dielectric layer via drop- casting.