WO2018192243A1 - 显示驱动装置、显示驱动组件和显示设备 - Google Patents

显示驱动装置、显示驱动组件和显示设备 Download PDF

Info

Publication number
WO2018192243A1
WO2018192243A1 PCT/CN2017/115896 CN2017115896W WO2018192243A1 WO 2018192243 A1 WO2018192243 A1 WO 2018192243A1 CN 2017115896 W CN2017115896 W CN 2017115896W WO 2018192243 A1 WO2018192243 A1 WO 2018192243A1
Authority
WO
WIPO (PCT)
Prior art keywords
display
impedance matching
matching network
signal
signal lines
Prior art date
Application number
PCT/CN2017/115896
Other languages
English (en)
French (fr)
Inventor
陈平
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/072,227 priority Critical patent/US20200380902A1/en
Publication of WO2018192243A1 publication Critical patent/WO2018192243A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • H03H7/40—Automatic matching of load impedance to source impedance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • Embodiments of the present disclosure relate to the field of display, and in particular, to a display driving device, a display driving component, and a display device.
  • a low voltage differential signal (LVDS) generated by a signal source such as a video card is transmitted to the timing control integrated circuit IC in the display driving device.
  • the timing control IC converts the received signal into a display data signal and a display control signal and transmits it to the display driving integrated circuit IC to control the display operation of the display panel. Since the transmitted signal is a high frequency signal, a signal transmitted from the timing control IC to the display driving IC is reflected on the transmission line, causing signal oscillation on the transmission line.
  • a display driving apparatus including:
  • a display controller for generating a plurality of output signals, the display controller having a plurality of output ports for respectively outputting the generated plurality of output signals;
  • a display driver for generating a display signal based on at least a portion of the plurality of output signals output by the output port
  • a termination impedance matching network is coupled between the display controller and the display driver via a plurality of signal lines.
  • the display controller is connected to the display driver via at least one pair of signal lines of the plurality of signal lines, the termination impedance matching network including A sub-impedance matching network connected between two signal lines in each pair of signal lines.
  • the sub-impedance matching networks have the same impedance value.
  • the impedance value of the sub-impedance matching network is in a range of approximately 80 ohms to 85 ohms.
  • the sub-impedance matching network is at least one resistor.
  • the display controller and the display driver are arranged in an approximately T-shaped layout.
  • the termination impedance matching network is as close as possible to the corresponding display driver.
  • the display controller includes a timing control IC for receiving an external signal and converting the received external signal into the plurality of output signals.
  • the plurality of output signals are high frequency signals transmitted in the form of LVDS.
  • a display driver component including:
  • a display controller for generating a plurality of output signals, the display controller having a plurality of output ports for respectively outputting the generated plurality of output signals;
  • a display driver for generating a display signal according to at least a portion of the plurality of output signals output by the output port
  • the printed circuit board has a terminal impedance matching network, and the terminal impedance matching network is connected between the display controller and the display driver via a plurality of signal lines on the printed circuit board.
  • the display controller is located on a center line of the printed circuit board.
  • the display controller is located at a center of the printed circuit board.
  • the display controller and the display driver are arranged in an approximately T-shaped layout.
  • the termination impedance matching network is as close as possible to the corresponding display driver.
  • the display controller includes a timing control IC for receiving an external signal and converting the received external signal into the plurality of output signals.
  • the plurality of output signals are high frequency signals transmitted in the form of LVDS.
  • the display controller is connected to the display driver via at least one pair of signal lines of the plurality of signal lines, the termination impedance matching network including A sub-impedance matching network connected between two signal lines in each pair of signal lines.
  • the sub-impedance matching networks have the same impedance value.
  • the impedance value of the sub-impedance matching network is in a range of approximately 80 ohms to 85 ohms.
  • the sub-impedance matching network is at least one resistor.
  • a display device including a display according to an embodiment of the present disclosure Drive unit.
  • a display device including a display driving assembly according to an embodiment of the present disclosure.
  • FIG. 1 shows a schematic block diagram of a display driving device according to an exemplary embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of a terminal impedance matching network in accordance with an example embodiment of the present disclosure
  • FIG. 3 illustrates a schematic block diagram of a display driving device according to another exemplary embodiment of the present disclosure
  • FIG. 4 shows a schematic block diagram of a display drive assembly in accordance with an example embodiment of the present disclosure
  • FIG. 5 shows a schematic block diagram of a display driving assembly in accordance with another example embodiment of the present disclosure.
  • Impedance Discontinuity means that the signal suddenly encounters a small or no transmission line impedance at the end of the transmission line, which causes a reflected signal at this end position.
  • One way to eliminate this reflection is to connect a terminating resistor of the same magnitude as the characteristic impedance of the transmission line at the end of the transmission line to make the impedance of the transmission line continuous. Since the transmission of the signal on the transmission line is bidirectional, a terminating resistor of the same size can be bridged at the other end of the transmission line.
  • Impedance mismatch refers to the impedance mismatch between the data transceiver and the transmission line. The reflection caused by this reason mainly occurs when the communication line is in the idle mode, and the entire network data transmission is disordered. To reduce the effect of reflected signals on the communication line, noise suppression and the addition of bias resistors are often used.
  • the LVDS device is a high speed, low power circuit design.
  • LVDS features a current-driven mode and a low-voltage swing, which provides higher signal rates and uses differential transmission to reduce both signal and EMI.
  • an LVDS signal is generated by a constant current source at the system side, for example, the constant current source can be a 3.5 mA current source.
  • the current is then transmitted through a path of the differential signal line (e.g., the positive of the data signal) to, for example, a timing control IC in the display driver. Since the timing control IC exhibits high resistance to DC, the current produces a voltage of 350 mV.
  • the timing control IC After receiving the external signal such as LVDS/DP (Display Port), the timing control IC performs signal conversion to provide a timing control IC output signal.
  • the timing control IC output signal may include a data signal that drives the display panel and various control signals. In this conversion process, for example, the data transmission rate of the LVDS signal can be as high as 655 Mbps, and the data transmission rate of the output signal can be as high as 1.923 Gbps.
  • the timing control IC transmits data to the source driver IC in the form of LVDS.
  • the signal wavelength is relatively short with respect to the transmission line, so that the signal forms a reflected wave at the end of the transmission line, thereby interfering with the original signal.
  • the load capacity of some source driver ICs may be insufficient at the critical value, causing poor display conditions and occurrence of snowflake points or line defects.
  • reflection of signals reaching the end of the transmission line can be alleviated by adding a terminal impedance matching network.
  • a termination impedance matching network By adding a termination impedance matching network, it is possible to match the impedance between the signal source and the transmission line to reduce reflections and avoid oscillations, while reducing noise, reducing radiation and preventing overshoot.
  • FIG. 1 shows a schematic diagram of a display driving device according to an exemplary embodiment of the present disclosure.
  • a display driving apparatus 100 may include a display controller 101 for generating a plurality of output signals, and the display controller 101 has a plurality of output ports 101 1 to 101 4 Outputting the generated plurality of output signals respectively; display drivers 102 1 - 102 3 for generating display signals according to at least a part of the plurality of output signals outputted by the output ports 101 1 - 101 4 ; and a terminal impedance matching network 103 1 to 103 2 are connected between the display controller 101 and the display driver via a plurality of signal lines 104 1+ , 104 1- , 104 2+ , 104 2- .
  • FIG. 1 is exemplified by three display drivers and two terminal impedance matching networks.
  • display drive devices in accordance with embodiments of the present disclosure may include other numbers of display drivers and termination impedance matching networks.
  • display controller 101 may include a timing control IC, and the signals output by display controller 101 to display drivers 102 1 - 102 3 may include four parallel Mini-LVDS signals.
  • display drivers 102 1 - 102 3 may be source driver ICs.
  • the source driver IC receives and stores the high frequency LVDS signal from the display driver, and based on the turn-on of the gate drive scan line, converts the LVDS signal into a voltage to be output to the pixel electrode to drive the display panel to display an image desired.
  • the four signal lines may include two pairs of signal lines (104 1+ , 104 1- ) and (104 2+ , 104 2- ), and the image data to be displayed is transmitted in the form of a positive data signal and a negative data signal, respectively.
  • the signals output by the display controller 101 to the display drivers 102 1 - 102 3 may also include a horizontal data start signal STH, a horizontal clock signal CPH, and the like.
  • the display controller 101 can also output a control signal required for display such as a vertical data start signal STV, a vertical clock signal CPV, or the like to, for example, the gate drive IC. According to the embodiment shown in Fig.
  • display controller 101 and display drivers 102 1 - 102 3 are arranged in an "L-shaped" layout.
  • a termination impedance matching network is not provided for display driver 102 2 .
  • FIG. 2 shows a schematic diagram of the termination impedance matching network 103 of FIG.
  • the termination impedance matching networks 103 1 and 103 2 in FIG. 1 may have the same structure.
  • the signal line 104 may include a first signal line pair (104 1+ , 104 1- ) and a second signal line pair (104 2+ , 104 2- ).
  • the termination impedance matching network 103 may include sub-impedance matching networks 1031 and 1032 that are spanned between two signal lines in each pair of signal lines.
  • the sub-impedance matching networks 1031 and 1032 may respectively include, for example, a resistor R1 connected between the signal line 104 1+ and the signal line 104 1- in FIG. 2 and connected between the signal line 104 2+ and the signal line 104 2- Resistor R2.
  • the sub-impedance matching networks 1031 and 1032 may have the same impedance value as each other.
  • the resistance of the resistors R1 and R2 may range from about 80 ohms to 100 ohms, for example, may range from about 80 ohms to 85 ohms, for example, 82 ohms.
  • resistor R1 and resistor R2 are shown in the form of a single resistor in FIG. 2, resistor R1 and resistor R2 may be implemented as a parallel resistor network or other form, As long as the required impedance value can be achieved.
  • the form of a shunt resistor network can provide system stability, minimizing the impact on system performance even if a single resistor fails.
  • FIG. 3 shows a schematic block diagram of a display driving device according to another example embodiment of the present disclosure. Unlike the embodiment shown in FIG. 1, the embodiment shown in FIG. 3 provides a terminal impedance arrangement of an approximate "T-type" layout, and the lateral and vertical sides of the "T-type" in an approximate T-type network. Add a termination impedance matching network at the intersection.
  • the display driving device 300 may include a display controller 301 for generating a plurality of output signals, the display controller 301 having a plurality of output ports 301 1 - 301 4 outputs the plurality of output signals generated; display driver 3021 ⁇ 3023 for generating display signals based on at least a portion of the plurality of output signals output from the output port 301 1 to 3,014; and an impedance matching terminal
  • the networks 303 1 to 303 3 are connected between the display controller 301 and the display drivers 302 1 to 302 3 via a plurality of signal lines 304 1+ , 304 1- , 304 2+ , 304 2- .
  • three display drivers and three corresponding terminal impedance matching networks are taken as an example for description.
  • the display driving device may include other numbers of display drivers and terminal impedance matching networks, and set the terminal impedance matching network in one-to-one correspondence with the display drivers.
  • the signal outputted by the display controller 301 may be four parallel-connected Mini-LVDS signals, and the four signal lines 304 1+ , 304 1- , 304 2+ , and 304 2- are respectively carried
  • the video data is output on the left and right panels of the display panel.
  • the display controller 301 and the display drivers 302 1 to 302 3 are arranged in an approximately T-shaped layout.
  • the intersection of the lateral side and the vertical side of the "T-type" may not be limited to the "T-type”.
  • the midpoint of the lateral side, and the angle between the lateral side and the vertical side of the "T-shaped" is not limited to 90.
  • the terminal impedance matching networks 303 1 to 303 are provided in one-to-one correspondence with the display drivers 302 1 to 302 3 . 3 , and make the terminal impedance matching networks 303 1 - 303 3 as close as possible to the corresponding display drivers 302 1 - 302 3 .
  • parallel terminal impedance matching networks and signal lines can be utilized in the case of reducing parallel applications
  • the distributed capacitance and the input capacitance of the latter circuit weaken the edge of the signal to prevent overshoot.
  • the output driver of the timing control IC is increased, even if the source driver IC with weak output capability is used, It also does not cause the clock swing of the source driver IC to exceed the IC design specifications and improve electromagnetic interference.
  • the terminal impedance matching networks 303 1 to 303 3 may have the same structure as the terminal impedance matching network 103 of FIG. 2, respectively.
  • the terminal impedance matching networks 303 1 - 303 3 may respectively include sub-impedance matching networks 1031 and 1032 spanning between two signal lines in each pair of signal lines.
  • the sub-impedance matching networks 1031 and 1032 may respectively include a resistor R1 connected between the signal line 304 1+ and the signal line 304 1- and a resistor R2 connected between the signal line 304 2+ and the signal line 304 2- .
  • the impedance value of each of the sub-impedance matching networks may be in the range of about 80 ohms to 100 ohms, for example, in the range of about 80 ohms to 85 ohms.
  • the impedance value of each sub-impedance matching network can be approximately 82 ohms.
  • the display controller outputs four channels of data signals to the display driver as an example.
  • the number of signal lines can be based on the resolution of the display panel. It is of course possible to transmit a data signal using, for example, a 6-way (3-pair) signal line or an 8-way (4-pair) signal line to support, for example, a display panel having a resolution of Ultra High Definition 4K to display an image.
  • FIG. 4 shows a schematic block diagram of a display drive assembly in accordance with an example embodiment of the present disclosure.
  • the display driving component 400 may include: a printed circuit board 405; a display controller 401 for generating a plurality of output signals, the display controller 401 having a plurality of output ports a plurality of output signals 4011 - 4014 respectively outputs the generated; display driver 4021 ⁇ 4023 for generating display signals based on at least a portion of the plurality of output signals output from the output port 4011 ⁇ 4014 in;
  • the printed circuit board 405 is further provided with terminal impedance matching networks 4052 1 - 4052 2 , which are connected via a plurality of signal lines 4051 1+ , 4051 1- , 4051 2+ , 4051 2- on the printed circuit board.
  • the display controller 401 and the plurality of display drivers 402 1 - 402 3 are described
  • display controller 401 and display drivers 402 1 - 402 3 are arranged in an "L-shaped" layout.
  • a termination impedance matching network is not provided for display driver 402 2 .
  • FIG. 5 shows a schematic block diagram of a display driving assembly in accordance with another example embodiment of the present disclosure.
  • a display driving component 500 may include: a printed circuit board 505; a display controller 501 for generating a plurality of output signals, the display controller 501 having a plurality of outputs Ports 501 1 to 501 4 output a plurality of generated output signals; display drivers 502 1 to 502 3 for generating display signals based on at least a part of the plurality of output signals output from the output ports 501 1 to 501 4 ;
  • the printed circuit board 505 is further provided with a terminal impedance matching network 5052 1 - 5052 3 , which is connected to the display via a plurality of signal lines 5051 1+ , 5051 1- , 5051 2+ , 5051 2- on the printed circuit board. between the controller 501 and the display driver 502 from 1 to 5,023.
  • the embodiment shown in FIG. 5 provides a terminal impedance arrangement of an approximate "T-type" layout, and the lateral and vertical sides of the "T-shaped" of the approximate T-type network. Add a termination impedance matching network at the intersection.
  • the display controller 501 can be disposed on the center line of the printed circuit board 505.
  • the display controller 501 can be disposed at the center of the printed circuit board 505, and the display controller 501 and the display drivers 502 1 - 502 3 are arranged in an approximate "T-type" layout, which can more effectively eliminate the output of the high-frequency signal. Signal reflection in the communication line.
  • the intersection of the lateral side and the vertical side of the "T-shape” may not be limited to the midpoint of the "T-shaped” lateral side, and the angle between the lateral side of the "T-shaped” and the vertical side is not limited to 90 degrees.
  • the terminal impedance matching network can be as close as possible to the corresponding signal receiver, that is, the display driver, thereby more effectively matching the impedance between the signal source and the transmission line, reducing reflection and avoiding oscillation.
  • the display controller 501 is coupled to the display driver via at least one of the plurality of signal lines, the termination impedance matching network including A sub-impedance matching network connected between two signal lines in each pair of signal lines.
  • the sub-impedance matching network has the same impedance value.
  • the impedance value of the sub-impedance matching network may be in the range of about 80 ohms to 100 ohms, for example, in the range of about 80 ohms to 85 ohms, for example, the impedance value of the sub-impedance matching network may be It is about 82 ohms.
  • An embodiment of the present disclosure also provides a display device including the display driving device according to an embodiment of the present disclosure as described above.
  • Embodiments of the present disclosure also provide a display device including the display drive assembly according to an embodiment of the present disclosure as described above.
  • the display device may be any product or component having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.
  • reflection of signals reaching the end of the transmission line can be alleviated by adding a terminal impedance matching network.
  • the impedance between the signal source and the transmission line can be matched to reduce reflections, avoid oscillations, and at the same time reduce noise, reduce radiation, and prevent overshoot.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Dc Digital Transmission (AREA)

Abstract

一种显示驱动装置(100)、一种显示驱动组件以及显示设备。显示驱动装置(100)包括：显示控制器(101, 301, 401, 501)，用于产生多个输出信号，显示控制器具有多个输出端口(1011~1014, 3011~3014, 4011~4014, 5011~5014)来分别输出所产生的多个输出信号；显示驱动器(1021~1023, 3021~3023, 4021~4023, 5021~5023)，用于根据由输出端口(1011~1014, 3011~3014, 4011~4014, 5011~5014)输出的多个输出信号中的至少一部分来产生显示信号；以及终端阻抗匹配网络(1031~1032, 3031~3032, 4031~4032, 5031~5032)，经由多个信号线(1041+1041-、1042+、1042-, 3041+、3041-、3042+、3042-, 4041+、4041-、4042+、4042-, 5041+、5041-、5042+、5042-)连接在显示控制器(101)和显示驱动器(1021~1023, 3021~3023, 4021~4023, 5021~5023)之间。

Description

显示驱动装置、显示驱动组件和显示设备 技术领域
本公开的实施例涉及显示领域，具体地，涉及一种显示驱动装置、一种显示驱动组件和一种显示设备。
背景技术
在显示驱动装置中，由例如显卡等信号源产生的低压差分信号(Low Voltage Differential Signal，简称LVDS)被传输到显示驱动装置中的时序控制集成电路IC。时序控制IC将接收到的信号转换为显示数据信号和显示控制信号并传输到显示驱动集成电路IC以控制显示面板的显示操作。由于传输的信号是高频信号，从时序控制IC传输到显示驱动IC的信号会在传输线路上发生反射，从而导致传输线路上出现信号振荡。
发明内容
根据本公开实施例的一个方面，提出了一种显示驱动装置，包括：
显示控制器，用于产生多个输出信号，所述显示控制器具有多个输出端口来分别输出所产生的多个输出信号；
显示驱动器，用于根据由输出端口输出的多个输出信号中的至少一部分来产生显示信号；以及
终端阻抗匹配网络，经由多个信号线连接在所述显示控制器和所述显示驱动器之间。
根据本公开示例实施例，针对所述显示驱动器中的每一个，所述显示控制器经由所述多个信号线中的至少一对信号线与所述显示驱动器相连，所述终端阻抗匹配网络包括连接在每对信号线中的两个信号线之间的子阻抗匹配网络。
根据本公开示例实施例，所述子阻抗匹配网络具有相同的阻抗值。
根据本公开示例实施例，所述子阻抗匹配网络的阻抗值在大约80欧姆到85欧姆的范围内。
根据本公开示例实施例，所述子阻抗匹配网络是至少一个电阻器。
根据本公开示例实施例，所述显示控制器和所述显示驱动器按照近似T型布局排列。
根据本公开示例实施例，所述终端阻抗匹配网络尽可能地靠近对应的显示驱动器。
根据本公开示例实施例，所述显示控制器包括：时序控制IC，用于接收外部信号，并将接收到外部信号转换成所述多个输出信号。
根据本公开示例所述，所述多个输出信号是以LVDS形式传输的高频信号。
根据本公开实施例的另一方面。提供了一种显示驱动组件，包括：
印刷电路板；
显示控制器，用于产生多个输出信号，所述显示控制器具有多个输出端口来分别输出所产生的多个输出信号；
显示驱动器，用于根据由输出端口输出的多个输出信号中的至少一部分来产生显示信号；
其中，所述印刷电路板上具有终端阻抗匹配网络，所述终端阻抗匹配网络经由印刷电路板上的多个信号线连接在所述显示控制器和所述显示驱动器之间。
根据本公开示例实施例，所述显示控制器位于所述印刷电路板的中线上。
根据本公开示例实施例，所述显示控制器位于所述印刷电路板的中心。
根据本公开示例实施例，显示控制器和所述显示驱动器按照近似T型布局排列。
根据本公开示例实施例，所述终端阻抗匹配网络尽可能地靠近对应的显示驱动器。
根据本公开示例实施例，所述显示控制器包括：时序控制IC，用于接收外部信号，并将接收到外部信号转换成所述多个输出信号。
根据本公开示例所述，所述多个输出信号是以LVDS形式传输的高频信号。
根据本公开示例实施例，针对所述显示驱动器中的每一个，所述显示控制器经由所述多个信号线中的至少一对信号线与所述显示驱动器相连，所述终端阻抗匹配网络包括连接在每对信号线中的两个信号线之间的子阻抗匹配网络。
根据本公开示例实施例，所述子阻抗匹配网络具有相同的阻抗值。
根据本公开示例实施例，所述子阻抗匹配网络的阻抗值在大约80欧姆到85欧姆的范围内。
根据本公开示例实施例，所述子阻抗匹配网络是至少一个电阻器。
根据本公开实施例的另一方面，提供了一种显示设备，包括根据本公开实施例的显示 驱动装置。
根据本公开实施例的另一方面，提供了一种显示设备，包括根据本公开实施例的显示驱动组件。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，图中：
图1示出了根据本公开一个示例实施例的显示驱动装置的示意方框图；
图2示出了根据本公开一个示例实施例的终端阻抗匹配网络的示意图；
图3示出了根据本公开另一个示例实施例的显示驱动装置的示意方框图；
图4示出了根据本公开一个示例实施例的显示驱动组件的示意方框图；以及
图5示出了根据本公开另一个示例实施例的显示驱动组件的示意方框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
在通信过程中，通常存在两种原因会导致信号反射：阻抗不连续和阻抗不匹配。阻抗 不连续是指信号在传输线的末端突然遇到传输线阻抗很小甚至没有，则在这个末端位置会引起反射信号。消除这种反射的方法之一是在传输线的末端跨接一个与传输线的特性阻抗同样大小的终端电阻器，使传输线的阻抗连续。由于信号在传输线上的传输是双向的，因此在传输线的另一端可跨接一个同样大小的终端电阻器。阻抗不匹配是指数据收发器与传输线之间的阻抗不匹配。这种原因引起的反射主要发生在通信线路处在空闲方式时，整个网络数据传输混乱。要减弱反射信号对通信线路的影响，通常采用噪声抑制和添加偏置电阻器的方法。
LVDS器件是一种高速、低功耗的电路设计。LVDS的特点是电流驱动模式以及低电压摆幅，由此可以提供更高的信号传输率，使用差分传输方式可以同时减少信号噪声和电磁干扰EMI。在显示领域中，由系统端的一个恒流源产生LVDS信号，例如该恒流源可以是3.5mA电流源。然后，电流通过差分信号线的一路(例如数据信号正极)传输到例如显示驱动装置中的时序控制IC。由于时序控制IC对于直流表现为高阻，电流产生350mV的电压。同时，电流经过差分信号线的另一路(例如数据信号负极)流回电流源。时序控制IC接收到例如LVDS/DP(Display Port)的外部信号后，进行信号转换以便提供时序控制IC输出信号。时序控制IC输出信号可以包括驱动显示面板的数据信号和各种控制信号。在这个转换过程中，例如LVDS信号的数据传输速率可以高达655Mbps，输出信号的数据传输速率可以高达1.923Gbps。时序控制IC以LVDS形式将数据传输到源极驱动IC。在这种高频数据传输情况下，信号波长相对于传输线较短，因此信号在传输线的末端会形成反射波，从而干扰原信号。此外，随着时序控制IC的输出信号频率提高，有些源极驱动IC的带载能力在临界值时会出现驱动能力不足的情况，引起显示状况不佳，出现雪花点或线不良。
根据本公开实施例，可以通过增加终端阻抗匹配网络来缓解信号到达传输线末端的反射。通过增加终端阻抗匹配网络，能够匹配信号源和传输线之间的阻抗以减少反射、避免振荡，同时能够减少噪声、降低辐射并防止过冲。
图1示出了根据本公开一个示例实施例的显示驱动装置的示意图。如图1所示，根据本公开一个示例实施例的显示驱动装置100可以包括：显示控制器101，用于产生多个输出信号，所述显示控制器101具有多个输出端口1011～1014来分别输出所产生的多个输出信号；显示驱动器1021～1023，用于根据由输出端口1011～1014输出的多个输出信号中的至少一部 分来产生显示信号；以及终端阻抗匹配网络1031～1032，经由多个信号线1041+、1041-、1042+、1042-连接在所述显示控制器101和显示驱动器之间。为了便于演示，图1中以3个显示驱动器和2个终端阻抗匹配网络为例进行说明。本领域技术人员可以理解，根据本公开实施例的显示驱动装置可以包括其他数目的显示驱动器和终端阻抗匹配网络。
例如，在图1的示例中，显示控制器101可以包括时序控制IC，显示控制器101向显示驱动器1021～1023输出的信号可以包括4路并联的Mini-LVDS信号。例如，显示驱动器1021～1023可以是源极驱动IC。源极驱动IC接收并存储来自显示驱动器的高频LVDS信号，基于栅驱动扫描线的开启，将LVDS信号转换成要输出至像素电极的电压以驱动显示面板显示所需的图像。例如，4条信号线可以包括2对信号线(1041+，1041-)以及(1042+，1042-)，分别以正数据信号和负数据信号的形式传输要显示的图像数据。本领域技术人员可以理解，由显示控制器101向显示驱动器1021～1023输出的信号还可以包括水平数据开始信号STH和水平时钟信号CPH等。当然，显示控制器101还可以向例如栅极驱动IC输出显示面板进行显示所需的控制信号，例如垂直数据开始信号STV、垂直时钟信号CPV等。根据图1所示的实施例，显示控制器101和显示驱动器1021～1023按照“L型”布局排列。在图1中，没有针对显示驱动器1022设置终端阻抗匹配网络。利用该技术方案，能够节约空间并简化终端阻抗匹配网络的设计。
图2示出了图1中终端阻抗匹配网络103的示意图。图1中的终端阻抗匹配网络1031和1032可以具有相同的结构。如图2所示，信号线104可以包括第一信号线对(1041+，1041-)以及第二信号线对(1042+，1042-)。根据本公开实施例，终端阻抗匹配网络103可以包括跨接在每对信号线中的两个信号线之间的子阻抗匹配网络1031和1032。子阻抗匹配网络1031和1032可以分别包括例如图2中连接在信号线1041+和信号线1041-之间的电阻器R1以及连接在信号线1042+和信号线1042-之间的电阻器R2。
根据本公开实施例，子阻抗匹配网络1031和1032可以具有彼此相同的阻抗值。根据电阻计算公式，导体的电阻值R＝ρl/S，其中ρ是电阻材料的电阻率，l是电阻材料的长度，S是电阻材料的截面面积。因此，在相同的长度下，截面积越小，则阻值就越大。因此，如果电阻值R变大，在电阻率和线长都是固定的情况下，需要调整S，S越小则R越大，S太小则会考验印刷电路板PCB的制程能力。考虑到PCB的制程能力，在图2所示的情况下， 电阻器R1和R2的阻值可以在大约80欧姆～100欧姆的范围内，例如可以在大约80欧姆～85欧姆的范围内，例如可以是82欧姆。此外，本领域技术人员可以理解，尽管图2中将电阻器R1和电阻器R2示出为单个电阻器的形式，然而可以将电阻器R1和电阻器R2实现为并联电阻器网络或其他形式，只要能够实现所需的阻抗值即可。同时，并联电阻器网络的形式能够提供系统稳定性，即使单个电阻器出现故障，也能够尽可能地减小对于系统性能的影响。
图3示出了根据本公开另一个示例实施例的显示驱动装置的示意方框图。与图1所示的实施例不同，图3所示的实施例提供了一种近似“T型”布局的终端阻抗排列方式，并且在近似T型网络中“T型”的横边与竖边交叉处增加终端阻抗匹配网络。
如图3所示，根据本公开另一个示例实施例的显示驱动装置300可以包括：显示控制器301，用于产生多个输出信号，所述显示控制器301具有多个输出端口3011～3014来分别输出所产生的多个输出信号；显示驱动器3021～3023，用于根据由输出端口3011～3014输出的多个输出信号中的至少一部分来产生显示信号；以及终端阻抗匹配网络3031～3033，经由多个信号线3041+、3041-、3042+、3042-连接在所述显示控制器301和显示驱动器3021～3023之间。图3中以3个显示驱动器和对应3个终端阻抗匹配网络为例进行说明。本领域技术人员可以理解，根据本公开实施例的显示驱动装置可以包括其他数目的显示驱动器和终端阻抗匹配网络，并且与显示驱动器一一对应地设置终端阻抗匹配网络。
类似地，在图3的示例中，显示控制器301输出的信号可以是4路并联的Mini-LVDS信号，4条信号线3041+、3041-、3042+、3042-分别承载要在显示面板的左半面板和右半面板的输出的视频数据。根据图3所示的实施例，显示控制器301和显示驱动器3021～3023按照近似T型”布局排列。例如，“T型”的横边与竖边的交叉可以不限于“T型”横边的中点，且“T型”的横边与竖边的夹角不限于90。在图3中，与显示驱动器3021～3023一一对应地设置终端阻抗匹配网络3031～3033，并使得终端阻抗匹配网络3031～3033尽可能靠近对应的显示驱动器3021～3023。利用该技术方案，能够在减少并联应用的情况下，利用并联的终端阻抗匹配网络和信号线的分布电容以及后级电路的输入电容，消弱信号边沿的陡峭程度，防止过冲。同时，在时序控制IC的输出频率增大的情况下，即使采用输出能力较弱的源极驱动IC，也不会使源极驱动IC的时钟摆幅值超出IC设计规格，同时能够改善电磁干扰。
根据本实施例，终端阻抗匹配网络3031～3033可以分别具有与图2中的终端阻抗匹配网络103相同的结构。终端阻抗匹配网络3031～3033可以分别包括跨接在每对信号线中的两个信号线之间的子阻抗匹配网络1031和1032。子阻抗匹配网络1031和1032可以分别包括连接在信号线3041+和信号线3041-之间的电阻器R1以及连接在信号线3042+和信号线3042-之间的电阻器R2。其中每个子阻抗匹配网络的阻抗值可以在大约80欧姆～100欧姆的范围内，例如可以在大约80欧姆～85欧姆的范围内。例如，每个子阻抗匹配网络的阻抗值可以是大约82欧姆。
图1至图3中均以显示控制器向显示驱动器输出4路数据信号为例进行描述。本领域技术人员可以理解，信号线的数目可以基于显示面板的分辨率。当然可以采用例如6路(3对)信号线或8路(4对)信号线来传输数据信号，以支持例如分辨率为超高清4K的显示面板来显示图像。
根据本公开实施例，还提供了一种显示驱动组件。图4示出了根据本公开一个示例实施例的显示驱动组件的示意方框图。如图4所示，根据本公开一个示例实施例的显示驱动组件400可以包括：印刷电路板405；显示控制器401，用于产生多个输出信号，所述显示控制器401具有多个输出端口4011～4014来分别输出所产生的多个输出信号；显示驱动器4021～4023，用于根据由输出端口4011～4014输出的多个输出信号中的至少一部分来产生显示信号；其中，所述印刷电路板405上还设置有终端阻抗匹配网络40521～40522，经由印刷电路板上的多个信号线40511+、40511-、40512+、40512-连接在所述显示控制器401和多个显示驱动器4021～4023之间。
例如，在图4的示例中，显示控制器401和显示驱动器4021～4023按照“L型”布局排列。在图4中，没有针对显示驱动器4022设置终端阻抗匹配网络。利用该技术方案，能够节约空间并简化终端阻抗匹配网络的设计。
图5示出了根据本公开另一个示例实施例的显示驱动组件的示意方框图。如图5所示，根据本公开另一个示例实施例的显示驱动组件500可以包括：印刷电路板505；显示控制器501，用于产生多个输出信号，所述显示控制器501具有多个输出端口5011～5014来输出所产生的多个输出信号；显示驱动器5021～5023，用于根据由输出端口5011～5014输出的多个输出信号中的至少一部分来产生显示信号；其中，所述印刷电路板505上还设置有终端阻 抗匹配网络50521～50523，经由印刷电路板上的多个信号线50511+、50511-、50512+、50512-连接在显示控制器501和显示驱动器5021～5023之间。
与图4所示的实施例不同，图5所示的实施例提供了一种近似“T型”布局的终端阻抗排列方式，并且在近似T型网络的“T型”的横边与竖边的交叉处增加终端阻抗匹配网络。显示控制器501可以设置在印刷电路板505的中线上。例如，显示控制器501可以设置在所述印刷电路板505的中心处，显示控制器501和显示驱动器5021～5023按照近似“T型”布局排列，可更有效消除输出的高频信号在通信线路中的信号反射。例如，“T型”的横边与竖边的交叉可以不限于“T型”横边的中点，且“T型”的横边与竖边的夹角不限于90度。终端阻抗匹配网络可以尽量靠近对应的信号接收器，即显示驱动器，由此可以更有效匹配信号源和传输线之间的阻抗，减少反射，避免振荡。
与参考图2所述的相似，针对显示驱动器5021～5023中的每一个，显示控制器501经由所述多个信号线中的至少一对信号线与显示驱动器相连，终端阻抗匹配网络包括连接在每对信号线中的两个信号线之间的子阻抗匹配网络。子阻抗匹配网络具有相同的阻抗值。考虑到印刷电路板的制程能力，子阻抗匹配网络的阻抗值可以在大约80欧姆～100欧姆的范围内，例如可以在大约80欧姆～85欧姆的范围内，例如子阻抗匹配网络的阻抗值可以是大约82欧姆。
本公开实施例还提供了一种显示设备，其包括如上所述根据本公开实施例的显示驱动装置。
本公开实施例还提供了一种显示设备，其包括如上所述根据本公开实施例的显示驱动组件。
根据本公开实施例的显示设备可以是电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
根据本公开实施例，通过增加终端阻抗匹配网络可以缓解信号到达传输线末端的反射。通过增加终端阻抗匹配网络并适当设置终端阻抗匹配网络的数目和位置，能够匹配信号源和传输线之间的阻抗以减少反射、避免振荡，同时能够减少噪声、降低辐射并防止过冲。
尽管已经参考本公开的典型实施例，具体示出和描述了本公开，但本领域普通技术人 员应当理解，在不脱离所附权利要求所限定的本公开的精神和范围的情况下，可以对这些实施例进行形式和细节上的多种改变。

Claims (22)

  1. 一种显示驱动装置，包括：
    显示控制器，用于产生多个输出信号，所述显示控制器具有多个输出端口来分别输出所产生的多个输出信号；
    显示驱动器，用于根据由输出端口输出的多个输出信号中的至少一部分来产生显示信号；以及
    终端阻抗匹配网络，经由多个信号线连接在所述显示控制器和所述显示驱动器之间。
  2. 根据权利要求1所述的显示驱动装置，其中，针对所述显示驱动器中的每一个，所述显示控制器经由所述多个信号线中的至少一对信号线与所述显示驱动器相连，所述终端阻抗匹配网络包括连接在每对信号线中的两个信号线之间的子阻抗匹配网络。
  3. 根据权利要求2所述的显示驱动装置，其中，所述子阻抗匹配网络具有相同的阻抗值。
  4. 根据权利要求3所述的显示驱动装置，其中，所述子阻抗匹配网络的阻抗值在大约80欧姆到85欧姆的范围内。
  5. 根据权利要求3所述的显示驱动装置，其中，所述子阻抗匹配网络包括至少一个电阻器。
  6. 根据权利要求1-5之一所述的显示驱动装置，其中，所述显示控制器和所述显示驱动器按照近似T型布局排列。
  7. 根据权利要求1-5之一的所述的显示驱动装置，其中，所述终端阻抗匹配网络尽可能地靠近对应的显示驱动器。
  8. 根据权利要求1所述显示驱动装置，其中，所述显示控制器包括：时序控制IC，用于接收外部信号，并将接收到外部信号转换成所述多个输出信号。
  9. 根据权利要求8所述的显示驱动装置，其中，所述多个输出信号是以LVDS形式传输的高频信号。
  10. 一种显示驱动组件，包括：
    印刷电路板；
    显示控制器，用于产生多个信号，所述显示控制器具有多个输出端口来分别输出所产生的多个信号；
    显示驱动器，用于根据由输出端口输出的多个信号中的至少一部分来产生显示信号；
    其中，所述印刷电路板上具有终端阻抗匹配网络，所述终端阻抗匹配网络经由印刷电路板上的多个信号线连接在所述显示控制器和所述显示驱动器之间。
  11. 根据权利要求10所述的显示驱动组件，其中，所述显示控制器位于所述印刷电路板的中线上。
  12. 根据权利要求11所述的显示驱动组件，其中，所述显示控制器位于所述印刷电路板的中心。
  13. 根据权利要求10-12之一所述的显示驱动组件，其中，所述显示控制器和所述显示驱动器按照近似T型布局排列。
  14. 根据权利要求10-12之一的所述的显示驱动组件，其中，所述终端阻抗匹配网络尽可能地靠近对应的显示驱动器。
  15. 根据权利要求10所述显示驱动组件，其中，所述显示控制器包括：时序控制IC，用于接收外部信号，并将接收到外部信号转换成所述多个输出信号。
  16. 根据权利要求15所述的显示驱动组件，其中，所述多个输出信号是以LVDS形式传输的高频信号。
  17. 根据权利要求10所述的显示驱动组件，其中，针对所述显示驱动器中的每一个，所述显示控制器经由所述多个信号线中的至少一对信号线与所述显示驱动器相连，所述终端阻抗匹配网络包括连接在每对信号线中的两个信号线之间的子阻抗匹配网络。
  18. 根据权利要求17所述的显示驱动组件，其中，所述子阻抗匹配网络具有相同的阻抗值。
  19. 根据权利要求18所述的显示驱动组件，其中，所述子阻抗匹配网络的阻抗值在大约80欧姆到85欧姆的范围内。
  20. 根据权利要求18所述的显示驱动组件，其中，所述子阻抗匹配网络是至少一个电阻器。
  21. 一种显示设备，包括如权利要求1-9之一所述的显示驱动装置。
  22. 一种显示设备，包括如权利要求10-20之一所述的显示驱动组件。
PCT/CN2017/115896 2017-04-21 2017-12-13 显示驱动装置、显示驱动组件和显示设备 WO2018192243A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/072,227 US20200380902A1 (en) 2017-04-21 2017-12-13 Display driving apparatus, display driving component, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710268846.7A CN108735179B (zh) 2017-04-21 2017-04-21 显示驱动装置、显示驱动组件和显示装置
CN201710268846.7 2017-04-21

Publications (1)

Publication Number Publication Date
WO2018192243A1 true WO2018192243A1 (zh) 2018-10-25

Family

ID=63856193

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/115896 WO2018192243A1 (zh) 2017-04-21 2017-12-13 显示驱动装置、显示驱动组件和显示设备

Country Status (3)

Country Link
US (1) US20200380902A1 (zh)
CN (1) CN108735179B (zh)
WO (1) WO2018192243A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109451651A (zh) * 2018-10-23 2019-03-08 惠科股份有限公司 一种电路板的差分走线及电路板
US11663994B2 (en) * 2019-07-03 2023-05-30 Magnachip Semiconductor, Ltd. Chip solution device for driving display panel comprising display driving integrated circuit (IC) and display control IC
CN113674667A (zh) * 2021-08-09 2021-11-19 Tcl华星光电技术有限公司 显示装置及移动终端

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447156A (zh) * 2007-11-29 2009-06-03 三星电子株式会社 显示设备及其驱动方法
CN101521492A (zh) * 2008-02-29 2009-09-02 瑞昱半导体股份有限公司 阻抗匹配电路及其相关方法
US20100085368A1 (en) * 2008-10-07 2010-04-08 Shin Ock Chul Timing controller capable of removing surge signal and display apparatus including the same
KR101008969B1 (ko) * 2010-03-05 2011-01-17 (주)아이에스피 엘이디 통합 제어장치
CN102651193A (zh) * 2011-09-06 2012-08-29 京东方科技集团股份有限公司 Led显示驱动器及显示设备
CN105427785A (zh) * 2014-09-17 2016-03-23 联发科技股份有限公司 用于动态刷新率切换的处理器与相关电子装置及方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100780715B1 (ko) * 2001-12-11 2007-11-30 엘지.필립스 엘시디 주식회사 액정 패널의 구동장치
CN103337233B (zh) * 2013-06-09 2016-03-30 京东方科技集团股份有限公司 显示驱动芯片、显示驱动芯片组件、显示装置
CN103702164B (zh) * 2014-01-07 2018-01-16 深圳创维－Rgb电子有限公司 一种超高清信号中转装置及网络机顶盒

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447156A (zh) * 2007-11-29 2009-06-03 三星电子株式会社 显示设备及其驱动方法
CN101521492A (zh) * 2008-02-29 2009-09-02 瑞昱半导体股份有限公司 阻抗匹配电路及其相关方法
US20100085368A1 (en) * 2008-10-07 2010-04-08 Shin Ock Chul Timing controller capable of removing surge signal and display apparatus including the same
KR101008969B1 (ko) * 2010-03-05 2011-01-17 (주)아이에스피 엘이디 통합 제어장치
CN102651193A (zh) * 2011-09-06 2012-08-29 京东方科技集团股份有限公司 Led显示驱动器及显示设备
CN105427785A (zh) * 2014-09-17 2016-03-23 联发科技股份有限公司 用于动态刷新率切换的处理器与相关电子装置及方法

Also Published As

Publication number Publication date
CN108735179A (zh) 2018-11-02
US20200380902A1 (en) 2020-12-03
CN108735179B (zh) 2020-06-30

Similar Documents

Publication Publication Date Title
US8390604B2 (en) Differential signaling system and flat panel display with the same
JP3828652B2 (ja) 差動信号伝送回路
WO2018192243A1 (zh) 显示驱动装置、显示驱动组件和显示设备
US8154538B2 (en) Differential signaling system and flat panel display with the same
US8018446B2 (en) Differential signaling system and display using the same
US10957270B1 (en) GOA circuit and liquid crystal display device having the same
JP2011242737A (ja) チップオングラス方式の液晶表示装置
JP2003333109A (ja) 多様ｒｓｄｓ−ｌｖｄｓ−ミニｌｖｄｓ−ｂｌｖｄｓ差動信号インターフェース回路
TWI459360B (zh) 自動調整訊號偏移的源極驅動裝置
US8279206B2 (en) Differential signaling system and flat panel display with the same
CN107481674B (zh) 显示设备
JP2006317828A (ja) 表示装置およびタイミングコントローラ
US11357100B2 (en) Data transmission circuit board, mobile industry processor interface and device
TWI407421B (zh) 用於驅動一液晶顯示面板之驅動裝置
WO2021103138A1 (zh) 一种驱动电路及液晶显示装置
CN103413516B (zh) 数据传输装置、数据传输方法及显示装置
US20090079716A1 (en) Apparatus for driving a display panel, display device having the apparatus for driving a display panel and information processing apparatus having the display device
US11839026B2 (en) Circuit board assembly, display apparatus, terminal, and signal processing system
WO2020093447A1 (zh) 一种显示装置的驱动电路
US7701453B2 (en) Driving device and related image transmission device of a flat panel display
US8964118B2 (en) Display signal processing system, circuit board, and liquid crystal display
WO2015172481A1 (zh) 时序控制器的信号频率的设定装置、方法以及显示设备
US11705049B2 (en) Differential signal interface and display device adopting the differential signal interface
CN101494040B (zh) 用于驱动一液晶显示面板的驱动装置
TW201019307A (en) Source driver and liquid crystal display device having the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17906388

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17906388

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03.04.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 17906388

Country of ref document: EP

Kind code of ref document: A1