WO2018191958A1

WO2018191958A1 - Tft array substrate, display panel and display device

Info

Publication number: WO2018191958A1
Application number: PCT/CN2017/081454
Authority: WO
Inventors: 韩超
Original assignee: 深圳市柔宇科技有限公司
Priority date: 2017-04-21
Filing date: 2017-04-21
Publication date: 2018-10-25
Also published as: CN108474987A

Abstract

A thin film transistor (TFT) array substrate, comprising: a plurality of gate lines (G1-Gn), the plurality of gate lines being used for connecting to a gate driving chip (2) by means of a corresponding lead (Y1-Yn); the width of each of the plurality of gate lines (G1-Gn) gradually increases from an end (P1) which is connected to the corresponding lead (Y1-Yn) to another end (P2) which is far from said corresponding lead (Y1-Yn). Also disclosed are a display panel and a display device. Display uniformity may be improved by means of configuring the shape of the gate lines (G1-Gn) as a specific shape.

Description

TFT array substrate, display panel and display device

Technical field

The present invention relates to a panel, and more particularly to a display panel and a display device having the same.

Background technique

At present, the large size of the display and the ultra-clearness are a trend. LCD (liquid crystal display) displays and OLED (organic light-emitting diode) displays have been widely used due to their small footprint and good display performance. At present, most display panels, such as most LCD display panels and OLED display panels, are driven by TFT (thin film transistor) arrays. However, as display size, display resolution, and refresh rate increase, the RC delay of the TFT array becomes a very large limiting factor. In particular, for a display panel of a 1G1D (single-sided row and column driver chip), the RC delay of a pixel farther from the panel driving chip is more serious, resulting in unevenness on the display screen.

Summary of the invention

The embodiment of the invention discloses a TFT array substrate, a display panel and a display device, which can effectively reduce the image caused by the RC delay of the TFT array and improve the display uniformity of the display screen.

The TFT array substrate disclosed in the embodiment of the present invention includes a plurality of gate lines respectively connected to a gate driving chip through corresponding leads, and any one of the gate lines is defined and described The first end of the lead electrically connected and the second end remote from the first end, the cross-sectional area of the second end of any one of the gate lines is larger than the cross-sectional area of the first end of the gate line.

The display panel disclosed in the embodiment of the invention includes a TFT array substrate and a gate driving chip. The TFT array substrate includes a plurality of gate lines, and the plurality of gate lines are respectively connected to a gate driving chip through corresponding leads. And any one of the gate lines is defined with a first end electrically connected to the lead and a second end remote from the first end, and a cross-sectional area of the second end of any one of the gate lines is greater than The cross-sectional area of the first end of the gate line.

The display device disclosed in the embodiment of the invention includes a display panel, the display panel includes a TFT array substrate and a gate driving chip, the TFT array substrate includes a plurality of gate lines, and the plurality of gate lines Connected to a gate driving chip through corresponding leads, each of the gate lines defining a first end electrically connected to the lead and a second end remote from the first end, any one of the A cross-sectional area of the second end of the gate line is greater than a cross-sectional area of the first end of the gate line.

In the TFT array substrate, the display panel, and the display device of the present invention, by setting the shape and size of the gate lines, the display uniformity of the display screen can be improved.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings to be used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

1 is a schematic view of a TFT array substrate in accordance with an embodiment of the present invention.

2 is a schematic view of a TFT array substrate in another embodiment of the present invention.

3 is a more complete schematic diagram of a TFT array substrate in accordance with an embodiment of the present invention.

4 is a block diagram showing the structure of a display panel in accordance with an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a display panel in accordance with an embodiment of the present invention.

FIG. 6 is a block diagram showing the structure of a display device according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Please refer to FIG. 1, which is a schematic diagram of a TFT array substrate 1 according to an embodiment of the present invention. Figure 1 As shown, the TFT array substrate 1 includes a plurality of gate lines G1-Gn connected to a gate driving chip 2 through corresponding leads Y1-Yn, respectively. Each of the plurality of gate lines G1-Gn defines a first end P1 electrically connected to the corresponding lead and a second end P2 away from the first end P1. That is, each of the plurality of gate lines G1-Gn includes an opposite first end P1 and a second end P2, and the first end P1 is electrically connected to the corresponding lead. The cross-sectional area of the second end P2 of any one of the plurality of gate lines G1-Gn is larger than the cross-sectional area of the first end P1 of the gate line. In the present application, the cross-sectional area of the second end P2 and the first end P1 refers to an extending direction perpendicular to the gate lines G1-Gn (ie, when a current flows through the gate lines G1-Gn) The area of the cross section of the flow direction). In other words, the second end P2 of any one of the plurality of gate lines G1-Gn is thicker than the first end P1.

The portion of each of the gate lines G1-Gn that is more severely delayed is generally located away from the second end P2 that is electrically connected to the leads. In the present application, since the cross-sectional area of the second end P2 of each gate line is larger than the cross-sectional area of the first end P1, the delay of the gate line itself can be reduced, thereby balancing the visual effect and reducing the unevenness of the display. Sex.

In some embodiments, a cross-sectional area of any one of the plurality of gate lines G1-Gn is gradually increased from the first end P1 to the second end P2.

As shown in FIG. 1, in some embodiments, the thickness of the plurality of gate lines G1-Gn is equal from the first end P1 to the second end P2, and any one of the plurality of gate lines G1-Gn a width of the second end P2 of one of the plurality is greater than a width of the first end P1, such that a cross-sectional area of the second end P2 of any one of the plurality of gate lines G1-Gn is larger than the gate The cross-sectional area of the first end P1 of the polar line.

In other embodiments, the widths of the plurality of gate lines G1-Gn are equal from the first end P1 to the second end P2, and the second of any one of the plurality of gate lines G1-Gn The thickness of the end P2 is greater than the thickness of the first end P1, and the cross-sectional area of the second end P2 of any one of the plurality of gate lines G1-Gn may be made larger than the first end of the gate line. The cross-sectional area of P1.

As shown in FIG. 1 , further, in this embodiment, the first end P1 of each of the gate lines and the second end P2 of the adjacent gate lines are located on the same side of the TFT array substrate 1 . Thereby, the leads Y1-Yn are alternately electrically connected to the gate lines G1-Gn in order from the both sides of the TFT array substrate 1 in a direction away from the gate driving chip 2. Thus, the RC delay is more serious The two ends P2 are alternately arranged on both sides of the TFT array substrate 1 in the arrangement direction along the gate lines G1-Gn, thereby making the RC delay phenomenon distribution of the TFT array substrate 1 more balanced, so that The display is more balanced.

It can be understood that in other embodiments, the second ends P2 of two adjacent gate lines may also be located on the same side of the TFT array substrate 1. Although the display effect when the second ends P2 of the two adjacent gate lines are all on the same side is not as good as the second terminals P2 are alternately arranged on both sides of the TFT array substrate 2, but each gate is better. The cross-sectional area of the second end P2 of the wire is larger than the cross-sectional area of the first end P1, and the display effect has been improved.

In some embodiments, as shown in FIG. 1 , the gate line G1 is disposed adjacent to the gate driving chip 2, and the plurality of gate lines G1-Gn are sequentially away from the gate driving chip 2 from bottom to top. Settings.

A cross-sectional area of at least one second end P2 relatively far from the gate line of the gate driving chip 2 is larger than a cross-sectional area of at least one second end P2 relatively close to a gate line of the gate driving chip 2.

That is, the cross-sectional area of the second end P2 of the at least one gate line is closer to at least one of the gate lines G1-Gn as the distance from the gate driving chip 2 increases. The second end P2 of the gate line of the gate driving chip 2 has a larger cross-sectional area.

For example, as shown in FIG. 1, in some embodiments, in a case where the thicknesses of the plurality of gate lines G1-Gn from the first end P1 to the second end P2 are the same, the plurality of gate lines G1 The width of the second end P2 of -Gn gradually increases as the distance between the plurality of gate lines G1-Gn and the gate driving chip 2 increases. Thereby, the cross-sectional area of the second end P2 of the plurality of gate lines G1-Gn gradually increases as the distance between the plurality of gate lines G1-Gn and the gate driving chip 2 increases.

In other embodiments, the cross-sectional area of the second end P2 of the plurality of gate lines G1-Gn increases as the distance between the plurality of gate lines G1-Gn and the gate driving chip 2 increases. It is a stepwise increase. For example, the cross-sectional areas of the second ends P2 of the gate lines G1-G3 are equal, and the cross-sectional areas of the second ends P2 of the gate lines G4-G5 are equal and larger than the second ends P2 of the gate lines G1-G3. The cross-sectional area, the cross-sectional area of the second end P2 of the gate lines G6-G7 is equal and larger than the cross-sectional area of the second end P2 of the gate lines G4-G5, and the like.

Since the RC delay farthest from the gate driving chip 2 is the most severe, the larger the cross-sectional area of the second end P2 of the gate line farther from the gate driving chip 2, the effect of the RC delay is further reduced.

In some embodiments, the first ends P1 of the plurality of gate lines G1-Gn have substantially the same cross-sectional area.

In some embodiments, at least one lead wire that is relatively connected to the gate line of the gate driving chip 2 has a cross-sectional area that is larger than at least one of the leads that are relatively close to the gate line of the gate driving chip 2 Cross-sectional area. That is, the plurality of gate lines G1-Gn have at least a cross-sectional area of the leads connected to the first end P1 of the at least one gate line as the distance from the gate driving chip 2 increases. A lead wire connected to the first end P1 of the gate line closer to the gate driving chip 2 has a larger cross-sectional area.

Wherein, in the present application, the cross-sectional area of the plurality of leads Y1-Yn refers to the area of the cross section perpendicular to the extending direction of the plurality of leads Y1-Yn.

For example, as shown in FIG. 1, the plurality of leads Y1-Yn have the same thickness from the gate driving chip 2 to the corresponding gate lines G1-Gn, and are respectively connected to the plurality of gate lines G1-Gn. The width of the leads Y1-Yn gradually increases as the distance between the correspondingly connected gate lines G1-Gn and the gate driving chip 2 increases. Therefore, as the distance between the plurality of gate lines G1-Gn and the gate driving chip 2 increases sequentially, the plurality of gate lines G1-Gn are in one-to-one correspondence with the horizontal lines of the connected leads Y1-Yn. The cross-sectional area also increases in one-to-one correspondence.

In other embodiments, as the distance between the plurality of gate lines G1-Gn and the gate driving chip 2 increases, the plurality of gate lines G1-Gn correspond to the crossing of the connected leads Y1-Yn. The cross-sectional area is increasing in a stepwise manner. For example, the cross-sectional areas of the leads Y1-Y3 to which the gate lines G1-G3 are connected are equal, and the cross-sectional areas of the leads Y4-Y5 to which the gate lines G4-G5 are connected are equal and larger than the gate lines G1-G3. The cross-sectional area of the connected leads Y1-Y3, the cross-sectional areas of the leads Y6-Y7 to which the gate lines G6-G7 are connected are equal and larger than the cross-sectional area of the leads Y4-Y5 to which the gate lines G4-G5 are connected ,and many more.

As shown in FIG. 1 , in an embodiment, the first side S1 of the plurality of gate lines G1-Gn parallel to the extending direction of the plurality of gate lines G1-Gn is planar, and the opposite second side S2 is curved, and at least one arcuate second side S2 of the gate line opposite to the gate driving chip 2 has an arc greater than at least one gate line relatively close to the gate driving chip 2 The curvature of the second side S2 of the curved surface. That is, as the distance between the plurality of gate lines G1-Gn and the gate driving chip 2 increases, the curvature of the second side S2 of the at least one gate line is closer to the gate than at least one of the gates The second side S2 of the gate line of the pole drive chip 2 has a larger arc.

In some embodiments, the curvature of the curved second side S2 of the plurality of gate lines G1-Gn is between the plurality of gate lines G1-Gn and the gate driving chip 2 The distance increases and gradually increases. That is, the plurality of gate lines G1-Gn have an arc shape, and as the distance between the plurality of gate lines G1-Gn and the gate driving chip 2 increases, the plurality of strips The curvature of the second side S2 of the gate lines G1-Gn also gradually increases.

In other embodiments, as the distance between the plurality of gate lines G1-Gn and the gate driving chip 2 increases, the plurality of gate lines G1-Gn are curved on the second side S2. The curvature increases in a stepwise manner. For example, the curvature of the second side S2 of the gate line G1-G3 is equal, and the curvature of the second side S2 of the gate line G4-G5 is equal and larger than the curvature of the gate line G1-G3. The curvature of the second side S2, the gate line G6-G7 is equal to the second side S2 of the curved surface and larger than the curvature of the second side S2 of the curved surface of the gate line G4-G5, and the like.

As shown in FIG. 1, the second side S2 of the adjacent ones of the plurality of gate lines G1-Gn is oppositely disposed, or is disposed opposite to the first side S1 of the plane.

The first side S1 of the plurality of gate lines G1-Gn specifically refers to a surface parallel to the extending direction of the plurality of gate lines G1-Gn and perpendicular to the plane of the TFT array substrate 1.

Thereby, the leads Y1-Yn connecting the gate lines G1-Gn are gradually thickened or stepped thick according to the increase of the distance of the gate lines G1-Gn away from the gate driving chip 2, so that the connection is farthest from the gate. The lead Yn of the gate line Gn of the driving chip 2 is the thickest, and the influence of the RC delay can be further reduced.

As shown in FIG. 2, in another embodiment, the third side S3 of the plurality of gate lines G1-Gn parallel to the extending direction of the plurality of gate lines G1-Gn is planar, and the third side S3 The opposite fourth side S4 is a sloped surface at an angle to the third side S3, and the at least one fourth side S4 relatively far from the gate line of the gate driving chip 2 is opposite to the third side S3 The angle is greater than an angle of at least one of the fourth side S4 of the gate line relatively close to the gate driving chip 2 with respect to the third side S3.

In some embodiments, an angle of the fourth side S4 of the plurality of gate lines G1-Gn with respect to the third side S3 along with the plurality of gate lines G1-Gn and the gate driving chip 2 The distance between them increases gradually. That is, as shown in FIG. 2, the plurality of gate lines G1-Gn are one horizontally trapezoidal shape, and along with the gate lines G1-Gn and the gate driving chip 2 The increase of the distance, the angle of the fourth side S4 of the plurality of gate lines G1-Gn relative to the third side S3 The degree is also gradually increased, so that the width variation of the gate lines G1-Gn is also gradually increased.

In other embodiments, the angle of the fourth side S4 of the plurality of gate lines G1-Gn relative to the third side S3 along with the plurality of gate lines G1-Gn and the gate driving chip The distance between 2 increases and increases in a stepwise manner. For example, for example, the fourth side S4 of the gate lines G1-G3 is equal to the angle of the third side S3, and the fourth side S4 of the gate line G4-G5 is equal to the angle of the third side S3 and larger than The angle of the fourth side S4 of the gate lines G1-G3 with respect to the third side S3, the fourth side S4 of the gate lines G6-G7 is equal to the angle of the third side S3 and larger than the gate line The angle of the fourth side S4 of G4-G5 with respect to the third side S3, and so on.

As shown in FIG. 2, the fourth side S4 of the adjacent gate lines of the plurality of gate lines G1-Gn is oppositely disposed, or the third side S3 of the straight plane is oppositely disposed.

Similarly, the third side S1 of the plurality of gate lines G1-Gn specifically refers to a surface parallel to the extending direction of the plurality of gate lines G1-Gn and perpendicular to the plane of the TFT array substrate 1.

Obviously, in other embodiments, the plurality of gate lines G1-Gn may have other shapes as long as the width of one end of the access lead to the other end is gradually increased.

Please refer to FIG. 3, which is a more complete schematic diagram of the TFT array substrate 1 in an embodiment. As shown in FIG. 3, the TFT array substrate 1 further includes a plurality of source lines D1-Dm parallel to each other, and the plurality of gate lines G1-Gn and the plurality of source lines D1-Dm are disposed perpendicular to each other. As shown in FIG. 3, the TFT array substrate 1 further includes a plurality of TFT transistors T1, and each of the TFT transistors T1 is disposed at an intersection J1 between any one of the gate lines and the source line, and The gate line and the source line are electrically connected. Here, only one TFT transistor T1 is illustrated in FIG.

The plurality of source lines D1-Dm are also connected to a source driving chip 3. The TFT array substrate 1 is driven by the gate driving chip 2 to turn on the corresponding TFT transistor T1, and a driving voltage is applied to the opened TFT transistor T1 under the driving of the source driving chip 3 to realize display driving.

Wherein, in some embodiments, the widths of the plurality of source lines D1-Dm are consistent in the extending direction, that is, the width is the same. In other embodiments, the width of each of the plurality of source lines D1-Dm may also be set as the front gate lines G1-Gn. In the present application, the shape of the source lines D1-Dm is not limited.

Please refer to FIG. 4 , which is a structural block diagram of the display panel 100 in some embodiments. In the embodiment, the display panel 100 is an LCD (liquid crystal display) display panel. Specific The display panel 100 includes the TFT array substrate 1 and the color filter substrate 4 . The display panel 100 further includes a gate driving chip 2 and the source driving chip 3 connected to the TFT array substrate 1.

Please refer to FIG. 5 , which is a schematic cross-sectional view of the display panel 100 . As shown in FIG. 5 , the color filter substrate 4 is located above the TFT array substrate 1 , and the color filter substrate 4 is used to issue the TFT array substrate 1 . The light is color-filtered to achieve a color display effect.

It can be understood that in other embodiments, the display panel 100 can also be an OLED (organic light-emitting diode) display panel. In this case, the color filter substrate 4 can be omitted.

Please refer to FIG. 6 , which is a structural block diagram of a display device 200 including the display panel 100 . The display device 200 is an LCD display or an OLED display, or may be an electronic device such as a mobile phone, a tablet computer, a television set or the like including an LCD display panel or an OLED display panel.

Obviously, the display device 200 may also include other components, which are not described herein because they are not related to the improvement of the present invention.

Thus, in the present invention, by setting the shape and arrangement of the gate lines G1-Gn, and/or further to the leads Y1-Yn between the gate lines G1-Gn and the gate driving chip 2 The thickness is set to effectively reduce the unevenness displayed on the display panel 100.

The above is a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. It is the scope of protection of the present invention.

Claims

A TFT array substrate includes a plurality of gate lines respectively connected to a gate driving chip through corresponding leads, and any one of the gate lines is defined to be electrically connected to the leads The first end and the second end away from the first end are characterized in that a cross-sectional area of the second end of any one of the gate lines is larger than a cross-sectional area of the first end of the gate line.
The TFT array substrate according to claim 1, wherein a cross-sectional area of the gate line is gradually increased from the first end to the second end.
The TFT array substrate according to claim 1, wherein the plurality of gate lines are sequentially disposed in a direction gradually away from the gate driving chip, and at least one gate relatively distant from the gate driving chip The cross-sectional area of the second end of the line is greater than the cross-sectional area of at least one second end of the gate line that is relatively close to the gate drive chip.
The TFT array substrate according to claim 1 , wherein at least one of the leads connected to the gate line of the gate driving chip has a cross-sectional area that is larger than at least one gate that is relatively close to the gate driving chip. The pole line corresponds to the cross-sectional area of the connected leads.
The TFT array substrate according to claim 1, wherein the first side of the plurality of gate lines parallel to the extending direction of the plurality of gate lines is planar, and the opposite second side is curved. And at least one arcuate second side of the gate line relatively far from the gate driving chip has an arc greater than at least one of the arcuate faces of the gate line of the gate driving chip The curvature of the two sides.
The TFT array substrate according to claim 1, wherein the third side of the plurality of gate lines parallel to the extending direction of the plurality of gate lines is planar, and the opposite fourth side is The third side is at an angled oblique side, and the angle of the fourth side of the at least one gate line relatively far from the gate driving chip is greater than the third side is closer to the gate driving chip. An angle of the fourth side of the gate line relative to the third side.
The TFT array substrate according to claim 1, wherein the first end of each of the gate lines and the second end of the adjacent gate line are on the same side of the TFT array substrate.
A display panel, comprising the array substrate according to any one of claims 1-7.
The display panel according to claim 8, wherein the display panel is an organic light emitting diode display panel.
A display device, characterized in that the display device comprises the display panel according to claim 9.