Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
  • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0003—Details of control, feedback or regulation circuits
  • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0003—Details of control, feedback or regulation circuits
  • H02M1/0029—Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
  • H02M1/096—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the power supply of the control circuit being connected in parallel to the main switching element
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/06—Modifications for ensuring a fully conducting state
  • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/16—Modifications for eliminating interference voltages or currents
  • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
  • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
  • H03K17/163—Soft switching
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
  • H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load

Definitions

• the present disclosure relates to transistor-based switches and, more particularly, to slew control for a high-side switch.
• High-side switches can be used to drive a variety of loads, and therefore can be used in a number of different applications.
• Typical systems and methods for driving a high-side switch utilize a charge-pump.
• a charge-pump is a DC to DC converter that uses capacitors as energy- storage elements to create either a higher- or lower-voltage power source.
• the charge-pump is relied on to supply other circuit components (such as amplifiers) in addition to supplying a DC current for driving the high-side switch. This method necessitates the use of large capacitors within the charge-pump to supply DC load currents. Large capacitors can take up valuable surface area if an on-chip integrated solution is required.
• high-side switches include three main elements: a pass element, a gate-control block, and an input logic block.
• the pass element is usually a transistor which is typically a metal-oxide-semiconductor field-effect transistor (MOSFET) or a laterally diffused metal oxide semiconductor transistor (LDMOS).
• MOSFET metal-oxide-semiconductor field-effect transistor
• LDMOS laterally diffused metal oxide semiconductor transistor
• the pass element operates in the linear region to pass the current from a power source to a load.
• the gate-control block provides a voltage to the gate of the pass element to switch it "on” or “off.”
• the input logic block interprets the on/off signal and triggers the gate control block to switch the pass element "on” or “off.”
• slew rate is defined as the change of voltage per unit of time. Exceeding a circuit's slew rate can cause signal distortion. Also, exceeding the slew rate can cause an increased amount of electromagnetic emissions (EME), thereby violating electromagnetic compatibility (EMC) standards, and potentially disturbing other electronic devices. Accordingly, the slew rate can place significant limitations on the operation of a corresponding circuit. Adding current limiters can provide some control over slew rate, but this solution still requires the use of a large charge pump.
• FIG. 1 is a circuit-level schematic of a known system and method for driving a high- side switch with additional current limiters.
• a charge-pump 2 is connected to a current controller 4.
• the current controller 4 includes an amplifier 6 and a transistor 10.
• the transistor 10 used is a p-channel metal-oxide semiconductor (pMOS).
• the current controller 4 is supplied by the charge-pump 2 and controls an output based on the voltage difference resulting from resistors 12, 24.
• the positive rail of the amplifier 6 is powered by the charge-pump 2 and the negative rail of the amplifier 6 is powered by a supply voltage 8.
• a current sensing resistor 12 is connected between the charge-pump 2 and the amplifier 6.
• a current-sensing FET 14 is connected between the amplifier 6 and an output pin 18.
• a high- side switch FET 16 has the drain side connected to the charge-pump 2, the gate side is connected to the output of the amplifier 6, via transistor 10, and the source side is connected to the output pin 18.
• the output pin 18 is used to connect the system to a circuit load 20.
• a resistor 32 is connected between the gate side and the source side of the FET 16.
• the circuit further includes a clock generator 22.
• a resistor 24 is connected between the charge-pump 2 and the amplifier 6.
• the circuit further includes a load reference 26.
• a FET 28 is connected in series with a resistor 30 for when the high-side switch FET 16 is turned “off.”
• Current limiters 34 are used to provide some control over the slew rate of the high-side switch FET 16. Still referring to FIG. 1, the charge-pump 2 needs to deliver a significant output current due to its connection to the amplifier 6 and the high-side switch FET 16. Quickly charging the
• the charge-pump 2 includes relatively large capacitors, making it difficult to integrate the circuit of FIG. 1 onto a single chip. Large integrated capacitors increase the silicon die size and thereby product cost. Should the large capacitors be extemally located, additional pins become necessary, and any extemal capacitors may increase the BOM cost, therefore increasing the cost of the overall system. Controlling the slew rate of the high-side switch FET 16 with the current limiters 34 results in the need for a large charge-pump 2.
• An exemplary circuit for slew rate control for a high-side switch comprises a sample and level-shift circuit.
• the sample and level-shift circuit is connected to the high-side switch.
• the circuit further comprises a sampling capacitor, and the sampling capacitor is configured to sample an input voltage corresponding to the sample and level-shift circuit.
• the circuit includes a charge-limiting mechanism, implementable as a circuit.
• the sampling capacitor is configured to charge a gate capacitance of the high-side switch.
• the charge-limiting mechanism is configured to limit a rate of charge transferred to the gate capacitance of the high-side switch per unit of time.
• An exemplary method for controlling a slew rate of a high-side switch comprises supplying an input current to a sample and level-shift circuit.
• the method further includes sampling an input voltage.
• a sampling capacitor is configured for the sampling of the input voltage.
• the method includes level-shifting the input voltage.
• the method includes charging a gate capacitance of the high-side switch using the sampling capacitor. Further, the method includes limiting a charge supplied to the sampling capacitor, the charge limited by at least one current sink.
• FIG. 1 is a circuit-level schematic of a known system and method for driving a high- side switch with current limiters.
• FIG. 2 is a circuit-level schematic of one embodiment of a system and method for controlling the slew rate of a high-side switch in accordance with the present disclosure.
• FIG. 3 is a circuit-level schematic of another embodiment of a system and method for controlling the slew rate of a high-side switch in accordance with the present disclosure.
• FIG. 4 is a circuit-level schematic of another embodiment of a system and method for controlling the slew rate of a high-side switch in accordance with the present disclosure.
• FIG. 5 is a circuit-level schematic of another embodiment of a system and method for controlling the slew rate of a high-side switch in accordance with the present disclosure.
• Embodiments of the present disclosure provide a system and a method for controlling the slew rate of a high-side switch, the high-side switch for use in selectively providing power to an output load.
• FIG. 2 is a circuit-level schematic of one embodiment of a system and method for controlling a slew rate of a high-side switch in accordance with the present disclosure.
• a sample and level-shift circuit 40 may be provided.
• the sample and level-shift circuit 40 may be connected to a voltage supply 42.
• the voltage supply 42 may be the output of an amplifier (for example, an operational amplifier). Alternatively, the voltage supply 42 may supply a fixed or variable supply voltage.
• the sample and level-shift circuit 40 may include a plurality of switches 50, 52, 54, 56.
• the sample and level-shift circuit 40 may further include a sampling capacitor 58.
• the sample and level-shift circuit 40 may include a field-effect transistor (FET) 60.
• FET field-effect transistor
• a slew control 80 may include current sinks 82, 84, 86 that may be connected in parallel. The slew control 80 may be connected in parallel with the FET 60.
• a high-side switch 70 may be an n- channel metal-oxide semiconductor field-effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor (nLDMOS transistor).
• nMOS transistor n-channel metal-oxide semiconductor field-effect transistor
• nLDMOS transistor n-channel laterally diffused metal oxide semiconductor transistor
• One output of the sample and level-shift circuit 40 may be connected to the gate side of the high-side switch 70.
• the drain side of the high- side switch 70 may be connected to a voltage supply 48.
• the output pin 72 may be connected to a circuit load.
• a low-side switch may be included and
• the sample and level-shift circuit 40 may eliminate a need for a charge-pump when driving the high-side switch 70.
• the sampling capacitor 58 may sample the voltage of the voltage supply 42.
• the sampling capacitor 58 may then be used to charge the gate side capacitance of the high-side switch 70.
• the charging of the gate side capacitance may enable the high-side switch 70 to turn “on. "
• an input voltage may be supplied to a circuit load.
• the gate capacitance of the high-side switch 70 may serve as a holding capacitor. Accordingly, there may be no DC loading required for a holding capacitor.
• the sample and level-shift circuit 40 may not provide any DC current.
• an explicit hold capacitor may be connected in parallel to the gate capacitance of the high-side switch 70. Again, there may be no DC loading required for a holding capacitor.
• the voltage supplies 48, 42 may supply a fixed voltage, as opposed to having charge-pump power amplifiers. In situations where an amplifier serves as the voltage supply 42, the amplifier may serve as a short-circuit current controller. In certain situations, it may be beneficial to use different amplifier configurations, or a different type of amplifier.
• an amplifier that is configured to function within a common mode voltage range from the voltage supply 48 down to several volts below the voltage supply 48.
• the amplifier may be specifically designed to handle a high input common mode voltage as well as a low output common mode voltage.
• the voltage supply 48, 42 may include a voltage supply 48, 42 that provides 3.3 volts.
• the voltage supply 48, 42 may supply any other predetermined voltage level, including 5, 12, 14, 24, and 48 volts.
• the voltage supplies 48, 42 may be configured to increase the respective supplied voltages over a predetermined time (i.e. ramp voltage).
• the disclosed system may be an integrated circuit on a single chip.
• the integrated circuit may use 1/3 of the chip surface area used by the charge- pump system as shown by FIG. 1.
• the disclosed system may use up to 99% of the chip surface area used by the charge-pump system as shown by FIG. 1.
• the sampling capacitor 58 may be smaller than the capacitors associated with the charge-pump system shown by FIG. 1.
• the sampling capacitor may be within a capacitance range of 2 pF to 250 pF.
• the number of pins included by the present disclosure may be less than the number of pins included by the charge-pump system as shown by FIG. 1. In one non-limiting example, the present disclosure may include one less pin than the charge- pump system as shown by FIG. 1. In another non-limiting example, the present disclosure may include up to three fewer pins than the charge-pump system as shown by FIG. 1. In one non-limiting embodiment, the current sinks 82, 84, 86 may each control the amount of charge stored in the sampling capacitor 58. By selecting which of the current sinks 82, 84, 86 is operating, the slew rate of charging of the high-side switch 70 may also be selected.
• each of the current sinks 82, 84, 86 may correspond to a different slew rate charging of the high-side switch 70.
• the FET 60 may be used to short each of the current sinks 82, 84, 86 when slew rate control is not desired. By controlling the amount of charge stored in the sampling capacitor 58, control may be possible over the charge rate to the VGS of the high- side switch 70.
• the sampling capacitor 58 may reach a full charge, and the slew rate of charging the high-side switch 70 may be relatively higher.
• the slew rate of the high-side switch 70 may be programmable. FIG.
• a sample and level-shift circuit 40 may be provided.
• the sample and level-shift circuit 40 may be connected to a voltage supply 42.
• the voltage supply 42 may be the output of an amplifier (for example, an operational amplifier).
• the voltage supply 42 may supply a fixed or variable supply voltage. In certain embodiments, it may be beneficial for the voltage supply 42 to be 1.8, 2.5, 3.3, or 5 volts. Alternatively, any other voltage level
• the sample and level-shift circuit 40 may include a plurality of switches 50, 52, 54, 56.
• the sample and level-shift circuit 40 may further include a sampling capacitor 58.
• the sample and level-shift circuit 40 may include a field-effect transistor (FET) 60.
• FET field-effect transistor
• a slew control 88 may include at least one current sink 82 that may be tunable. The slew control 88 may be connected in parallel with the FET 60.
• a high-side switch 70 may be an n- channel metal-oxide semiconductor field-effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor (nLDMOS transistor).
• nMOS transistor is considered to be a type of nMOS transistor. In certain situations, it may be beneficial to use a different type of transistor.
• One output of the sample and level-shift circuit 40 may be connected to the gate side of the high-side switch 70.
• the drain side of the high- side switch 70 may be connected to a voltage supply 48.
• the output pin 72 may be connected to a circuit load.
• a low-side switch may be included and connected to the output pin 72, such that the high-side switch 70 and the low-side switch constitute a half-bridge configuration.
• the sample and level-shift circuit 40 may eliminate a need for a charge-pump when driving the high-side switch 70.
• the sampling capacitor 58 may sample the voltage of the voltage supply 42.
• the sampling capacitor 58 may then be used to charge the gate side capacitance of the high-side switch 70.
• the charging of the gate side capacitance may enable the high-side switch 70 to turn “on.”
• an input voltage may be supplied to a circuit load.
• the current sink 82 controls the amount of charge stored in the sampling capacitor 58.
• the slew rate of charging of the high-side switch 70 may also be selected.
• the FET 60 may be used to short the current sink 82 when slew rate control is not desired.
• control may be possible over the charge rate to the VGS of the high- side switch 70.
• the sampling capacitor 58 may reach a full charge, and the slew rate of charging the high-side switch 70 may be relatively higher.
• the slew rate of the high-side switch 70 may be programmable.
• one non-limiting example embodiment includes three current sinks 82, 84, 86 connected in parallel. Alternatively, any number of current sinks connected in parallel may be included. Any of the current sinks 82, 84, 86 may be tunable and selectable.
• FIG. 4 is a circuit-level schematic of another embodiment of a system and method for controlling a slew rate of a high-side switch in accordance with the present disclosure.
• a sample and level-shift circuit 90 may be provided.
• the sample and level-shift circuit 90 may be connected to a voltage supply 42.
• the voltage supply 42 may be the output of an amplifier (for example, an operational amplifier).
• the voltage supply 42 may supply a fixed or variable supply voltage. In certain embodiments, it may be beneficial for the voltage supply 42 to be 1.8, 2.5, 3.3, or 5 volts. Alternatively, any other voltage level may be supplied by the voltage supply 42.
• the sample and level-shift circuit 40 may include a plurality of switches 50, 52, 54, 56.
• the sample and level-shift circuit 40 may further include a sampling capacitor 92. Slew control may be implemented via the sampling capacitor 92.
• a high-side switch 70 may be an n- channel metal-oxide semiconductor field-effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor (nLDMOS transistor).
• nMOS transistor is considered to be a type of nMOS transistor. In certain situations, it may be beneficial to use a different type of transistor.
• One output of the sample and level-shift circuit 40 may be connected to the gate side of the high-side switch 70.
• the drain side of the high- side switch 70 may be connected to a voltage supply 48.
• the output pin 72 may be connected to a circuit load.
• a low-side switch may be included and connected to the output pin 72, such that the high-side switch 70 and the low-side switch constitute a half-bridge configuration.
• the sample and level-shift circuit 90 may eliminate a need for a charge-pump when driving the high-side switch 70.
• the sampling capacitor 92 may sample the voltage of the voltage supply 42.
• the sampling capacitor 92 may then be used to charge the gate side capacitance of the high-side switch 70.
• the charging of the gate side capacitance may enable the high-side switch 70 to turn “on.”
• an input voltage may be supplied to a circuit load.
• the sampling capacitor 92 may be adjustable. In certain situations, it may be beneficial to include an adjustable sampling capacitor 92, as the sampling capacitor 92 may then be used as a charge-limiting mechanism. In this non-limiting embodiment, the sampling capacitance corresponds to the sample and level-shift circuit. Therefore, adjusting the capacitance of the sampling capacitor 92 may enable slew control of the high-side switch 70.
• FIG. 5 is a circuit-level schematic of another embodiment of a system and method for controlling a slew rate of a high-side switch in accordance with the present disclosure.
• a sample and level-shift circuit 96 may be provided.
• the sample and level-shift circuit 96 may be connected to a voltage supply 98.
• the sample and level-shift circuit 40 may include a plurality of switches 50, 52, 54, 56.
• the sample and level-shift circuit 40 may further include a sampling capacitor 58.
• a high-side switch 70 may be an n- channel metal-oxide semiconductor field-effect transistor (nMOS transistor) or an n-channel laterally diffused metal oxide semiconductor transistor (nLDMOS transistor).
• nMOS transistor n-channel metal-oxide semiconductor field-effect transistor
• nLDMOS transistor n-channel laterally diffused metal oxide semiconductor transistor
• One output of the sample and level-shift circuit 96 may be connected to the gate side of the high-side switch 70.
• the drain side of the high- side switch 70 may be connected to a voltage supply 48.
• the output pin 72 may be connected to a circuit load.
• a low-side switch may be included and connected to the output pin 72, such that the high-side switch 70 and the low-side switch constitute a half-bridge configuration.
• the sample and level-shift circuit 96 may eliminate a need for a charge-pump when driving the high-side switch 70.
• the sampling capacitor 96 may sample the voltage of the voltage supply 98.
• the sampling capacitor 96 may then be used to charge the gate side capacitance of the high-side switch 70.
• the charging of the gate side capacitance may enable the high-side switch 70 to turn “on.”
• an input voltage may be supplied to a circuit load.
• the voltage supply 98 may supply a fixed or variable supply voltage. In certain embodiments, it may be beneficial for the voltage supply 42 to be 1.8, 2.5, 3.3, or 5 volts.
• any other voltage level may be supplied by the voltage supply 42.
• the voltage supply 98 may be configured to increase the supplied voltage over a predetermined time (i.e. ramp voltage).
• the voltage supply 98 may be used as a charge-limiting mechanism.
• An adjustable voltage supply 98 may limit a voltage corresponding to charging the sampling capacitor. As such, the slew rate of the high-side switch may be controlled.
• the slew control circuit may include other types of charge-limiting mechanisms.
• the charge-limiting mechanism may limit the sampled current of the sampling capacitor 58.
• the charge-limiting mechanism may limit the sampled voltage of the sampling capacitor 58.
• the sampled current may be within the range 5 ⁇ to 5 mA.
• the sampled voltage may be within the range 0% to 100% of the final target gate-source voltage.
• the charge-limiting mechanism may be configured to limit a frequency corresponding to a sample and level-shift circuit.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Electronic Switches (AREA)

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• 2018
  • 2018-04-09 CN CN201880011210.7A patent/CN110268630B/zh active Active
  • 2018-04-09 WO PCT/US2018/026686 patent/WO2018191154A1/en active Application Filing
  • 2018-04-09 KR KR1020197022569A patent/KR102498234B1/ko active IP Right Grant
  • 2018-04-10 TW TW107112217A patent/TW201842725A/zh unknown

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