WO2018189613A1 - Dispositif à semi-conducteur, dispositif d'imagerie et système d'affichage - Google Patents

Dispositif à semi-conducteur, dispositif d'imagerie et système d'affichage Download PDF

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WO2018189613A1
WO2018189613A1 PCT/IB2018/052221 IB2018052221W WO2018189613A1 WO 2018189613 A1 WO2018189613 A1 WO 2018189613A1 IB 2018052221 W IB2018052221 W IB 2018052221W WO 2018189613 A1 WO2018189613 A1 WO 2018189613A1
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data
layer
unit
transistor
neural network
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PCT/IB2018/052221
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English (en)
Japanese (ja)
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池田隆之
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株式会社半導体エネルギー研究所
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Priority to JP2019512040A priority Critical patent/JP7179718B2/ja
Publication of WO2018189613A1 publication Critical patent/WO2018189613A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00—Image coding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/12—Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/136—Incoming video signal characteristics or properties
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof

Definitions

  • One embodiment of the present invention relates to a semiconductor device, an imaging device, and a display system.
  • one embodiment of the present invention is not limited to the above technical field.
  • Technical fields of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, and an input / output Devices, their driving methods, or their manufacturing methods can be cited as examples.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device.
  • a display device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell and an organic thin film solar cell), and an electronic device may include a semiconductor device.
  • TV Television
  • 8K digital television broadcasting is desired to be able to display high-definition images as the screen becomes larger, and ultra-high resolution television broadcasting is being promoted.
  • trial broadcasting of 8K digital television broadcasting started, and various electronic devices for supporting 8K broadcasting have been developed.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device which is less deteriorated and can compress data at a high compression rate. Another object of one embodiment of the present invention is to provide a semiconductor device capable of simplifying data compression processing. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed operation. Another object of one embodiment of the present invention is to provide a semiconductor device with a small circuit area.
  • one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be one that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, claims, drawings, etc., and other issues will be extracted from the description of the specification, claims, drawings, etc. Is possible.
  • a semiconductor device includes a classification unit, a division unit, and a compression unit, and the classification unit classifies image data and outputs first data corresponding to the classification result.
  • the dividing unit has a function of dividing the image data into a plurality of second data, and the compression unit compresses any one of the plurality of second data and outputs the third data.
  • the classifying unit has a first neural network
  • the compression unit has a second neural network
  • image data is input to the input layer of the first neural network
  • the first data is output from the output layer of the neural network
  • one of the plurality of second data is input to the input layer of the second neural network
  • the output layer of the second neural network The third data is output Is, the weighting coefficients of the second neural network is determined based on the first data.
  • the semiconductor device includes a classification unit, a division unit, a compression unit, and a storage unit.
  • the classification unit classifies image data and corresponds to a classification result.
  • the division unit has a function of dividing the image data into a plurality of second data, and the compression unit compresses any one of the plurality of second data, and 3,
  • the storage unit has a function of storing a plurality of weight coefficients,
  • the classification unit has a first neural network, and the compression unit has a second neural network.
  • Image data is input to the input layer of the first neural network
  • the first data is output from the output layer of the first neural network
  • a plurality of data is input to the input layer of the second neural network. Any one of the second data of From the output layer of the second neural network, the third data is output, any one of a plurality of weighting coefficients based on the first data is selected and outputted from the storage unit to a second neural network.
  • the semiconductor device includes a reduction unit, and the reduction unit has a function of reducing the image data.
  • the reduced image data is input to the input layer of the first neural network. It may be entered.
  • the second neural network may be configured by an input layer and an intermediate layer of an auto encoder.
  • An imaging device includes a light receiving unit and a compression unit including the semiconductor device.
  • the light reception unit generates imaging data and transmits the imaging data to the compression unit.
  • the compression unit has a function of compressing the imaging data, and the transistor included in the light receiving unit is stacked above the transistor included in the compression unit.
  • a display system includes a signal generation unit including the semiconductor device and a display unit, and the signal generation unit includes an image processing unit and an encoder.
  • the unit has a decoder, the encoder has a semiconductor device, the encoder has a function of compressing the image signal generated by the image processing unit, and the decoder has a function of expanding the compressed image signal.
  • a novel semiconductor device can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with little deterioration and capable of compressing data with a high compression rate can be provided.
  • a semiconductor device capable of simplifying data compression processing can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a semiconductor device capable of high-speed operation can be provided.
  • a semiconductor device with a small circuit area can be provided.
  • FIG. 9 illustrates a configuration example of a semiconductor device.
  • FIG. 11 illustrates a configuration example of an imaging device.
  • FIG. 11 illustrates a configuration example of an imaging device.
  • the figure which shows the structural example of a pixel The figure which shows the structural example of a display system.
  • the figure which shows the structural example of a display part The figure which shows the structural example of a display part.
  • the figure which shows the structural example of a display part The figure which shows the structural example of a display part.
  • FIG. 11 illustrates a configuration example of a display panel.
  • FIG. 6 illustrates a configuration example of a display device.
  • FIG. 6 illustrates a configuration example of a display device.
  • FIG. 6 illustrates a configuration example of a display device.
  • FIG. 6 illustrates a configuration example of a display device.
  • FIG. 9 illustrates a structure example of a transistor.
  • FIG. 9 illustrates a structure example of a transistor.
  • FIG. 9 illustrates a structure example of a transistor.
  • FIG. 9 illustrates a structure example of a transistor.
  • FIG. 9 illustrates a configuration example of a semiconductor device.
  • FIG. 9 illustrates a configuration example of an electronic device.
  • FIG. 9 illustrates a configuration example of an electronic device.
  • FIG. 9 illustrates a configuration example of an electronic device.
  • a metal oxide is a metal oxide in a broad expression.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like.
  • oxide semiconductors also referred to as oxide semiconductors or simply OS
  • the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short.
  • a transistor including a metal oxide in a channel region is also referred to as an OS transistor.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride. Details of the metal oxide will be described later.
  • X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and things other than the connection relation shown in the figure or text are also described in the figure or text.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element that enables electrical connection between X and Y for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • Element, light emitting element, load, etc. are not connected between X and Y, and X and Y are not connected via an element that enables electrical connection between X and Y. This is the case when connected.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • the switch has a function of controlling on / off. That is, the switch is in an on state or an off state, and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a current flow path.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down
  • X and Y are functionally connected.
  • the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
  • one component may have the functions of a plurality of components. is there.
  • one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
  • FIG. 1 shows a configuration example of the semiconductor device 10.
  • the semiconductor device 10 has a function of encoding (compressing) data input from the outside. Therefore, the semiconductor device 10 can also be called an encoder.
  • the semiconductor device 10 has a function of compressing data by utilizing artificial intelligence (AI: Artificial Intelligence).
  • AI Artificial Intelligence
  • the semiconductor device 10 has an artificial neural network (ANN: Artificial Neural Network), and classifies image data and compresses the image data according to the result of the classification (inference (recognition)) using the artificial neural network. It has the function performed by.
  • ANN Artificial Neural Network
  • Artificial intelligence is a general term for computers that mimic human intelligence.
  • artificial intelligence includes artificial neural networks.
  • An artificial neural network is a circuit that mimics a neural network composed of neurons and synapses.
  • the term “neural network” particularly refers to an artificial neural network.
  • artificial intelligence includes a computer that performs computation using machine learning.
  • the semiconductor device 10 having artificial intelligence will be described in detail.
  • the semiconductor device 10 includes a reduction unit 20, a classification unit 30, a division unit 40, a distribution unit 50, a plurality of compression units 60, and a storage unit 70. Any of these can be configured by a circuit.
  • Image data (data D) is input to the semiconductor device 10.
  • the content of the data D is not particularly limited, and for example, imaging data acquired by an imaging element or the like, a wired or wireless broadcast signal, or the like can be used.
  • Data D is compressed by the semiconductor device 10 and output as data Dcom.
  • the reduction unit 20 has a function of reducing the data D.
  • the data D reduced by the reduction unit 20 is output to the classification unit 30 as data Dred.
  • By reducing the data D it is possible to reduce the processing load required for the classification of the image data by the classification unit 30 and improve the operation speed.
  • the method for reducing the data D is not particularly limited, and can be freely selected.
  • FIG. 2 shows an example of processing by the reduction unit 20.
  • the data D shown in FIG. 2 includes n 0 ⁇ m 0 data Dp corresponding to the gradation of the image displayed on the pixel pix in n 0 rows and m 0 columns (n 0 , m 0 is an integer of 1 or more). It is constituted by.
  • the reduction unit 20 has a function of generating data Dpp based on a plurality of data Dp belonging to a specific region A.
  • the data Dpp for example, the maximum value, the minimum value, or the average value of the plurality of data Dp belonging to the region A can be used.
  • N 1 ⁇ m 1 data Dpp corresponding to the gradation of the image to be generated is generated. These data Dpp are output to the classification unit 30 as data Dred.
  • FIG. 2 shows a configuration in which the region A includes the pixels pix of 2 rows and 2 columns
  • the region A can be set freely.
  • the number of data Dp included in the region A can be arbitrarily set.
  • the classification unit 30 has a function of classifying image data based on the data Dred.
  • the classification unit 30 includes a neural network NN1, and has a function of classifying image data by inference by the neural network NN1.
  • the neural network NN1 may be configured by hardware or software.
  • FIG. 3A illustrates the classification unit 30 having the neural network NN1.
  • the neural network NN1 includes an input layer IL, an output layer OL, and a hidden layer (intermediate layer) HL.
  • a plurality of data Dpp constituting the data Dred is input to the input layer IL.
  • the neural network NN1 may be a network having a plurality of hidden layers HL (DNN: deep neural network). Learning with a deep neural network is sometimes called deep learning.
  • the output layer OL, the input layer IL, and the hidden layer HL each have a plurality of units (neuron circuits). The output data of each unit is multiplied by weights (coupling strengths), and then is transmitted to units provided in different layers. Supplied. Note that the number of units included in each layer can be freely set.
  • a function for classifying the data Dred based on the data Dpp 1 to Dpp i is added to the neural network NN1 by learning.
  • arithmetic processing is performed in each layer. Arithmetic processing in each layer is executed by, for example, a product-sum operation between the output data of the unit in the previous layer and a weight coefficient.
  • the coupling between layers may be a total coupling in which all the units are coupled, or may be a partial coupling in which some units are coupled.
  • data Dc 1 to Dc j (j is an integer of 1 or more) are output from the output layer OL.
  • Data Dc 1 to Dc j correspond to the result of classifying data Dred into j classes c 1 to c j .
  • FIG. 3B shows an example of a class.
  • An image IMG in the figure represents a reduced image corresponding to the data Dred.
  • the data Dred includes, for example, a class c 1 when characters are displayed on the image IMG, a character above the image IMG, a class c 2 when an object is displayed below, and a character below the image IMG.
  • Class classification can be performed according to the contents of the image IMG, such as class c 3 when an object is displayed above, class c 4 when an object is displayed on the image IMG, and so on.
  • the data Dc 1 to Dc j can correspond to the probability that the data Dred belongs to the classes c 1 to c j , respectively. Therefore, it is estimated that the data Dred belongs to the class corresponding to the data Dc having the largest value. Therefore, the data Dred can be classified based on the data Dc 1 to Dc j output from the output layer OL.
  • the neural network NN1 it is preferable to use an auto encoder. Details of the auto encoder will be described later.
  • a neural network that performs supervised learning can be used as the neural network NN1.
  • the number of units of the output layer OL is j, and a softmax function or the like can be used as an activation function of the output layer OL.
  • a convolutional neural network (CNN) having a convolutional layer, a pooling layer, and a fully connected layer can be used as the neural network NN1.
  • CNN convolutional neural network having a convolutional layer, a pooling layer, and a fully connected layer
  • the number of units in the output layer of all coupling layers may be j.
  • Various machine learning methods may be used for the classification of the data Dred.
  • the data Dred is classified by the neural network NN1.
  • the classification result is output to the storage unit 70 as data Dcls.
  • one storage unit 70 is shown in FIG. 1, a plurality of storage units 70 can be arranged around the compression unit 60, respectively.
  • the data D is reduced to the data Dred and then input to the neural network NN1. Therefore, the amount of calculation by the neural network NN1 can be reduced and the processing speed can be improved.
  • the data amount of the data D is large, for example, when the data D is image data for displaying an image (2K1K, 4K2K, 8K4K, etc.) having a resolution higher than full high-definition, the image data is classified. It can be done smoothly.
  • the reduction unit 20 can be omitted and the data D can be input to the classification unit 30.
  • the dividing unit 40 has a function of dividing the data D into a plurality of data Ddiv.
  • FIG. 4 shows an example of processing by the dividing unit 40.
  • the dividing unit 40 has a function of dividing the data D for each region B and generating data Ddiv including a plurality of data Dp included in the region B.
  • the data D becomes N ⁇ M pieces of data Ddiv (Ddiv [1,1] to Ddiv [N, M]) where N is an integer of 1 to less than n 0 and M is an integer of 1 to less than m 0.
  • the data is divided and output to the distribution unit 50.
  • FIG. 4 shows a configuration in which the region B includes the pixels pix of 2 rows and 2 columns
  • the region B can be set freely.
  • the number of data Dp included in the region B can be arbitrarily set.
  • the dividing unit 40 may divide the data D spatially or may divide based on the image configuration.
  • the distribution unit 50 has a function of distributing the data Ddiv to any one of the plurality of compression units 60.
  • the data Ddiv can be supplied to different compression units 60, and the image data can be compressed for each data Ddiv. Therefore, even when the data amount of the data D is large, the data can be compressed smoothly.
  • the distribution unit 50 can be configured by, for example, a demultiplexer.
  • the number of data Ddiv and the number of compression units 60 are the same will be described as an example, but the number of compression units 60 may be smaller than the number of data Ddiv. In this case, a plurality of data Ddiv is compressed by one compression unit 60.
  • Each of the plurality of compression units 60 has a function of compressing the data Ddiv.
  • the compression unit 60 includes a neural network NN2, and has a function of compressing data Ddiv by inference by the neural network NN2 to generate data Ddivc.
  • FIG. 5 shows a configuration example of the compression unit 60 having the neural network NN2.
  • the data Ddiv [1,1] to Ddiv [N, M] are respectively stored in the neural networks NN2 [1,1] to NN2 [N, M] included in the compression units 60 [1,1] to 60 [N, M]. M] is shown.
  • the neural network NN2 has an input layer IL, an output layer OL, and a hidden layer HL. Data Ddiv is input to the input layer IL.
  • the neural network foreground NN2 may be a deep neural network.
  • the neural network NN2 may be configured by hardware or software.
  • a function for generating compressed data Ddivc of data Ddiv is added to the neural network NN2 by learning.
  • the neural network NN2 has a function of extracting features from the data Ddiv input to the input layer IL and outputting data Ddivc corresponding to the features from the output layer OL.
  • an auto encoder can be used for the neural network NN2.
  • a configuration example of the auto encoder AE is shown in FIG.
  • the auto encoder AE includes an input layer IL, an output layer OL, and intermediate layers HL 1 to HL 2L-1 (L is an integer of 1 or more).
  • L is an integer of 1 or more.
  • the number of units of the intermediate layer HLL of the Lth layer is smaller than the number of units of the input layer IL and the output layer OL.
  • the weighting coefficient of the auto encoder AE is set so that the error between the data Ddiv input to the input layer IL and the data Ddiv output from the output layer OL is below a certain level.
  • data output from the intermediate layer HL L can be regarded as data obtained by reducing the dimensionality of the input data Ddiv to the input layer IL. Therefore, the area from the input layer IL to the intermediate layer HL L can be regarded as an encoder ENC that encodes the data Ddiv, and the area from the intermediate layer HL L to the output layer OL can be regarded as a decoder DEC that decodes the data Ddiv.
  • the data Ddivc output from the intermediate layer HL L corresponds to the compressed data of the data Ddiv input to the input layer IL.
  • the area of the encoder ENC in the auto encoder AE can be used as the neural network NN2 in FIG.
  • the neural network NN2 is composed of an input layer IL and the intermediate layer HL 1 to HL L.
  • the intermediate layer HL L of the auto encoder AE corresponds to the output layer OL of the neural network NN2.
  • the data D compressed by the encoder ENC can be decoded by inputting the data Ddivc to the decoder DEC configured by the intermediate layers HL L to HL 2L-1 and the output layer OL.
  • the number of intermediate layers HL of the auto encoder AE and the number of units included in the intermediate layer HL can be freely set. By increasing the number of intermediate layers HL or increasing the number of units included in the intermediate layer HL, it is possible to improve the accuracy of encoding and decoding and suppress degradation of image data.
  • the auto encoder AE may be called a deep auto encoder.
  • a neural network NN2 [1,1] to NN2 [N, M] is configured using the auto encoder AE and the data Ddiv [1,1] to Ddiv [N, M] is compressed, whereby the data Ddivc [ 1,1] to Ddivc [N, M].
  • the auto encoder AE shown in FIG. 6 can also be used for the neural network NN1.
  • the neural network NN1 is configured by the input layer IL and the intermediate layers HL 1 to HL L (encoder ENC).
  • the intermediate layer HL L of Autoencoder AE encoded data of the data Dred is output.
  • This encoded data corresponds to data Dcls output from the output layer OL of the neural network NN1, and class classification is performed based on the encoded data. For example, if the number of units of the intermediate layer HL L is j, encoded data of 2 j values can be obtained by encoding the data Dred.
  • the value output from the unit is associated with data “1” when the probability indicating a certain state is high, and is associated with data “0” when the probability indicating a certain state is low.
  • a binary number can be obtained.
  • the classification unit 30 can classify the image data into 2 j classes, and the compression unit 60 can use 2 j types of weighting factors W. An example of using a probability model for the auto encoder AE will be described later with reference to FIG.
  • the network configurations of the neural networks NN2 [1,1] to NN2 [N, M] can be set independently. Specifically, individual weighting factors Wcom [1,1] to Wcom [N, M] can be used for the neural networks NN2 [1,1] to NN2 [N, M], respectively. Thereby, the contents of data compression can be controlled for each compression unit 60.
  • the weighting factors Wcom [1,1] to Wcom [N, M] are supplied from the storage unit 70 shown in FIG.
  • the compression can be performed by a relatively simple process. Therefore, simplification of data compression processing or reduction of power consumption can be achieved.
  • the storage unit 70 has a function of storing a plurality of weighting factors Wcom. Then, based on the data Dcls indicating the classification result of the image data, any one of the plurality of weighting factors Wcom stored in the storage unit 70 is selected and output to the neural network NN2. Thereby, the weighting factor Wcom of the neural network NN2 can be switched according to the classification result of the image data, and the compression can be performed by a method suitable for the attribute of the input image data.
  • FIG. 7 shows an example of processing by the neural network NN2 corresponding to the class of image data.
  • FIG. 7 shows an example in which the data D is classified into the four classes c 1 to c 4 shown in FIG.
  • data D is divided into classes c 1
  • the data D it is inferred that mainly data of an image in which characters are displayed (FIG. 7 (A)).
  • a weighting factor W character suitable for compression of character data is used for the neural network NN2 that compresses the data Ddiv.
  • data D is divided into classes c 2 or c 3
  • the data D is presumed to be the image data characters and objects are displayed (FIG. 7 (B), (C) ).
  • a region in which characters are displayed top of class c 2 images, and the lower class c 3 of the image) to the neural network NN2 for compressing data Ddiv corresponding to, suitable for the character of the data compression
  • the weighting factor W character is used.
  • the object is (lower character class c 2 images, and the upper class c 3 image characters) is the region displayed on the neural network NN2 for compressing data Ddiv corresponding to the object data
  • a weighting factor W object suitable for compression is used.
  • the compression of the plurality of data Ddiv included in the data D is individually performed using the weighting coefficient Wcom selected according to the content of the image.
  • the type of the weight coefficient Wcom is not limited to the above.
  • the weighting factor Wcom may be set for each character type (alphabetic characters, numbers, etc.), or the weighting factor Wcom may be set for each type of object (human, building, background, etc.).
  • Data Dcom is composed of data Ddivc [1,1] to Ddivc [N, M] generated by the compression units 60 [1,1] to 60 [N, M] (FIG. 1).
  • the data Dcom is output to the outside of the semiconductor device 10 as compressed data of the data D.
  • the semiconductor device 10 classifies the image data using the neural network NN1, and can independently control the compression conditions of the plurality of divided image data according to the classification result. .
  • image data can be compressed with a high degree of compression with little deterioration, and the accuracy of the semiconductor device 10 can be improved.
  • the number of compression units 60 may be the number of classification classes of data Ddiv.
  • the compression unit 60 may be provided according to the contents of the data Ddiv, such as a compression unit 60 that compresses character data and a compression unit 60 that compresses object data.
  • the distribution unit 50 distributes the data Ddiv to the compression unit 60 based on the data Dcls. Thereby, the data Ddiv is compressed according to the attribute.
  • FIG. 8 shows a configuration example of the arithmetic device 80.
  • a computer having excellent arithmetic processing capability such as a dedicated server or a cloud can be used.
  • a computer having excellent arithmetic processing capability such as a dedicated server or a cloud
  • learning by the neural networks NN1 and NN2 can be performed on the software using the arithmetic device 80.
  • the learning result can be reflected in the neural networks NN1 and NN2.
  • the arithmetic unit 80 includes a reduction unit 20a, a neural network NN1a, a dividing unit 40a, and a plurality of neural networks NN2a.
  • a configuration in which the arithmetic device 80 includes k neural networks NN2a [1] to NN2a [k] (k is an integer of 2 or more) is shown.
  • the reduction unit 20a and the division unit 40a have the same functions as the reduction unit 20 and the division unit 40 in FIG. 1, respectively.
  • the storage device 90 stores learning image data (data Da).
  • the reducing unit 20a When the data Da is input from the storage device 90 to the arithmetic device 80, the reducing unit 20a generates reduced data Dreda of the data Da, and the dividing unit 40a divides the data Da into a plurality of data Ddiva.
  • the neural network NN1a has a configuration corresponding to the neural network NN1, and the neural network NN2a has a configuration corresponding to the neural network NN2.
  • the neural network NN1a can be configured by a network having the same number of layers as the neural network NN1 and the number of units included in each layer, and the neural network NN2a is equal in number of layers and the number of units included in each layer. It can be configured by a network.
  • the neural network NN1a performs learning using the data Dreda as a learning sample.
  • the learning method of the neural network NN1a is not particularly limited, and can be freely selected.
  • the learning may be unsupervised learning or supervised learning.
  • teacher data corresponding to the correct classification result of the data Da is supplied from the storage device 90 to the neural network NN1a. Then, the weighting coefficient is updated so that the error between the learning data and the teacher data is below a certain level.
  • a gradient descent method using an error function or the like can be used.
  • the neural network NN1a can also be configured by an auto encoder AE shown in FIG. In this case, the weighting coefficient is updated so that the error between the data Dreda input to the input layer IL of the neural network NN1a and the data output from the output layer OL is below a certain level.
  • Wcls be the weighting factor of the neural network NN1a that has completed learning and is capable of classifying the data Da with a predetermined accuracy.
  • the weighting coefficient Wcls is supplied to the classification unit 30 of the semiconductor device 10 and stored in the neural network NN1, whereby the learning result is reflected in the neural network NN1.
  • the classification result of the data Da by the neural network NN1 is output to the dividing unit 40a. Then, the dividing unit 40a outputs a plurality of data Ddiva to the predetermined neural network NN2a according to the classification result of the neural network NN1.
  • the plurality of neural networks NN2a [1] to NN2a [k] perform learning using the data Ddiva as learning samples, respectively.
  • the neural network NN2a is configured by the auto encoder AE shown in FIG. 6, and the weighting coefficient is set so that the error between the data Ddiva input to the input layer IL and the data output from the output layer OL is below a certain level. Updated.
  • Each of the neural networks NN2a [1] to NN2a [k] is responsible for compression of a predetermined class of data Ddiva.
  • the neural network NN2a [1] compresses character data
  • the neural network NN2a [2] compresses object data
  • the neural network NN2a [3] compresses background data.
  • the plurality of data Ddiva generated by the dividing unit 40a is input to a specific neural network NN2a according to the class of the data Ddiva.
  • Each of the neural networks NN2a [1] to NN2a [k] performs learning using the data Ddiva as a learning sample.
  • the weighting coefficients of the neural networks NN2a [1] to NN2a [k] that have completed learning and are capable of encoding and decoding image data with a predetermined accuracy are W 1 to W k , respectively.
  • the weighting factors W 1 to W k are supplied to the semiconductor device 10, it is stored in the storage unit 70.
  • the weight coefficient Wcom corresponding to the classification result input from the classification unit 30 is supplied to each of the plurality of neural networks NN2.
  • the weighting factor Wcom from the weighting coefficients W 1 to W k obtained by the above learning is any one of the weighting coefficient selected on the basis of the data DCLS.
  • compression using any of weighting coefficients W 1 to W k is performed by a neural network NN2. In this way, the learning result by the neural network NN2a is reflected in the neural network NN2.
  • prior learning can be used for learning by the auto encoder AE.
  • Prior learning is a method of obtaining an initial value of a weighting factor by performing learning for each layer at the time of learning by the auto encoder AE. Thereby, learning by the auto encoder AE can be performed efficiently. In particular, when there are a plurality of intermediate layers HL of the auto encoder AE, the pre-learning is effective.
  • FIG. 9 shows an example of prior learning by the auto encoder AE.
  • a method of performing learning by the auto encoder AE for each adjacent layer will be described.
  • learning of two adjacent layers among the layers from the input layer IL to the intermediate layer HL L of the auto encoder AE is sequentially performed from the input layer IL side (greedy learning for each layer).
  • a network constituted by two adjacent layers is regarded as a restricted Boltzmann machine (RBM) which is a probabilistic model, and an intermediate layer from an RBM [1] constituted by an input layer IL and an intermediate layer HL 1 is used. Learning is sequentially performed up to RBM [L] configured by HL L-1 and the intermediate layer HL L.
  • RBM restricted Boltzmann machine
  • RBM [1] learning by RBM [1] is performed first, and when the learning is completed, the weighting coefficient between the input layer IL and the intermediate layer HL 1 is fixed.
  • the output data of the intermediate layer HL 1 is used as input data for learning by the higher-order RBM (RBM [2]).
  • RBM higher-order RBM
  • RBM contrastive divergence method or the like can be used for learning by RBM.
  • learning by the neural networks NN1 and NN2 can be performed by the arithmetic device 80.
  • the configuration of the neural networks NN1 and NN2 provided in the semiconductor device 10 can be simplified.
  • FIG. 10 is a flowchart illustrating an operation example of the semiconductor device 10 when image data is compressed. Note that, when compressing image data, the weighting coefficient obtained by the above-described learning is stored in advance in the neural network NN1 and the storage unit 70 (see FIG. 8).
  • data D (image data) is input to the semiconductor device 10 and supplied to the reduction unit 20 and the division unit 40 (step S1). Then, the data D is reduced by the reduction unit 20 (step S2), and is output to the classification unit 30 as data Dred.
  • the data Dred is input to the input layer IL of the neural network NN1 included in the classification unit 30. Then, the neural network NN1 classifies the data D by inference using the data Dred as input data (step S3). Then, data Dcls corresponding to the classification result is output to the storage unit 70.
  • the storage unit 70 supplies the plurality of compression units 60 with a weight coefficient Wcom corresponding to the result of classification by the classification unit 30.
  • a weighting coefficient Wcom suitable for compression of character data is supplied to the compression unit 60 that compresses data corresponding to the upper character of the image shown in FIG. 7B.
  • a weighting factor Wcom suitable for compression of object data is supplied to the compression unit 60 that compresses data corresponding to the object below the character shown in FIG.
  • the weighting factors Wcom supplied to the plurality of compression units 60 can be selected from the weighting factors W 1 to W k (see FIG. 8) stored in the storage unit 70, respectively.
  • the dividing unit 40 to which the data D is input divides the data D into a plurality of data Ddiv (step S5).
  • the plurality of data Ddiv is supplied to the distribution unit 50.
  • the distribution unit 50 distributes the data Ddiv to different compression units 60 (step S6).
  • the number of compression units 60 is smaller than the number of data Ddiv, a plurality of data Ddiv are input to one compression unit 60.
  • the data Ddiv is input to the input layer of the neural network NN2 included in the compression unit 60. Then, the neural network NN2 compresses the data Ddiv by inference (step S7).
  • the inference by the neural network NN2 is performed using the weighting coefficient Wcom supplied from the storage unit 70 based on the classification result of the data D. Therefore, compression is performed by a method suitable for the attribute of the data Ddiv.
  • the data Ddivc output from the output layer of the neural network NN2 included in the compression unit 60 is integrated to generate data Dcom.
  • the data Dcom is output to the outside of the semiconductor device 10 as compressed data of the data D (step S8). In this way, the image data can be compressed using the neural networks NN1 and NN2.
  • the semiconductor device can perform compression of image data according to an image classification result using artificial intelligence.
  • compression can be performed by a method suitable for the attribute of the image data. Therefore, the image data can be compressed with little deterioration, and the accuracy of the semiconductor device 10 can be improved.
  • the storage unit 70 supplies a predetermined weight coefficient Wcom to the neural network NN2 according to the data Dcls.
  • the weighting factor Wcom is composed of a plurality of parameters for determining the coupling strength between units of the neural network NN2.
  • the plurality of parameters are collectively output to the neural network NN2 when the weighting factor Wcom is switched.
  • FIG. 11 shows a configuration example of the storage unit 70 that can switch the weighting coefficient Wcom at high speed.
  • the storage unit 70 includes a storage circuit Mem and a switch circuit SC.
  • the memory circuit Mem stores k parameter sets individually (weighting factors Wcom [1] to Wcom [k]).
  • the switch circuit SC includes switches SW [1] to SW [k].
  • the weighting factors Wcom [1] to Wcom [k] are supplied to the neural network NN2 via the switches SW [1] to SW [k].
  • the supply of the weight coefficient Wcom to the neural network NN2 is controlled by the switch circuit SC.
  • Weighting factor Wcom supplied to the neural network NN2 is controlled by the context signal S CTX.
  • the context signal S CTX it is possible to use a signal based on the data DCLS.
  • FIG. 12 shows a configuration example of the storage unit 70 for realizing the context method. 12 has a configuration in which the memory circuit Mem and the switch circuit SC in FIG. 11 are integrated.
  • the coupling strength between units of the neural network NN2 is represented by a k value will be described.
  • the storage unit 70 includes k rows of memory cells MC.
  • the number of columns of memory cells MC is the same as the number of parameters included in one weighting factor Wcom.
  • FIG. 12 shows two rows of memory cells MC as a representative example, other memory cells MC can have the same configuration.
  • FIG. 12 shows units U A , U B , and U C as representative examples of units included in the neural network NN2.
  • Each of the memory cells MC includes transistors Tr1, Tr2, Tr3, and a capacitor C1.
  • the transistors Tr1, Tr2, and Tr3 are n-channel type, but these transistors may be n-channel type or p-channel type, respectively.
  • the gate of the transistor Tr1 is connected to the wiring WL, one of the source and the drain is connected to the gate of the transistor Tr2 and one electrode of the capacitor C1, and the other of the source and the drain is connected to the wiring BL.
  • One of the source and the drain of the transistor Tr2 is connected to the wiring OUT, and the other of the source and the drain is connected to one of the source and the drain of the transistor Tr3.
  • the gate of the transistor Tr3 is connected to the wiring CTX, and the other of the source and the drain is connected to the wiring IN.
  • the other electrode of the capacitive element C1 is connected to a wiring to which a predetermined potential is supplied.
  • a node connected to one of the source and the drain of the transistor Tr1, the gate of the transistor Tr2, and one electrode of the capacitor C1 is referred to as a node N1.
  • the wiring OUT [1] is connected to a unit U A
  • wiring IN [1] and the wiring OUT [2] is connected to the unit U B
  • wiring IN [2] is connected to the unit U C ing.
  • parameters for determining the binding strength between the units in the first column of the memory cell MC [1, 1] to MC [k, 1] U A and the unit U B is stored
  • the second column the memory cell MC [1, 2] to MC parameters for determining the binding strength between the [, k 2] units U B and the unit U C is stored.
  • the parameters configuring the weighting factors Wcom [1] to Wcom [k] are stored in the memory cells MC in the first to kth rows, respectively.
  • the potential of the wiring WL is controlled to turn on the transistor Tr1.
  • the potential of the wiring BL is supplied to the node N1 (parameter writing).
  • the potential of the wiring BL at this time corresponds to a parameter stored in the memory cell MC.
  • the potential of the wiring WL is controlled to turn off the transistor Tr1.
  • the node N1 becomes a floating state, and the potential of the node N1 is held (parameter holding).
  • the conduction state of the transistor Tr2 provided between the wiring OUT and the wiring IN is determined by the potential of the node N1. Therefore, the conduction state between the wiring OUT and the wiring IN can be controlled by controlling the potential of the node N1.
  • the memory cells MC [1,1] to MC [k, 1] share the wiring OUT [1] and the wiring IN [1], and the memory cells MC [1,2] to MC [k, 2] OUT [2] and wiring IN [2] are shared. Then, by supplying the signal SCTX to any one of the wirings CTX [1] to CTX [k], the memory cells MC in a predetermined row can be selected. Thereby, the weighting factor Wcom can be switched by the context method.
  • the weight coefficient Wcom [1] when the weight coefficient Wcom [1] is selected, the potential of the wiring CTX [1] is controlled to turn on the transistor Tr3 of the memory cell MC in the first row. Further, the potentials of the wirings CTX [2] to CTX [k] are controlled to turn off the transistors Tr3 of the memory cells MC in the second to kth rows. Accordingly, the conduction state between the wiring OUT [1] and the wiring IN [1] is controlled by the potential of the node N1 of the memory cell MC [1,1], and the conduction between the wiring OUT [2] and the wiring IN [2]. The state is controlled by the potential of the node N1 of the memory cell MC [1,2]. Similarly, when selecting the weighting factors Wcom [2] to Wcom [k], the weighting factors Wcom are selected by controlling the potentials of the wirings CTX [2] to CTX [k].
  • an OS transistor is preferably used as the transistor Tr1. Since the off-state current of the OS transistor is extremely small, the potential of the node N1 can be maintained for a long time in a period in which the transistor Tr1 is off. As a result, the frequency of parameter refresh can be greatly reduced, and the power consumption of the storage unit 70 can be reduced. In addition, the parameters can be held even during the period when the supply of power to the storage unit 70 is stopped.
  • the memory cell MC can be configured with a small number of transistors (three in the memory cell MC). Thereby, the area of the memory
  • the OS transistor can be stacked over another transistor. Therefore, the area of the memory cell MC can be reduced by stacking the transistor Tr1 on the transistor Tr2 or the transistor Tr3. Thereby, the area of the storage unit 70 can be further reduced.
  • a transistor other than the OS transistor can be used as the transistor Tr1.
  • a transistor whose channel formation region is formed in part of a substrate including a single crystal semiconductor (hereinafter also referred to as a single crystal transistor) may be used.
  • the substrate having a single crystal semiconductor include a single crystal silicon substrate and a single crystal germanium substrate. Since the single crystal transistor can operate at high speed, the operation speed of the memory circuit can be improved by using the single crystal transistor for the memory circuit.
  • the transistor other than the OS transistor a transistor in which a channel formation region is formed in a film containing a semiconductor other than an oxide semiconductor can be used.
  • Examples of semiconductors other than oxide semiconductors include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and organic semiconductors. These semiconductors may be single crystal semiconductors or non-single crystal semiconductors such as amorphous semiconductors, microcrystalline semiconductors, and polycrystalline semiconductors.
  • the transistors Tr2 and Tr3 can be the same transistor as the transistor Tr1.
  • FIG. 13 illustrates a configuration example of the storage unit 70 including the drive circuit 71 and the drive circuit 72.
  • the wiring CTX and the wiring WL are connected to the drive circuit 71, and the wiring BL is connected to the drive circuit 72.
  • the drive circuit 71 has a function of supplying a signal for selecting the memory cell MC to the wiring WL and the wiring CTX.
  • the drive circuit 72 has a function of supplying a potential corresponding to a parameter included in the weighting coefficient Wcom to the wiring BL.
  • FIG. 14 shows a configuration example of the imaging apparatus 100 having a function of compressing imaging data.
  • the imaging apparatus 100 includes a light receiving unit 110 and a compression unit 120.
  • the light receiving unit 110 has a function of converting irradiated light into an electrical signal. This electrical signal is output to the compression unit 120 as data D.
  • the compression unit 120 has a function of compressing the data D into data Dcom and outputting the data Dcom to the outside. As the compression unit 120, the semiconductor device 10 described in the above embodiment can be used.
  • FIG. 15A shows a configuration example of the light receiving unit 110.
  • the light receiving unit 110 includes a plurality of pixels 111, and each pixel 111 has a function of outputting an electrical signal corresponding to the intensity of irradiated light.
  • the pixel 111 includes a photoelectric conversion element PD and transistors Tr11, Tr12, Tr13, Tr14.
  • One electrode of the photoelectric conversion element PD is connected to one of a source and a drain of the transistor Tr11 and one of a source and a drain of the transistor Tr12, and the other electrode is connected to a wiring to which a predetermined potential is supplied.
  • the gate of the transistor Tr11 is connected to the wiring RS, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied.
  • the gate of the transistor Tr12 is connected to the wiring TX, and the other of the source and the drain is connected to the gate of the transistor Tr13 and the gate of the transistor Tr14.
  • One of a source and a drain of the transistor Tr13 is connected to the wiring LO1, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied.
  • One of a source and a drain of the transistor Tr14 is connected to the wiring LO2, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. Note that the wiring LO2 is shared by the plurality of pixels 111 and connected to the plurality of transistors Tr14.
  • a node connected to one electrode of the photoelectric conversion element PD, one of the source or drain of the transistor Tr11, and one of the source or drain of the transistor Tr12 is defined as a node NR.
  • a node connected to the gate of the transistor Tr13 and the gate of the transistor Tr14 is a node ND.
  • the photoelectric conversion element PD has a function of converting irradiated light into an electrical signal.
  • As the photoelectric conversion element PD an element capable of obtaining a photocurrent corresponding to the irradiated light can be used. Thereby, the potential of the node NR becomes a value corresponding to the intensity of light irradiated to the photoelectric conversion element PD.
  • the photoelectric conversion element PD include a PN photodiode, a PIN photodiode, an avalanche diode, an NPN buried diode, a Schottky diode, a phototransistor, an X-ray photoconductor, and an infrared sensor. Etc.
  • the element which has a selenium in a photoelectric converting layer can also be used as photoelectric converting element PD.
  • a photodiode is used as the photoelectric conversion element PD.
  • the transistor Tr11 functions as a reset transistor that initializes the potential of the node NR. By controlling the potential of the wiring RS and turning on the transistor Tr11, the potential of the node NR is initialized.
  • the transistor Tr12 functions as a transfer transistor that transfers the potential of the node NR to the node ND. After the initialization of the potential of the node NR, when light is irradiated to the photoelectric conversion element PD in a period in which the transistors Tr11 and Tr12 are in an off state, the potential of the node NR becomes a potential corresponding to the intensity of the irradiated light. . Then, the potential of the node NR is supplied to the node ND by controlling the potential of the wiring TX to turn on the transistor Tr12.
  • the transistor Tr13 functions as an amplification transistor that outputs a signal (potential or current) corresponding to the potential of the node ND.
  • a signal output from the transistor Tr13 is supplied to the wiring LO1 as imaging data.
  • Data D is composed of a plurality of imaging data acquired by the plurality of pixels 111.
  • the transistor Tr14 functions as an amplification transistor that outputs a signal (potential or current) corresponding to the potential of the node ND.
  • a signal output from the transistor Tr14 is supplied to the wiring LO2.
  • the wiring LO2 is connected to a plurality of transistors Tr14. Therefore, a signal reflecting imaging data of the plurality of pixels 111 is supplied to the wiring LO2.
  • the potential of the wiring LO2 can be a signal corresponding to the maximum value of the imaging data of the plurality of pixels 111.
  • a signal supplied to the wiring LO2 or a signal obtained by appropriately processing the signal corresponds to a signal obtained by integrating a plurality of imaging data. Therefore, this signal can be used as the data Dred in FIG. Therefore, the reduction unit 20 illustrated in FIG. 1 can be omitted by providing the transistor Tr14 in the pixel 111.
  • the potentials of the node NR and the node ND are held when the transistors Tr11 and Tr12 are turned off. Therefore, it is preferable to use transistors with low off-state current for the transistors Tr11 and Tr12.
  • a transistor having high withstand voltage As the transistors Tr11 and Tr12, OS transistors that have extremely low off-state current and high withstand voltage than transistors having silicon in a channel formation region (hereinafter also referred to as Si transistors).
  • the transistors Tr13 and Tr14 are desired to have excellent amplification characteristics, they are preferably transistors with high on-current. Therefore, it is preferable to use single crystal transistors or the like as the transistors Tr13 and Tr14. With such a configuration, it is possible to realize an imaging device that can output a signal with high noise detection sensitivity at low illuminance and low noise. In addition, since the light detection sensitivity is high, the light capture time can be shortened and imaging can be performed at high speed. In addition, since the leakage of electric charges in the pixels 111 is small, driving using a global shutter method in which electric charges are accumulated in all the pixels can be easily applied.
  • the structure of the transistor is not limited to the above structure.
  • OS transistors may be used for the transistors Tr13 and Tr14
  • single crystal transistors may be used for the transistors Tr11 and Tr12.
  • the structure of the imaging device 100 is not limited to FIG. 15A, and other elements (such as a transistor, a capacitor, and a resistor) may be included as appropriate.
  • a transistor Tr15 may be provided between the transistor Tr13 and the wiring LO1.
  • the timing at which imaging data is output to the wiring LO1 can be controlled by controlling the conduction state of the transistor Tr15.
  • the conduction state of the transistor Tr15 can be controlled by controlling the potential of the wiring SE1 connected to the gate of the transistor Tr15.
  • a transistor Tr16 may be provided between the plurality of transistors Tr14 and the wiring LO2.
  • the timing at which the imaging data is output to the wiring LO2 can be controlled by controlling the conduction state of the transistor Tr16.
  • the conduction state of the transistor Tr16 can be controlled by controlling the potential of the wiring SE2 connected to the gate of the transistor Tr16.
  • FIG. 16 shows a specific configuration example of the imaging apparatus 100.
  • FIG. 16A is a cross-sectional view illustrating a configuration example of the transistors TrA, TrB, TrC, and TrD in the channel length direction.
  • 16B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 16A and illustrates a cross section of the transistor TrA in the channel width direction.
  • FIG. 16C is a cross-sectional view taken along dashed-dotted line Y1-Y2 in FIG. 16A and illustrates a cross section of the transistor TrC in the channel width direction.
  • the layer L1 includes the photoelectric conversion element PD including the electrode 141, the photoelectric conversion unit 142, and the electrode 143.
  • the layer L2 includes transistors TrA and TrB (OS transistors).
  • the layer L3 includes transistors TrC and TrD (Si transistors).
  • TrC and TrD Si transistors
  • a structure in which the transistors TrC and TrD have channel formation regions in the single crystal semiconductor substrate 130 is shown; however, the transistors TrC and TrD are formed on a crystalline semiconductor layer provided over an insulating surface such as a glass substrate. A channel formation region may be included.
  • the transistors TrA and TrB can be stacked above the transistors TrC and TrD. Thereby, the area of the imaging device 100 can be reduced.
  • the transistors Tr11 and Tr12 shown in FIG. 15A are used as the transistors TrA and TrB, and the transistors Tr13 and Tr14 shown in FIG. 15A are used as the transistors TrC and TrD, thereby reducing the area of the pixel 111. Can do.
  • transistors included in the light receiving unit 110 for example, transistors Tr11 and Tr12
  • transistors TrA and TrB are used as the transistors TrA and TrB, and transistors (for example, the neural networks NN1 and NN2 in FIG.
  • the light receiving unit 110 and the compression unit 120 can be integrated, and the area of the imaging device 100 can be reduced.
  • the layer L1 can include a partition 144 in addition to the photoelectric conversion element PD.
  • the partition wall 144 is provided between the electrodes 141 of adjacent pixels.
  • the transistors TrA and TrB both have a configuration having a back gate BG, either one may have a back gate BG.
  • the back gate BG may be connected to a front gate FG of a transistor provided opposite to the back gate BG as shown in FIG. 16B, or even if a fixed potential different from that of the front gate FG is supplied to the back gate BG. Good.
  • An insulating layer 151 is provided between the region where the OS transistor is formed and the region where the Si transistor is formed. Hydrogen in the insulating layer provided in the vicinity of the channel formation regions of the transistors TrC and TrD terminates the dangling bond of silicon. Therefore, the hydrogen has an effect of improving the reliability of the transistors TrC and TrD. On the other hand, hydrogen in the insulating layer provided in the vicinity of the metal oxide layer that is the active layer of the transistors TrA and TrB is one of the factors that generate carriers in the metal oxide layer. Therefore, the hydrogen may be a factor that decreases the reliability of the transistors TrA and TrB.
  • an insulating layer 151 having a function of preventing hydrogen diffusion is preferably provided therebetween.
  • the reliability of the transistors TrC and TrD can be improved by confining hydrogen in one layer by the insulating layer 151.
  • the reliability of the transistors TrA and TrB can be improved.
  • the insulating layer 151 for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.
  • aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.
  • FIG. 17 shows a configuration example of the display system 300.
  • the display system 300 has a function of generating a signal (hereinafter also referred to as an image signal) for displaying an image based on data received from the outside, and displaying the image based on the signal.
  • the display system 300 can be used, for example, as a television system having a function of receiving broadcast signals and displaying images.
  • the display system 300 includes a display unit 310 and a signal generation unit 320. Note that both the display unit 310 and the signal generation unit 320 can be formed of a semiconductor device. Therefore, the display portion 310 and the signal generation portion 320 can also be called semiconductor devices.
  • the display unit 310 has a function of displaying an image based on the image signal input from the signal generation unit 320.
  • the display portion 310 includes a pixel portion 311, a driver circuit 312, and a driver circuit 313.
  • the pixel portion 311 includes a plurality of pixels and has a function of displaying an image. Each pixel has a display element and has a function of displaying an image of a predetermined gradation. The gradation of the image displayed on the pixel is controlled by signals output from the driving circuit 312 and the driving circuit 313, and a predetermined image is displayed on the pixel portion 311.
  • the driver circuit 312 has a function of supplying a signal for selecting a pixel (hereinafter also referred to as a selection signal) to the pixel portion 311.
  • the driver circuit 313 has a function of supplying a signal (hereinafter also referred to as an image signal) for displaying an image with a predetermined gradation on the pixel to the pixel portion 311.
  • a predetermined image is displayed on the pixel portion 311 by supplying an image signal to the pixel to which the selection signal is supplied.
  • the signal generation unit 320 has a function of generating an image signal based on data input from the outside.
  • the signal generation unit 320 includes a front end unit 321, a decoder 322, an image processing unit 333, a reception unit 334, an interface 335, and a control unit 336.
  • the front end unit 321 has a function of receiving a signal input from the outside and performing signal processing. Image data such as a broadcast signal is input to the front end unit 321.
  • the front end unit 321 can have a function of performing demodulation, digital-analog conversion, and the like of a received signal. Further, the front end unit 321 may have a function of performing error correction.
  • the decoder 322 has a function of decoding the encoded signal.
  • the signal is expanded by the decoder 322.
  • the decoder 322 can have functions for performing entropy decoding, inverse quantization, inverse orthogonal transform such as inverse discrete cosine transform (IDCT) and inverse discrete sine transform (IDST), intraframe prediction, and interframe prediction. .
  • IDCT inverse discrete cosine transform
  • IDST inverse discrete sine transform
  • the encoding standard for 8K broadcasting includes H.264. H.265 / MPEG-H High Efficiency Video Coding (hereinafter referred to as HEVC) is employed.
  • HEVC High Efficiency Video Coding
  • the decoder 322 performs CABAC (Context Adaptive Binary Arithmetic Coding) decoding.
  • the image processing unit 333 has a function of performing image processing on the signal input from the decoder 322. Specifically, the image processing unit 333 can have a function of performing gamma correction, light control, color adjustment, and the like. An image signal is generated by image processing by the image processing unit 333.
  • the receiving unit 334 has a function of receiving a control signal input from the outside.
  • the input of the control signal to the reception unit 334 can be performed using a remote controller, a portable information terminal (such as a smartphone or a tablet), an operation button provided on the display unit 310, or the like.
  • the interface 335 has a function of appropriately performing signal processing on the control signal received by the receiving unit 334 and outputting the signal to the control unit 336.
  • the control unit 336 has a function of supplying a control signal to each circuit included in the signal generation unit 320.
  • the control unit 336 has a function of supplying a control signal to the image processing unit 333. Control by the control unit 336 can be performed based on a control signal received by the reception unit 334.
  • the signal generation unit 320 includes an encoder 351, and the display unit 310 includes a decoder 352.
  • the encoder 351 has a function of extracting features of the image signal generated by the image processing unit 333 and compressing the image signal.
  • the decoder 352 has a function of expanding the image signal compressed by the encoder 351.
  • the display unit 310 and the signal generation unit 320 are connected using a cable such as FPC (Flexible Printed Circuits).
  • FPC Flexible Printed Circuits
  • the image signal is transmitted from the signal generation unit 320 to the display unit 310 in a compressed state. Therefore, the transmission of the image signal can be performed at high speed. In addition, the power required for transmitting the image signal can be reduced.
  • the encoder 351 the semiconductor device 10 described in the above embodiment can be used. Then, the image signal generated by the image processing unit 333 can be compressed by the semiconductor device 10.
  • An auto encoder AE can be used for data compression.
  • the encoder 351 can be provided with the encoder ENC shown in FIG. 6, and the decoder 352 can be provided with the decoder DEC shown in FIG. Then, the encoder 351 performs feature extraction of the image signal using the neural network NN1, and compresses the image signal using the neural network NN2.
  • the decoder 352 expands the image signal compressed using the neural network.
  • the resolution of the image signal input to the encoder 351 and the image signal output from the decoder 352 do not necessarily match.
  • the resolution of the image signal may be intentionally lowered for programs that the viewer does not feel dissatisfied even if the image quality is somewhat low, such as animations for children and news programs.
  • the resolution of the image data output from the decoder 352 is lower than the image data input to the encoder 351. Thereby, power consumption in the display unit 310 can be reduced.
  • FIG. 18A illustrates a configuration example of the display portion 310.
  • the display portion 310 includes a pixel portion 311, a driver circuit 312, and a driver circuit 313.
  • the pixel unit 311 includes a plurality of pixels pix.
  • the pixels pix are connected to the wiring SL and the wiring GL, respectively. Further, the wiring GL is connected to the driving circuit 312, and the wiring SL is connected to the driving circuit 313.
  • Each pixel pix has a display element.
  • the display element provided in the pixel pix include a liquid crystal element and a light emitting element.
  • a liquid crystal element a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, or the like can be used.
  • a display element a shutter type MEMS (Micro Electro Mechanical Systems) element, an optical interference type MEMS element, a microcapsule type, an electrophoretic method, an electrowetting method, an electropowder fluid (registered trademark) method, etc. are applied.
  • a display element or the like can also be used.
  • light-emitting elements include self-luminous light-emitting elements such as OLEDs (Organic Light Emitting Diodes), LEDs (Light Emitting Diodes), QLEDs (Quantum-dot Light Emitting Diodes), and semiconductor lasers.
  • OLEDs Organic Light Emitting Diodes
  • LEDs Light Emitting Diodes
  • QLEDs Quadantum-dot Light Emitting Diodes
  • semiconductor lasers A specific configuration example of the pixel pix will be described later.
  • the number of pixels pix can be set freely. In order to display a high-definition image, it is preferable to arrange many pixels. For example, when a 2K1K image is displayed, it is preferable to provide 1920 ⁇ 1080 pixels or more. In the case of displaying a 4K2K image, it is preferable to provide 3840 ⁇ 2160 pixels or more, or 4096 ⁇ 2160 pixels or more. In the case of displaying an 8K4K image, it is preferable to provide 7680 ⁇ 4320 or more pixels. In addition, the pixel portion 311 can display an image with a higher definition than 8K4K.
  • the drive circuit 312 has a function of supplying a selection signal to the pixel pix. Specifically, the drive circuit 312 has a function of supplying a selection signal to the wiring GL, and the wiring GL has a function of transmitting the selection signal output from the drive circuit 312 to the pixel pix. Note that the wiring GL can also be referred to as a selection signal line, a gate line, or the like.
  • the drive circuit 313 has a function of supplying an image signal to the pixel pix. Specifically, the drive circuit 313 has a function of supplying an image signal to the wiring SL, and the wiring SL has a function of transmitting the image signal output from the drive circuit 313 to the pixel pix. Note that the wiring SL can also be referred to as an image signal line, a source line, or the like.
  • FIG. 18B shows a configuration example of a pixel pix using a light-emitting element as a display element.
  • a pixel pix illustrated in FIG. 18B includes transistors Tr21 and Tr22, a capacitor C21, and a light emitting element LE.
  • the transistors Tr21 and Tr22 are n-channel type here, the polarity of the transistors can be changed as appropriate.
  • the gate of the transistor Tr21 is connected to the wiring GL, one of the source and the drain is connected to the gate of the transistor Tr22 and one electrode of the capacitor C21, and the other of the source or the drain is connected to the wiring SL.
  • One of the source and the drain of the transistor Tr22 is connected to the other electrode of the capacitor C21 and the one electrode of the light emitting element LE, and the other of the source and the drain is connected to a wiring to which the potential Va is supplied.
  • the other electrode of the light emitting element LE is connected to a wiring to which the potential Vc is supplied.
  • a node connected to one of the source and the drain of the transistor Tr21, the gate of the transistor Tr22, and one electrode of the capacitor C21 is referred to as a node N21.
  • a node connected to one of the source and the drain of the transistor Tr22 and the other electrode of the capacitor C21 is referred to as a node N22.
  • the potential Va is a high power supply potential and the potential Vc is a low power supply potential will be described.
  • the potential Va and the potential Vc can each be a common potential for the plurality of pixels pix.
  • the capacitor C21 functions as a storage capacitor for holding the potential of the node N21.
  • the transistor Tr21 has a function of controlling supply of the potential of the wiring SL to the node N21. Specifically, by controlling the potential of the wiring GL to turn on the transistor Tr21, the potential of the wiring SL corresponding to the image signal is supplied to the node N21, and writing to the pixel pix is performed. After that, the potential of the node N21 is held by controlling the potential of the wiring GL to turn off the transistor Tr21.
  • the amount of current flowing between the source and drain of the transistor Tr22 is controlled according to the voltage between the nodes N21 and N22, and the light emitting element LE emits light with a luminance corresponding to the amount of current. Thereby, the gradation of the image displayed on the pixel pix can be controlled.
  • the transistor Tr22 is preferably operated in a saturation region.
  • FIG. 18C shows a configuration example of both elements pix using a liquid crystal element as a display element.
  • a pixel pix illustrated in FIG. 18C includes a transistor Tr23, a capacitor C22, and a liquid crystal element LC.
  • the transistor Tr23 is an n-channel type here, the polarity of the transistor can be changed as appropriate.
  • the gate of the transistor Tr23 is connected to the wiring GL, one of the source and the drain is connected to one electrode of the liquid crystal element LC and one electrode of the capacitor C22, and the other of the source or drain is connected to the wiring SL. .
  • the other electrode of the liquid crystal element LC is connected to a wiring to which the potential Vcom is supplied.
  • the other electrode of the capacitive element C22 is connected to a wiring to which a predetermined potential is supplied.
  • a node connected to one of the source and the drain of the transistor Tr23, one electrode of the liquid crystal element LC, and one electrode of the capacitor C22 is referred to as a node N23.
  • the potential Vcom can be a common potential for a plurality of pixels pix. Note that the potential Vcom may be the same potential as the wiring connected to the other electrode of the capacitor C22. Further, the capacitor C22 has a function as a storage capacitor for holding the potential of the node N23.
  • the transistor Tr23 has a function of controlling supply of the potential of the wiring SL to the node N23. Specifically, by controlling the potential of the wiring GL to turn on the transistor Tr23, the potential of the wiring SL corresponding to the image signal is supplied to the node N23, and writing to the pixel pix is performed. After that, the potential of the node N23 is held by controlling the potential of the wiring GL to turn off the transistor Tr23.
  • the liquid crystal element LC includes a pair of electrodes and a liquid crystal layer including a liquid crystal material to which a voltage between the pair of electrodes is applied.
  • the orientation of the liquid crystal molecules contained in the liquid crystal element LC changes in accordance with the value of the voltage applied between the pair of electrodes, thereby changing the transmittance of the liquid crystal layer. Therefore, the gradation of an image displayed on the pixel pix can be controlled by controlling the potential supplied from the wiring SL to the node N23.
  • the first frame image can be displayed.
  • the progressive method or the interlace method may be used to select the wiring GL.
  • the supply of the image signal to the wiring SL may be performed using dot sequential driving for sequentially supplying the image signal to the wiring SL, or line sequential driving for supplying the image signal to all the wirings SL at the same time. You may go. Further, the image signal may be supplied in order for each of the plurality of wirings SL.
  • a Group 14 element such as silicon or germanium, a compound semiconductor such as gallium arsenide, an organic semiconductor, a metal oxide, or the like can be used.
  • the semiconductor may be a non-single-crystal semiconductor (amorphous semiconductor, microcrystalline semiconductor, polycrystalline semiconductor, or the like) or a single-crystal semiconductor.
  • the transistor included in the pixel pix preferably includes an amorphous semiconductor, particularly hydrogenated amorphous silicon (a-Si: H), in a channel formation region. Since a transistor using an amorphous semiconductor can easily cope with an increase in the area of a substrate, a manufacturing process is required when a large-screen display device that can handle 4K2K broadcasting, 8K4K broadcasting, or the like is manufactured. Can be simplified.
  • a-Si: H hydrogenated amorphous silicon
  • a transistor including a metal oxide in a channel formation region can be used as the transistor included in the pixel pix.
  • An OS transistor has higher field effect mobility than a transistor using hydrogenated amorphous silicon.
  • the crystallization step required for a transistor using polycrystalline silicon is not necessary.
  • the frequency of updating the image signal can be set extremely low in a period in which the image displayed on the pixel portion 311 is not changed or in a period in which the change is less than a certain value.
  • the frequency of updating the image signal can be set to, for example, not more than once every 0.1 seconds, or less than once per second, or less than once every 10 seconds.
  • FIG. 19 illustrates a configuration example of the display portion 310 in which the pixel portion 311 is divided into a plurality of regions.
  • the display unit 310 includes a pixel unit 311 having a plurality of pixels pix, a plurality of drive circuits 312, and a plurality of drive circuits 313.
  • the pixel portion 311 When a large number of pixels pix are provided in the pixel portion 311 in order to display high-resolution images such as 2K1K, 4K2K, and 8K4K, the lengths of the wiring GL and the wiring SL increase, and accordingly, the wiring GL and the wiring SL The parasitic resistance increases. Further, as shown in FIG. 19, the wiring GL and the wiring SL are provided so as to cross each other. Therefore, when the number of pixels pix increases, the number of intersections also increases, and the parasitic capacitance formed by the wiring GL and the wiring SL increases. Therefore, in FIG. 19, the pixel portion 311 is divided into a plurality of regions 315, and a driving circuit 312 and a driving circuit 313 are provided for each region 315.
  • the pixel portion 311 is divided into four regions 315 (315 (1,1) to 315 (2,2)), and the four regions 315 each have x rows and y columns (x, y columns). Is an integer of 1 or more).
  • four drive circuits 312 (312 (1, 1) to 312 (2, 2)) and four drive circuits 313 (313 (1, 1) to 313 (2, 2)) are provided.
  • a wiring GL connected to the driving circuits 312 (1, 1) and 312 (1, 2) is referred to as a wiring GL 1 and the driving circuits 312 (2, 1) and 312 (2, 2).
  • the wiring SL connected to the drive circuits 313 (1, 1), 313 (1, 2), 313 (2, 1), and 313 (2, 2) is connected to the wiring SL 11 , the wiring SL 12 , and the wiring SL, respectively. 21 and a wiring SL 22 .
  • Image signals are supplied from the driving circuits 313 (1, 1) to 313 (2, 2) to the regions 315 (1, 1) to 315 (2, 2), respectively. Therefore, the upper drive circuits 313 (313 (1, 1), 313 (1, 2) are connected to the pixels pix belonging to the upper region 315 (315 (1, 1), 315 (1, 2)) of the pixel portion 311. )), And the pixel pix belonging to the lower region 315 (315 (2, 1), 315 (2, 2)) of the pixel portion 311 is supplied to the lower drive circuit 313 (313 (2). , 1), 313 (2, 2)). Accordingly, since the wiring SL connected to the one driver circuit 313 can be shortened, parasitic resistance and parasitic capacitance can be reduced, and an image signal can be supplied at high speed. Therefore, a high resolution image can be accurately displayed.
  • the upper region of the pixel portion 311 is further divided into two regions 315 (1, 1) and 315 (1, 2), and the lower region of the pixel portion 311 is further divided into two regions 315.
  • a configuration example divided into (2, 1) and 315 (2, 2) is shown. In this case, the timing at which the image signals are output from the drive circuits 313 (1, 1) and 313 (1, 2) is synchronized, and the image signals are output from the drive circuits 313 (2, 1) and 313 (2, 2). Timing is synchronized.
  • a driver circuit that supplies image signals to the regions 315 (1, 1) and 315 (1, 2) is configured by a circuit in which the driver circuits 313 (1, 1) and 313 (1, 2) are integrated. Also good.
  • the driving circuit that supplies the image signals to the areas 315 (2, 1) and 315 (2, 2) is configured by a circuit in which the driving circuits 313 (2, 1) and 313 (2, 2) are integrated. Also good.
  • the drive circuits 313 (1, 1), 313 (1, 2), 313 (2, 1), and 313 (2, 2) may each be composed of a plurality of drive circuits.
  • two drive circuits 312 are connected to one wiring GL.
  • the pixels pix included in the regions 315 (1, 1) and 315 (1, 2) are connected to the drive circuits 312 (1, 1) and 312 (1, 2) via the wiring GL. Yes.
  • the pixels pix included in the regions 315 (2, 1) and 315 (2, 2) are connected to the drive circuits 312 (2, 1) and 312 (2, 2) through the wiring GL.
  • the timing at which the selection signals are output from the drive circuits 312 (1, 1) and 312 (1, 2) is synchronized, and the selection signals are output from the drive circuits 312 (2, 1) and 312 (2, 2). Timing is synchronized.
  • the selection signal can be supplied from both ends of the wiring GL, and the selection signal can be supplied at high speed. Note that when there is no problem in transmission of the selection signal, one of the drive circuits 312 (1, 1) and 312 (1, 2) and one of the drive circuits 312 (2, 1) and 312 (2, 2). Can be omitted.
  • FIG. 19 illustrates the case where the pixel portion 311 is divided into four regions 315, the number of divisions is not particularly limited and can be freely set.
  • FIG. 19 shows an example in which the number of columns and rows of the pixels pix included in the four regions 315 are the same.
  • the present invention is not limited to this, and the number of columns and rows of the pixels pix is Each can be set freely.
  • the number of areas 315 can be set to the number of divisions (N ⁇ M) of the data D in FIG. As a result, the image signal can be compressed and expanded for each region 315.
  • FIG. 20 shows a configuration example of the display unit 310 having a plurality of display panels DP.
  • Each of the plurality of display panels DP included in the display unit 310 has a function of displaying an image based on an image signal input from the signal generation unit 320 (see FIG. 17).
  • FIG. 20 shows a display unit 310 having a display panel DP with N rows and M columns.
  • Each of the plurality of display panels DP includes a pixel portion 311, a driver circuit 312, and a driver circuit 313 which are illustrated in FIG.
  • the display area of the image can be enlarged.
  • the display unit 310 having a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more can be realized.
  • a high-resolution display unit having a resolution of full high-definition or higher, for example, 2K1K, 4K2K, 8K4K, or higher can be realized.
  • the size of one display panel DP does not need to be large. Therefore, it is not necessary to increase the size of the manufacturing apparatus for manufacturing the display panel.
  • a manufacturing apparatus for a small and medium display panel can be used, it is not necessary to separately prepare equipment for a large display apparatus, and manufacturing costs can be reduced.
  • the number of display panels DP can be the number of divisions (N ⁇ M) of the data D in FIG. As a result, the image signal can be compressed and expanded for each display panel DP.
  • the plurality of display panels DP are arranged so that display areas are continuous between adjacent display panels DP.
  • a configuration example and an arrangement example of the display panel DP are shown in FIG.
  • a display panel DP illustrated in FIG. 21A includes a display region 371, a region 372 that transmits visible light, and a region 373 that blocks visible light, which are adjacent to the display region 371.
  • FIG. 21A illustrates an example in which an FPC 374 is provided on the display panel DP.
  • the display area 371 corresponds to the pixel unit 311 and includes a plurality of pixels pix (not shown).
  • a pair of substrates constituting the display panel DP and a sealing material for sealing the display elements sandwiched between the pair of substrates may be provided.
  • a member having a light-transmitting property with respect to visible light is used for a member provided in the region 372.
  • a wiring connected to the pixel pix included in the display region 371 can be provided.
  • the driver circuit 312 or the driver circuit 313 may be provided in the region 373.
  • a terminal connected to the FPC 374, a wiring connected to the terminal, and the like may be provided.
  • FIG. 21B illustrates an arrangement example of the display panel DP illustrated in FIG.
  • four adjacent display panels DPa, DPb, DPc, and DPd are shown.
  • FIG. 21C is a schematic perspective view when the four display panels are viewed from the side opposite to the display surface side.
  • Each display panel DP is arranged so as to have an area overlapping with another display panel DP.
  • the display panel DPa has a region in which the visible light transmission region 372 included in one display panel DP overlaps the display region 371 included in the other display panel DP (on the display surface side).
  • DPb, DPc, DPd are arranged.
  • the display panels DPa, DPb, DPc, and DPd are arranged so that the region 373 that shields visible light of one display panel DP does not overlap the display region 371 of the other display panel DP.
  • an area along the short side of the display area 371a of the display panel DPa and a part of the area 372b of the display panel DPb are provided so as to overlap each other.
  • an area along the long side of the display area 371a of the display panel DPa and a part of the area 372c of the display panel DPc are provided so as to overlap each other.
  • the area 372d of the display panel DPd is provided so as to overlap with the area along the long side of the display area 371b of the display panel DPb and the area along the short side of the display area 371c of the display panel DPc.
  • the entire display region 371 can be viewed from the display surface side.
  • an area in which the display areas 371a, 371b, 371c, and 371d are continuously arranged without a joint can be used as the display area 375 of the display unit 310.
  • substrate used for display panel DP has flexibility
  • display panel DP has flexibility.
  • a part of the display panel DPa on the side where the FPC 374a is provided is curved, and the FPC 374a is disposed below the display area 371b of the adjacent display panel DPb. can do.
  • the FPC 374a can be disposed without physically interfering with the back surface of the display panel DPb.
  • the display panel DPa and the display panel DPb are bonded together, it is not necessary to consider the thickness of the FPC 374a.
  • the upper surface of the area 372b of the display panel DPb and the upper surface of the display area 371a of the display panel DPa can be reduced. As a result, it can suppress that the edge part of display panel DPb located on the display area 371a is visually recognized.
  • the height of the upper surface of the display area 371b of the display panel DPb is made to coincide with the height of the upper surface of the display area 371a of the display panel DPa. Can be gently curved. Therefore, it is possible to make the heights of the respective display areas uniform except for the vicinity of the area where the display panel DPa and the display panel DPb overlap, and the display quality of the image displayed in the display area 375 can be improved.
  • the thickness of the display panel DP is preferably thin in order to reduce a step between two adjacent display panels DP.
  • the thickness of the display panel DP is 1 mm or less, preferably 300 ⁇ m or less, more preferably 100 ⁇ m or less.
  • FIG. 22 shows an example of a cross-sectional structure of the display device 400.
  • a transmissive liquid crystal element 420 is applied as a display element is shown.
  • the substrate 412 side is the display surface side.
  • the display device 400 has a structure in which a liquid crystal 422 is sandwiched between a substrate 411 and a substrate 412.
  • the liquid crystal element 420 includes a conductive layer 421 provided on the substrate 411 side, a conductive layer 423 provided on the substrate 412 side, and a liquid crystal 422 sandwiched therebetween.
  • An alignment film 424 a is provided between the liquid crystal 422 and the conductive layer 421, and an alignment film 424 b is provided between the liquid crystal 422 and the conductive layer 423.
  • the conductive layer 421 functions as a pixel electrode.
  • the conductive layer 423 functions as a common electrode or the like.
  • each of the conductive layers 421 and 423 has a function of transmitting visible light. Therefore, the liquid crystal element 420 is a transmissive liquid crystal element.
  • a colored layer 441 and a light shielding layer 442 are provided on the surface of the substrate 412 on the substrate 411 side.
  • An insulating layer 426 is provided to cover the coloring layer 441 and the light-blocking layer 442, and a conductive layer 423 is provided to cover the insulating layer 426.
  • the colored layer 441 is provided in a region overlapping with the conductive layer 421.
  • the light shielding layer 442 is provided to cover the transistor 430 and the connection portion 438.
  • a polarizing plate 439 a is disposed outside the substrate 411, and a polarizing plate 439 b is disposed outside the substrate 412. Further, a backlight unit 490 is provided outside the polarizing plate 439a.
  • the substrate 412 side is the display surface side.
  • a semiconductor layer 432, a transistor 430, a capacitor 460, and the like are provided over the substrate 411.
  • the transistor 430 functions as a pixel selection transistor.
  • the transistor 430 is connected to the liquid crystal element 420 through the connection portion 438.
  • a transistor 430 illustrated in FIG. 22 is a so-called bottom-gate / channel-etched transistor.
  • the transistor 430 includes a conductive layer 431 functioning as a gate electrode, an insulating layer 434 functioning as a gate insulating layer, a semiconductor layer 432, and a pair of conductive layers 433a and 433b functioning as a source electrode and a drain electrode.
  • a portion of the semiconductor layer 432 overlapping with the conductive layer 431 functions as a channel formation region.
  • the semiconductor layer 432 is connected to the conductive layer 433a and the conductive layer 433b.
  • the capacitor 460 includes a conductive layer 431a, an insulating layer 434, and a conductive layer 433b.
  • An insulating layer 482 and an insulating layer 481 are stacked to cover the transistor 430 and the like.
  • a conductive layer 421 functioning as a pixel electrode is provided over the insulating layer 481.
  • the conductive layers 421 and 433b are electrically connected to each other through openings provided in the insulating layers 481 and 482.
  • the insulating layer 481 preferably functions as a planarization layer.
  • the insulating layer 482 preferably has a function as a protective film for suppressing diffusion of impurities or the like into the transistor 430 or the like.
  • an inorganic insulating material can be used for the insulating layer 482 and an organic insulating material can be used for the insulating layer 481.
  • FIG. 23 illustrates an example in which the coloring layer 441 is provided on the substrate 411 side. Thereby, the structure by the side of the board
  • the insulating layer 481 may not be provided.
  • FIG. 24 is a schematic cross-sectional view of a display device having a liquid crystal element to which an FFS (Fringe Field Switching) mode is applied.
  • FFS Frringe Field Switching
  • the liquid crystal element 420 includes a conductive layer 421 that functions as a pixel electrode, and a conductive layer 423 that overlaps with the conductive layer 421 with the insulating layer 483 interposed therebetween.
  • the conductive layer 423 has a slit-like or comb-like upper surface shape.
  • a capacitor is formed in a portion where the conductive layer 421 and the conductive layer 423 overlap, and this can be used as the capacitor 460. Therefore, since the area occupied by the pixels can be reduced, a high-definition display device can be realized. In addition, the aperture ratio can be improved.
  • the conductive layer 423 functioning as a common electrode is positioned on the liquid crystal 422 side, but as shown in FIG. 25, the conductive layer 421 functioning as a pixel electrode may be positioned on the liquid crystal 422 side. Good. At this time, the conductive layer 421 has a slit-like or comb-like top shape.
  • the manufacturing cost can be reduced as the photolithography process in the manufacturing process is smaller, that is, as the number of photomasks is smaller.
  • a formation step of the conductive layer 431 and the like, a formation step of the semiconductor layer 432, a formation step of the conductive layer 433 a and the like, a formation step of the opening serving as the connection portion 438, And the conductive layer 421 can be manufactured through a total of five photolithography steps. That is, a backplane substrate can be manufactured using five photomasks.
  • a total of four photomasks can be reduced compared to the case where they are formed by a photolithography method.
  • a semiconductor containing silicon can be used for the semiconductor layer 432 or 432p of each transistor illustrated in FIGS.
  • the semiconductor containing silicon hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used, for example.
  • it is preferable to use hydrogenated amorphous silicon because it can be formed over a large substrate with high yield.
  • the display device of one embodiment of the present invention can display favorable images even with a transistor to which amorphous silicon with relatively low field-effect mobility is applied.
  • the transistor illustrated in FIG. 26A includes a pair of impurity semiconductor layers 435 functioning as a source region and a drain region.
  • the impurity semiconductor layer 435 is provided between the semiconductor layer 432 and the conductive layer 433a and between the semiconductor layer 432 and the conductive layer 433b.
  • the semiconductor layer 432 and the impurity semiconductor layer 435 are provided in contact with each other, and the impurity semiconductor layer 435 and the conductive layer 433a or the conductive layer 433b are provided in contact with each other.
  • the impurity semiconductor film included in the impurity semiconductor layer 435 is formed using a semiconductor to which an impurity element imparting one conductivity type is added.
  • a semiconductor to which an impurity element imparting one conductivity type is added includes, for example, silicon to which P or As is added.
  • B can be added as the impurity element imparting one conductivity type, but the transistor is preferably n-type.
  • the impurity semiconductor layer may be formed using an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor.
  • the transistor illustrated in FIG. 26B includes a semiconductor layer 437 between the semiconductor layer 432 and the impurity semiconductor layer 435.
  • the semiconductor layer 437 may be formed using a semiconductor film similar to the semiconductor layer 432.
  • the semiconductor layer 437 can function as an etching stopper for preventing the semiconductor layer 432 from disappearing by etching when the impurity semiconductor layer 435 is etched. Note that although FIG. 26B illustrates an example in which the semiconductor layer 437 is separated into right and left, a part of the semiconductor layer 437 may cover a channel formation region of the semiconductor layer 432.
  • the semiconductor layer 437 may contain a lower concentration of impurities than the impurity semiconductor layer 435. Accordingly, the semiconductor layer 437 can function as an LDD (Lightly Doped Drain) region, and hot carrier deterioration when the transistor is driven can be suppressed.
  • LDD Lightly Doped Drain
  • an insulating layer 484 is provided over a channel formation region of the semiconductor layer 432.
  • the insulating layer 484 functions as an etching stopper when the impurity semiconductor layer 435 is etched.
  • a transistor illustrated in FIG. 26D includes a semiconductor layer 432 p instead of the semiconductor layer 432.
  • the semiconductor layer 432p includes a semiconductor film with high crystallinity.
  • the semiconductor layer 432p includes a polycrystalline semiconductor or a single crystal semiconductor.
  • a transistor illustrated in FIG. 26E includes a semiconductor layer 432 p in a channel formation region of the semiconductor layer 432.
  • the transistor illustrated in FIG. 26E can be formed by being locally crystallized by irradiating a semiconductor film serving as the semiconductor layer 432 with laser light or the like. Thereby, a transistor with high field effect mobility can be realized.
  • the transistor illustrated in FIG. 26F includes a crystalline semiconductor layer 432p in a channel formation region of the semiconductor layer 432 of the transistor illustrated in FIG.
  • the transistor illustrated in FIG. 26G includes a crystalline semiconductor layer 432p in a channel formation region of the semiconductor layer 432 of the transistor illustrated in FIG.
  • an insulating layer 484 is provided over a channel formation region of the semiconductor layer 432.
  • the insulating layer 484 functions as an etching stopper when the conductive layers 433a and 433b are etched.
  • the insulating layer 484 covers the semiconductor layer 432 and extends over the insulating layer 434.
  • the conductive layer 433a and the conductive layer 433b are connected to the semiconductor layer 432 through an opening provided in the insulating layer 484.
  • a transistor illustrated in FIG. 27C includes an insulating layer 485 and a conductive layer 486.
  • the insulating layer 485 is provided to cover the semiconductor layer 432, the conductive layer 433a, and the conductive layer 433b.
  • the conductive layer 486 is provided over the insulating layer 485 and has a region overlapping with the semiconductor layer 432.
  • the conductive layer 486 is located on the side opposite to the conductive layer 431 with the semiconductor layer 432 interposed therebetween. In the case where the conductive layer 431 is a first gate electrode, the conductive layer 486 can function as a second gate electrode. By applying the same potential to the conductive layer 431 and the conductive layer 486, the on-state current of the transistor can be increased. Further, by applying a potential for controlling the threshold voltage to one of the conductive layers 431 and 486 and a potential for driving to the other, the threshold voltage of the transistor can be controlled.
  • the transistor illustrated in FIG. 27D is a top-gate transistor, and a conductive layer 431 functioning as a gate electrode is provided above the semiconductor layer 432 (on the side opposite to the formation surface).
  • An insulating layer 434 and a conductive layer 431 are stacked over the semiconductor layer 432.
  • the insulating layer 482 is provided so as to cover the upper surface and side end portions of the semiconductor layer 432 and the conductive layer 431.
  • the conductive layer 433 a and the conductive layer 433 b are provided over the insulating layer 482.
  • the conductive layers 433 a and 433 b are connected to the semiconductor layer 432 through openings provided in the insulating layer 482.
  • the insulating layer 434 may be provided so as to cover the upper surface and the side end portion of the semiconductor layer 432. .
  • a physical distance between the conductive layer 431 and the conductive layer 433a or the conductive layer 433b can be easily separated; thus, parasitic capacitance between them can be reduced.
  • the transistor illustrated in FIG. 27E is different from FIG. 27D in that it includes a conductive layer 487 and an insulating layer 488.
  • the conductive layer 487 has a region overlapping with the semiconductor layer 432.
  • the insulating layer 488 is provided so as to cover the conductive layer 487.
  • the conductive layer 487 functions as a second gate electrode. Therefore, it is possible to increase the on-current, control the threshold voltage, and the like.
  • the semiconductor layer 432 may include a region 432n.
  • the region 432n has a region in contact with the insulating layer 482 containing nitrogen or hydrogen. Then, nitrogen or hydrogen in the insulating layer 482 is added to the region 432n, so that the region 432n is n-type. In this case, the region 432n functions as a source region or a drain region. Note that the concentration of nitrogen or hydrogen contained in the region 432n is higher than that of the channel formation region. In addition, the carrier density of the region 432n is higher than that of the channel formation region.
  • the semiconductor layer 432 may include a region 432j.
  • the region 432j functions as a junction region between the channel formation region and the source region or the drain region.
  • the concentration of nitrogen or hydrogen contained in the region 432j is lower than the region 432n and higher than the channel formation region.
  • the carrier density of the region 432j is lower than that of the region 432n and higher than that of the channel formation region.
  • substrate As the substrate included in the display device, a material having a flat surface can be used. A substrate that extracts light from the display element is formed using a material that transmits the light. For example, materials such as glass, quartz, ceramic, sapphire, and organic resin can be used.
  • the display panel can be reduced in weight and thickness. Further, by using a substrate that is thin enough to have flexibility, a flexible display panel can be realized. Alternatively, glass that is thin enough to be flexible can be used for the substrate. Alternatively, a composite material in which glass and a resin material are bonded to each other with an adhesive layer may be used.
  • the transistor includes a conductive layer that functions as a gate electrode, a semiconductor layer, a conductive layer that functions as a source electrode, a conductive layer that functions as a drain electrode, and an insulating layer that functions as a gate insulating layer.
  • the structure of the transistor included in the display device of one embodiment of the present invention there is no particular limitation on the structure of the transistor included in the display device of one embodiment of the present invention.
  • a planar transistor, a staggered transistor, or an inverted staggered transistor may be used.
  • a top-gate or bottom-gate transistor structure may be employed.
  • gate electrodes may be provided above and below the channel.
  • crystallinity of the semiconductor material used for the transistor there is no particular limitation on the crystallinity of the semiconductor material used for the transistor, and either an amorphous semiconductor or a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor partially including a crystal region) is used. May be used. It is preferable to use a crystalline semiconductor because deterioration of transistor characteristics can be suppressed.
  • a semiconductor material used for the transistor for example, a Group 14 element (silicon, germanium, or the like) or a metal oxide can be used for the semiconductor layer.
  • a semiconductor containing silicon, a semiconductor containing gallium arsenide, a metal oxide containing indium, or the like can be used.
  • a semiconductor containing silicon hydrogenated amorphous silicon can be used, for example.
  • a transistor using a metal oxide having a larger band gap than silicon can hold charge accumulated in a capacitor connected in series with the transistor for a long time because of the low off-state current.
  • the driving circuit can be stopped while maintaining the gradation of an image displayed in each display region. As a result, a display device with extremely reduced power consumption can be realized.
  • the semiconductor layer is represented by an In-M-Zn-based oxide containing at least indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It is preferable to include a film. In addition, in order to reduce variation in electric characteristics of a transistor including the semiconductor layer, a stabilizer is preferably included together with the transistor.
  • Examples of the stabilizer include the metals described in M above, and examples include gallium, tin, hafnium, aluminum, and zirconium.
  • Other stabilizers include lanthanoids such as lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.
  • an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as main components, and there is no limitation on the ratio of In, Ga, and Zn. Metal elements other than Zn may be contained.
  • the semiconductor layer and the conductive layer may have the same metal element among the above oxides.
  • Manufacturing costs can be reduced by using the same metal element for the semiconductor layer and the conductive layer.
  • the manufacturing cost can be reduced by using metal oxide targets having the same metal composition.
  • an etching gas or an etching solution for processing the semiconductor layer and the conductive layer can be used in common.
  • the semiconductor layer and the conductive layer may have different compositions even if they have the same metal element. For example, a metal element in a film may be detached during a manufacturing process of a transistor and a capacitor to have a different metal composition.
  • the metal oxide constituting the semiconductor layer preferably has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
  • the metal oxide forming the semiconductor layer is an In-M-Zn oxide
  • the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ⁇ M, Zn ⁇ It is preferable to satisfy M.
  • the atomic ratio of the metal element of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element included in the sputtering target as an error.
  • the semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, more preferably 1 ⁇ 10 11 / cm 3. 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3, it is possible to use a 1 ⁇ 10 -9 / cm 3 metal oxide or more carrier density.
  • a semiconductor layer has stable characteristics because it has a low impurity concentration and a low density of defect states.
  • the material is not limited thereto, and a material having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor.
  • a material having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor.
  • the concentration of silicon or carbon in the semiconductor layer is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less. preferable.
  • the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry in the semiconductor layer is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less. preferable.
  • the semiconductor layer may have a non-single crystal structure, for example.
  • the non-single crystal structure includes, for example, a polycrystalline structure, a microcrystalline structure, or an amorphous structure.
  • the amorphous structure has the highest density of defect states.
  • a metal oxide having an amorphous structure has, for example, disordered atomic arrangement and no crystal component.
  • an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.
  • the semiconductor layer may be a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, and a single crystal structure region.
  • the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.
  • Examples of materials that can be used for a conductive layer such as a gate, a source, and a drain of a transistor as well as various wirings and electrodes constituting a display device include aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, A metal such as silver, tantalum, or tungsten, or an alloy containing the same as a main component can be given. A film containing any of these materials can be used as a single layer or a stacked structure.
  • Two-layer structure to stack, two-layer structure to stack copper film on titanium film, two-layer structure to stack copper film on tungsten film, titanium film or titanium nitride film, and aluminum film or copper film on top of it A three-layer structure for forming a titanium film or a titanium nitride film thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film stacked thereon, and a molybdenum film or a There is a three-layer structure for forming a molybdenum nitride film.
  • an oxide such as indium oxide, tin oxide, or zinc oxide may be used. Further, it is
  • a light-transmitting conductive material that can be used for conductive layers such as various wirings and electrodes included in a display device includes indium oxide, indium tin oxide, A conductive oxide such as indium zinc oxide, zinc oxide, zinc oxide to which gallium is added, or graphene can be used.
  • a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy material containing the metal material can be used.
  • a nitride (eg, titanium nitride) of the metal material may be used.
  • a metal material or an alloy material (or a nitride thereof) it may be thin enough to have a light-transmitting property.
  • a stacked film of the above materials can be used as a conductive layer.
  • a laminated film of an alloy of silver and magnesium and indium tin oxide because the conductivity can be increased.
  • conductive layers such as various wirings and electrodes constituting the display device and conductive layers (conductive layers functioning as pixel electrodes and common electrodes) included in the display element.
  • Insulating materials that can be used for each insulating layer include, for example, resins such as acrylic and epoxy, resins having a siloxane bond such as silicone, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide. Inorganic insulating materials can also be used.
  • the insulating film with low water permeability examples include a film containing nitrogen and silicon such as a silicon nitride film and a silicon nitride oxide film, and a film containing nitrogen and aluminum such as an aluminum nitride film.
  • a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like may be used.
  • liquid crystal element for example, a liquid crystal element to which a vertical alignment (VA: Vertical Alignment) mode is applied can be used.
  • VA Vertical Alignment
  • MVA Multi-Domain Vertical Alignment
  • PVA Power Planed Vertical Alignment
  • ASV Advanced Super View
  • liquid crystal elements to which various modes are applied can be used.
  • VA mode Transmission Nematic
  • IPS In-Plane-Switching
  • FFS Ringe Field Switching
  • ASM Analy Symmetrical Aligned Micro-cell
  • a liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal.
  • the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field).
  • a thermotropic liquid crystal a low molecular liquid crystal
  • a polymer liquid crystal a polymer dispersed liquid crystal
  • PNLC polymer network type liquid crystal
  • Ferroelectric liquid crystals antiferroelectric liquid crystals, and the like can be used.
  • These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.
  • liquid crystal material either a positive type liquid crystal or a negative type liquid crystal may be used, and an optimal liquid crystal material may be used according to an applied mode or design.
  • An alignment film can be provided to control the alignment of the liquid crystal.
  • liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used.
  • the blue phase is one of the liquid crystal phases.
  • a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic.
  • a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. .
  • liquid crystal element examples include a transmissive liquid crystal element, a reflective liquid crystal element, and a transflective liquid crystal element.
  • a transmissive liquid crystal element can be particularly preferably used.
  • two polarizing plates are provided so as to sandwich a pair of substrates.
  • a backlight is provided outside the polarizing plate.
  • the backlight may be a direct type backlight or an edge light type backlight. It is preferable to use a direct-type backlight including an LED (Light Emitting Diode) because local dimming is facilitated and contrast can be increased.
  • An edge light type backlight is preferably used because the thickness of the module including the backlight can be reduced.
  • see-through display can be performed by turning off the edge-light type backlight.
  • Examples of materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, and the like.
  • the light-shielding layer examples include carbon black, titanium black, metal, metal oxide, and composite oxide containing a solid solution of a plurality of metal oxides.
  • the light shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal.
  • a stacked film of a film containing a material for the colored layer can be used for the light shielding layer.
  • a stacked structure of a film including a material used for a colored layer that transmits light of a certain color and a film including a material used for a colored layer that transmits light of another color can be used. It is preferable to use a common material for the coloring layer and the light-shielding layer because the apparatus can be shared and the process can be simplified.
  • a display device using a liquid crystal element as a display element is described in this embodiment mode, a light-emitting element can also be used as a display element.
  • FIG. 28A is a top view illustrating a structural example of a transistor.
  • 28B is a cross-sectional view taken along line X1-X2 in FIG. 28A
  • FIG. 28C is a cross-sectional view taken along line Y1-Y2.
  • the X1-X2 line direction may be referred to as a channel length direction
  • the Y1-Y2 line direction may be referred to as a channel width direction.
  • FIG. 28B illustrates a cross-sectional structure of the transistor in the channel length direction
  • FIG. 28C illustrates a cross-sectional structure of the transistor in the channel width direction. Note that in order to clarify the device structure, some components are not illustrated in FIG.
  • the semiconductor device includes insulating layers 812 to 820, metal oxide films 821 to 824, and conductive layers 850 to 853.
  • the transistor 801 is formed on an insulating surface.
  • FIG. 28 illustrates the case where the transistor 801 is formed over the insulating layer 811.
  • the transistor 801 is covered with an insulating layer 818 and an insulating layer 819.
  • each of the insulating layer, the metal oxide film, the conductive layer, and the like included in the transistor 801 may be a single layer or a stack of a plurality of films.
  • various film forming methods such as sputtering, molecular beam epitaxy (MBE), pulsed laser ablation (PLA), CVD, atomic layer deposition (ALD) can be used.
  • the CVD method includes a plasma CVD method, a thermal CVD method, an organic metal CVD method, and the like.
  • the conductive layer 850 has a region functioning as a gate electrode of the transistor 801.
  • the conductive layer 851 and the conductive layer 852 have a region functioning as a source electrode or a drain electrode.
  • the conductive layer 853 includes a region functioning as a back gate electrode.
  • the insulating layer 817 has a region functioning as a gate insulating layer on the gate electrode (front gate electrode) side, and the insulating layer formed by stacking the insulating layers 814 to 816 functions as a gate insulating layer on the back gate electrode side. It has the area to do.
  • the insulating layer 818 functions as an interlayer insulating layer.
  • the insulating layer 819 functions as a barrier layer.
  • the metal oxide films 821 to 824 are collectively referred to as an oxide layer 830.
  • the oxide layer 830 includes a region where a metal oxide film 821, a metal oxide film 822, and a metal oxide film 824 are stacked in this order.
  • the pair of metal oxide films 823 are located over the conductive layers 851 and 852, respectively.
  • a channel formation region is mainly formed in the metal oxide film 822 in the oxide layer 830.
  • the metal oxide film 824 covers the metal oxide films 821 to 823, the conductive layer 851, and the conductive layer 852.
  • the insulating layer 817 is located between the metal oxide film 823 and the conductive layer 850.
  • the conductive layer 851 and the conductive layer 852 each have a region overlapping with the conductive layer 850 with the metal oxide film 823, the metal oxide film 824, and the insulating layer 817 interposed therebetween.
  • the conductive layer 851 and the conductive layer 852 are formed using a hard mask for forming the metal oxide film 821 and the metal oxide film 822. Therefore, the conductive layer 851 and the conductive layer 852 do not have a region in contact with the side surfaces of the metal oxide film 821 and the metal oxide film 822.
  • the metal oxide films 821 and 822, the conductive layer 851, and the conductive layer 852 can be manufactured through the following steps. First, a conductive film is formed over two stacked metal oxide films. The conductive film is processed (etched) into a desired shape to form a hard mask. The shape of the two-layer metal oxide film is processed using a hard mask, so that a stacked metal oxide film 821 and a metal oxide film 822 are formed. Next, the hard mask is processed into a desired shape, so that a conductive layer 851 and a conductive layer 852 are formed.
  • the insulating material used for the insulating layers 811 to 818 includes aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, Examples include yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate.
  • the insulating layers 811 to 818 are formed of a single layer or a stack of these insulating materials.
  • the layers forming the insulating layers 811 to 818 may include a plurality of insulating materials.
  • an oxynitride is a compound having a higher oxygen content than nitrogen
  • a nitrided oxide means a compound having a higher nitrogen content than oxygen
  • the insulating layers 816 to 818 are preferably insulating layers containing oxygen.
  • the insulating layers 816 to 818 are more preferably formed using an insulating film from which oxygen is released by heating (hereinafter also referred to as “insulating film containing excess oxygen”).
  • insulating film containing excess oxygen By supplying oxygen from the insulating film containing excess oxygen to the oxide layer 830, oxygen vacancies in the oxide layer 830 can be compensated. The reliability and electrical characteristics of the transistor 801 can be improved.
  • An insulating film containing excess oxygen refers to oxygen molecules in a temperature range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower in TDS (Thermal Desorption Spectroscopy).
  • a film having a release amount of 1.0 ⁇ 10 18 [molecules / cm 3 ] or more is used. Released oxygen molecules is more preferably 3.0 ⁇ 10 20 molecules / cm 3 or more.
  • the insulating film containing excess oxygen can be formed by performing treatment for adding oxygen to the insulating film.
  • the treatment for adding oxygen include heat treatment under an oxygen atmosphere, plasma treatment, treatment using an ion implantation method, ion doping method, or plasma immersion ion implantation method.
  • oxygen gas such as 16 O 2 or 18 O 2 , nitrous oxide gas, or ozone gas can be used.
  • the hydrogen concentration in the insulating layers 812 to 819 is preferably reduced.
  • the hydrogen concentration is 2 ⁇ 10 20 atoms / cm 3 or less, preferably 5 ⁇ 10 19 atoms / cm 3 or less, more preferably 1 ⁇ 10 19 atoms / cm 3 or less, and 5 ⁇ More preferably, it is 10 18 atoms / cm 3 or less.
  • the above-mentioned hydrogen concentration is a value measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).
  • the transistor 801 preferably has a structure in which the oxide layer 830 is surrounded by an insulating layer having a barrier property against oxygen and hydrogen (hereinafter also referred to as a barrier layer). With such a structure, release of oxygen from the oxide layer 830 and entry of hydrogen into the oxide layer 830 can be suppressed. The reliability and electrical characteristics of the transistor 801 can be improved.
  • the insulating layer 819 may function as a barrier layer, and at least one of the insulating layers 811, 812, and 814 may function as a barrier layer.
  • the barrier layer can be formed using a material such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or silicon nitride.
  • the insulating layers 811 to 818 each function as a barrier layer.
  • the insulating layers 816 to 818 are oxide layers containing excess oxygen.
  • the insulating layer 811 is silicon nitride
  • the insulating layer 812 is aluminum oxide
  • the insulating layer 813 is silicon oxynitride.
  • the insulating layers 814 to 816 each functioning as a gate insulating layer on the back gate electrode side are stacked layers of silicon oxide, aluminum oxide, and silicon oxide.
  • the insulating layer 817 having a function as a gate insulating layer on the front gate electrode side is silicon oxynitride.
  • the insulating layer 818 functioning as an interlayer insulating layer is silicon oxide.
  • the insulating layer 819 is aluminum oxide.
  • the conductive material used for the conductive layers 850 to 853 includes a metal such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or a metal nitride containing any of the above metals (tantalum nitride, Titanium nitride, molybdenum nitride, tungsten nitride) and the like.
  • a conductive material such as tin oxide can be used.
  • the conductive layer 850 is tantalum nitride, a single tungsten layer, or a stacked layer of tantalum nitride and tungsten (conductive layers 850a and 850b).
  • the conductive layer 850 is a stack including tantalum nitride, tantalum, and tantalum nitride.
  • the conductive layer 851 is a single layer of tantalum nitride or a stack of tantalum nitride and tungsten.
  • the structure of the conductive layer 852 is the same as that of the conductive layer 851.
  • the conductive layer 853 is a single layer of tantalum nitride or a stacked layer of tantalum nitride and tungsten (conductive layers 853a and 853b).
  • the metal oxide film 822 preferably has a large energy gap, for example.
  • the energy gap of the metal oxide film 822 is 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.
  • the oxide layer 830 preferably has crystallinity. At least, the metal oxide film 822 preferably has crystallinity. With the above structure, the transistor 801 with excellent reliability and electrical characteristics can be realized.
  • Examples of the oxide that can be used for the metal oxide film 822 are In—Ga oxide, In—Zn oxide, and In—M—Zn oxide (M is Al, Ga, Y, or Sn).
  • the metal oxide film 822 is not limited to the oxide layer containing indium.
  • the metal oxide film 822 can be formed using, for example, a Zn—Sn oxide, a Ga—Sn oxide, a Zn—Mg oxide, or the like.
  • the metal oxide films 821, 823, and 824 can also be formed using the same oxide as the metal oxide film 822. In particular, each of the metal oxide films 821, 823, and 824 can be formed using a Ga oxide.
  • the metal oxide film 821 preferably includes at least one of metal elements included in the metal oxide film 822 as a component. Accordingly, an interface state is hardly formed at the interface between the metal oxide film 822 and the metal oxide film 821, and variation in electrical characteristics such as a threshold voltage of the transistor 801 can be reduced.
  • the metal oxide film 824 preferably includes at least one of metal elements included in the metal oxide film 822 as a component. Accordingly, interface scattering is unlikely to occur at the interface between the metal oxide film 822 and the metal oxide film 824, and movement of carriers is hardly inhibited, so that the field-effect mobility of the transistor 801 can be increased.
  • the metal oxide film 822 preferably has the highest carrier mobility. Accordingly, a channel can be formed in the metal oxide film 822 that is separated from the insulating layers 816 and 817.
  • an In-containing metal oxide such as an In-M-Zn oxide can increase carrier mobility by increasing the In content.
  • In-M-Zn oxides s orbitals of heavy metals mainly contribute to carrier conduction, and by increasing the indium content, more s orbitals overlap, so an oxide with a high indium content is The mobility is higher than that of an oxide having a low indium content. Therefore, carrier mobility can be increased by using an oxide containing a large amount of indium for the metal oxide film.
  • the metal oxide film 822 is formed using In—Ga—Zn oxide, and the metal oxide films 821 and 823 are formed using Ga oxide.
  • the In content in the metal oxide films 822 is higher than the In content in the metal oxide films 821 and 823.
  • the In content can be changed by changing the atomic ratio of the metal element of the target.
  • the atomic ratio In: M: Zn of the target metal element used for forming the metal oxide film 822 is preferably 1: 1: 1, 3: 1: 2, or 4: 2: 4.1.
  • the atomic ratio In: M: Zn of the target metal element used for forming the metal oxide films 821 and 823 is preferably 1: 3: 2 or 1: 3: 4.
  • the impurity concentration of the oxide layer 830 is preferably reduced.
  • hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component are impurities.
  • hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density.
  • Silicon and carbon contribute to the formation of impurity levels in the metal oxide.
  • the impurity level becomes a trap and may deteriorate the electrical characteristics of the transistor.
  • the oxide layer 830 has a region with a silicon concentration of 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less. The same applies to the carbon concentration of the oxide layer 830.
  • the oxide layer 830 has a region with an alkali metal concentration of 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less. The same applies to the alkaline earth metal concentration of the oxide layer 830.
  • the oxide layer 830 has a hydrogen concentration of less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , more preferably It has a region of less than 1 ⁇ 10 18 atoms / cm 3 .
  • the impurity concentration of the oxide layer 830 listed above is a value obtained by SIMS.
  • the metal oxide film 822 has oxygen vacancies
  • hydrogen may enter a site of oxygen vacancies to form donor levels.
  • the on-state current of the transistor 801 is reduced. Note that oxygen deficient sites are more stable when oxygen enters than when hydrogen enters. Therefore, the on-state current of the transistor 801 can be increased by reducing oxygen vacancies in the metal oxide film 822 in some cases. Therefore, it is effective for the on-current characteristics to reduce hydrogen in the metal oxide film 822 so that hydrogen does not enter oxygen deficient sites.
  • Hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Since the channel formation region is provided in the metal oxide film 822, the transistor 801 is likely to be normally on when the metal oxide film 822 contains hydrogen. For this reason, it is preferable that hydrogen in the metal oxide film 822 be reduced as much as possible.
  • the metal oxide film 822 may include an n-type region 822n in a region in contact with the conductive layer 851 or the conductive layer 852.
  • oxygen in the metal oxide film 822 is extracted to the conductive layer 851 or the conductive layer 852, or a conductive material contained in the conductive layer 851 or the conductive layer 852 is combined with an element in the metal oxide film 822. It is formed by a phenomenon such as.
  • contact resistance between the conductive layer 851 or the conductive layer 852 and the metal oxide film 822 can be reduced.
  • FIG. 28 illustrates an example in which the oxide layer 830 has a four-layer structure; however, the invention is not limited to this.
  • the oxide layer 830 can have a three-layer structure without the metal oxide film 821 or the metal oxide film 823.
  • a metal oxide film similar to the metal oxide films 821 to 824 may be placed between any layers of the oxide layer 830, at least two places above the oxide layer 830 and below the oxide layer 830. Layers or multiples can be provided.
  • FIG. 29 is a schematic diagram of an energy band structure of a channel formation region of the transistor 801.
  • Ec816e, Ec821e, Ec822e, Ec824e, and Ec817e indicate the energy at the lower end of the conduction band of the insulating layer 816, the metal oxide film 821, the metal oxide film 822, the metal oxide film 824, and the insulating layer 817, respectively. ing.
  • the difference between the vacuum level and the energy at the bottom of the conduction band is obtained by subtracting the energy gap from the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Value.
  • the energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300).
  • the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) device (PHI VersaProbe).
  • UPS ultraviolet photoelectron spectroscopy
  • Ec816e and Ec817e are closer to a vacuum level (smaller electron affinity) than Ec821e, Ec822e, and Ec824e.
  • the metal oxide film 822 has a higher electron affinity than the metal oxide films 821 and 824.
  • the difference in electron affinity between the metal oxide film 822 and the metal oxide film 821 and the difference in electron affinity between the metal oxide film 822 and the metal oxide film 824 are 0.07 eV or more and 1.3 eV or less, respectively. It is.
  • the difference in electron affinity is preferably from 0.1 eV to 0.7 eV, and more preferably from 0.15 eV to 0.4 eV. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.
  • a channel is mainly formed in the metal oxide film 822 having high electron affinity among the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824. It is formed.
  • the metal oxide film 824 preferably contains indium gallium oxide.
  • the gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.
  • the metal oxide film 821 and the metal oxide film 822 may be a mixed region of the metal oxide film 821 and the metal oxide film 822 between the metal oxide film 821 and the metal oxide film 822.
  • the oxide layer 830 having such an energy band structure, electrons mainly move through the metal oxide film 822. Therefore, even if a level exists at the interface between the metal oxide film 821 and the insulating layer 816 or at the interface between the metal oxide film 824 and the insulating layer 817, the oxide layer 830 is caused by these interface levels. Since the movement of electrons moving inside is hardly inhibited, the on-state current of the transistor 801 can be increased.
  • the difference between Ec821e and Ec822e and the difference between Ec824e and Ec822e are preferably 0.1 eV or more, More preferably, it is 0.15 eV or more.
  • the transistor 801 can have a structure without a back gate electrode.
  • FIG. 30 illustrates an example of a stacked structure of a semiconductor device 860 in which a transistor Tr100 that is a Si transistor, a Tr200 that is an OS transistor, and a capacitor C100 are stacked.
  • the semiconductor device 860, CMOS layer 871, the wiring layer W 1 to W 5, is composed of a stacked transistor layer 872, the wiring layer W 6, W 7.
  • a transistor Tr100 is provided in the CMOS layer 871.
  • a channel formation region of the transistor Tr100 is provided in the single crystal silicon wafer 870.
  • the gate electrode 873 of the transistor Tr100 via the wiring layer W 1 to W 5, and is connected to one electrode 875 of the capacitor C100.
  • a transistor Tr200 is provided in the transistor layer 872.
  • the transistor Tr200 has a structure similar to that of the transistor 801 (FIG. 28).
  • An electrode 874 corresponding to one of a source and a drain of the transistor Tr200 is connected to one electrode 875 of the capacitor C100.
  • the transistor Tr200 is exemplified a case having a back gate electrode to the wiring layer W 5. Further, the wiring layer W 6 being the capacitor C100 is provided.
  • the circuit area can be reduced by stacking the OS transistor and other elements.
  • the above structure can be used for the semiconductor device described in the above embodiment.
  • the transistor Tr100 can be used as the transistors Tr2 and Tr3 in FIG. 12
  • the transistor Tr200 can be used as the transistor Tr1
  • the capacitor C100 can be used as the capacitor C1.
  • the transistor Tr100 can be provided in the same layer as the transistors TrC and TrD in FIG. 16A, and the transistor Tr200 can be provided in the same layer as the transistors TrA and TrB in FIG.
  • the CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is a carrier. This function prevents electrons from flowing.
  • a function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
  • the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-described conductive function
  • the insulating region has the above-described insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material, respectively.
  • the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
  • the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
  • the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
  • CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
  • the CAC-OS is one structure of a material in which elements forming a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
  • elements forming a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
  • the state mixed with is also referred to as a mosaic or patch.
  • the metal oxide preferably contains at least indium.
  • One kind selected from the above or a plurality of kinds may be included.
  • a CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
  • X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1 or in X2 Zn Y2 O Z2, is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.
  • CAC-OS includes a region GaO X3 is the main component, and In X2 Zn Y2 O Z2, or InO x1 is the main component region is a composite metal oxide having a structure that is mixed.
  • the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
  • IGZO is a common name and may refer to one compound of In, Ga, Zn, and O.
  • ZnO ZnO
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystal) structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
  • CAC-OS relates to a material structure of a metal oxide.
  • CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In.
  • the region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
  • the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions.
  • a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
  • a region GaO X3 is the main component, and In X2 Zn Y2 O Z2 or InO x1 is the main component region, in some cases clear boundary can not be observed.
  • the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In.
  • the region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.
  • the CAC-OS can be formed by a sputtering method, for example, without heating the substrate.
  • a CAC-OS is formed by a sputtering method
  • any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good.
  • the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .
  • the CAC-OS has a feature that a clear peak is not observed when measurement is performed using a ⁇ / 2 ⁇ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.
  • XRD X-ray diffraction
  • an electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam) has a ring-like region having a high luminance and a plurality of bright regions in the ring region. A point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
  • a region in which GaO X3 is a main component is obtained by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In X2 Zn Y2 O Z2 or InO x1 is a main component is unevenly distributed and mixed.
  • EDX energy dispersive X-ray spectroscopy
  • the CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That, CAC-OS is a region such as GaO X3 is a region which is a main component, In X2 Zn Y2 O Z2 or InO x1 is phase-separated from each other region and, in the main component, is mainly composed of the elements Has a mosaic structure.
  • a region containing In X2 Zn Y2 O Z2 or InO x1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2 or InO x1, is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In X2 Zn Y2 O Z2 or InO x1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility ( ⁇ ) can be realized.
  • areas such as GaO X3 is the main component, as compared to the In X2 Zn Y2 O Z2 or InO x1 is the main component area, it is highly regions insulating. That is, a region containing GaO X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor element, high insulation is achieved by the complementary action of the insulating properties caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO x1.
  • An on-current (I on ) and high field effect mobility ( ⁇ ) can be realized.
  • CAC-OS is optimal for various semiconductor devices.
  • the semiconductor device can be used for a camera module or the like.
  • the camera module can be added with a function of compressing image data using artificial intelligence.
  • FIG. 31 shows a configuration example of the camera module 2000.
  • the camera module 2000 includes a lens unit 2001, an autofocus unit 2002, a lid glass 2003, a sensor cover 2004, a semiconductor device 2005, a substrate 2006, and an FPC 2007.
  • the semiconductor device 2005 (see FIG. 1) can be mounted on the semiconductor device 2005.
  • the camera module 2000 includes a display device, a personal computer, an image playback device including a recording medium (typically a device having a display that can play back a recording medium such as a DVD: Digital Versatile Disc, and display the image). It can be used for various electronic devices.
  • electronic devices that can use the semiconductor device according to one embodiment of the present invention, mobile phones, portable game machines, portable data terminals, electronic book terminals, video cameras, digital still cameras, and the like , Goggles type display (head-mounted display), navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, etc. Is mentioned. Specific examples of these electronic devices are shown in FIGS.
  • FIG. 32A illustrates a portable game machine including a housing 3001, a housing 3002, a display portion 3003, a display portion 3004, a microphone 3005, a speaker 3006, operation keys 3007, a stylus 3008, a camera 3009, and the like. Note that although the portable game machine illustrated in FIG. 32A includes two display portions 3003 and 3004, the number of display portions included in the portable game device is not limited thereto.
  • the semiconductor device 10 according to one embodiment of the present invention can be used for the camera 3009.
  • FIG. 32B illustrates a portable data terminal, which includes a housing 3011, a display portion 3012, a camera 3019, and the like. Information can be input and output by a touch panel function of the display portion 3012.
  • the semiconductor device 10 according to one embodiment of the present invention can be used for the camera 3019.
  • FIG. 32C illustrates a wristwatch-type information terminal, which includes a housing 3031, a display portion 3032, a wristband 3033, a camera 3039, and the like.
  • the display unit 3032 may be a touch panel.
  • the semiconductor device 10 according to one embodiment of the present invention can be used for the camera 3039.
  • FIG. 32D illustrates a monitoring camera, which includes a housing 3051, a lens 3052, a support portion 3053, and the like.
  • This monitoring camera can include the semiconductor device of one embodiment of the present invention.
  • FIG. 32E illustrates a digital camera, which includes a housing 3061, a shutter button 3062, a microphone 3063, a light-emitting portion 3067, a lens 3065, and the like.
  • This digital camera can include the semiconductor device of one embodiment of the present invention.
  • FIG. 32F illustrates a video camera, which includes a first housing 3071, a second housing 3072, a display portion 3073, operation keys 3074, a lens 3075, a connection portion 3076, and the like.
  • the operation key 3074 and the lens 3075 are provided in the first housing 3071
  • the display portion 3073 is provided in the second housing 3072.
  • the first housing 3071 and the second housing 3072 are connected by the connection portion 3076, and the angle between the first housing 3071 and the second housing 3072 can be changed by the connection portion 3076. is there.
  • the image on the display unit 3073 may be switched according to the angle between the first housing 3071 and the second housing 3072 in the connection unit 3076.
  • the semiconductor device of one embodiment of the present invention can be provided at a position where the lens 3075 is focused.
  • the display system including the semiconductor device described in any of the above embodiments can be mounted on an electronic device.
  • 33 and 34 show examples of electronic devices in which the display system described in the above embodiment can be mounted.
  • FIG. 33A illustrates an example of a television device.
  • a display portion 7000 is incorporated in a housing 7101.
  • a structure in which the housing 7101 is supported by a stand 7103 is shown.
  • Operation of the television device 7100 illustrated in FIG. 33A can be performed with an operation switch included in the housing 7101 or a separate remote controller 7111.
  • the display portion 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display portion 7000 with a finger or the like.
  • the remote controller 7111 may include a display unit that displays information output from the remote controller 7111. Channels and volume can be operated with an operation key or a touch panel included in the remote controller 7111, and an image displayed on the display portion 7000 can be operated.
  • the television device 7100 is provided with a receiver, a modem, and the like.
  • a general television broadcast can be received by the receiver.
  • information communication is performed in one direction (from the sender to the receiver) or in two directions (between the sender and the receiver or between the receivers). It is also possible.
  • FIG. 33B illustrates a laptop personal computer 7200.
  • a laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like.
  • a display portion 7000 is incorporated in the housing 7211.
  • 34A and 34B show examples of digital signage (electronic signage).
  • a digital signage 7300 illustrated in FIG. 34A includes a housing 7301, a display portion 7000, a speaker 7303, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.
  • FIG. 34B illustrates a digital signage 7400 attached to a columnar column 7401.
  • the digital signage 7400 includes a display portion 7000 provided along the curved surface of the column 7401.
  • the wider the display unit 7000 the more information can be provided at one time.
  • the wider the display unit 7000 the more easily noticeable to the human eye.
  • the advertising effect can be enhanced.
  • a touch panel By applying a touch panel to the display unit 7000, not only an image is displayed on the display unit 7000, but also a user can operate intuitively, which is preferable. In addition, when it is used for providing information such as route information or traffic information, usability can be improved by an intuitive operation.
  • the digital signage 7300 or the digital signage 7400 can be linked with the information terminal 7311 or the information terminal 7411 such as a smartphone possessed by the user by wireless communication.
  • advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). As a result, an unspecified number of users can participate and enjoy the game at the same time.
  • 10 semiconductor device 20 reduction unit, 20a reduction unit, 30 classification unit, 40 division unit, 40a division unit, 50 distribution unit, 60 compression unit, 70 storage unit, 71 drive circuit, 72 drive circuit, 80 calculation unit, 90 storage Device, 100 imaging device, 110 light receiving unit, 111 pixel, 120 compression unit, 130 single crystal semiconductor substrate, 141 electrode, 142 photoelectric conversion unit, 143 electrode, 144 partition, 151 insulation layer, 300 display system, 310 display unit, 311 Pixel part, 312 drive circuit, 313 drive circuit, 315 area, 320 signal generation part, 321 front end part, 322 decoder, 33 Image processing unit, 334 receiving unit, 335 interface, 336 control unit, 351 encoder, 352 decoder, 371 display area, 371a display area, 371b display area, 371c display area, 371d display area, 372c area, 372c area, 372b area 372d area, 373 area, 374 FPC, 374a FPC, 375 display area, 400 display device, 411 substrate,

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Abstract

L'invention concerne un nouveau dispositif à semi-conducteur. Le dispositif à semi-conducteur a une fonction de compactage de données utilisant l'intelligence artificielle. Plus spécifiquement, le dispositif à semi-conducteur comporte un réseau neuronal artificiel et a une fonction de classification de données d'image et de compactage de données d'image qui correspond au résultat de la classification par inférence (cognition) effectuée par le réseau neuronal artificiel. Ainsi, étant donné que les données d'image peuvent être efficacement compactées conformément à l'attribut de celles-ci, il est possible de compacter des données d'image à un taux de compression élevé avec une dégradation mineure, ce qui permet d'améliorer la précision du dispositif à semi-conducteur.
PCT/IB2018/052221 2017-04-11 2018-03-30 Dispositif à semi-conducteur, dispositif d'imagerie et système d'affichage WO2018189613A1 (fr)

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US11276793B2 (en) 2020-06-04 2022-03-15 Visera Technologies Company Limited Semiconductor device
JP7109518B2 (ja) 2020-06-04 2022-07-29 采▲ぎょく▼科技股▲ふん▼有限公司 半導体装置
WO2024084660A1 (fr) * 2022-10-20 2024-04-25 日本電気株式会社 Dispositif de codage d'image, dispositif de décodage d'image, système de traitement des images, dispositif d'apprentissage de modèle, procédé de codage d'image, procédé de décodage d'image et support d'enregistrement lisible par ordinateur

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