WO2018188312A1 - 用于显示面板的放电控制电路和方法以及显示装置 - Google Patents

用于显示面板的放电控制电路和方法以及显示装置 Download PDF

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Publication number
WO2018188312A1
WO2018188312A1 PCT/CN2017/107574 CN2017107574W WO2018188312A1 WO 2018188312 A1 WO2018188312 A1 WO 2018188312A1 CN 2017107574 W CN2017107574 W CN 2017107574W WO 2018188312 A1 WO2018188312 A1 WO 2018188312A1
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WIPO (PCT)
Prior art keywords
supply voltage
control circuit
display panel
representation
discharge control
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Ceased
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PCT/CN2017/107574
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English (en)
French (fr)
Inventor
王建军
汪敏
马睿
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/763,135 priority Critical patent/US11403980B2/en
Publication of WO2018188312A1 publication Critical patent/WO2018188312A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a discharge control circuit and method for a display panel, and a display device including the same.
  • the display device is generally provided with a discharge control circuit for eliminating the afterimage of the shutdown.
  • the discharge control circuit monitors a change in the power supply voltage when the display device is turned off, and initiates discharge of the pixel array in the display device when the discharge condition is satisfied, for example, by turning on a switching thin film transistor (TFT) in each pixel circuit. This allows the charge stored in each pixel circuit to be released, thereby eliminating the shutdown artifacts.
  • TFT switching thin film transistor
  • the discharge control circuit may malfunction due to erroneous detection that the discharge condition is satisfied, resulting in an undesirable expectation for the pixel circuit or the like. Damage.
  • a discharge control circuit for a display panel including a pixel array.
  • the discharge control circuit includes a flip flop configured to generate a representation of the power supply voltage based on a power supply voltage of the display panel, the representation of the power supply voltage being such that a pixel array of the display panel is discharged
  • the discharge condition can be unsatisfied when the display panel is powered on or during operation and is satisfied when the display panel is turned off; and a level shifter configured to control timing signals for controlling operation of the pixel array Level shifting is performed and the level shifted said timing signal is provided to the display panel, and discharging of the pixel array is initiated in response to the discharging condition being satisfied.
  • the flip flop is configured to cancel by a rising edge of the supply voltage to a steeper rising edge in the representation of the supply voltage or in a representation of the supply voltage The rising edge of the supply voltage generates a representation of the supply voltage.
  • the flip-flop includes a Schmitt trigger configured to cause a rising edge of the supply voltage to be converted to a steeper of the representation of the supply voltage A rising edge and the falling edge of the supply voltage is converted to a steeper falling edge in the representation of the supply voltage.
  • the Schmitt trigger has a forward threshold voltage that is selected such that a rising edge of the supply voltage during the rising edge of the supply voltage is at the discharge The rising edge of the representation of the supply voltage is converted before the condition is satisfied.
  • the Schmitt trigger has a negative threshold voltage that is within a selected range that is less than a nominal value of the supply voltage such that at the supply voltage The falling edge of the supply voltage during the falling edge is converted as early as the falling edge of the representation of the supply voltage.
  • the negative threshold voltage is in the range of 80% to 90% of the nominal value of the supply voltage.
  • the flip flop includes a falling edge flip flop that is insensitive to a rising edge of the supply voltage such that a rising edge of the supply voltage is cancelled in the representation of the supply voltage.
  • the discharge control circuit further includes a voltage dividing circuit connected between the power supply voltage and a ground voltage to output the divided power supply voltage. The flip flop is configured to receive the divided supply voltage and convert it to a representation of the supply voltage.
  • the trigger is built into the level shifter.
  • the voltage divider circuit includes a resistor in series.
  • the discharge control circuit further includes a voltage converter operable to generate the supply voltage from an input voltage.
  • the voltage converter is selected from the group consisting of a linear regulator and a DC/DC converter.
  • the linear regulator is a low dropout linear regulator.
  • a display device comprising: a display panel including a pixel array; a timing controller configured to provide a timing signal for controlling an operation of the pixel array; and as described above Discharge control circuit.
  • a method of controlling discharge of a pixel array in a display panel using a discharge control circuit as described above includes generating a representation of the power supply voltage based on a power supply voltage of the display panel, the representation of the power supply voltage being such that a discharge condition under which a pixel array of the display panel is discharged can be turned on when the display panel is powered on Or during operation is not satisfied and is satisfied when the display panel is turned off; and initiating discharge of the pixel array in response to the discharge condition being satisfied.
  • generating the representation of the supply voltage includes converting a rising edge of the supply voltage to a steeper rising edge in the representation of the supply voltage or in a representation of the supply voltage The rising edge of the power supply voltage is cancelled. .
  • FIG. 1 is a block diagram of a typical discharge control circuit for a display panel
  • FIG. 2 is a block diagram of a display device in accordance with an embodiment of the present disclosure
  • FIG. 3 is a block diagram of a discharge control circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram showing input-output characteristics of a Schmitt trigger as a flip-flop in the discharge control circuit shown in FIG. 3;
  • Figure 5 is a block diagram showing a modification of the discharge control circuit shown in Figure 3;
  • Figure 6 is a block diagram of a variation of the discharge control circuit shown in Figure 5;
  • FIG. 7 is a flow chart of a discharge control method in accordance with an embodiment of the present disclosure.
  • the discharge control circuit includes a low dropout regulator LDO, resistors R1 and R2, and a level shifter LS.
  • the low dropout regulator LDO converts the input voltage Vin to the supply voltage DVDD.
  • the power supply voltage DVDD is divided by the resistors R1 and R2, and the divided voltage is supplied to the level shifter LS as the voltage monitor signal XAO.
  • the level shifter LS operates to level shift the timing signal from the timing controller TCON such that the level shifted timing signal satisfies the logic level requirements required to drive the display panel.
  • the timing controller TCON operates in a logic level configuration having a high level of 3.3V and a low level of 0V, while the display panel has a high level VGH (eg, 24V) and a low level VGL (eg, - 7V) operates in a logic level configuration.
  • the level shifter LS operates to shift the high and low levels of the timing signal supplied from the timing controller TCON from 3.3V to 24V and from 0V to -7V, respectively, while maintaining the timing signal. The timing is unchanged.
  • the level shifter LS is also operative to initiate discharge of the array of pixels in the display panel. Specifically, when turned off, the voltage monitoring signal XAO decreases as the power supply voltage DVDD falls, and when the level shifter LS detects a discharge condition (eg, XAO falls to a critical value (eg, 1.2V) and at the same time VGH When >15V) is satisfied, the level shifter LS can output a timing signal that causes the pixel array in the display panel to discharge, regardless of the timing signal from the timing controller TCON.
  • a discharge condition eg, XAO falls to a critical value (eg, 1.2V) and at the same time VGH
  • >15V the level shifter LS can output a timing signal that causes the pixel array in the display panel to discharge, regardless of the timing signal from the timing controller TCON.
  • the level shifter LS may erroneously detect that the discharge condition is satisfied due to the slow rising edge of the input voltage Vin at the time of power-on, and undesirably turn on the discharge function.
  • the implementation of the level shifter LS is known in the art, and a detailed description thereof is therefore omitted herein so as not to obscure the subject matter of the present disclosure.
  • the display device 200 includes a display panel 210, a timing controller 220, a gate driver 230, a data driver 240, and a discharge control circuit 250.
  • the display panel 210 is connected to the plurality of gate lines GL and the plurality of data lines DL.
  • the display panel 210 displays an image having a plurality of gradations based on the output image data RGBD'.
  • the gate line GL may extend in the first direction D1
  • the data line DL may extend in the second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel 210 may include an array of pixels including a plurality of pixels (not shown) arranged in a matrix, each of the pixels being electrically connected to a corresponding one of the gate lines and the corresponding ones of the gate lines GL line.
  • these pixels may be liquid crystal (LC) based pixels or pixels based on organic light emitting devices (eg, organic light emitting diodes).
  • the timing controller 220 controls the operations of the display panel 210, the gate driver 230, and the data driver 240.
  • the timing controller 220 receives input image data RGBD and an input control signal CONT from an external device.
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels.
  • Each of the input pixel data may include red gradation data R, green gradation data G, and blue gradation data B for a corresponding one of the plurality of pixels.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical sync signal, a horizontal sync signal, and the like.
  • the timing controller 220 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • the output image data RGBD' is supplied to the data driver 240.
  • the output image data RGBD' may be substantially the same image data as the input image data RGBD.
  • the output image data RGBD' may be compensated image data generated by compensating the input image data RGBD.
  • the first control signal CONT1 is supplied to the discharge control circuit 250 for level shifting.
  • the level shifted first control signal CONT1' is supplied to the gate driver 230, and the driving timing of the gate driver 230 can be controlled based on the level shifted first control signal CONT1'.
  • the second control signal CONT2 is supplied to the data driver 240, and the driving timing of the data driver 240 can be controlled based on the second control signal CONT2.
  • the gate driver 230 receives the level shifted first control signal CONT1' from the discharge control circuit 250.
  • the gate driver 230 generates a plurality of gate signals for driving the gate lines GL based on the level-shifted first control signal CONT1'.
  • the gate driver 230 may sequentially apply a plurality of gate signals to the gate lines GL.
  • the gate driver 230 may be disposed (eg, directly integrated) on the display panel 210, or may be connected to the display panel 210, for example, in a Tape Carrier Package (TCP) type. Accordingly, the gate driver 230 can be considered to be part of the display panel 210.
  • TCP Tape Carrier Package
  • the data driver 240 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 220.
  • the data driver 240 generates a plurality of data voltages (e.g., analog data voltages) based on the second control signal CONT2 and the output image data RGBD' (e.g., digital image data).
  • the data driver 240 can apply a plurality of data voltages to the data lines DL.
  • the discharge control circuit 250 operates to level shift the first control signal CONT1 from the timing controller 220 such that the level shifted first control signal CONT1 satisfies the logic level requirements required to drive the display panel 210. Discharge control circuit 250 is also operative to initiate discharge of a pixel array in display panel 210. The configuration of the discharge control circuit 250 will be described in detail below in conjunction with Figures 3-6.
  • the display device 200 can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 3 is a block diagram of the discharge control circuit 250 in the display device 200 shown in FIG. 2.
  • the discharge control circuit 250 includes a power supply voltage generator 252, a flip flop 254, and a level shifter 256, but the power supply voltage generator 252 is not necessary.
  • a timing controller 220 and display panel 210 that are operatively coupled to level shifter 256.
  • the power supply voltage generator 252 operates to generate a power supply voltage DVDD from the input voltage Vin. This can be done by a voltage converter such as, for example, a DC/DC converter or a low dropout regulator (LDO).
  • a voltage converter such as, for example, a DC/DC converter or a low dropout regulator (LDO).
  • the flip flop 254 operates to generate a representation XAO of the power supply voltage DVDD based on the power supply voltage DVDD.
  • the representation of the power supply voltage XAO causes discharge conditions under which the pixel array (not shown) of the display panel 210 is discharged to be unsatisfied and displayed during or after operation of the display panel 210 The panel 210 is satisfied when it is turned off.
  • Examples of flip flops 254 include, but are not limited to, Schmitt triggers and falling edge flip flops.
  • Level shifter 256 operates to power timing signals from timing controller 220 The shifting is performed and the level-shifted timing signal is supplied to the display panel 210.
  • the level shifter 256 is also operative to initiate discharge of the array of pixels in the display panel 210 in response to the discharge condition being satisfied. As described above, this can be achieved by having all of the outputs of the level shifter 256 follow a high level, and the discharge condition includes the representation of the power supply voltage DVDD having a threshold value of XAO. This threshold can depend on actual requirements.
  • the flip-flop 254 for example, the slow rising edge of the supply voltage DVDD occurring at power up is converted to a steeper rising edge in the representation XAO of the supply voltage DVDD or even cancelled (discussed below). This can prevent the discharge control circuit 250 from erroneously detecting that the discharge condition is satisfied during power-on, thereby avoiding malfunction of the display panel 210.
  • FIG. 4 is a schematic diagram illustrating input-output characteristics of a Schmitt trigger as flip-flop 254 of FIG.
  • Schmitt triggers have a forward threshold voltage V+ and a negative threshold voltage V-. As shown in FIG. 4, when the input voltage Vi increases from low to high and reaches the forward threshold voltage V+, the output voltage Vo jumps (in this example, transitions from a low level to a high level), and when input When the voltage Vi falls from high to low and reaches V-, the output voltage Vo jumps (in this example, transitions from a high level to a low level).
  • Such an input-output characteristic of the Schmitt trigger can be advantageously utilized such that the rising edge of the supply voltage DVDD is converted to a steeper rising edge of the supply voltage DVDD representing XAO. This makes it possible to cause the discharge condition to be satisfied without causing a slow rising edge of the power supply voltage DVDD during power-on.
  • the forward threshold voltage V+ of the Schmitt trigger is set to have a smaller value such that the Schmitt trigger is triggered during power up shortly after the power supply voltage DVDD arrives, and The rising edge of the power supply voltage DVDD is converted to a rising edge of the power supply voltage DVDD indicating XAO before the discharge condition is satisfied, thereby preventing the discharge condition from being satisfied.
  • the falling edge of the supply voltage DVDD can be converted by the Schmitt trigger into a steeper falling edge of the power supply voltage DVDD representing XAO.
  • the negative threshold voltage V- of the Schmitt trigger is set to have a larger value, for example, within a selected range that is less than the nominal value of the power supply voltage DVDD. For example, a range of 80% to 90% of the rated value of the power supply voltage DVDD may be suitable. This allows the Schmitt trigger to be triggered early during power down, ie, the falling edge of the supply voltage DVDD is converted to a steeper falling edge by the Schmitt trigger as early as possible.
  • the discharge condition is satisfied in advance during the falling edge of the power supply voltage DVDD as compared with the case where the Schmitt trigger does not otherwise exist, so that the discharge is level-shifted
  • the 256 is initiated as early as possible and thus the shutdown afterimage is eliminated as early as possible.
  • flip flop 254 is implemented using a falling edge flip flop. Unlike Schmitt triggers that operate in a level-triggered manner, the falling edge flip-flop operates in an edge-triggered manner and is therefore insensitive to the rising edge of the supply voltage DVDD. This allows the rising edge of the power supply voltage DVDD to be canceled in the representation XAO of the power supply voltage DVDD, thereby eliminating the possibility that the discharge condition is satisfied during power-on. Additionally, the falling edge flip flop can be operative to convert the falling edge of the supply voltage DVDD to a steeper falling edge of the power supply voltage DVDD representing XAO. Therefore, the level shifter 256 can normally detect that the discharge condition is satisfied and initiate the discharge during the power down.
  • flip-flop 254 is illustrated and described above as being separate from level shifter 256, other embodiments are also contemplated.
  • FIG. 5 is a block diagram of a variation 250A of the discharge control circuit 250 shown in FIG.
  • the discharge control circuit 250A includes a power supply voltage generator 252, a flip flop 254, and a level shifter 256. As previously mentioned, the supply voltage generator 252 is not required.
  • Discharge control circuit 250A differs from the embodiment shown in FIG. 3 in that flip-flop 254 is built in (eg, integrated) into level shifter 256. This can facilitate the simplification of the circuit connection and improve the reliability of the discharge control circuit.
  • Other configurations of supply voltage generator 252, flip-flop 254, and level shifter 256 are the same as those described above with respect to Figures 2-4, and thus will not be repeated here for the sake of brevity.
  • FIG. 6 is a block diagram of a variation 250B of the discharge control circuit 250A shown in FIG.
  • the discharge control circuit 250B includes a power supply voltage generator 252, a flip flop 254, and a level shifter 256. As previously mentioned, the supply voltage generator 252 is not required.
  • Discharge control circuit 250B differs from the embodiment shown in FIG. 5 in that supply voltage generator 252 includes a voltage converter such as, for example, a DC/DC converter or LDO and a voltage divider circuit 253 in series with the voltage converter.
  • the voltage dividing circuit 253 is connected between the power supply voltage DVDD and the ground voltage to output the divided power supply voltage as the voltage monitoring signal XAO.
  • the voltage monitoring signal XAO is provided to the flip flop 254.
  • the configuration of the flip-flop 254 and the level shifter 256 are the same as those described above with respect to FIG. 5, and thus will not be repeated here for the sake of brevity. It will be understood that the configuration of the supply voltage generator 252 of FIG. 6 can also be applied to the embodiment shown in FIG.
  • voltage divider circuit 253 includes resistors R1 and R2 in series, although other embodiments are also contemplated.
  • FIG. 7 is a flow chart of a discharge control method 700 in accordance with an embodiment of the present disclosure.
  • Method 700 is for controlling pixel array discharge in a display panel.
  • step 710 a supply voltage is generated from the input voltage.
  • step 720 a representation of the power supply voltage is generated based on a power supply voltage of the display panel.
  • step 730 a discharge to the array of pixels is initiated in response to the discharge condition being satisfied.
  • step 720 can include converting a rising edge of the supply voltage to a steeper rising edge in the representation of the supply voltage. In some embodiments, step 720 can include canceling a rising edge of the supply voltage in the representation of the supply voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种用于显示面板（210）的放电控制电路（250），包括：触发器（254），被配置成基于显示面板（210）的电源电压生成该电源电压的表示，该电源电压的表示使得在其下显示面板（210）的像素阵列被放电的放电条件能够在显示面板（210）开机时或操作期间不被满足并且在显示面板（210）关机时被满足；以及电平移位器（256），被配置成对用于控制该像素阵列的操作的时序信号进行电平移位并将经电平移位的该时序信号提供给显示面板（210），以及响应于放电条件被满足而发起对像素阵列的放电。

Description

用于显示面板的放电控制电路和方法以及显示装置
相关申请的交叉引用
本申请要求2017年4月11日提交的中国专利申请号No.201710232606.1的权益，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种用于显示面板的放电控制电路和方法、以及一种包括该放电控制电路的显示装置。
背景技术
显示装置一般提供有用于消除关机残影的放电控制电路。在显示装置关机时，放电控制电路监测电源电压的变化，并且当满足放电条件时发起显示装置中的像素阵列的放电，例如，通过打开各像素电路中的开关薄膜晶体管(TFT)。这允许各像素电路中存储的电荷被释放，从而消除关机残影。然而，当电源电压不稳定时，例如在显示装置开机时电源电压缓慢地上升到额定值，放电控制电路可能由于错误地检测到放电条件被满足而发生误动作，造成对于像素电路等的不期望的损坏。
发明内容
提供一种可以缓解、减轻或消除上述问题中的一个或多个的放电控制电路将是有利的。
根据本公开的一个方面，提供了一种用于显示面板的放电控制电路，该显示面板包括像素阵列。所述放电控制电路包括：触发器，其被配置成基于所述显示面板的电源电压生成所述电源电压的表示，所述电源电压的表示使得在其下所述显示面板的像素阵列被放电的放电条件能够在所述显示面板开机时或操作期间不被满足并且在所述显示面板关机时被满足；以及电平移位器，其被配置成对用于控制所述像素阵列的操作的时序信号进行电平移位并将经电平移位的所述时序信号提供给所述显示面板，以及响应于所述放电条件被满足而发起对所述像素阵列的放电。
在某些示例性实施例中，所述触发器被配置成通过将所述电源电压的上升沿转换为所述电源电压的表示中的更陡峭的上升沿或者在所述电源电压的表示中取消所述电源电压的上升沿来生成所述电源电压的表示。
在某些示例性实施例中，所述触发器包括施密特触发器，该施密特触发器被配置使得所述电源电压的上升沿被转换为所述电源电压的表示中的更陡峭的上升沿，并且所述电源电压的下降沿被转换为所述电源电压的表示中的更陡峭的下降沿。
在某些示例性实施例中，所述施密特触发器具有正向阈值电压，该正向阈值电压被选择使得在所述电源电压的上升沿期间所述电源电压的上升沿在所述放电条件被满足之前被转换为所述电源电压的表示的上升沿。
在某些示例性实施例中，所述施密特触发器具有负向阈值电压，该负向阈值电压在小于所述电源电压的额定值的经选择的范围内以使得在所述电源电压的下降沿期间所述电源电压的下降沿被尽早地转换为所述电源电压的表示的下降沿。在一些实施例中，所述负向阈值电压在所述电源电压的额定值的80％至90％的范围内。
在某些示例性实施例中，所述触发器包括对所述电源电压的上升沿不敏感的下降沿触发器以使得所述电源电压的上升沿在所述电源电压的表示中被取消。在某些示例性实施例中，所述放电控制电路还包括分压电路，该分压电路连接在所述电源电压与地电压之间以便输出经分压的电源电压。所述触发器被配置成接收所述经分压的电源电压并且将其转换为所述电源电压的表示。在一些实施例中，所述触发器内建在所述电平移位器中。在一些实施例中，所述分压电路包括串联的电阻。
在某些示例性实施例中，所述放电控制电路还包括可操作用于从输入电压生成所述电源电压的电压转换器。在一些实施例中，所述电压转换器选自线性稳压器和直流/直流转换器所组成的组。在一些实施例中，所述线性稳压器为低压差线性稳压器。
根据本公开的另一方面，提供了一种显示装置，包括：显示面板，包括像素阵列；时序控制器，被配置成提供用于控制所述像素阵列的操作的时序信号；以及如上所述的放电控制电路。
根据本公开的又另一方面，提供了一种使用如上所述的放电控制电路控制显示面板中的像素阵列放电的方法。所述方法包括基于所述显示面板的电源电压生成所述电源电压的表示，所述电源电压的表示使得在其下所述显示面板的像素阵列被放电的放电条件能够在所述显示面板开机时或操作期间不被满足并且在所述显示面板关机时被满足；以及响应于所述放电条件被满足而发起对所述像素阵列的放电。
在某些示例性实施例中，生成所述电源电压的表示包括：将所述电源电压的上升沿转换为所述电源电压的表示中的更陡峭的上升沿或者在所述电源电压的表示中取消所述电源电压的上升沿。。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1为一种典型的用于显示面板的放电控制电路的框图；
图2为根据本公开实施例的显示装置的框图；
图3为根据本公开实施例的放电控制电路的框图；
图4为图示出作为图3所示的放电控制电路中的触发器的施密特触发器的输入-输出特性的示意图；
图5为图3所示的放电控制电路的变型的框图；
图6为图5所示的放电控制电路的变型的框图；并且
图7为根据本公开实施例的放电控制方法的流程图。
具体实施方式
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另一个 元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件。相反，当元件被称为“直接连接到另一个元件”或“直接耦合到另一个元件”时，没有中间元件存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
下面将结合附图详细描述本公开的实施例。
图1为一种典型的用于显示面板的放电控制电路的框图。如图1所示，该放电控制电路包括低压差稳压器LDO、电阻R1和R2、以及电平移位器LS。
低压差稳压器LDO将输入电压Vin转换为电源电压DVDD。电源电压DVDD被电阻R1和R2分压，并且经分压的电压被提供给电平移位器LS作为电压监测信号XAO。
电平移位器LS操作来对来自时序控制器TCON的时序信号进行电平移位，使得经电平移位的时序信号满足驱动显示面板所需的逻辑电平要求。例如，时序控制器TCON在具有3.3V的高电平和0V的低电平的逻辑电平配置中操作，而显示面板在具有高电平VGH(例如，24V)和低电平VGL(例如，-7V)的逻辑电平配置中操作。在这种情况下，电平移位器LS操作来将时序控制器TCON提供的时序信号的高电平和低电平分别从3.3V移位到24V和从0V移位到-7V，同时保持时序信号的时序不变。
电平移位器LS还操作来发起对显示面板中的像素阵列的放电。具体而言，当关机时，电压监测信号XAO随着电源电压DVDD的下降而下降，并且当电平移位器LS检测到放电条件(例如，XAO下降到临界值(例如，1.2V)且同时VGH＞15V)被满足时，电平移位器LS可以输出促使显示面板中的像素阵列放电的时序信号，而不管来自时序控制器TCON的时序信号如何。例如，电平移位器LS的所有输出端跟随高电平VGH，使得像素阵列中的各像素电路的开关TFT被打开，并且各像素电路中存储的电荷被释放，从而消除关机残影。如前所述， 电平移位器LS在上电时可能由于输入电压Vin的缓慢的上升沿而错误地检测到放电条件被满足，并且不合期望地开启放电功能。电平移位器LS的实现是本领域已知的，其详细描述因此在本文中被省略以便不模糊本公开的主题。
图2为根据本公开实施例的显示装置200的框图。参考图2，显示装置200包括显示面板210、时序控制器220、栅极驱动器230、数据驱动器240和放电控制电路250。
显示面板210连接至多个栅极线GL和多个数据线DL。显示面板210基于输出图像数据RGBD’显示具有多个灰度的图像。栅极线GL可在第一方向D1延伸，并且数据线DL可在与第一方向D1交叉(例如，基本垂直)的第二方向D2延伸。显示面板210可包括像素阵列，该像素阵列包括以矩阵形式排列的多个像素(未示出)，每个像素电连接至栅极线GL的对应一个栅极线和数据线DL的对应一个数据线。取决于显示面板210的实现，这些像素可以是基于液晶(LC)的像素或者是基于有机发光器件(例如，有机发光二极管)的像素。
时序控制器220控制显示面板210、栅极驱动器230和数据驱动器240的操作。时序控制器220从外部设备接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于多个像素的多个输入像素数据。每个输入像素数据可包括用于多个像素中的对应一个的红色灰度数据R、绿色灰度数据G和蓝色灰度数据B。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。时序控制器220基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。输出图像数据RGBD’被提供给数据驱动器240。在一些实施例中，输出图像数据RGBD’可以是与输入图像数据RGBD基本相同的图像数据。在一些实施例中，输出图像数据RGBD’可以是通过补偿输入图像数据RGBD生成的补偿图像数据。第一控制信号CONT1被提供给放电控制电路250进行电平移位。经电平移位的第一控制信号CONT1’被提供给栅极驱动器230，并且栅极驱动器230的驱动时序可基于经电平移位的第一控制信号CONT1’被控制。第二控制信号CONT2被提供给数据驱动器240，并且数据驱动器240的驱动时序可基于第二控制信号CONT2被控制。
栅极驱动器230从放电控制电路250接收经电平移位的第一控制信号CONT1’。栅极驱动器230基于经电平移位的第一控制信号CONT1’生成用于驱动栅极线GL的多个栅极信号。栅极驱动器230可顺序地将多个栅极信号施加至栅极线GL。在一些示例性实施例中，栅极驱动器230可被设置(例如，直接集成)在显示面板210上，或者可以例如带式载体封装(Tape Carrier Package，TCP)类型连接至显示面板210。因此，栅极驱动器230可以被视为为显示面板210的一部分。
数据驱动器240从时序控制器220接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动器240基于第二控制信号CONT2和输出图像数据RGBD’(例如，数字图像数据)生成多个数据电压(例如，模拟数据电压)。数据驱动器240可将多个数据电压施加至数据线DL。
放电控制电路250操作来对来自时序控制器220的第一控制信号CONT1进行电平移位，使得经电平移位的第一控制信号CONT1满足驱动显示面板210所需的逻辑电平要求。放电控制电路250还操作来发起对显示面板210中的像素阵列的放电。放电控制电路250的配置将在下面结合图3-6进行详细描述。
显示装置200可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图3为图2所示的显示装置200中的放电控制电路250的框图。参考图3，放电控制电路250包括电源电压生成器252、触发器254和电平移位器256，但是电源电压生成器252不是必需的。图3中还示出了与电平移位器256可操作地耦合的时序控制器220和显示面板210。
电源电压生成器252操作来从输入电压Vin生成电源电压DVDD。这可以通过诸如例如直流/直流(DC/DC)转换器或低压差稳压器(LDO)之类的电压转换器来完成。
触发器254操作来基于所述电源电压DVDD生成所述电源电压DVDD的表示XAO。如下面讨论的，所述电源电压的表示XAO使得在其下显示面板210的像素阵列(图中未示出)被放电的放电条件能够在显示面板210开机时或操作期间不被满足并且在显示面板210关机时被满足。触发器254的示例包括但不限于施密特触发器和下降沿触发器。
电平移位器256操作来对来自时序控制器220的时序信号进行电 平移位并将经电平移位的所述时序信号提供给所述显示面板210。电平移位器256还操作来响应于放电条件被满足而发起对所述显示面板210中的像素阵列的放电。如上所述的，这可以通过使电平移位器256的所有输出端跟随高电平来实现，并且所述放电条件包括所述电源电压DVDD的表示XAO具有临界值。该临界值可以取决于实际要求。
借助于触发器254，例如在上电时出现的电源电压DVDD的缓慢上升沿在电源电压DVDD的表示XAO中被转换为更陡峭的上升沿或者甚至被取消(下面讨论)。这可以防止放电控制电路250在上电期间错误地检测到放电条件被满足，从而避免显示面板210的误动作。
图4为图示出作为图3中的触发器254的施密特触发器的输入-输出特性的示意图。
如已知的，施密特触发器具有正向阈值电压V+和负向阈值电压V-。如图4所示，当输入电压Vi由低向高增加并且达到正向阈值电压V+时，输出电压Vo发生跳变(在该示例中，从低电平跳变至高电平)，并且当输入电压Vi由高向低下降并且达到V-时，输出电压Vo发生跳变(在该示例中，从高电平跳变至低电平)。
施密特触发器的这样的输入-输出特性可以被有利地利用，使得电源电压DVDD的上升沿被转换成电源电压DVDD的表示XAO的更陡峭的上升沿。这使得在上电期间电源电压DVDD的缓慢上升沿不会导致放电条件被满足成为可能。在一些实施例中，施密特触发器的正向阈值电压V+被设置为具有较小的值，使得施密特触发器在上电期间在电源电压DVDD到来之后的短时间内被触发，并且将所述电源电压DVDD的上升沿在所述放电条件被满足之前转换为所述电源电压DVDD的表示XAO的上升沿，从而防止放电条件被满足。附加地，电源电压DVDD的下降沿可以被施密特触发器转换成电源电压DVDD的表示XAO的更陡峭的下降沿。在一些实施例中，施密特触发器的负向阈值电压V-被设置为具有较大的值，例如，在小于电源电压DVDD的额定值的经选择的范围内。例如，电源电压DVDD的额定值的80％至90％的范围可以是合适的。这允许施密特触发器在掉电期间被尽早地触发，也即，电源电压DVDD的下降沿被施密特触发器尽早地转换成更陡峭的下降沿。与施密特触发器否则不存在的情况相比，在电源电压DVDD的下降沿期间所述放电条件被提前满足，使得放电被电平移位 器256尽早地发起并且因此关机残影被尽早地消除。
在可替换的实施例中，触发器254利用下降沿触发器来实现。不同于以电平触发的方式操作的施密特触发器，下降沿触发器以边沿触发的方式操作，并且因此对电源电压DVDD的上升沿不敏感。这允许在所述电源电压DVDD的表示XAO中取消所述电源电压DVDD的上升沿，从而消除在上电期间放电条件被满足的可能性。另外，下降沿触发器可以操作来将电源电压DVDD的下降沿转换成电源电压DVDD的表示XAO的更陡峭的下降沿。因此，在掉电期间电平移位器256可以正常地检测到放电条件被满足并且发起放电。
虽然在上文中触发器254被图示和描述为与电平移位器256相分离，但是还设想了其他实施例。
图5为图3所示的放电控制电路250的变型250A的框图。参考图5，放电控制电路250A包括电源电压生成器252、触发器254和电平移位器256。如前所述，电源电压生成器252不是必需的。
放电控制电路250A不同于图3所示的实施例，在于触发器254被内建(例如，集成)到电平移位器256中。这可以有利于电路连接的简化，提高放电控制电路的可靠性。电源电压生成器252、触发器254和电平移位器256的其他配置与上面关于图2-4描述的那些相同，并且因此在此为了简洁起见不再重复。
图6为图5所示的放电控制电路250A的变型250B的框图。参考图6，放电控制电路250B包括电源电压生成器252、触发器254和电平移位器256。如前所述，电源电压生成器252不是必需的。
放电控制电路250B不同于图5所示的实施例，在于电源电压生成器252包括诸如例如DC/DC转换器或LDO的电压转换器和与电压转换器串联的分压电路253。分压电路253连接在电源电压DVDD与地电压之间以便输出经分压的电源电压作为电压监测信号XAO。电压监测信号XAO被提供给触发器254。触发器254和电平移位器256的配置与上面关于图5描述的那些相同，并且因此在此为了简洁起见不再重复。将理解的是，图6中的电源电压生成器252的配置也可以应用于图3所示的实施例。
在图6的实施例中，分压电路253包括串联的电阻R1和R2，尽管还设想了其他实施例。
图7为根据本公开实施例的放电控制方法700的流程图。方法700用于控制显示面板中的像素阵列放电。
在步骤710中，从输入电压生成电源电压。在步骤720中，基于所述显示面板的电源电压生成所述电源电压的表示。在步骤730中，响应于放电条件被满足而发起对所述像素阵列的放电。
在一些实施例中，步骤720可以包括将所述电源电压的上升沿转换为所述电源电压的表示中的更陡峭的上升沿。在一些实施例中，步骤720可以包括在所述电源电压的表示中取消所述电源电压的上升沿。
方法700的实现方式和优点已经在上文参考放电控制电路实施例进行了详细描述，并且因此为了简洁起见在此不再重复。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种用于显示面板的放电控制电路，该显示面板包括像素阵列，所述放电控制电路包括：
    触发器，被配置成基于所述显示面板的电源电压生成所述电源电压的表示，所述电源电压的表示使得在其下所述显示面板的像素阵列被放电的放电条件能够在所述显示面板开机时或操作期间不被满足并且在所述显示面板关机时被满足；以及
    电平移位器，被配置成对用于控制所述像素阵列的操作的时序信号进行电平移位并将经电平移位的所述时序信号提供给所述显示面板，以及响应于所述放电条件被满足而发起对所述像素阵列的放电。
  2. 如权利要求1所述的放电控制电路，其中所述触发器被配置成通过将所述电源电压的上升沿转换为所述电源电压的表示中的更陡峭的上升沿或者在所述电源电压的表示中取消所述电源电压的上升沿来生成所述电源电压的表示。
  3. 如权利要求2所述的放电控制电路，其中所述触发器包括施密特触发器，该施密特触发器被配置使得所述电源电压的上升沿被转换为所述电源电压的表示中的更陡峭的上升沿，并且所述电源电压的下降沿被转换为所述电源电压的表示中的更陡峭的下降沿。
  4. 如权利要求3所述的放电控制电路，其中所述施密特触发器具有正向阈值电压，该正向阈值电压被选择使得在所述电源电压的上升沿期间所述电源电压的上升沿在所述放电条件被满足之前被转换为所述电源电压的表示的上升沿。
  5. 如权利要求4所述的放电控制电路，其中所述施密特触发器具有负向阈值电压，该负向阈值电压在小于所述电源电压的额定值的经选择的范围内以使得在所述电源电压的下降沿期间所述电源电压的下降沿被尽早地转换为所述电源电压的表示的下降沿。
  6. 如权利要求5所述的放电控制电路，其中所述负向阈值电压在所述电源电压的额定值的80％至90％的范围内。
  7. 如权利要求2所述的放电控制电路，其中所述触发器包括对上升沿不敏感的下降沿触发器以使得所述电源电压的上升沿在所述电源电压的表示中被取消。
  8. 如权利要求1所述的放电控制电路，还包括分压电路，该分压电路连接在所述电源电压与地电压之间以便输出经分压的电源电压，其中所述触发器被配置成接收所述经分压的电源电压并将其转换成所述电源电压的表示。
  9. 如权利要求8所述的放电控制电路，其中所述触发器内建在所述电平移位器中。
  10. 如权利要求8所述的放电控制电路，其中所述分压电路包括串联的电阻。
  11. 如权利要求1-10任一项所述的放电控制电路，还包括可操作用于从输入电压生成所述电源电压的电压转换器。
  12. 如权利要求11所述的放电控制电路，其中所述电压转换器选自线性稳压器和直流/直流转换器所组成的组。
  13. 如权利要求12所述的放电控制电路，其中所述线性稳压器为低压差线性稳压器。
  14. 一种显示装置，包括：
    显示面板，包括像素阵列；
    时序控制器，被配置成提供用于控制所述像素阵列的操作的时序信号；以及
    如权利要求1-13任一项所述的放电控制电路。
  15. 一种使用如权利要求1-13任一项所述的放电控制电路控制显示面板中的像素阵列放电的方法，所述方法包括：
    基于所述显示面板的电源电压生成所述电源电压的表示，所述电源电压的表示使得在其下所述显示面板的像素阵列被放电的放电条件能够在所述显示面板开机时或操作期间不被满足并且在所述显示面板关机时被满足；以及
    响应于所述放电条件被满足而发起对所述像素阵列的放电。
  16. 如权利要求15所述的方法，其中生成所述电源电压的表示包括：将所述电源电压的上升沿转换为所述电源电压的表示中的更陡峭的上升沿或者在所述电源电压的表示中取消所述电源电压的上升沿。
PCT/CN2017/107574 2017-04-11 2017-10-25 用于显示面板的放电控制电路和方法以及显示装置 Ceased WO2018188312A1 (zh)

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