WO2018182715A1

WO2018182715A1 - Junctionless field effect transistors

Info

Publication number: WO2018182715A1
Application number: PCT/US2017/025505
Authority: WO
Inventors: Sean T. MA; Justin R WEBER; Harold W. KENNEL; Gilbert Dewey; Willy Rachmady; Cheng-Ying Huang; Nicholas G. MINUTILLO; Jack T. Kavalieros; Anand S. Murthy; Tahir Ghani
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

Solid-state devices having dielectric layers including localized charges of a first polarity, and processes to form the dielectric layers are provided. The first polarity can be opposite to a second polarity of mobile charges within a carrier-doped semiconductor layer included in the solid-state devices. Each of the solid state devices can have multiple electrodes, where a first electrode and a second electrode can permit biasing the solid-state device and causing transport of carriers through a channel region. The multiple electrodes also include a third electrode that can serve as a gate contact. In one example, a charged dielectric layer of a solid-state device can be adjacent to the channel region and can separate the third electrode from the second electrode. In addition, the carrier-doped semiconductor layer also can be adjacent to the channel region and can form an interface with the second electrode. The opposite charge polarity of the localized charges and mobile charges can improve the current transported across the channel region.

Description

JUNCTIO LESS FIELD EFFECT TRANSISTORS

BACKGROUND

[0001] Leakage floor in the OFF-state in a Si field effect transistor (FET), a III-V FET, or other FETs without wide-bandgap channel material can be driven by band-to-band tunneling (BTBT) current at a high electrical field across a drain junction in the FET. Although junctionless FETs have been proposed in order to reduce BTBT and associated leakage floor, these devices usually have elevated external resistance (R_ext), with ensuing poor performance. Therefore, much remains to be improved in the design of FETs in order to reduce R_ext. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings are an integral part of the disclosure and are

incorporated into the subject specification. The drawings illustrate example embodiments of the disclosure and, in conjunction with the description and claims, serve to explain at least in part various principles, features, or aspects of the disclosure. Certain embodiments of the disclosure are described more fully below with reference to the accompanying drawings. However, various aspects of the disclosure can be implemented in many different forms and should not be construed as limited to the implementations set forth herein. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0003] FIG. 1 presents a schematic cross-sectional view of an example junctionless FET (an 77-FET or a p-FET) in accordance with one or more embodiments of the disclosure.

[0004] FIG. 2 presents a schematic cross-sectional view of an example solid-state device in a cut across a fin member of the device, in accordance with one or more embodiments of the disclosure.

[0005] FIG. 3 presents another schematic cross-sectional view of an example solid-state device in a cut across a fin member of the device, in accordance with one or more embodiments of the disclosure.

[0006] FIG. 4 presents results of a simulation of performance of junctionless «-FETs having different amounts of localized charges at spacer layers, in accordance with one or more embodiments of the disclosure. [0007] FIG. 5A presents examples of electronic energy diagrams for solid-state devices in accordance with one or more embodiments of the disclosure.

[0008] FIG. 5B presents other examples of electronic energy diagrams for solid-state devices in accordance with one or more embodiments of the disclosure.

[0009] FIG. 6 presents an example of a method of fabricating a solid-state assembly in accordance with one or more embodiments of the disclosure.

[0010] FIG. 7 presents an example of a system that utilizes solid-state devices in accordance with one or more embodiments of the disclosure. DETAILED DESCRIPTION

[0011] The disclosure recognizes and addresses, in at least some embodiments, the issue of the external resistance bottleneck in junctionless FETs. In general, without intending to be bound by theory and/or modeling, junctionless FETs can have elevated external resistance because respective regions under a spacer between a gate contact and a source contact and/or another spacer between the gate contact and a drain contact can have a concentration of mobile carriers that is insufficient to conduct current. The deficiency of mobile carriers in these regions can be a result of each of such regions being undoped in order to mitigate or otherwise avoid BTBT and a further result of not turning "ON" due to being too far from the gate contact. As described in greater details below, embodiments of the disclosure provide mobile carriers in the "external" regions under respective spacer layers between a gate electrode and a source electrode and the gate electrode and the drain electrode of a FET in order to mitigate or otherwise avoid the R_ext bottleneck. The mobile carriers can serve to connect channel charge to the source electrode and the drain electrode when the FET is turned on. The mobile carriers— electrons for NMOS devices and holes for PMOS devices— in the external regions can be induced by a fixed charge of opposite polarity— a positive charge for NMOS devices and negative charge for PMOS devices— in a spacer layer. In some embodiments, the mobile carriers can be generated without doping the external regions (such as, for example, by introducing doped regions to form a source contact or a drain contact). More specifically, embodiments of the disclosure can provide solid- state devices having dielectric layers including localized charges of a first polarity. In addition or in other embodiments provide processes to form such dielectric layers. In some embodiments, the first polarity can be opposite to a second polarity of mobile charges within a carrier-doped semiconductor layer included in the solid-state devices. Each of the solid state devices can have multiple electrodes, where a first electrode and a second electrode can permit biasing the solid- state device and causing transport of carriers through a channel region. The multiple electrodes also include a third electrode that can serve as a gate contact. In one example, a charged dielectric layer of a solid-state device can be adjacent to the channel region and can separate the third electrode from the second electrode. In addition or in other embodiments, the carrier-doped semiconductor layer also can be adjacent to the channel region and can form an interface with the second electrode. Without intending to be bound by theory and/or modeling, the external regions can achieve a low electrical field at least because the regions are nominally undoped (or intrinsic), thus mitigating or otherwise avoiding BTBT.

[0012] With reference to the drawings, FIG. 1 illustrates a schematic cross-sectional view of a solid-state assembly 100 that can embody or can constitute a solid-state device, in accordance with one or more embodiments of the disclosure. As mentioned, in some embodiments, the solid-state device can embody or can constitute a non-planar FET, such as a FinFET, all-around- gate FETs, tri-gate FETs, dual -gate FETs, or other types of non-planar FETs having contact members (e.g., a source contact member and/or a drain contact member) embodied in one or more nanowires. The solid-state assembly 100 can include a semiconductor substrate 110. The semiconductor substrate 110 can be formed from or can include an intrinsic semiconductor material, such as Si, Ge, Si_xGe_y, III-V semiconductor compounds (e.g., InAs, GaAs, In_xGa_yAs, InP, GaP, In_xAl_yAs, Ga_xAl_yAs, InSb, GaAs_xSb_y, InAs_xSb_y, In_xGa_yAs_zPi_-z), II- VI compounds, a combination thereof, or the like. The indices x, y, z are real numbers indicative of a defined stoichiometry of a compound. The semiconductor substrate 110 can include a channel region 120 that is intrinsic (or nominally undoped). The channel region 120 can form interfaces with respective layers included in the solid-state assembly 100. Specifically, in some aspects, a first portion of the channel region 120 can form a first interface with a first conductive layer 180a, and a second portion of the channel region 120 can form a second interface with a second conductive layer 180b. Each of the first conductive layer 180a and the second conductive layer 180b can be formed from or can include a carrier-doped semiconductor material or another type of conductive material. The carrier-doped semiconductor material can have «-type doping of a defined carrier concentration n_e or /?-type doping of a defined concentration τ¾. Both n_e and τ¾ represent respective real numbers in units of carrier density (e.g., number of carriers per unit of surface).

[0013] The first conductive layer 180a and the second conductive layer 180a form respective interfaces with a first electrode member 130 and a second electrode member 140. Each of the first electrode member 130 and the second electrode member 140 can be formed from or can include a conductive material. Thus, in some aspects, the first conductive layer 180a can reduce contact resistance between the electrode member 130 and at least a first portion of the channel region 120. In addition, the second conductive layer 180b can reduce contact resistance between the electrode member 140 and at least a second portion of the channel region 120. In some embodiments, the conductive material can be embodied in or can include, for example, a metal, a doped semiconductor, a conductive ceramic, or the like. The metal can include one or more of copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, nickel, or an alloy of two or more of the foregoing metals. In one example scenario, the first electrode member 130 and the second electrode member 140 can embody or can constitute, respectively, a source contact and a drain contact. In another example scenario, the first electrode member 130 and the second electrode member 140 can embody or can constitute, respectively, the drain contact and the source contact.

[0014] A portion of the channel region 120 also can be in contact or can form an interface with a dielectric layer 160. The dielectric layer 160 can be referred to as a gate dielectric and can be formed from or can include a high- dielectric. The dielectric layer 160 can form another interface with a gate electrode member 150 (which also may be referred to as a gate contact). In some embodiments, high- dielectric materials can include, for example, alumina; silicon monoxide (SiO, K of about 5.0); silicon dioxide (Si0₂, K of about 3.9); titanium dioxide; silicon nitride (S1O₃N₄, K of about 6); boron nitride (BN, K of about 4.5); alkali halides (such as rubidium bromide (RbBr, K of about 4.7), lithium fluoride (LiF, K of about 9.2), barium titanate (BaTi0₃, Ovaries from about 130 to about 1000), lead titanate (PbTi0₃, K ranges between about 200 to about 400); and metal oxides (e.g., hafnium dioxide (Hf0₂, K of about 40), tantalum oxide (TaC"5 K of about 27), tungsten oxide (W0₃, K of about 42) and zirconium dioxide (Zr0₂, K of about 24.7). Other high- materials can include, for example, La₂0₃, SrTi0₃, LaA10₃, Y₂0₃, Al₂O_xN_y, HfO_xN_y, ZrO_xN_y, La₂O_xN_y, TiO_xN_y, SrTiO_xN_y, LaA10_xN_y,Y₂O_xN_y, SiON, SiN, a silicate thereof, or an alloy thereof. [0015] The solid-state assembly 100 also can include a first spacer layer 170a and a second spacer layer 170b, each separating an electrode member of the device from at least the gate electrode member 150. As illustrated, the first spacer layer 170a separates the first electrode member 130 from the gate member 150, and the second spacer layer 170b separates the second electrode member 140 from the gate member 150. In some embodiments, the first spacer layer 170a and the second spacer layer 170b can have respective substantially uniform thicknesses t_a and tb, each having a magnitude within the range from about 2 nm to about 20 nm. In one aspect, a distance between the first spacer layer 170a and the second spacer layer 170b can define a channel length. In some embodiments, the channel length can have a magnitude in a range from about 15 nm to about 40 nm. In addition, each of the first spacer layer 170a and the second spacer layer 170b can be formed from or can include a \ow-K dielectric material, such as an oxide, a nitride, a carbide, a silicate, a combination thereof (e.g., multiple layers of different materials), or the like. In some examples, the oxide can be embodied in or can include beryllium oxide, magnesium oxide, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, scandium oxide, gadolinium oxide, and the like. In other examples, the nitride can be embodied in or can include boron nitride, aluminum nitride, silicon nitride, and the like. In yet other example, the carbide can be embodied in or can include wide-bandgap polytypes of silicon carbide, such as 2H and 4H, and the like. In still other examples, a silicate can be embodied in or can include hafnium silicate, zirconium silicate, and the like. As such, in some aspects, the first spacer layer 170a can mitigate capacitive coupling between the electrode member 130 and the gate electrode member 150, and the second spacer layer 170b can mitigate capacitive coupling between the electrode member 140 and the gate member 150. In some embodiments t_a and t_b can have essentially the same magnitude— e.g., a difference between t_a and can be due to a spatial resolution of a deposition process utilized to form the spacer layer.

[0016] In some embodiments, the first spacer layer 170a can include a first amount of localized charges having a first defined polarity (e.g., positive or negative), and the second spacer layer 170b can include a second amount of localized charges having a second defined polarity. Each (or, in some embodiments, at least some) of the localized charges in the first spacer layer 170a can be located in the vicinity of respective point defects. Similarly, each (or, in some embodiments, at least some) of the localized charges in the second spacer layer 170b also can be located in the vicinity of respective point defects. Point defects can include, for example, vacancies, interstitial atoms (self-interstitial atoms and/or impurity interstitial atoms), dangling bonds, or the like. In some aspects, each of the first spacer layer 170a and second spacer layer 170b can be formed to have a density of point defects in the range from about

12 2 13 2

10 cm^" to about 10 cm^" . Thus, in some embodiments, each of the first amount of localized charges and the second amount of localized charges can range from about 10¹² cm^"2 to about 10¹³ cm^"2. In other embodiments, the density of point defects can be greater than about 10¹³ cm^"2 and, therefore, the second amount of localized charges can be greater than about 10¹³ cm^"2.

[0017] The first defined polarity of the localized charges in the spacer layer 170a can be the same as the second defined polarity of charges in the spacer layer 170b. In addition, each of the first defined polarity and the second defined polarity can be opposite a polarity of mobile carriers or charges) in the first conductive layer 180a and the second conductive layer 180b. Therefore, in response to a difference in electrostatic potential between the first electrode 130 and the second electrode 140, at least some of the first amount of localized charges in the spacer layer 170a can attract mobile carriers from the first conductive layer 180a to a first portion of the channel region 120. In addition, at least some of the second amount of localized charges in the second spacer layer 170b can attract mobile carriers from the second conductive layer 180b to a second portion of the channel region 120. As such, the first conductive layer 180a and the second conductive layer 180b can supply carriers (e.g., electrons or holes, depending on doping) to the channel region 120. The first portion of the channel region 120 and the second portion of the channel region 120 can be located in the vicinity of the first conductive layer 180a and the second conductive layer 180b, respectively. In FIG. 1, the mobile carriers that can be attracted are represented, simply for the sake of illustration, as negative ("-") mobile carriers (or mobile carriers of negative polarity). The disclosure is not limited in that respect and, in some embodiments, positive ("+") mobile carriers can be attracted.

[0018] More specifically, in some embodiments, the channel region 120 can constitute a fin member of a solid-state device (e.g., a FinFET). As is illustrated in FIG. 2, a spacer layer 210 can coat or otherwise cover a sub-region 220 of the channel region 120. A thickness w (a real number in units of length) of the sub-region 220 can define a width of the channel region 120 and can have a magnitude in a range from about 5 nm to about 15 nm. The spacer layer 210 represents the first spacer layer 170a and the second spacer layer 170b. The sub-region 220 represents the first portion of the channel region 120 and the second portion of the channel region 120 located, respectively, adjacent the first conductive layer 180a and adjacent the second conductive layer 180b. The spacer layer 210 can be embodied in a conformal layer forming an interface with the sub-region 220. Thus, in one aspect, localized charges included in the spacer layer 210 can attract mobile carriers from either the first conductive layer 180a or the second conductive layer 180b to the sub-region 220 in response to biasing the solid-state device. To that end, in some embodiments, as is illustrated in FIG. 3, each of the first conductive layer 180a and the second conductive layer 180b can be embodied in a conformal conductive layer 320 that coats or otherwise covers a sub-region 330 of the channel region 120. For the sake of illustration, in FIG. 2, the localized charges in the spacer layer 210 are illustrated as localized positive charges (represented with "+") and the attracted mobile carriers are illustrated as negative mobile carriers (represented with "-"). The disclosure is not limited in that respect and localized charges and mobile carriers of other respective polarities also are contemplated. The conductive layer 320 can have, for example, a substantially uniform thicknesses t (a real number in units of length) having a magnitude within the range from about 2 nm to about 20 nm. An electrode member 310 representing the first electrode member 130 and the second electrode member 140 can be conformal with the conductive layer 320.

[0019] In some aspects, the injection of mobile carriers into at least a portion of the channel region 120 can reduce R_EXT of a solid-state device that includes the solid assembly 100 and, thus, increase current from between electrodes in the solid-state device. Without intending to be bound by theory and/or modeling, FIG. 4 illustrates results of simulations of current I_D through an electrode (either the first electrode 130 or the second electrode 140) of the solid-state assembly 100 as a function of voltage V_G applied at the gate member 160. The results of the simulations represent how conductive the channel region 120 is. Specifically, traces 410-430 in FIG. 4 illustrate current through the second electrode 140 as a function of V_G (in Volts) for different amounts of localized charge at each of spacer layer 170a and spacer layer 170b. The localized charge can have a uniform distribution of magnitude NQ (a real number in units of the reciprocal of area, for example). Simulated current is indicated as a percentage of defined reference current I₀ at the second electrode 140, at a defined voltage V_D = 0.5 V. Trace 410 illustrates current I_D for a neutral spacer layer 170b, corresponding to NQ = 0. Trace 420 illustrates current I_D for a positively charged spacer layer 170b having an amount of localized charges having a uniform charge density NQ = 5- 10¹² cm^"2. As it can be gleaned from the results shown by trace 420, the positively charged spacer layer 170b can improve the performance of the solid-state device with respect to the performance of a solid-state device in which the spacer layer 170b is neutral. For some values of V_G, the performance can improve by about 40 %.

Without intending to be bound by theory and/or simulation, in some aspects, the improvement in performance can be due to the positive localized charges in the spacer layer 170b attracting the electrons being transported through the channel region 120. As such, in some aspect, it can be gleaned from simulation results that positively charged spacer layer 170b can remove or otherwise mitigate the R_EXT bottleneck present in conventional devices, resulting in higher drive performance.

[0020] Trace 430 in FIG. 4 illustrates current I_D for a negatively charged spacer layer 170b having an amount of localized charge having a uniform charge density NQ = -5- 10¹² cm^"2. As it can be gleaned from the results shown by trace 430, a negatively charged spacer layer 170b can be detrimental to the performance of the solid-state device. Without intending to be bound by theory and/or simulation, in some aspects, the reduction in performance can be due to the negative localized charges in the spacer layer 170b repelling the electrons being transported through the channel region 120, thus reducing the number of mobile electrons in the external regions and also reducing the drain current in the ON state of the solid-state device that includes the solid assembly 100.

[0021] As mentioned, the presence of point defects in a spacer layer in accordance with aspects of this disclosure can permit or otherwise facilitate, at least in part, having localized charges within the spacer layer. The point defects in the spacer layer (e.g., first spacer layer 170a or second spacer layer 170b) can include neutral defects and/or charged defects, e.g., singly-charged defect(s) and/or multiply-charged defect(s) (doubly-charged defect(s), triply- charged defect(s), and the like). Regardless of a particular charge configuration of a point defect within the spacer layer, an electronic state energy of the point defect can determine the polarity of a spacer layer, e.g., a positively charged spacer layer or a negatively charged spacer layer. More specifically and without intending to be bound by theory and/or modeling, in some aspects, the electronic state energy of the point defect relative to a conduction band minimum (CBM) and/or a valence band maximum (VBM) of the material that forms the channel region 120 can determine the polarity of spacer layer. Specifically, in a scenario in which the electronic state energy of a point defect of donor type is greater than the CBM, the polarity of the spacer layer can be positive. In another scenario in which the electronic state energy of a point defect of acceptor type is less than the VBM, the polarity of the spacer layer can be negative.

[0022] In some embodiments, a type of \ow-K dielectric material (e.g., an oxide, a nitride, a carbide, a silicate) that constitutes a spacer layer having localized charges, and parameters of a deposition process to form the spacer layer can be selected or otherwise configured in order to form the spacer layer having a defined amount of localized charges in accordance with aspects of this disclosure. Such parameters can include, for example, temperature, partial pressures of respective precursor gases, flow rates of respective precursor gases, pressure of an environment within a reactor (or, in some embodiments, a deposition chamber or reaction chamber), a combination of the foregoing, or the like. In some embodiments, the parameters can be selected to form a non-stoichiometric compound embodying the \ow-K dielectric material in order to achieve a defined amount of point defects (e.g., vacancies) within the spacer layer. The type of the \ow-K dielectric material and the type(s) of the point defects can determine the electronic structure of the spacer layer, including electronic states associated with the type(s) of point defects.

[0023] More specifically, without intending to be bound by theory and/or modeling, impurity dangling bonds (or, in some embodiments, other types of point defects) can be leveraged to introduce electronic states in the bandgap of a dielectric film or another type of layer that forms a spacer layer (e.g., spacer layer 170a or spacer layer 170b). Insofar as the electronic states of the dangling bonds (or, in some embodiments, the other types of point defects) are satisfactorily separated from the energy bandgap of a material that forms or otherwise constitutes the channel region 120— e.g., InAs, GaAs, In^Ga^As, Ali_-xGa_xSb, In_xAl_yAs, Ga_xAl_yAs, InSb, GaAs_xSb_y, InAs_xSb_y, In_xGa_yAs_zPi_-z, a combination thereof, or the like, where x, y, and z represents a real number indicative of the stoichiometry of the compound— , the electronic states can become either positively charged or negatively charged as a localized charge. In some aspects, such a localized charge in the film or layer can attract mobile carriers of an opposite polarity to the channel region 120 or can repel mobile carries of the same polarity from the channel region 120..

[0024] As an illustration, FIG. 5A presents examples of electronic energy diagrams for CBM and VBM for materials that can form or otherwise constitute solid-state devices in accordance with one or more embodiments of the disclosure. FIG. 5A also illustrates energies for electronic states of specific types of point defects (e.g., dangling bonds) in a spacer layer in accordance with one or more embodiments of the disclosure. The solid-state device can include «-FETs or p- FETs. While the illustrated diagrams correspond to two \ow-K dielectric materials— A1₂0₃ and Si H— , the disclosure is not limited in that respect and other \ow-K dielectric materials can be contemplated. The point defects correspond to dangling bonds (DBs) within the spacer layer, and the electronic states of such point defects have corresponding energies within the bandgap of the \ow-K dielectric material that forms the spacer layer. In some embodiments, in order to introduce positive localized charge for «-FET, an Al-rich and O-deficient solid film can be utilized as a spacer layer. In other embodiments, a H-rich and N-deficient solid film can introduce positive localized charge and, thus, the film can embody or otherwise constitute the spacer layer.

[0025] Positive localized charges can be formed in a dielectric material having sufficiently large conduction band offset with respect to a semiconductor material that forms or otherwise constitutes the channel region 120— e.g., there is a sufficient number of unoccupied electron states of donor type in the spacer layer 170a or the spacer layer 170b that have respective electronic energies greater than the bottom conduction band of the semiconductor material. In some embodiments, any dielectric material having a conduction band offset greater than 1 eV can be utilized to form a spacer layer in accordance with aspects of this disclosure. In some embodiments, the \ow-K dielectric material that forms or otherwise constitute the spacer layer can have a conduction band offset greater than 2 eV, e.g. greater than 3 eV or greater than 4 eV. Sufficient conduction band offset between the \ow-K dielectric material and the material of the channel region 120 can permit or otherwise facilitate, in response to the growth processing of the selected dielectric material as described below, forming positive localized charge in the spacer layer 170a or the spacer layer 170b.

[0026] FIG. 5B presents other examples of electronic energy diagrams for solid-state devices in accordance with one or more embodiments of the disclosure. An energy bandgap of each material illustrated in FIG. 5B is the energy difference (in electron volts, shown along the vertical axis of FIG. 5B) between the top of the valence band 524 and the bottom of the conduction band 526, labeled in FIG. 5B only for silicon dioxide (Si02) as an example.

[0027] As is illustrated in FIG. 5B, some dielectric materials may be excluded from being used for creating fixed charges of a particular polarity (positive polarity or negative polarity) because their band offset from the respective channel/slab material may not be sufficiently large. In this context, when evaluating a potential dielectric material for forming a dielectric layer having localized positive charges, the terminology conduction band offset refers to the difference in energy values between the bottom of the conduction band of the potential dielectric material and the bottom of the conduction band of the material in the channel region 120. On the other hand, when evaluating a potential dielectric material for forming a dielectric layer having localized negative charges, the terminology valence band offset refers to the difference in energy values between the top of the valence band of the sufin material and the top of the valence band of the potential dielectric material. For example, as it can be gleaned from FIG. 5B, the energy bandgap of gallium oxide (Ga₂0₃) is such that there are relatively few unoccupied electron states of donor type, as indicated by their bottom of the conduction band values 526, which are higher in energy than the bottom of the conduction bands of the channel/slab materials that form or otherwise constitute the channel region 120— e.g., the conduction band offset is relatively small, compared to other dielectric materials illustrated in FIG. 5B. Therefore, gallium oxide would not be the preferred dielectric material to form a dielectric layer having localized positive charges in accordance with aspects of this disclosure. Similarly, the bandgap of tantalum pentoxide (Ta₂0₅) is such that, compared to gallium oxide (Ga₂0₃), there are somewhat more unoccupied electron states of donor type which are higher in energy than the conduction bands of the channel/slab materials that can form or otherwise constitute the channel region 120. Thus, in some aspects, tantalum pentoxide can provide a better selection than gallium oxide for use in the fabrication of a dielectric layer having positive localized charges. However, compared to still other dielectric materials illustrated in FIG. 5B, even tantalum pentoxide has relatively few unoccupied electron states of donor type which are higher in energy than the bottom of the conduction bands of the channel/slab materials illustrated in FIG. 5B.

[0028] Without intending to be limited to the illustrated materials, the dielectric materials shown in FIG. 5B can be suitable to implement localized negative charges in a charged dielectric layer in solid-state assemblies and/or solid-state devices in accordance with aspects of this disclosure. Specifically, all of the dielectric materials illustrated in FIG. 5B appear to have adequate numbers of occupied electron states of acceptor type, as indicated by their values 524 of respective valence band maxima, which values are less than valence bands maxima of candidate channel/slab materials shown in FIG. 5B. In other words, all of the dielectric materials shown in FIG. 5B appear to have sufficiently large valence band offsets compared to typical subfin materials).

[0029] Some of the dielectric materials shown in FIG. 5B appear to be suitable for implementing both dielectric layers having localized positive charges and other dielectric layers having localized negative charges, such as e.g. silicon dioxide (Si02) which could have both unoccupied electron states of donor type (as indicated by its bottom of the conduction band 526 being sufficiently far, in terms of eV, from the conduction band of candidate channel/slab materials shown in FIG. 5B) for forming localized positive charges as well as occupied electron states of acceptor type (as indicated by its valence band maximum 524 being sufficiently far, in terms of eV, from the valence band of candidate channel/slab materials shown in FIG. 5B) for forming negative fixed charges. Whether such a material can have localized positive charges or localized negative charges can be based at least on how the material is processed or otherwise fabricated, as described in greater detail below. In other words, a given dielectric material (e.g., a material having a certain valence and conduction band values), can be processed to deliberately have a certain concentration of positive charges or a certain concentration of negative charges.

[0030] To form a spacer layer (e.g., the spacer layer 170a or the spacer layer 170b) in accordance with aspects of this disclosure, in some aspects, an amount of a \ow-K dielectric material can be deposited according to one or a combination of numerous deposition processes under deposition conditions that promote incorporation of localized charges of a defined polarity— e.g., positive localized charges or negative localized charges— within the spacer layer. As mentioned, in some aspects, deposition parameters can determine such deposition conditions. The deposition processes can include, for example, chemical vapor deposition (CVD); atomic layer deposition (ALD); physical vapor deposition (PVD); sputtering; chemical solution deposition; or the like. Chemical vapor deposition can include, for example, metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0031] In some aspects, CVD or ALD can include a chemical process in which one or more reactive precursor gases are introduced into a reactor (or, in some embodiments, a reaction chamber) and can be directed towards a substrate in order to induce controlled chemical reactions that result in the growth of a desired material on the substrate. The one or more reactive precursor gases may be provided to the reactor at a flow rate from about 5 standard cubic centimeter per minute (seem) to about 500 seem, for example, including all values and ranges therein. Each (or, in some embodiments, at least one) of the reactive precursor gas(es) can be provided by means of a carrier gas, such as an inert gas (e.g., argon, helium, or the like). In some embodiments, the reactor can be maintained, during deposition, at a defined pressure and a defined temperature. The pressure can have a magnitude in a range from about 1 milliTorr to about 100 milliTorr, including all values and ranges therein, and the temperature can have a magnitude in a range from about 100 °C to 500 °C, including all values and ranges therein. The substrate also can be heated. In some embodiments, the process may be plasma assisted where electrodes are provided within the reactor and are used to ionize the gases. In addition or in other embodiments, plasma may be formed outside of the chamber and then supplied into the reactor. In the reactor, in some aspects, a layer of solid thin film material can be deposited on the surface of the substrate due to reaction of the gas(es).

[0032] A substrate placed in a CVD reactor, ALD reactor, or PVD reactor can include, for example, a solid assembly having a semiconductor slab that embodies a channel stack including the channel region 120. The layer of solid thin film material deposited on a surface of such a substrate due to reaction of precursor gases in the reactor can embody or can constitute a spacer layer having positive localized charge in accordance with aspects described herein. A selection of particular one or more precursor gases can depend on the \ow-K dielectric material that forms or otherwise constitutes the spacer layer. Deposition conditions that permit or otherwise facilitate incorporation of positive localized charges, e.g., formation of native point defects, can include a cation-rich environment in the reactor, the doping of the \ow-K dielectric material being formed with positively-charged impurity atoms, and/or the injection of negatively-charged hydrogen atoms into the reactor (e.g., a hydrogen ambient growth).

[0033] In some embodiments, providing cation-rich growth conditions can include configuring and/or maintaining a partial pressure of cation-precursor species in the reactor nearly at or above a defined threshold, which threshold can be provided either as an absolute value or a value relative to partial pressure of other gasses in the chamber, e.g., such as anion-precursor gases. In some embodiments, establishing cation-rich growth conditions can include ensuring that the respective partial pressure(s) of one or more cation precursor gases can be greater than the partial pressure of the anion precursor gases. For example, the partial pressure of the cation precursor gas(es) can have a magnitude in a range from about one time to about hundred times greater than the partial pressure of the anion precursor gases, including all values and ranges therein. For deposition of a positively charged spacer layer in accordance with aspects of this disclosure, the cation precursor gases can include one or more metal-containing precursors bound by a non-metal element, such as chlorine, fluorine, bromine, iodine, or the like. For instance, in some embodiments, the cation precursor gases can include beryllium chloride;

magnesium chloride; aluminum chloride; hafnium chloride; zirconium chloride; lanthanum chloride; yttrium chloride; scandium chloride; gadolinium chloride; analogous metal-based precursors bound by fluorine, bromine, iodine, etc.; a combination thereof; or the like In other embodiments, the cation precursor gases can include metal-based carbon-containing and/or metal -based hydrogen-containing precursor gases, such as metal-containing amidinates and actinates.

[0034] Doping with impurity atoms that lead to positive localized charges within a spacer layer of this disclosure can be performed by in-situ doping during the CVD or ALD deposition of an amount of \ow-K dielectric material that forms or otherwise constitutes the spacer layer. In some embodiments, impurity atoms that lead to positive localized charges can be incorporated into a \ow-K dielectric material being grown by means of introduction of impurity -level quantities of dopant-containing precursor gases during the growth, and controlled through the partial pressure of such gases. In embodiments in which the \ow-K dielectric material is embodied in an oxide or a silicate, suitable dopant atoms to be provided in a dopant-containing precursor gas can include fluorine, chlorine, bromine, halogens, or the like. In embodiments in which the \ow-K dielectric material is embodied in a nitride, suitable dopant atoms to be provided in a dopant-containing precursor gas can include oxygen, sulfur, selenium, tellurium, or other elements from the oxygen group of the periodic table. In embodiments in which the \ow-K dielectric material is embodied in a carbide, suitable dopant atoms to be provided in a dopant- containing precursor gas can include nitrogen, phosphorus, arsenic, or other elements from the nitrogen group of the periodic table.

[0035] In some embodiments, providing a hydrogen ambient growth can include

incorporating, during growth, atomic hydrogen into the \ow-K dielectric material that forms a spacer layer (e.g., spacer layer 170a or spacer layer 170b) in accordance with aspects of this disclosure. To that end, in one example, a negatively-charged hydrogen ambient (such as hydrogen gas, PE-atomic hydrogen, water, and the like) can be provided during deposition of the spacer layer. The amphoteric nature of atomic hydrogen can permit or otherwise facilitate neutralizing the charge of intentionally incorporated positively-charged point defects (e.g., vacancies, impurities, or the like). This hydrogen-induced charge stabilization can yield more favorable conditions for incorporation of positively-charged point defects, as they are neutralized by atomic hydrogen.

[0036] An as-deposited spacer layer (e.g., spacer layer 170a or spacer layer 170b) can be annealed in order to remove at least a portion of incorporated negatively-charged hydrogen atoms (e.g., about 80 % of the incorporated negatively-charged H atoms) from the spacer layer, thus retaining positive localized charges. In some embodiments, annealing the spacer layer can include heating up a solid-state assembly including the spacer layer to a temperature within a range from about 200 degrees Celsius (° C) to about 600 ⁰ C for a defined period of about 1 minute to about 120 minutes. In some embodiments, \ow-K dielectric materials having oxygen coordination equal to or greater than four in a stoichiometric compound can be more suitable for the application of the disclosed hydrogen technique for incorporation of positive localized charge. Such \ow-K dielectric materials can include, for example, beryllium oxide, magnesium oxide, boron nitride, aluminum nitride, silicon carbide, and the like.

[0037] As disclosed herein, in order to increase drive current in a solid-state device (e.g., a FET) in accordance with aspects of this disclosure, a first polarity of mobile carriers within a carrier-doped epilayer (e.g., doped contact layer 180a or doped contact layer 180b) can be opposite to a second polarity of localized charges within a spacer layer (e.g., spacer layer 170a and spacer layer 180b). Thus, in embodiments in which the carrier-doped epilayer is embodied in a p-type doped epilayer, the spacer layer can include negative localized charges.

[0038] As disclosed herein, negative localized charges can be formed in a \ow-K dielectric material that has sufficiently large valence band offset with respect to a semiconductor material that forms or otherwise constitutes the channel region 120— e.g., there is a sufficient number of occupied electron states of acceptor type in the spacer layer 170a or the spacer layer 170b that have respective electronic energies less than the valence band maximum of the semiconductor material. A dielectric material (\ow-K or otherwise) having a sufficiently large valence band offset from that of the semiconductor material can be utilized to form a spacer layer in accordance with aspects of this disclosure. In some embodiments, any \ow-K dielectric material that has a valence band offset greater than zero can be selected to form a negatively-charged spacer layer. For instance, in some embodiments, the low-K dielectric material can have a valence band offset greater than 1 eV, e.g. equal to or greater than 2 eV, or equal to or greater than 3 eV. Sufficient valence band offset between the \ow-K dielectric material and the material of the channel region 120 can permit or otherwise facilitate, in response to the growth processing of the selected dielectric material as described below, forming negative localized charge in the spacer layer 170a or the spacer layer 170b.

[0039] A spacer layer that includes negative localized charges can be formed by depositing an amount of a \ow-K dielectric material according to one or a combination of numerous deposition processes under deposition conditions that promote incorporation of negative localized charge within the spacer layer. As mentioned, in some aspects, deposition parameters can determine such deposition conditions. The deposition processes can include, for example, CVD; ALD; PVD; sputtering; chemical solution deposition; or the like. Chemical vapor deposition can include, for example, MOCVD, LPCVD, or PECVD. More specifically, in some embodiments, the amount of the \ow-K dielectric material can be deposited on a surface of a solid-assembly including a channel member (a portion of a fin in a FinFET, for example) to form a solid thin film that embodies or otherwise constitutes the spacer layer including the negative localized charges. The solid thin film can be, for example, conformal with such a surface (see FIG. 2, for example). The amount of the \ow-K dielectric material deposited on the surface of such a solid-state assembly can be formed the solid thin film due to reaction of gasses in a reactor (e.g., a CVD reactor, an ALD reactor, a PVD reactor) utilized for the deposition process.

[0040] A selection of particular one or more anion precursor gases can depend on the \ow-K dielectric material that forms or otherwise constitutes the spacer layer including negative localized charges. Deposition conditions that promote the formation of negative localized charges, e.g. the formation of native point defects, can include the formation or retention of an anion-rich environment within the reactor, the doping of the \ow-K dielectric material with negatively charged impurity atoms during deposition, and/or the addition of positively-charged hydrogen atoms to the reactor (e.g., the provision of a hydrogen ambient growth environment).

[0041] In some embodiments, providing anion-rich deposition conditions can include configuring and/or maintaining the partial pressure of anion-precursor species in the reactor nearly at or above a defined threshold. The threshold can be provided either as an absolute value or a value relative to partial pressure of other gasses in the chamber, such as cation-precursor gases. In one example, providing an anion-rich deposition condition can include configuring and maintaining the partial pressure of an anion precursor gas at a level that is greater than the partial pressures of respective cation precursor gases. For example, the partial pressure of the anion precursor gas can have a magnitude in range from about one time to about hundred times greater than the partial pressure of the cation precursor gases, including all values and ranges therein. For deposition of the negative fixed charge dielectric layer as described herein, the anion precursor gases can include, for example, one or more of oxygen-containing precursors (e.g. oxygen gas, water, hydrogen peroxide, etc.); nitrogen-containing precursors (e.g. nitrogen gas, ammonia, nitrous oxide, etc.); or carbon-containing precursors (e.g. carbon dioxide, carbon monoxide, methane, etc.).

[0042] In some embodiments, doping with impurity atoms that lead to negative localized charges in a spacer layer of this disclosure can be performed by in-situ doping during the CVD or ALD deposition of an amount of a \ow-K dielectric material that forms or otherwise constitutes the spacer layer. Impurity atoms that can lead to negative localized charges can be incorporated into the \ow-K dielectric material by means of the introduction of impurity-level amounts of dopant-containing precursor gases during the deposition, and can be controlled through the partial pressure of such gases. In embodiments in which the \ow-K dielectric material is embodied in or includes an oxide or a silicate, suitable dopant atoms to be provided in a dopant-containing precursor gas can include nitrogen, phosphorus, arsenic, or other elements from the nitrogen group of the periodic table. In an embodiment in which the \ow-K dielectric material is embodied in or includes a nitride, suitable dopant atoms to be provided in a dopant- containing precursor gas can include carbon, silicon, germanium, or elements from the carbon group of the periodic table. In embodiments in which the \ow-K dielectric material is embodied in or includes a carbide, suitable dopant atoms to be provided in a dopant-containing precursor gas can include boron, aluminum, gallium, or other elements from the boron group of the periodic table.

[0043] Providing hydrogen-ambient growth for a spacer layer in accordance with aspects of this disclosure can include incorporating atomic hydrogen into a \ow-K dielectric material during the deposition of the spacer layer. To that end, in some embodiments, a positively-charged hydrogen ambient can be provided during growth (such as hydrogen gas, PE-atomic hydrogen, water, and the like). The amphoteric nature of atomic hydrogen can permit or otherwise facilitate neutralizing the charge of intentionally incorporated negatively-charged point defects (e.g., vacancies, impurities, or the like). This hydrogen-induced charge stabilization can yield more favorable conditions for the incorporation of negatively-charged point defects, as they are neutralized by atomic hydrogen.

[0044] An as-deposited spacer layer (e.g., spacer layer 170a or spacer layer 170b) can be annealed in order to remove at least a portion of incorporated positive hydrogen atoms from the spacer layer, thus retaining negative localized charges. In some embodiments, annealing the spacer layer can include heating up a solid-state assembly including the spacer layer to a temperature of about 200 ⁰ C to about 600 ⁰ C for a defined period of about 1 minute to about 120 minutes.

[0045] In view of the various aspects of solid-state assemblies and solid-state devices includes therein, a number of processes or methods for fabricating such assemblies can be implemented in accordance with aspects of this disclosure. As an illustration, FIG. 6 presents an example of a method of fabricating a solid-assembly in accordance with one or more

embodiments of the disclosure. At block 610, a semiconductor slab having a surface can be provided. At block 620, a dielectric layer can be provided. The dielectric layer can be formed or adjacent to the semiconductor slab. As such, the dielectric layer can form a first interface with a portion of the surface and including localized charges of a first polarity. In some embodiments, providing the dielectric layer adjacent to the semiconductor slab can include depositing, on at least the portion of the surface, an amount of a \ow-K dielectric material having a first conduction band minimum (CBM) energy greater than a second CBM energy of a semiconductor compound forming the semiconductor slab. In at least some of those embodiments, depositing the amount of such a \ow-K dielectric material can include subjecting at least the portion of the surface to CVD or ALD of the amount of the \ow-K dielectric material. Depositing the amount of such a \ow-K dielectric material also can include configuring and/or maintaining, during deposition within a reactor, a first partial pressure of cation-precursor species above a second partial pressure of anion-precursor species. In addition or in other embodiments, depositing the amount of such a \ow-K dielectric material can include injecting negatively-charged hydrogen atoms into the reactor during deposition, resulting in a second amount of negatively-charged hydrogen atoms being incorporated into the amount of \ow-K dielectric material. While not illustrated in FIG. 6, in some embodiments, the example method 600 also can include annealing the dielectric layer at a defined temperature during a time interval to remove at least a portion of the second amount of negatively-charged hydrogen atoms.

[0046] In other embodiments, providing the dielectric layer adjacent to the semiconductor slab can include depositing, on at least the portion of the surface, an amount of a \ow-K dielectric material having a first valence band maximum (VBM) energy less than a second VBM energy of a semiconductor compound forming the semiconductor slab. Similar to other embodiments disclosed herein, in some embodiments, depositing the amount of such a \ow-K dielectric material can include subjecting at least the portion of the surface to CVD or ALD of the amount of the \ow-K dielectric material. In at least some of those embodiments, depositing the amount of the low-K dielectric material can include configuring and/or maintaining, during deposition within a reactor, a first partial pressure of anion-precursor species above a second partial pressure of cation-precursor species. In addition or in other embodiments, depositing the amount of the \ow-K material can include injecting positively-charged hydrogen atoms into the reactor during deposition, resulting in a second amount of positively-charged hydrogen atoms being incorporated into the amount of \ow-K dielectric material. While not illustrated in FIG. 6, in some embodiments, the example method 600 also can include annealing the dielectric layer at a defined temperature during a time interval to remove at least a portion of the second amount of positively-charged hydrogen atoms.

[0047] At block 630, a carrier-doped semiconductor layer can be provided. The carrier- doped semiconductor layer can be formed adjacent to the dielectric layer and further adjacent to the semiconductor slab. In some aspect, the carrier-doped semiconductor layer can form a second interface with a second portion of the surface, and can include mobile charges of a second polarity opposite the first polarity. At block 640, an electrode member can be provided. The electrode member can be formed adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.

[0048] FIG. 7 depicts an example of a system 700 according to one or more embodiments of the disclosure. In one embodiment, system 700 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 700 can include a system on a chip (SOC) system or a system-in-package (SiP). [0049] In one embodiment, system 700 includes multiple processors including processor 710 and processor N 705, where processor 705 has logic similar or identical to the logic of processor 710. In one embodiment, processor 710 has one or more processing cores (represented here by processing core 712 and processing core 712N, where 712N represents the Nth processor core inside processor 710, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 7). In some embodiments, processing core 712 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some

embodiments, processor 710 has a cache memory 716 to cache instructions and/or data for system 700. Cache memory 716 may be organized into a hierarchical structure including one or more levels of cache memory.

[0050] In some embodiments, processor 710 includes a memory controller (MC) 714, which is configured to perform functions that enable the processor 710 to access and communicate with memory 730 that includes a volatile memory 732 and/or a non-volatile memory 734. In some embodiments, processor 710 can be coupled with memory 730 and chipset 720. Processor 710 may also be coupled to a wireless antenna 778 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna interface 778 operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0051] In some embodiments, volatile memory 732 includes, but is not limited to,

Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 734 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0052] Memory device 730 stores information and instructions to be executed by processor 710. In one embodiment, memory 730 may also store temporary variables or other intermediate information while processor 710 is executing instructions. In the illustrated embodiment, chipset 720 connects with processor 710 via Point-to-Point (PtP or P-P) interface 717 and P-P interface 722. Chipset 720 enables processor 710 to connect to other elements in system 700. In some embodiments of the disclosure, P-P interface 717 and P-P interface 722 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0053] In some embodiments, chipset 720 can be configured to communicate with processor 710, 705N, display device 740, and other devices 772, 776, 774, 760, 762, 764, 766, 777, etc. Chipset 720 may also be coupled to the wireless antenna 778 to communicate with any device configured to transmit and/or receive wireless signals.

[0054] Chipset 720 connects to display device 740 via interface 726. Display 740 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 710 and chipset 720 are integrated into a single SOC. In addition, chipset 720 connects to bus 750 and/or bus 755 that interconnect various elements 774, 760, 762, 764, and 766. Bus 750 and bus 755 may be interconnected via a bus bridge 772. In one embodiment, chipset 720 couples with a non-volatile memory 760, a mass storage device(s) 762, a keyboard/mouse 764, and a network interface 766 via interface 724 and/or 704, smart TV 776, consumer electronics 777, etc.

[0055] In one embodiment, mass storage device(s) 762 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 766 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0056] While the modules shown in FIG. 7 are depicted as separate blocks within the system 900, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 716 is depicted as a separate block within processor 710, cache memory 716 or selected elements thereof can be incorporated into processor core 712.

[0057] It is noted that the system 700 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers,

microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor devices (for example, the semiconductor device described in connection with FIG. 1) or other types of semiconductor devices, as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0058] The semiconductor devices or other types of solid-state devices, as described herein, may be embody or may constitute one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel®

Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (e.g., Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0059] Additionally or alternatively, the semiconductor devices, as described herein, may embody or may constitute one or more memory chips or other types of memory devices. The memory chips may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR- SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non- volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0060] In example embodiments, the electronic device in which the semiconductor devices in accordance with this disclosure are provided may be a computing device. Such a computing device may house one or more boards on which the semiconductor package connections may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the

semiconductor package. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing

device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0061] The semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.). [0062] Additionally or alternatively, semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure may be used in connection with one or more memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR- SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0063] In example embodiments, an electronic device in which the semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure can be used and/or provided may be a computing device. Such a computing device may house one or more boards on which the interconnects may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the interconnects. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0064] Further Examples.— The following example embodiments pertain to further embodiments of this disclosure. Example 1 is a solid-state assembly, comprising: a

semiconductor slab having a surface; a dielectric layer adjacent to the semiconductor slab, the dielectric layer forming a first interface with a portion of the surface and including localized charges of a first polarity; a carrier-doped semiconductor layer adjacent to the dielectric layer and further adjacent to the semiconductor slab, the carrier-doped semiconductor layer forming a second interface with a second portion of the surface and including mobile charges of a second polarity opposite the first polarity; and an electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.

[0065] In Example 2, the assembly of Example 1 can optionally include the semiconductor slab comprises a III-V semiconductor compound, and wherein the dielectric layer comprising a \ow-K dielectric material selected from the group consisting of an oxide, a nitride, a carbide, and a silicate. In Example 3, the assembly of any one of Examples 1-2 can optionally include the oxide comprising beryllium oxide, magnesium oxide, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, scandium oxide, or gadolinium oxide.

[0066] In Example 4, the assembly of any one of Examples 1-3 can optionally include the nitride comprises boron nitride, aluminum nitride, or silicon nitride.

[0067] In Example 5, the assembly of any one of Examples 1-4 can optionally include the carbide comprising a wide-bandgap polytype of silicon carbide.

[0068] In Example 6, the assembly of any one of Examples 1-5 can optionally include the carbide comprising a wide-bandgap polytype of silicon carbide.

[0069] In Example 7, the assembly of any one of Examples 1-6 can optionally include the dielectric layer has a substantially uniform thickness of a magnitude in a range from about 2 nm to about 20 nm.

[0070] In Example 8, the assembly of any one of Examples 1-7 can optionally include the localized charges of the first polarity being arranged within the dielectric layer with a defined

12 2 13 2

average charge density in a range from about 10 cm^" to about 10 cm^" .

[0071] In Example 9, the assembly of any one of Examples 1-8 can optionally include the first polarity being positive polarity, and wherein the carrier-doped semiconductor layer comprises an «-type epitaxial semiconductor layer.

[0072] In Example 10, the assembly of any one of Examples 1-9 can optionally include the semiconductor slab comprising a III-V semiconductor compound, and the dielectric layer comprising point defects having respective electronic states of energy greater than a conduction band minimum of the III-V semiconductor compound.

[0073] In Example 11, the assembly of any one of Examples 1-10 can optionally include the dielectric layer comprising a second conduction band minimum, an energy difference between the second conduction band minimum and the conduction band minimum being greater than about 1 eV.

[0074] In Example 12, the assembly of any one of Examples 1-11 can optionally include the III-V semiconductor compound being selected from the group consisting of InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAs and GaAs, a second alloy of InAl and AlAs, a third alloy of GaAs and AlAs, a fourth alloy of GaAs and GaSb, and a fifth alloy of InAs and InSb, and the dielectric layer being selected from the group consisting of Al-rich aluminum oxide and N-deficient silicon nitride.

[0075] In Example 13, the assembly of any one of Examples 1-12 can optionally include the first polarity being negative polarity, and the carrier-doped semiconductor layer comprising a p- type epitaxial semiconductor layer.

[0076] In Example 14, the assembly of any one of Examples 1-13 can optionally include the semiconductor slab comprising a III-V semiconductor compound, and the dielectric layer comprising point defects having respective electronic states of energy less than a valence band maximum of the III-V compound.

[0077] In Example 15, the assembly of any one of Examples 1-14 can optionally include the dielectric layer comprising a second valence band maximum, an energy difference between the valence band maximum and the second valence band maximum being greater than about 1 eV.

[0078] In Example 16, the assembly of any one of Examples 1-15 can optionally include the III-V semiconductor compound being selected from the group consisting of InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAs and GaAs, a second alloy of InAl and AlAs, a third alloy of GaAs and AlAs, a fourth alloy of GaAs and GaSb, and a fifth alloy of InAs and InSb, and the dielectric layer being selected form the group comprising O-rich aluminum oxide and N- rich silicon nitride.

[0079] Example 17 is a method, comprising: providing a semiconductor slab having a surface; providing a dielectric layer adjacent to the semiconductor slab, the dielectric layer forming a first interface with a portion of the surface and including localized charges of a first polarity; providing a carrier-doped semiconductor layer adjacent to the dielectric layer and further adjacent to the semiconductor slab, the carrier-doped semiconductor layer forming a second interface with a second portion of the surface and including mobile charges of a second polarity opposite the first polarity; and providing an electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.

[0080] In Example 18, the method of Example 17 can optionally include providing the dielectric layer adjacent to the semiconductor slab comprises depositing, on at least the portion of the surface, an amount of a low-K dielectric material having a first conduction band minimum (CBM) energy greater than a second CBM energy of a semiconductor compound forming the semiconductor slab.

[0081] In Example 19, the method of any one of Examples 17-18 can optionally include the depositing comprising subjecting at least the portion of the surface to chemical vapor deposition (CVD) or atomic layer deposition (ALD) of the amount of the low-K dielectric material, wherein the depositing further comprises maintaining, during deposition within a reactor, a first partial pressure of cation-precursor species above a second partial pressure of anion-precursor species.

[0082] In Example 20, the method of any one of Examples 17-19 can optionally include the depositing further comprising injecting negatively-charged hydrogen atoms into the reactor during deposition, resulting in a second amount of negatively-charged hydrogen atoms being incorporated into the amount of low-K dielectric material.

[0083] In Example 21, the method of Examples 17-20 can optionally include annealing the dielectric layer at a defined temperature during a time interval to remove at least a portion of the second amount of negatively-charged hydrogen atoms.

[0084] In Example 22, the method of any one of Examples 17-21 can optionally include providing the dielectric layer adjacent to the semiconductor slab comprising depositing, on at least the portion of the surface, an amount of a low-K dielectric material having a first valence band maximum (VBM) energy less than a second VBM energy of a semiconductor compound forming the semiconductor slab.

[0085] In Example 23, the method of any one of Examples 17-22 can optionally include the depositing comprising subjecting at least the portion of the surface to chemical vapor deposition (CVD) or atomic layer deposition (ALD) of the amount of the low-K dielectric material, the depositing further comprising maintaining, during deposition within a reactor, a first partial pressure of anion-precursor species above a second partial pressure of cation-precursor species.

[0086] In Example 24, the method of any one of Examples 17-23 can optionally include the depositing further comprising injecting positively-charged hydrogen atoms into the reactor during deposition, resulting in a second amount of positively-charged hydrogen atoms being incorporated into the amount of low-K dielectric material.

[0087] In Example 25, the method of any one of Examples 17-24 can optionally include annealing the dielectric layer at a defined temperature during a time interval to remove at least a portion of the second amount of positively-charged hydrogen atoms.

[0088] Example 26 is an electronic device, comprising: at least one semiconductor die having circuitry assembled therein, the circuitry comprising a plurality of solid-state devices, at least one of the plurality of solid-state devices comprising, a semiconductor slab having a surface; a dielectric layer adjacent to the semiconductor slab, the dielectric layer forming a first interface with a portion of the surface and including localized charges of a first polarity; a carrier-doped semiconductor layer adjacent to the dielectric layer and further adjacent to the semiconductor slab, the carrier-doped semiconductor layer forming a second interface with a second portion of the surface and including mobile charges of a second polarity opposite the first polarity; and an electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.

[0089] In Example 27, the device of Example 26 can optionally include the semiconductor slab comprising a III-V semiconductor compound, and the dielectric layer comprising a low-K dielectric material selected from the group consisting of an oxide, a nitride, a carbide, and a silicate.

[0090] In Example 28, the device of any one of Examples 26-27 can optionally include the dielectric layer having a substantially uniform thickness of a magnitude in a range from about 2 nm to about 20 nm.

[0091] In Example 29, the device of any one of Examples 26-28 can optionally include the localized charges of the first polarity being arranged within the dielectric layer with a defined

12 2 13 2

average charge density in a range from about 10 cm^" to about 10 cm^" .

[0092] In Example 30, the device of any one of Examples 26-29 can optionally include the first polarity being positive polarity, and the carrier-doped semiconductor layer comprising an n- type epitaxial semiconductor layer.

[0093] In Example 31, the device of any one of Examples 26-30 can optionally include the semiconductor slab comprising a III-V semiconductor compound, and the dielectric layer comprising point defects having respective electronic states of energy greater than a conduction band minimum of the III-V semiconductor compound.

[0094] In Example 32, the device of any one of Examples 26-31 can optionally include the dielectric layer comprising a second conduction band minimum, an energy difference between the second conduction band minimum and the conduction band minimum being greater than about 1 eV.

[0095] In Example 33, the device of any one of Examples 26-32 can optionally include the III-V semiconductor compound being selected from the group consisting of InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAs and GaAs, a second alloy of InAl and AlAs, a third alloy of GaAs and AlAs, a fourth alloy of GaAs and GaSb, and a fifth alloy of InAs and InSb, and the dielectric layer being selected from the group consisting of Al-rich aluminum oxide and N-deficient silicon nitride.

[0096] In example 34, the device of any one of Examples 26-33 can optionally include the first polarity being negative polarity, and the carrier-doped semiconductor layer comprising a p- type epitaxial semiconductor layer.

[0097] In Example 35, the device of any one of Examples 26-34 can optionally include the semiconductor slab comprising a III-V semiconductor compound, and the dielectric layer comprising point defects having respective electronic states of energy less than a valence band maximum of the III-V compound.

[0098] In Example 36, the device of any one of Examples 26-35 can optionally include the dielectric layer comprising a second valence band maximum, an energy difference between the valence band maximum and the second valence band maximum being greater than about 1 eV.

[0099] In Example 37, the device of any one of Examples 26-36 can optionally the III-V semiconductor compound being selected from the group consisting of InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAs and GaAs, a second alloy of InAl and AlAs, a third alloy of GaAs and AlAs, a fourth alloy of GaAs and GaSb, and a fifth alloy of InAs and InSb, and the dielectric layer being selected form the group comprising O-rich aluminum oxide and N-rich silicon nitride.

[0100] As mentioned, unless otherwise expressly stated, it is in no way intended that any protocol, procedure, process, or method set forth herein be construed as requiring that its acts or steps be performed in a specific order. Accordingly, where a process or method claim does not actually recite an order to be followed by its acts or steps or it is not otherwise specifically recited in the claims or descriptions of the subject disclosure that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps or operational flow; plain meaning derived from grammatical organization or punctuation; the number or type of embodiments described in the specification or annexed drawings, or the like.

[0101] Conditional language, such as, among others, "can," "could," "might," or "may," unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain implementations could include, while other

implementations do not include, certain features, elements, and/or operations. Thus, such conditional language generally is not intended to imply that features, elements, and/or operations are in any way required for one or more implementations or that one or more implementations necessarily include logic for deciding, with or without user input or prompting, whether these features, elements, and/or operations are included or are to be performed in any particular implementation.

[0102] As used herein, the term "substantially" indicates that each of the described dimensions is not a strict boundary or parameter and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the term "substantially" in connection with a numerical parameter indicates that the numerical parameter includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.

[0103] Further, certain relationships between dimensions of layers of a semiconductor device in accordance with this disclosure and between other elements of the semiconductor device are described herein using the term "substantially equal." As used herein, the term "substantially equal" indicates that the equal relationship is not a strict relationship and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the term "substantially equal" in connection with two or more described dimensions indicates that the equal relationship between the dimensions includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit of the dimensions. As used herein, the term "substantially constant" indicates that the constant relationship is not a strict relationship and does not exclude functionally similar variations therefrom.

[0104] As used herein, the term "substantially parallel" indicates that the parallel relationship is not a strict relationship and does not exclude functionally similar variations therefrom. As used herein the term "substantially perpendicular" indicates that the perpendicular relationship between two or more elements of a semiconductor device in accordance with this disclosure are not a strict relationship and does not exclude functionally similar variations therefrom.

[0105] The term "horizontal" as used herein may be defined as a direction parallel to a plane or surface (e.g., surface of a substrate), regardless of its orientation. The term "vertical," as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as "on," "above," "below," "bottom," "top," "side" (as in "sidewall"), "higher," "lower," "upper," "over," and "under," may be referenced with respect to the horizontal plane. The term "processing" as used herein is generally intended to include deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in forming a described structure.

[0106] What has been described herein in the present specification and annexed drawings includes examples of solid-state semiconductor devices having dielectric layers including localized charges of a first polarity, and processes for providing such dielectric layers. It is, of course, not possible to describe every conceivable combination of elements and/or

methodologies for purposes of describing the various features of the disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of the claimed subject matter are possible. Accordingly, it may be apparent that various modifications can be made to the disclosure without departing from the scope or spirit thereof. In addition or in the alternative, other embodiments of the disclosure may be apparent from consideration of the specification and annexed drawings, and practice of the disclosure as presented herein. It is intended that the examples put forward in the specification and annexed drawings be considered, in all respects, as illustrative and not restrictive. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

claimed is:

A solid assembly, comprising:

a semiconductor slab having a surface;

a dielectric layer adjacent to the semiconductor slab, the dielectric layer forming a first interface with a portion of the surface and including localized charges of a first polarity;

a carrier-doped semiconductor layer adjacent to the dielectric layer and further adjacent to the semiconductor slab, the carrier-doped semiconductor layer forming a second interface with a second portion of the surface and including mobile charges of a second polarity opposite the first polarity; and

an electrode member adjacent to the dielectric layer and further adjacent to the carrier- doped semiconductor layer.

The solid assembly of claim 1, wherein the semiconductor slab comprises a III-V semiconductor compound, and wherein the dielectric layer comprises a \ow-K dielectric material selected from the group consisting of an oxide, a nitride, a carbide, and a silicate.

The solid assembly of claim 1, wherein the dielectric layer has a substantially uniform thickness of a magnitude in a range from about 2 nm to about 20 nm.

The solid assembly of claim 1, wherein the localized charges of the first polarity are arranged within the dielectric layer with a defined average charge density in a range from about 10¹² cm^"2 to about 10¹³ cm^"2.

The solid assembly of claim 4, wherein the first polarity is positive polarity, and wherein the carrier-doped semiconductor layer comprises an «-type epitaxial semiconductor layer.

6. The solid assembly of claim 5, wherein the semiconductor slab comprises a III-V semiconductor compound, and wherein the dielectric layer comprises point defects having respective electronic states of energy greater than a conduction band minimum of the III-V semiconductor compound.

7. The solid assembly of claim 6, wherein the III-V semiconductor compound is selected from the group consisting of InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAs and GaAs, a second alloy of InAl and AlAs, a third alloy of GaAs and AlAs, a fourth alloy of GaAs and GaSb, and a fifth alloy of InAs and InSb, and wherein the dielectric layer is selected from the group consisting of Al-rich aluminum oxide and N- deficient silicon nitride.

8. The solid assembly of claim 3, wherein the first polarity is negative polarity, and wherein the carrier-doped semiconductor layer comprises a p-type epitaxial semiconductor layer.

9. The solid assembly of claim 8, wherein the semiconductor slab comprises a III-V

semiconductor compound, and wherein the dielectric layer comprises point defects having respective electronic states of energy less than a valence band maximum of the III-V semiconductor compound.

10. The solid assembly of claim 9, wherein the III-V semiconductor compound is selected from the group consisting of InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAs and GaAs, a second alloy of InAl and AlAs, a third alloy of GaAs and AlAs, a fourth alloy of GaAs and GaSb, and a fifth alloy of InAs and InSb, and wherein the dielectric layer is selected from a group comprising O-rich aluminum oxide and N-rich silicon nitride.

11. A method of fabricating a solid-state device, comprising:

providing a semiconductor slab having a surface;

providing a dielectric layer adjacent to the semiconductor slab, the dielectric layer

forming a first interface with a portion of the surface and including localized charges of a first polarity;

providing a carrier-doped semiconductor layer adjacent to the dielectric layer and further adjacent to the semiconductor slab, the carrier-doped semiconductor layer forming a second interface with a second portion of the surface and including mobile charges of a second polarity opposite the first polarity; and

providing an electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.

12. The method of claim 11, wherein providing the dielectric layer adjacent to the

semiconductor slab comprises depositing, on at least the portion of the surface, an amount of a \ow-K dielectric material having a first conduction band minimum (CBM) energy greater than a second CBM energy of a semiconductor compound forming the semiconductor slab.

13. The method of claim 12, wherein the depositing comprises subjecting at least the portion of the surface to chemical vapor deposition (CVD) or atomic layer deposition (ALD) of the amount of the \ow-K dielectric material,

wherein the depositing further comprises maintaining, during deposition within a reactor, a first partial pressure of cation-precursor species above a second partial pressure of anion-precursor species.

14. The method of claim 13, wherein the depositing further comprises injecting negatively- charged hydrogen atoms into the reactor during deposition, resulting in a second amount of negatively-charged hydrogen atoms being incorporated into the amount of the \ow-K dielectric material. The method of claim 14, further comprising annealing the dielectric layer at a defined temperature during a time interval to remove at least a portion of the second amount of negatively-charged hydrogen atoms.

The method of claim 11, wherein providing the dielectric layer adjacent to the semiconductor slab comprises depositing, on at least the portion of the surface, an amount of a \ow-K dielectric material having a first valence band maximum (VBM) energy less than a second VBM energy of a semiconductor compound forming the semiconductor slab.

The method of claim 16, wherein the depositing comprises subjecting at least the portion of the surface to chemical vapor deposition (CVD) or atomic layer deposition (ALD) of the amount of the \ow-K dielectric material,

wherein the depositing further comprises maintaining, during deposition within a reactor, a first partial pressure of anion-precursor species above a second partial pressure of cation-precursor species.

The method of claim 17, wherein the depositing further comprises injecting positively- charged hydrogen atoms into the reactor during deposition, resulting in a second amount of positively-charged hydrogen atoms being incorporated into the amount of the \ow-K dielectric material.

The method of claim 18, further comprising annealing the dielectric layer at a defined temperature during a time interval to remove at least a portion of the second amount of positively-charged hydrogen atoms.

An electronic device, comprising:

at least one semiconductor die having circuitry assembled therein, the circuitry

comprising a plurality of solid-state devices, at least one of the plurality of solid-state devices comprising,

a semiconductor slab having a surface; a dielectric layer adjacent to the semiconductor slab, the dielectric layer forming a first interface with a portion of the surface and including localized charges of a first polarity;

a carrier-doped semiconductor layer adjacent to the dielectric layer and further

adjacent to the semiconductor slab, the carrier-doped semiconductor layer forming a second interface with a second portion of the surface and including mobile charges of a second polarity opposite the first polarity; and

an electrode member adjacent to the dielectric layer and further adjacent to the

carrier-doped semiconductor layer.

The electronic device of claim 20, wherein the semiconductor slab comprises a III-V semiconductor compound, and wherein the dielectric layer comprises a \ow-K dielectric material selected from the group consisting of an oxide, a nitride, a carbide, and a silicate.

The electronic device of claim 20, wherein the first polarity is positive polarity, and wherein the carrier-doped semiconductor layer comprises an «-type epitaxial

semiconductor layer.

The electronic device of claim 22, wherein the semiconductor slab comprises a III-V semiconductor compound, and wherein the dielectric layer comprises point defects having respective electronic states of energy greater than a conduction band minimum of the III-V semiconductor compound.

The electronic device of claim 20, wherein the first polarity is negative polarity, and wherein the carrier-doped semiconductor layer comprises a p-type epitaxial

semiconductor layer.

The electronic device of claim 24, wherein the semiconductor slab comprises a III-V semiconductor compound, and wherein the dielectric layer comprises point defects having respective electronic states of energy less than a valence band maximum of the III-V semiconductor compound.