WO2018178798A1

WO2018178798A1 - Display device and method for driving display device

Info

Publication number: WO2018178798A1
Application number: PCT/IB2018/051793
Authority: WO
Inventors: 宍戸英明; 魚地秀貴; 山崎舜平
Original assignee: 株式会社半導体エネルギー研究所
Priority date: 2017-03-27
Filing date: 2018-03-19
Publication date: 2018-10-04

Abstract

The present invention provides a display device capable of high-speed operation. The display device comprises: a plurality of pixels arranged in m rows and n columns; scanning lines arranged in m rows; video signal lines arranged in n columns; and m+1 common lines. The m+1 common lines extend substantially parallel to the scanning lines arranged in the m rows. Pixels in the xth row (x is an integer greater than or equal to 1 and less than or equal to m−1) and in the odd numbered columns are electrically connected to the scanning line in the xth row, the video signal lines in the odd numbered columns, and the xth common line, and pixels 111 in the xth row and in the even numbered columns are electrically connected to the scanning line in the xth row, the video signal lines in the even numbered columns, and the (x+1)th common line. Pixels in the mth row and in the odd numbered columns are electrically connected to the scanning line in the mth row, the video signal lines in the odd numbered columns, and the mth common line, and pixels 111 in the mth row and in the even numbered columns are electrically connected to the scanning line in the mth row, the video signal lines in the even numbered columns, and the (m+1)th common line.

Description

Display device and driving method of display device

One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the invention disclosed in this specification and the like relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, the present invention relates to a semiconductor device, a display device, or a driving method of the display device.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may be referred to as a semiconductor device. Alternatively, it may be said that these include semiconductor devices.

In recent years, high-resolution display devices have been demanded. For example, in a television device for home use (also referred to as a television or a television receiver), the resolution is full high-definition (pixel number 1920 × 1080), but 4K (pixel number 3840 × 2160). In addition, development of high-resolution display devices such as 8K (the number of pixels: 7680 × 4320) is in progress. In addition, stationary display devices tend to have a screen size of 30 inches or more diagonally, and developments are being made with a view to screen sizes of 60 inches diagonal or more and 120 inches diagonal or more. ing. Further, in order to improve display quality, an improvement in frame frequency is required.

As a display device that realizes such a requirement, an active matrix display device is known. For example, an active matrix type liquid crystal display device using a liquid crystal element as a display element, an active matrix type light emitting display device using a light emitting element such as an organic EL (Electro Luminescence) element as a display element, and the like are known.

In an active matrix liquid crystal display device, a common inversion driving method is known as a driving method with low power consumption. For example, Patent Document 1 discloses a liquid crystal display device that combines a common inversion driving method and a dot inversion driving method.

JP 11-119193 A

However, in Patent Document 1, since the polarity of the common voltage of the entire display unit is inverted every frame period (corresponding to “one field period” in Patent Document 1), insufficient writing of common voltage (insufficient inversion). Is likely to occur. In particular, in the case of a display device having a large screen size, the display quality tends to deteriorate. In addition, there is a problem that the frame frequency cannot be increased because the writing of the common voltage becomes insufficient as the frame frequency increases.

An object of one embodiment of the present invention is to provide a display device with high display quality, a driving method thereof, or the like. Another object is to provide a display device with low power consumption, a driving method thereof, or the like. Another object is to provide a display device that can operate at high speed, a driving method thereof, or the like. Another object is to provide a display device with high productivity or a driving method thereof. Another object is to provide a display device with high reliability, a driving method thereof, or the like. Another object is to provide a novel display device or the like. Another object is to provide a novel driving method of a display device or the like.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

(1) According to one embodiment of the present invention, a plurality of pixels arranged in m rows and n columns (m and n are each an integer of 2 or more), m rows of scanning lines, n columns of video signal lines, m + 1 common lines, the m + 1 common lines extend in a direction substantially parallel to the m rows of scanning lines, and each of the plurality of pixels includes a transistor and a display element, and x The pixel in the row j column (x is an integer from 1 to m-1 and j is an integer from 1 to n) is the x-th scanning line, the j-th video signal line, and the x-th common line. The pixel in the xth row, j + 1th column is electrically connected to the xth row scanning line, the j + 1th column video signal line, and the x + 1th common line, and the mth row, jth column. The pixels are electrically connected to the m-th scanning line, the j-th video signal line, and the m-th common line. Scan lines, a display device, characterized in that it is connected j + 1 column of the video signal lines, and m + and electrically one th common line.

(2) Another aspect of the present invention includes a plurality of pixels arranged in m rows and n columns, m rows of scanning lines, n columns of video signal lines, and m + 1 common lines, The m + 1 common lines extend in a direction substantially parallel to the m rows of scanning lines, and each of the plurality of pixels includes a transistor and a display element. The x row and the j column (x is 1 or more and m) -1 or less integer, j is an integer between 1 and n inclusive) is electrically connected to the x-th scanning line, the j-th video signal line, and the (x + 1) -th common line, and x-row j + 1 The pixel in the column is electrically connected to the scanning line in the x-th row, the video signal line in the j + 1-th column, and the x-th common line, and the pixel in the m-th row and j-th column is the scanning line in the m-th row, The video signal line in the jth column and the m + 1th common line are electrically connected, and the pixel in the mth row, j + 1th column is the scanning line in the mth row, the video in the j + 1th column. Line, and a display device, characterized in that m is the first common line electrically connected.

Another embodiment of the present invention is the display device according to (1) or (2) described above, in a period in which a pixel in the p-th row (p is an integer of 1 to m-2) is selected. The display device driving method is characterized in that the polarity of the voltage supplied to the p + 2 common line is inverted.

Another embodiment of the present invention is the display device described in (1) or (2) above, in which the voltage supplied to the first common line in the period in which the pixels in the (m−1) th row are selected. The display device driving method is characterized in that the polarity of the display is reversed.

Another embodiment of the present invention is the display device described in the above (1) or (2), wherein the polarity of the voltage supplied to the first common line during the period when the m-th row pixel is selected. Is a method for driving a display device.

Another embodiment of the present invention is the display device described in the above (1) or (2), wherein the polarity of the voltage supplied to the second common line during the period when the m-th row pixel is selected. Is a method for driving a display device.

(3) Another aspect of the present invention is that a plurality of pixels arranged in m rows and n columns (m and n are integers of 4 or more, respectively), m rows of scanning lines, and n first videos A signal line, n second video signal lines, and m + 1 common lines, the m + 1 common lines extending in a direction substantially parallel to the m rows of scanning lines, Each pixel includes a transistor and a display element, and the pixel in the xth row and jth column (x is an integer from 1 to m-2 and j is an integer from 1 to n) is the scanning line in the xth row, The pixels of the (x + 1) th row and the jth column are electrically connected to the jth first video signal line and the xth common line, and the x + 1th row scanning line, the jth second video signal line, and the x + 1th row are connected. The pixel in the xth row, j + 1th column is electrically connected to the common line, the xth row scanning line, the j + 1th first video signal line, and the x + 1th row. The pixel in the (x + 1) th row and the (j + 1) th column is electrically connected to the (x + 1) th row scanning line, the (j + 1) th second video signal line, and the (x + 2) th common line, and m− The pixel in the 1st row and the jth column is electrically connected to the m−1th row scanning line, the jth first video signal line, and the m−1th common line. , The m-th scanning line, the j-th second video signal line, and the m-th common line are electrically connected to the m−1-th row j + 1-column pixel, The pixel in the m-th row, j + 1-th column is electrically connected to the j + 1-th first video signal line and the m-th common line, and the m-th row, j + 1-th column pixel is the m + 1-th scanning line, the j + 1-th second video signal line, The display device is electrically connected to the common line.

(4) According to another aspect of the present invention, a plurality of pixels arranged in m rows and n columns (m and n are integers of 4 or more, respectively), m rows of scanning lines, and n first videos A signal line, n second video signal lines, and m + 1 common lines, the m + 1 common lines extending in a direction substantially parallel to the m rows of scanning lines, Each pixel includes a transistor and a display element, and the pixel in the xth row and jth column (x is an integer from 1 to m-2 and j is an integer from 1 to n) is the scanning line in the xth row, The pixels of the (x + 1) th row and the jth column are electrically connected to the jth first video signal line and the (x + 1) th common line, and the x + 1th row scanning line, the jth second video signal line, and the (x + 2) th row are connected. The xth row, j + 1th column pixel is electrically connected to the xth scanning line, j + 1th first video signal line, and xth row. The pixel in the (x + 1) th row and the (j + 1) th column is electrically connected to the (x + 1) th row scanning line, the (j + 1) th second video signal line, and the (x + 1) th common line. The pixel in the 1st row and the jth column is electrically connected to the scanning line in the (m-1) th row, the jth first video signal line, and the mth common line, and the pixel in the mth and jth column is m The pixels in the (m−1) th row, (j + 1) th column are electrically connected to the scanning line in the row, the jth second video signal line, and the m + 1th common line. The first video signal line and the (m-1) th common line are electrically connected to each other, and the pixel in the mth row, j + 1th column is the mth row scanning line, the j + 1th second video signal line, and the mth row. The display device is electrically connected to the common line.

Another embodiment of the present invention is the display device according to (3) or (4) described above, in a period in which a pixel in the p-th row (p is an integer of 1 to m-3) is selected. The display device driving method is characterized by inverting the polarity of the voltage supplied to the p + 2 common line and the polarity of the voltage supplied to the p + 3 common line.

Another embodiment of the present invention is the display device described in (3) or (4) above, in which the voltage supplied to the first common line during the period in which the pixel on the (m-2) th row is selected. The display device driving method is characterized in that the polarity of the display is reversed.

Another embodiment of the present invention is the display device described in the above (3) or (4), wherein the polarity of the voltage supplied to the first common line during the period when the m-th row pixel is selected. Is a method for driving a display device.

Another embodiment of the present invention is the display device described in the above (3) or (4), wherein the polarity of the voltage supplied to the second common line in the period when the m-th row pixel is selected. And a polarity of the voltage supplied to the third common line, respectively.

As the display element, a liquid crystal element or the like can be used. As the semiconductor layer of the transistor, silicon, metal oxide, or the like can be used.

According to one embodiment of the present invention, a display device with high display quality, a driving method thereof, or the like can be provided. Alternatively, a display device with low power consumption or a driving method thereof can be provided. Alternatively, a display device that can operate at high speed or a driving method thereof can be provided. Alternatively, a display device with high productivity or a driving method thereof can be provided. Alternatively, a display device with favorable reliability or a driving method thereof can be provided. Alternatively, a novel display device or the like can be provided. Alternatively, a novel driving method of the display device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

FIG. 10 illustrates a display device. 8A and 8B illustrate a circuit configuration example of pixels and a combination example of sub-pixels. FIG. 10 illustrates a display device. FIG. 10 illustrates a display device. FIG. 10 illustrates a display device. FIG. 10 illustrates a display device. The figure explaining the common inversion drive method. 6 is a timing chart illustrating operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 10 illustrates a display device. FIG. 10 illustrates a display device. 6 is a timing chart illustrating operation of a display device. 6 is a timing chart illustrating operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. FIG. 14 illustrates operation of a display device. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. 6A and 6B illustrate a structure example of a transistor. FIG. 10 illustrates a display device. FIG. 10 illustrates a display device. 10A and 10B each illustrate an electronic device. 10A and 10B each illustrate an electronic device.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In addition, the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally lost due to a process such as etching, but may be omitted to facilitate understanding of the invention.

In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may not be described in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.

In the present specification and the like, ordinal numbers such as “first” and “second” are used to avoid confusion between components, and do not indicate any order or order such as process order or stacking order. In addition, even in terms that do not have an ordinal number in this specification and the like, an ordinal number may be added in the claims to avoid confusion between the constituent elements. In addition, the ordinal numbers given in this specification and the like may differ from the ordinal numbers given in the claims. Even in the present specification and the like, terms with ordinal numbers are sometimes omitted in the claims.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are provided integrally.

The “voltage” often indicates a potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, it may be possible to paraphrase “voltage” and “potential”.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and drain via the channel formation region. It is possible to pass a current through. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

The transistors described in this specification and the like are enhancement-type (normally-off) field-effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is greater than 0 V unless otherwise specified.

Note that in this specification and the like, Vth of a transistor having a back gate refers to Vth when the potential of the back gate is the same as that of the source or the gate unless otherwise specified.

In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). In the n-channel transistor, the potential difference between the gate and the source (hereinafter also referred to as “Vg”) with respect to the source is lower than the threshold voltage Vth unless otherwise specified. A state, a p-channel transistor, refers to a state where the voltage Vg between the gate and the source is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when Vg is lower than a threshold voltage (hereinafter also referred to as “Vth”).

In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

In this specification and the like, the term “leakage current” may be used in the same meaning as off-state current. In this specification and the like, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. Therefore, even in the case of being expressed as “electrically connected”, in an actual circuit, there is a case where there is no physical connection portion and the wiring is merely extended.

In the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below and is in direct contact. For example, in the expression “electrode B on the insulating layer A”, the electrode B does not need to be provided directly on the insulating layer A, and another configuration is provided between the insulating layer A and the electrode B. Do not exclude things that contain elements.

Further, in this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °, unless otherwise specified. Therefore, the case of −5 ° to 5 ° is also included. In addition, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °, unless otherwise specified. “Vertical” and “orthogonal” refer to a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less, unless otherwise specified. Therefore, the case of 85 ° to 95 ° is also included. In addition, “substantially vertical” refers to a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less, unless otherwise specified.

In addition, in this specification, etc., the terms “same”, “same”, “equal”, “uniform” (including these synonyms), etc. with respect to the count value and the measured value, unless otherwise specified. And an error of plus or minus 20%.

(Embodiment 1)
Configuration examples of the display device 100 of one embodiment of the present invention are described with reference to drawings.

<Configuration example>
FIG. 1A is a block diagram for explaining a configuration example of the display device 100. The display device 100 includes a display unit 110, a scanning line driving circuit 121, a signal line driving circuit 131, a signal line driving circuit 132, and a common line driving circuit 141. Note that a generic term for circuits included in the scanning line driver circuit 121, the signal line driver circuit 131, the signal line driver circuit 132, and the common line driver circuit 141 may be referred to as “peripheral driver circuit” or “driver circuit”. As the peripheral driver circuit, various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit can be used.

FIG. 1B is a block diagram illustrating part of the display portion 110. The display unit 110 includes a plurality of pixels 111. For example, the pixel 111 includes a plurality of pixels 111 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). In this specification and the like, the pixel 111 located in the i-th row and j-th column (i is an integer of 1 to m. J is an integer of 1 to n) is denoted as a pixel 111 [i, j].

In FIG. 1B, the pixel 111 in the i-th row and j-th column is electrically connected to the i + 1-th wiring COM, and the pixel 111 in the i-th row j + 1 column is electrically connected to the i-th wiring COM. A block diagram is shown. However, the configuration is not limited to this, and the pixel 111 in the i-th row and j-th column is electrically connected to the i-th wiring COM, and the pixel 111 in the i-th row j + 1 column is electrically connected to the i + 1-th wiring COM. But you can.

<< Wiring GL >>
In addition, the display device 100 includes m wirings GL. Each of the m wirings GL extends in the row direction. In addition, each of the m wirings GL is electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110. Note that in this specification and the like, the wiring GL in the first row is denoted as a wiring GL [1]. The wiring GL in the m-th row is denoted as wiring GL [m]. In addition, the i-th line GL is referred to as a line GL [i].

One end of the wiring GL is electrically connected to the scan line driver circuit 121. The scan line driver circuit 121 has a function of sequentially supplying a selection signal from the wiring GL [1] to the wiring GL [m]. In other words, the scan line driver circuit 121 has a function of sequentially scanning the wirings GL [1] to GL [m]. After scanning up to the wiring GL [m], scanning is performed again from the wiring GL [1] again.

The wiring GL has a function of transmitting a selection signal supplied from the scan line driver circuit 121 to the pixel 111. Note that in this specification and the like, the wiring GL may be referred to as a “gate line” or a “scan line”.

<< Wiring SL >>
In addition, the display device 100 includes n wirings SL. Each of the n wirings SL extends in the column direction (scanning direction). In addition, each of the n wirings SL is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110. In this specification and the like, the wiring SL in the first column is denoted as a wiring SL [1]. In addition, the wiring SL in the n-th column is denoted as a wiring SL [n]. In addition, the j-th line wiring GL is denoted as a wiring SL [j].

One end of the wiring SL is electrically connected to the signal line driver circuit 131, and the other end of the wiring SL is electrically connected to the signal line driver circuit 132. Therefore, the signal line driver circuit 131 and the signal line driver circuit 132 are provided at positions facing each other with the display portion 110 interposed therebetween. The wiring SL has a function of transmitting an image signal (also referred to as a “video signal”) supplied from the signal line driver circuit 131 and the signal line driver circuit 132 to the pixel 111. Note that in this specification and the like, the wiring SL may be referred to as a “source line” or a “signal line”.

By simultaneously supplying image signals from the signal line driver circuit 131 and the signal line driver circuit 132 to the same wiring SL, the supply capability of the image signals to the wiring SL can be increased. Thereby, the charge / discharge time of the wiring SL can be shortened. Therefore, even a display device with an extremely high resolution such as 4K or 8K can be operated using a transistor with low field-effect mobility. Further, it becomes easy to realize a large display device having a screen size of 50 inches diagonal or more, 60 inches diagonal or more, or 70 inches diagonal or more. Note that one of the signal line driver circuit 131 and the signal line driver circuit 132 may be omitted depending on the purpose or the like.

<< Wiring COM >>
In addition, the display device 100 includes m + 1 wirings COM. Each of the m + 1 wirings COM extends in the row direction. Therefore, the wiring COM extends substantially parallel to the wiring GL. Note that in this specification and the like, the first wiring COM is referred to as wiring COM [1]. In addition, the (m + 1) th wiring COM is denoted as a wiring COM [m + 1]. The i-th wiring COM is denoted as wiring COM [i]. One end of the wiring COM is electrically connected to the common line driving circuit 141. The common line driver circuit 141 has a function of supplying a common potential signal in order from the wiring COM [1] to the wiring COM [m + 1].

The common line driving circuit 141 and the scanning line driving circuit 121 are provided at positions facing each other across the display unit 110. The wiring COM has a function of transmitting a common potential signal supplied from the common line driver circuit 141 to the pixel 111. Note that in this specification and the like, the wiring COM may be referred to as a “common line”.

<< Connection of Pixel 111 and Wiring COM >>
Of the plurality of pixels 111 arranged in the first row, one of the odd-numbered or even-numbered pixels 111 is electrically connected to the first wiring COM. In addition, among the plurality of pixels 111 arranged in the first row, the other pixel 111 in the odd-numbered column or the even-numbered column is electrically connected to the second wiring COM. Of the plurality of pixels 111 arranged in the m-th row, one of the odd-numbered columns or even-numbered columns 111 is electrically connected to the m-th wiring COM. In addition, among the plurality of pixels 111 arranged in the m-th row, the other pixel 111 in the odd-numbered column or the even-numbered column is electrically connected to the (m + 1) th wiring COM.

In FIG. 1B, the i-th wiring COM includes the pixel 111 in the (i−1) th row and jth column, the pixel 111 in the (i−1) th row j + 2th column, the pixel 111 in the ith row j + 1th column, and the ith row j + 3th column. An example in which the eye pixel 111 is electrically connected is shown.

The connection relationship between the pixel 111 and the wiring COM will be described more specifically.

[Connection example 1]
The case where the odd-numbered wiring lines COM and the pixels 111 in the odd-numbered columns are connected and the even-numbered wiring lines COM and the pixels 111 in the even-numbered columns are connected will be described.

Of the plurality of pixels 111 arranged in the first row, the odd-numbered pixels 111 are electrically connected to the first wiring COM, and the even-numbered pixels 111 are electrically connected to the second wiring COM. . Of the plurality of pixels 111 arranged in the second row, the odd-numbered pixels 111 are electrically connected to the second wiring COM, and the even-numbered pixels 111 are electrically connected to the third wiring COM. Is done. Of the plurality of pixels 111 arranged in the m-th row, the odd-numbered columns 111 are electrically connected to the m-th wiring COM, and the even-numbered pixels 111 are electrically connected to the m + 1-th wiring COM. Is done.

That is, when x is an integer of 1 to m−1, the pixel 111 in the x-row odd column is electrically connected to the wiring GL in the x-th row, the wiring SL in the odd-numbered column, and the x-th wiring COM. Then, the pixel 111 in the x-th even column is electrically connected to the wiring GL in the x-th row, the wiring SL in the even-numbered column, and the x + 1-th wiring COM. The pixel 111 in the m-th row and odd-numbered column is electrically connected to the wiring GL in the m-th row, the wiring SL in the odd-numbered column, and the x-th wiring COM, and the pixel 111 in the m-th row and even-numbered column It is electrically connected to the wiring GL in the row, the wiring SL in the even-numbered column, and the m + 1th wiring COM.

If y is an integer greater than or equal to 0, the pixel 111 in the x-th row 2y + 1 column is electrically connected to the x-th wiring GL, the 2y + 1-th column wiring SL, and the x-th wiring COM, and the x-th row The pixel 111 in the 2y + 2 column is electrically connected to the wiring GL in the x-th row, the wiring SL in the 2y + 2 column, and the x + 1-th wiring COM. The pixel 111 in the m-th row 2y + 1 column is electrically connected to the m-th line wiring GL, the 2y + 1-th line wiring SL, and the m-th wiring COM, and the m-th row 2y + second-column pixel 111 is m It is electrically connected to the wiring GL in the row, the wiring SL in the 2y + 2 column, and the m + 1th wiring COM.

[Connection example 2]
A case will be described in which the odd-numbered wiring lines COM and the pixels 111 in the even-numbered columns are connected, and the even-numbered wiring lines COM and the pixels 111 in the odd-numbered columns are connected.

Of the plurality of pixels 111 arranged in the first row, the even-numbered pixels 111 are electrically connected to the first wiring COM, and the odd-numbered pixels 111 are electrically connected to the second wiring COM. . In addition, among the plurality of pixels 111 arranged in the second row, the pixels 111 in the even columns are electrically connected to the second wiring COM, and the pixels 111 in the odd columns are electrically connected to the third wiring COM. Is done. Of the plurality of pixels 111 arranged in the m-th row, the even-numbered pixels 111 are electrically connected to the m-th wiring COM, and the odd-numbered pixels 111 are electrically connected to the m + 1-th wiring COM. Is done.

That is, when x is an integer of 1 to m−1, the pixel 111 in the x-th even column is electrically connected to the x-th line wiring GL, the even-numbered line wiring SL, and the x-th line COM. Then, the pixels 111 in the x-th row and odd-numbered columns are electrically connected to the wiring GL in the x-th row, the wiring SL in the odd-numbered column, and the x + 1-th wiring COM. The pixels 111 in the m-th even column are electrically connected to the wiring GL in the m-th row, the wiring SL in the even-numbered column, and the x-th wiring COM, and the pixel 111 in the m-th odd column is m It is electrically connected to the wiring GL in the row, the wiring SL in the odd-numbered column, and the (m + 1) th wiring COM.

If y is an integer greater than or equal to 0, the pixel 111 in the x row 2y + 2 column is electrically connected to the wiring GL in the x row, the wiring SL in the 2y + 2 column, and the x th wiring COM, and the x row The pixel 111 in the 2y + 1 column is electrically connected to the wiring GL in the x-th row, the wiring SL in the 2y + 1 column, and the x + 1-th wiring COM. The pixel 111 in the m-th row 2y + 2 column is electrically connected to the m-th wiring GL, the 2y + 2-th column wiring SL, and the m-th wiring COM. It is electrically connected to the wiring GL in the row, the wiring SL in the 2y + 1th column, and the m + 1th wiring COM.

<< Configuration Example of Pixel 111 >>
FIG. 2 shows a circuit configuration example that can be used for the pixel 111. The pixel 111 includes a pixel circuit 534 and a display element 462.

[Display element]
Various display elements can be used for the display element 462. Examples of display elements include EL (electroluminescence) elements (organic EL elements, inorganic EL elements, or EL elements including organic and inorganic substances), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (Transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, GLV (grating light valve), display device using MEMS (micro electro mechanical system), DMD (digital Micromirror device), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interferometric modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electrowetting Child, piezoceramic display, display using carbon nanotubes, etc., by electrical or magnetic action, those having contrast, brightness, reflectance, a display medium such as transmittance changes. Further, quantum dots may be used as the display element.

Note that an example of a display device using an EL element as the display element 462 is an EL display. As an example of a display device using an electron-emitting device, there is an FED (Field Emission Display) or an SED type flat display (SED: Surface-conduction Electron-emitter Display). An example of a display device using quantum dots is a quantum dot display. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper. The display device may be a PDP (plasma display panel). The display device may be a retinal scanning type projection device. Moreover, the display apparatus using micro LED may be sufficient.

The liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, and / or an oblique electric field). When a liquid crystal element is used as the display element 462, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

As the liquid crystal material, either a positive type liquid crystal or a negative type liquid crystal may be used, and an optimal liquid crystal material may be used according to an applied mode or design.

In order to control the alignment of the liquid crystal, an alignment film can be provided. Note that when a horizontal electric field method is employed, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic. In addition, a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . Therefore, the productivity of the liquid crystal display device can be improved.

Note that by using a liquid crystal material that operates in a guest-host mode for the liquid crystal element, functional members such as a light diffusion layer and a polarizing plate can be omitted. Thus, productivity of the display device can be increased. Further, by not providing a functional member such as a polarizing plate, it is possible to increase the reflection brightness, the amount of transmitted light, and the like of the display element 462 of the display unit 110. Therefore, the visibility of the display device can be increased.

In addition, the reflective liquid crystal display device using a circularly polarizing plate is switched between the on state and the off state (switching between the bright state and the dark state) by aligning the major axis of the liquid crystal molecules in a direction substantially perpendicular to the substrate, It is done by aligning in a substantially horizontal direction. In general, a liquid crystal element that operates in a lateral electric field mode such as an IPS (In-Plane-Switching) mode has a major axis of liquid crystal molecules aligned in a substantially horizontal direction with respect to a substrate in both an on state and an off state. Difficult to use in equipment.

A liquid crystal element that operates in the VA-IPS mode operates in a lateral electric field mode, and switches between an on state and an off state so that the major axis of the liquid crystal molecules is aligned in a direction substantially perpendicular to the substrate, or is substantially horizontal to the substrate. It is done by aligning the direction. Therefore, when a liquid crystal element that operates in a horizontal electric field mode is used for a reflective liquid crystal display device, it is preferable to use a liquid crystal element that operates in a VA-IPS (Vertical Alignment In-Plane-Switching) mode.

Further, a method called multi-domain or multi-domain design, which is devised to divide the pixel 111 into several regions and tilt the molecules in different directions, can be used.

The specific resistance of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹¹ Ω · cm or more, and more preferably 1 × 10 ¹² Ω · cm or more. In addition, the value of the specific resistance in this specification shall be the value measured at 20 degreeC.

Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

In addition, when using LED, you may arrange | position graphene or graphite under the electrode and nitride semiconductor of LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor, for example, an n-type GaN semiconductor layer having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor layer having a crystal or the like can be provided thereon to form an LED. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having a crystal. Note that the GaN semiconductor layer of the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED can be formed by a sputtering method.

[Pixel circuit]
[Example of pixel circuit for liquid crystal display device]
A pixel circuit 534 illustrated in FIG. 2A includes a transistor 461 and a capacitor 463. In addition, the pixel circuit 534 illustrated in FIG. 2A is electrically connected to a liquid crystal element that can function as the display element 462.

One potential of the pair of electrodes of the display element 462 is appropriately set in accordance with the specification of the pixel circuit 534. For example, a common potential (common potential) may be applied to one of the pair of electrodes of the display element 462, or the potential may be the same as that of a capacitor line CL which will be described later. Further, a different potential may be applied to one of the pair of electrodes of the display element 462 for each pixel 532. The other of the pair of electrodes of the display element 462 is electrically connected to the node 466. The orientation state of the display element 462 is set by data written to the node 466.

As a driving method of the liquid crystal element, for example, a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, a VA (Vertical Alignment Aligned Coaxial) mode, an ASM (Axially Symmetrical Bounded Micro mode). , FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA (Multi Vertical Domain) mode, PVA (Patterned Vertical Alignment) mode S mode, FFS (Fringe Field Switching) mode, VA-IPS mode or TBA the like may be used (Transverse Bend Alignment) mode. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal mode), and other driving methods for liquid crystal elements. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In the pixel circuit 534 in the i-th row and j-th column, one of a source and a drain of the transistor 461 is electrically connected to the wiring SL [j], and the other is electrically connected to the node 466. A gate of the transistor 461 is electrically connected to the wiring GL [i]. A video signal is supplied from the wiring SL [j]. The transistor 461 has a function of controlling writing of a video signal to the node 466.

One of the pair of electrodes of the capacitor 463 is electrically connected to the wiring COM [i + 1], and the other is electrically connected to the node 466. The capacitor 463 has a function as a storage capacitor that stores data written to the node 466.

For example, in the display device 100 including the pixel circuit 534 in FIG. 2A, the scan line driver circuit 121 sequentially selects the pixel circuits 534 in each row, turns on the transistors 461, and writes a video signal to the node 466.

The pixel circuit 534 in which the video signal is written to the node 466 enters the holding state when the transistor 461 is turned off. By sequentially performing this for each row, an image can be displayed on the display unit 110.

In the pixel circuit 534 in the i-th row and j + 1-th column, one of a source and a drain of the transistor 461 is electrically connected to the wiring SL [j + 1], and the other is electrically connected to the node 466. A gate of the transistor 461 is electrically connected to the wiring GL [i]. A video signal is supplied from the wiring SL [j + 1]. The transistor 461 has a function of controlling writing of a video signal to the node 466.

In the pixel circuit 534 in the i-th row j + 1-th column, one of the pair of electrodes of the capacitor 463 is electrically connected to the wiring COM [i], and the other is electrically connected to the node 466. The capacitor 463 has a function as a storage capacitor that stores data written to the node 466.

In addition, as illustrated in FIG. 2B, a transistor having a back gate may be used as the transistor 461. A gate of the transistor 461 illustrated in FIG. 2B is electrically connected to the back gate. Therefore, the gate and the back gate are always at the same potential.

The pixel 111 can function as a subpixel. As shown in FIG. 2C, full color display can be realized by combining at least three pixels 111 to function as one pixel 112. Each of the three pixels 111 controls the transmittance, reflectance, light emission amount, etc. of red light (R), green light (G), or blue light (B). Note that the color of light controlled by the three pixels 111 is not limited to a combination of red, green, and blue, and may be yellow (Y), cyan (C), and magenta (M).

Further, as shown in FIG. 2D, a pixel 111 that controls white light (W) is added to a pixel that controls red light, green light, and blue light, and the four pixels 111 are combined into one pixel. 112 may function. The luminance of the display image can be increased by adding the pixel 111 that controls white light.

Further, a pixel 111 that controls yellow light (Y) may be provided instead of the pixel 111 that controls white light (W). Alternatively, the pixels 111 that control yellow (Y), cyan (C), magenta (M), and white (W) light may be combined.

Further, by increasing the number of pixels 111 that function as one pixel 112 and using an appropriate combination of red, green, blue, yellow, cyan, and magenta, a richer halftone expression can be realized.

In addition, color gamuts of various standards can be reproduced by combining pixels 111 that control light of different colors. For example, PAL (Phase Alternating Line) standard and NTSC (National Television System Committee) standard used in TV broadcasting, sRGB (standard RGB) widely used in electronic devices such as personal computers, digital cameras, and printers And ITU-R BT. Used in the Adobe RGB standard and HDTV (also known as High Definition Television). 709 (International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709) Standard, DCI-P3 (DigitalCineMitiTitiHit3P) R BT. A color gamut such as 2020 (REC. 2020 (Recommendation 2020)) standard can be reproduced.

When the pixels 112 are arranged in a 1920 × 1080 matrix, the display device 100 that can display at a resolution of so-called full high-definition (also referred to as “2K resolution”, “2K1K”, or “2K”) can be realized. it can. Further, for example, when the pixels 112 are arranged in a 3840 × 2160 matrix, the display device 100 that can display at a resolution of so-called ultra high vision (also referred to as “4K resolution”, “4K2K”, or “4K”) is provided. Can be realized. For example, when the pixels 112 are arranged in a matrix of 7680 × 4320, the display device 100 that can display at a resolution of so-called super high vision (also referred to as “8K resolution”, “8K4K”, or “8K”) is provided. Can be realized. By increasing the number of pixels 112, it is possible to realize the display device 100 that can display at a resolution of 16K or 32K.

<Modification>
A modification of the display device 100 will be described with reference to the drawings. In order to reduce the repetition of the description, portions different from the display device 100 will be mainly described.

<< Modification 1 >>
FIG. 3A is a block diagram for describing a configuration example of the display device 100A. The display device 100 A includes a scanning line driving circuit 122 at a position facing the scanning line driving circuit 121 with the display unit 110 interposed therebetween. One end of the wiring GL is electrically connected to the scan line driver circuit 121, and the other end of the wiring GL is electrically connected to the scan line driver circuit 122. The scan line driver circuit 122 has a function similar to that of the scan line driver circuit 121. By simultaneously supplying selection signals to the same wiring GL from the scanning line driving circuit 121 and the scanning line driving circuit 122, the supply capability of the selection signal to the wiring GL can be increased.

3A, the scan line driver circuit 122 is provided between the display portion 110 and the common line driver circuit 141; however, the common line driver circuit 141 is provided between the display portion 110 and the scan line driver circuit 122. It may be provided. Further, the common line driver circuit 141 may have the function of the scanning line driver circuit 122. Further, the scan line driver circuit 122 may have the function of the common line driver circuit 141.

<< Modification 2 >>
FIG. 3B is a block diagram for describing a configuration example of the display device 100B. In addition to the configuration of the display device A, the display device 100B includes a common line drive circuit 142 at a position facing the common line drive circuit 141 with the display unit 110 interposed therebetween. In addition, one end of the wiring COM is electrically connected to the common line driving circuit 141, and the other end of the wiring COM is electrically connected to the common line driving circuit 142. The common line drive circuit 142 has the same function as the common line drive circuit 141. By supplying a common potential signal to the same wiring COM from the common line driving circuit 141 and the common line driving circuit 142 at the same time, the common potential signal supply capability to the wiring COM can be increased.

3B, the scan line driver circuit 121 is provided between the display portion 110 and the common line drive circuit 142; however, the common line drive circuit 142 is provided between the display portion 110 and the scan line drive circuit 121. It may be provided. Further, the common line driver circuit 142 may have the function of the scan line driver circuit 121. Further, the scan line driver circuit 121 may have the function of the common line driver circuit 142.

<< Modification 3 >>
FIG. 4A is a block diagram for describing a configuration example of the display device 100C. The display device 100C has a configuration in which the display unit 110 is vertically divided. In FIG. 4A, the upper side (upstream side in the scanning direction) of the display unit 110 is shown as a display unit 110a, and the lower side (downstream side in the scanning direction) of the display unit 110 is shown as a display unit 110b.

The display device 100C includes n wirings SLa and n wirings SLb. Each of the n wirings SLa extends in the scanning direction (column direction) and is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110a. Each of the n wirings SLb extends in the scanning direction (column direction) and is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110b. The wiring SLa and the wiring SLb have the same function and structure as the wiring SL. That is, the display device 100C has a structure in which the wiring SL is divided into the wiring SLa and the wiring SLb.

The upstream line GL in the scanning direction and the upstream line COM in the scanning direction are electrically connected to the display unit 110a. The downstream wiring GL in the scanning direction and the downstream wiring COM in the scanning direction are electrically connected to the display unit 110b.

In FIG. 4A, the wiring SLa electrically connected to the pixel 111 in the first column in the display portion 110a is illustrated as a wiring SLa [1]. A wiring SLa electrically connected to the pixel 111 in the j-th column is denoted as a wiring SLa [j]. A wiring SLa electrically connected to the pixel 111 in the n-th column is denoted as a wiring SLa [n].

In addition, the wiring SLb electrically connected to the pixel 111 in the first column in the display portion 110b is denoted as a wiring SLb [1]. A wiring SLb electrically connected to the pixel 111 in the j-th column is denoted as a wiring SLb [j]. A wiring SLb electrically connected to the pixel 111 in the n-th column is denoted as a wiring SLb [n]. One end of the wiring SLa is electrically connected to the signal line driver circuit 131, and one end of the wiring SLb is electrically connected to the signal line driver circuit 132.

By dividing the wiring SL into the wiring SLa and the wiring SLb, the wiring resistance and parasitic capacitance per wiring can be halved. Therefore, the influence (time constant) on the delay and rounding of the video signal can be reduced to ¼. That is, the display quality of the display device can be improved. In addition, since the time for writing the video signal to the pixel 111 can be shortened, the frame frequency can be increased. In addition, since the output load of the signal line driver circuit is reduced, the reliability of the display device can be increased.

<< Modification 4 >>
FIG. 4B is a block diagram for describing a configuration example of the display device 100D. The display device 100D has a configuration obtained by modifying the display device 100C. The display device 100D includes a scanning line driving circuit 121a, a scanning line driving circuit 121b, a common line driving circuit 141a, and a common line driving circuit 141b. The scan line driver circuit 121 a and the scan line driver circuit 121 b have the same functions as the scan line driver circuit 121. The common line drive circuit 141a and the common line drive circuit 141b have the same functions as the common line drive circuit 141.

The display device 100D includes m wirings GLa, m wirings GLb, m + 1 wirings COMa, and m + 1 wirings COMb. The wiring GLa and the wiring GLb have the same function and structure as the wiring GL. The wiring COMa and the wiring COMb have the same function and structure as the wiring COM.

Each of the m wirings GLa extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display portion 110a. One end of the wiring GLa is electrically connected to the scan line driver circuit 121a. In the display portion 110a, the wiring GLa electrically connected to the pixel 111 in the first row is denoted as wiring GLa [1], and the wiring GLa electrically connected to the pixel 111 in the mth row is denoted as wiring GLa [m]. Yes. The scan line driver circuit 121a has a function of sequentially supplying a selection signal from the wiring GLa [1] to the wiring GLa [m].

Each of the m wirings GLb extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display portion 110b. One end of the wiring GLb is electrically connected to the scan line driver circuit 121b. In the display portion 110b, the wiring GLb electrically connected to the pixel 111 in the first row is denoted as a wiring GLb [1], and the wiring GLb electrically connected to the pixel 111 in the m-th row is denoted as a wiring GLb [m]. Yes. The scan line driver circuit 121b has a function of sequentially supplying a selection signal from the wiring GLb [1] to the wiring GLb [m].

Each of the m + 1 wirings COMa extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display portion 110a. One end of the wiring COMa is electrically connected to the common line driving circuit 141a. In the display portion 110a, the first wiring COMa is denoted as wiring COMa [1], and the (m + 1) th wiring COMa is denoted as wiring COMa [m + 1]. The common line driver circuit 141a has a function of sequentially supplying a selection signal from the wiring COMa [1] to the wiring COMa [m + 1].

Each of the m + 1 wirings COMb extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110b. One end of the wiring COMb is electrically connected to the common line driving circuit 141b. In the display portion 110b, the first wiring COMb is denoted as wiring COMb [1], and the (m + 1) th wiring COMb is denoted as wiring COMb [m + 1]. The common line driver circuit 141b has a function of sequentially supplying a selection signal from the wiring COMb [1] to the wiring COMb [m + 1].

The display portion 110a and the common line drive circuit 141a are provided for the display portion 110a, and the scan line drive circuit 121b and the common line drive circuit 141b are provided for the display portion 110b, whereby the display portion 110a and the display portion 110b are provided. It can be operated independently. In addition, since video signals can be simultaneously written into the pixel 111 included in the display portion 110a and the pixel 111 included in the display portion 110b, the frame frequency of the entire display portion 110 can be increased.

<< Modification 5 >>
FIG. 5A is a block diagram for describing a configuration example of the display device 100E. The display device 100E has a configuration obtained by modifying the display device 100B. The display device 100E has a configuration in which the display unit 110 is divided into left and right. In FIG. 5A, the left side (scanning line driver circuit 121 side) of the display portion 110 is indicated as a display portion 110a, and the right side of the display portion 110 (scanning line driver circuit 122 side) is indicated as a display portion 110b.

The display device 100E includes m wirings GLa, m wirings GLb, m + 1 wirings COMa, and m + 1 wirings COMb.

Each of the m wirings GLa extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display portion 110a. One end of the wiring GLa is electrically connected to the scan line driver circuit 121. The scan line driver circuit 121 has a function of sequentially supplying a selection signal from the wiring GLa [1] to the wiring GLa [m].

Each of the m wirings GLb extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display portion 110b. One end of the wiring GLb is electrically connected to the scan line driver circuit 122. The scan line driver circuit 122 has a function of sequentially supplying a selection signal from the wiring GLb [1] to the wiring GLb [m].

Each of the m + 1 wirings COMa extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display portion 110a. One end of the wiring COMa is electrically connected to the common line driving circuit 142. The common line driver circuit 142 has a function of sequentially supplying a selection signal from the wiring COMa [1] to the wiring COMa [m + 1].

Each of the m + 1 wirings COMb extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110b. One end of the wiring COMb is electrically connected to the common line driving circuit 141. The common line driver circuit 141 has a function of sequentially supplying a selection signal from the wiring COMb [1] to the wiring COMb [m + 1].

The wiring GLa and the wiring GLb have the same function and structure as the wiring GL. That is, the display device 100E has a configuration in which the wiring GL is divided into the wiring GLa and the wiring GLb.

The wiring COMa and the wiring COMb have the same function and structure as the wiring COM. That is, the display device 100E has a configuration in which the wiring COM is divided into the wiring COMa and the wiring COMb.

By dividing the wiring GL into the wiring GLa and the wiring GLb, the wiring resistance and the parasitic capacitance per wiring can be halved. By dividing the wiring COM into the wiring COMa and the wiring COMb, the wiring resistance and parasitic capacitance per wiring can be halved. Therefore, the influence (time constant) on signal delay and rounding can be reduced to ¼. That is, the display quality of the display device can be improved. In addition, the frame frequency can be increased. In addition, since the output load of the scan line driver circuit and the common line driver circuit is reduced, the reliability of the display device can be increased.

<< Modification 6 >>
FIG. 5B is a block diagram for describing a configuration example of the display device 100F. The display device 100F has a configuration obtained by modifying the display device 100E.

The display device 100F includes a signal line driver circuit 131a, a signal line driver circuit 131b, a signal line driver circuit 132a, and a signal line driver circuit 132b. The signal line driver circuit 131a and the signal line driver circuit 131b have the same functions as the signal line driver circuit 131. The signal line driver circuit 132 a and the signal line driver circuit 132 b have the same functions as the signal line driver circuit 132.

The display device 100F includes n wirings SLa and n wirings SLb. Each of the n wirings SLa extends in the scanning direction (column direction) and is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110a. In addition, one end of the wiring SLa is electrically connected to the signal line driver circuit 131a, and the other end is electrically connected to the signal line driver circuit 132a.

Each of the n wirings SLb extends in the scanning direction (column direction) and is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110b. One end of the wiring SLb is electrically connected to the signal line driver circuit 131b, and the other end is electrically connected to the signal line driver circuit 132b. The wiring SLa and the wiring SLb have the same function and structure as the wiring SL.

The signal line driver circuit 131a and the signal line driver circuit 132a are provided for the display portion 110a, and the signal line driver circuit 131b and the signal line driver circuit 132b are provided for the display portion 110b, whereby the display portion 110a and the display portion 110b are provided. It can be operated independently. In addition, since video signals can be simultaneously written into the pixel 111 included in the display portion 110a and the pixel 111 included in the display portion 110b, the frame frequency of the entire display portion 110 can be increased.

<< Modification 7 >>
FIG. 6A is a block diagram for describing a configuration example of the display device 100G. The display device 100G has a configuration obtained by modifying the display device 100F. The display device 100G includes a display unit 110a, a display unit 110b, a display unit 110c, and a display unit 110d. The display device 100G has a structure in which the display unit 110a and the display unit 110b in the display device 100F are vertically divided into two.

The upstream wiring GLa in the scanning direction and the upstream wiring COMa in the scanning direction are electrically connected to the plurality of pixels 111 arranged in the row direction in the display portion 110a. The wiring GLa on the downstream side in the scanning direction and the wiring COMa on the downstream side in the scanning direction are electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110c. The upstream wiring GLb in the scanning direction and the upstream wiring COMb in the scanning direction are electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110b. The downstream wiring GLb in the scanning direction and the downstream wiring COMb in the scanning direction are electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110d.

The display device 100G includes n wirings SLa, n wirings SLb, n wirings SLc, and n wirings SLd. The wiring SLa, the wiring SLb, the wiring SLc, and the wiring SLd have functions and structures similar to those of the wiring SL. That is, the display device 100G has a structure in which the wiring SL is divided into the wiring SLa and the wiring SLc. In addition, the display device 100G has a structure in which the wiring SL is divided into a wiring SLb and a wiring SLd.

Each of the n wirings SLa extends in the scanning direction (column direction) and is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110a. Each of the n wirings SLb extends in the scanning direction (column direction) and is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110b. Each of the n wirings SLc extends in the scanning direction (column direction) and is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110c. Each of the n wirings SLd extends in the scanning direction (column direction) and is electrically connected to the plurality of pixels 111 arranged in the column direction in the display portion 110d.

One end of the wiring SLa is electrically connected to the signal line driver circuit 131a. One end of the wiring SLb is electrically connected to the signal line driver circuit 131b. One end of the wiring SLc is electrically connected to the signal line driver circuit 132a. One end of the wiring SLd is electrically connected to the signal line driver circuit 132b.

By dividing the wiring SL into the wiring SLa and the wiring SLc, the wiring resistance and parasitic capacitance per wiring can be halved. Further, by dividing the wiring SL into the wiring SLb and the wiring SLd, the wiring resistance and parasitic capacitance per wiring can be halved. Therefore, the influence (time constant) on the delay and rounding of the video signal can be reduced to ¼. That is, the display quality of the display device can be improved. In addition, since the time for writing the video signal to the pixel 111 can be shortened, the frame frequency can be increased. In addition, since the output load of the signal line driver circuit is reduced, the reliability of the display device can be increased.

<< Modification 8 >>
FIG. 6B is a block diagram for describing a configuration example of the display device 100H. The display device 100H has a configuration obtained by modifying the display device 100G.

The display device 100H includes a scan line driver circuit 121a, a scan line driver circuit 121b, a scan line driver circuit 122a, a scan line driver circuit 122b, a common line driver circuit 141a, a common line driver circuit 141b, a common line driver circuit 142a, and a common line. A driving circuit 142b is included. The scan line driver circuit 121 a and the scan line driver circuit 121 b have the same functions as the scan line driver circuit 121. The scan line driver circuit 122 a and the scan line driver circuit 122 b have the same functions as the scan line driver circuit 122. The common line drive circuit 141a and the common line drive circuit 141b have the same functions as the common line drive circuit 141. The common line drive circuit 142 a and the common line drive circuit 142 b have the same functions as the common line drive circuit 142.

Further, the display device 100H includes m wirings GLa, m wirings GLb, m wirings GLc, m wirings GLd, m + 1 wirings COMa, m + 1 wirings COMb, m + 1 wirings COMc, and It has m + 1 wirings COMd. The wiring GLa, the wiring GLb, the wiring GLc, and the wiring GLd have the same function and structure as the wiring GL. The wiring COMa and the wiring COMb have the same function and structure as the wiring COM.

Each of the m wirings GLa and the m + 1 wirings COMa extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display portion 110a. One end of the wiring GLa is electrically connected to the scan line driver circuit 121a. One end of the wiring COMa is electrically connected to the common line driving circuit 142a.

Each of the m wirings GLb and the m + 1 wirings COMb extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110b. One end of the wiring GLb is electrically connected to the scan line driver circuit 122a. One end of the wiring COMb is electrically connected to the common line driving circuit 141a.

Each of the m wirings GLc and the m + 1 wirings COMc extends in the row direction, and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110c. One end of the wiring GLc is electrically connected to the scan line driver circuit 121b. One end of the wiring COMc is electrically connected to the common line driving circuit 142b.

Each of the m wirings GLd and the m + 1 wirings COMd extends in the row direction and is electrically connected to the plurality of pixels 111 arranged in the row direction in the display unit 110d. One end of the wiring GLd is electrically connected to the scan line driver circuit 122b. One end of the wiring COMd is electrically connected to the common line driving circuit 141b.

A scanning line driving circuit 121a and a common line driving circuit 142a are provided for the display portion 110a, a scanning line driving circuit 122a and a common line driving circuit 141a are provided for the display portion 110b, and a scanning line driving circuit is provided for the display portion 110c. 121b and a common line driving circuit 142b are provided, and a scanning line driving circuit 122b and a common line driving circuit 141b are provided for the display portion 110d, whereby the display portion 110a, the display portion 110b, the display portion 110c, and the display portion 110d are provided. Can be operated independently. In addition, since video signals can be simultaneously written in the pixels 111 included in the display portion 110a, the display portion 110b, the display portion 110c, and the display portion 110d, the frame frequency of the entire display portion 110 can be increased.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a method for driving the display device 100 will be described with reference to drawings. As an example, a driving method example of a liquid crystal display device using a liquid crystal element as a display element will be described.

<Driving method example>
First, a general driving method example of a liquid crystal display device will be described.

《Example of general driving method》
[Frame inversion drive method]
In general, a liquid crystal element tends to be deteriorated when a DC voltage is continuously applied. For this reason, in a display device using a liquid crystal element as a display element, a driving method (also referred to as a “frame inversion driving method”) that reverses the polarity applied to the liquid crystal element for each frame is used. For example, a positive potential signal is supplied to all pixels in an odd frame, and a negative potential signal is supplied to all pixels in an even frame. The polarity inversion is not limited to every frame, but may be performed every specific number of frames depending on the liquid crystal element used.

In addition, in the frame inversion driving method in which potentials of the same polarity are supplied to all pixels, phenomena such as flicker and crosstalk are likely to occur during image display, and the display quality of the display device may deteriorate. In order to suppress such a phenomenon, driving methods such as a source line inversion driving method, a gate line inversion driving method, and a dot inversion driving method have been devised.

[Source line inversion drive method]
The source line inversion driving method (also referred to as “column inversion driving method” or “column inversion driving method”) is a signal supplied to a pixel for each specific number of frames and each specific number of signal lines (source lines). This is a driving method for inverting the polarity.

[Gate line inversion drive method]
The gate line inversion driving method (also referred to as “row inversion driving method” or “row inversion driving method”) is a signal supplied to a pixel for each specific number of frames and each specific number of scanning lines (gate lines). This is a driving method for inverting the polarity.

[Dot inversion drive method]
The dot inversion driving method (also referred to as “row inversion driving method”, “row inversion driving method”, etc.) inverts the polarity of signals supplied to adjacent pixels in a specific number of frames and in the row and column directions. This is a driving method. The signal polarity inversion in the dot inversion driving method can be performed for each specific number of pixels. For example, the polarity of a signal supplied for each pixel may be inverted, or the polarity of a signal supplied for each of a plurality of pixels may be inverted.

The dot inversion driving method is more effective in suppressing phenomena such as flicker and crosstalk than the source line inversion driving method and the gate line inversion driving method. Therefore, the dot inversion driving method is often used as a driving method for the liquid crystal display device.

[Common inversion drive method]
The operation state of the liquid crystal element is a voltage V _LC that is a voltage difference between the voltage V _{SL of the} video signal written to the node 466 and the voltage supplied to the wiring COM (also referred to as “voltage V _COM ” or “common voltage”). Determined by. A driving method for keeping the voltage V _COM constant during a period in which an image is displayed on the display portion 110 is referred to as a “common DC driving method” (see FIG. 7A).

When writing voltage _{V SL,} by setting the voltage _{V COM} to the opposite polarity of the voltage _{V SL,} it is possible to reduce the amplitude of the voltage _{V SL} without changing the voltage _{V LC.} Therefore, the output load of the peripheral driver circuit is reduced, and the power consumption of the display device can be reduced. Such a driving method is generally called a “common inversion driving method” (see FIG. 7B).

The common inversion driving method can be combined with the above-described frame inversion driving method, source line inversion driving method, gate line inversion driving method, or dot inversion driving method.

In the display device 100 of one embodiment of the present invention, the common inversion driving method and the dot inversion driving method are used in combination.

<< Example of Driving Method of One Embodiment of the Present Invention >>
An example of a method for driving the display device 100 of one embodiment of the present invention is described. In this embodiment, a driving method is described in the case where the display device 100 includes the display portion 110 in which 20 pixels 111 are provided in a matrix of 4 rows and 5 columns.

FIG. 8 is a timing chart for explaining the driving method. In the present embodiment, a driving method example of the display device 100 will be described by illustrating the kth frame (k is an arbitrary natural number) and the (k + 1) th frame. One frame has four periods. In this embodiment, the four periods of the kth frame are denoted as periods T1 to T4. In addition, four periods included in the (k + 1) th frame are denoted as periods T5 to T8.

9 to 13 are diagrams illustrating the operation state of the display unit 110 for each period. When an H potential is supplied to the wiring GL, the pixels 111 in the first to fifth columns are selected in the row to which the wiring GL is connected, and a video signal is written to each pixel 111 through the wiring SL. When an L potential is supplied to the wiring GL, the pixels 111 in the first to fifth columns are not selected in the row to which the wiring GL is connected, and a video signal is not written.

9 to 13, “H” is attached to the wiring GL to which the H potential is supplied, and “L” is attached to the wiring GL to which the L potential is supplied. When there is a change in the potential supplied to the wiring GL, “H” or “L” is used as an enclosing character. Further, “+” is attached to the wiring COM to which the positive voltage is supplied, and “−” is attached to the wiring COM to which the negative voltage is supplied. When there is a change in the polarity of the voltage supplied to the wiring COM, “+” or “−” is enclosed.

In FIGS. 9 to 13, the pixel 111 to which the video signal is supplied is hatched. Further, “+” is added to the pixel 111 supplied with the positive video signal, and “−” is added to the pixel 111 supplied with the negative video signal.

As an initial state, it is assumed that a positive video signal is written to the odd-numbered and odd-numbered pixels 111 and a negative-polarity video signal is written to the even-numbered and even-numbered pixels 111 in the period T0. Further, it is assumed that the L potential is supplied to the wirings GL [1] to GL [3] and the H potential is supplied to the wiring GL [4]. Further, a positive voltage is supplied to the wiring COM [1] and the wiring COM [4], and a negative voltage is supplied to the wiring COM [2], the wiring COM [3], and the wiring COM [5]. Shall.

First, the rewriting operation of the pixel 111 in the kth frame will be described.

[Period T1]
In the period T1, the L potential is supplied to the wiring GL [4] and the H potential is supplied to the wiring GL [1] (see FIG. 9A). Then, the pixels 111 in the first row and first column to the first row and fifth column are selected, and a video signal is written to each pixel 111 through the wiring SL. In the period T1, a negative video signal is written to the pixels 111 in the first row and odd columns, and a positive video signal is written to the pixels 111 in the first row and even columns. Further, a positive voltage (common voltage) is supplied to the wiring COM [3].

The pixels 111 in the first row and odd columns are electrically connected to the wiring COM [1] to which a positive voltage is supplied, and the pixels 111 in the first row and even columns are connected to the wiring COM to which a negative voltage is supplied. [2] is electrically connected. A voltage having a polarity opposite to the polarity of the video signal written to the pixel 111 in the first row is supplied to the wiring COM [1] and the wiring COM [2]. Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T2]
In the period T2, the L potential is supplied to the wiring GL [1] and the H potential is supplied to the wiring GL [2] (see FIG. 9B). Then, the pixels 111 in the second row, first column to the second row, fifth column are selected, and a video signal is written to each pixel 111 through the wiring SL. In the period T2, a positive video signal is written to the pixels 111 in the second row and odd columns, and a negative video signal is written to the pixels 111 in the second row and even columns. Further, a negative voltage is supplied to the wiring COM [4].

The pixels 111 in the second row and odd columns are electrically connected to the wiring COM [2] to which a negative voltage is supplied, and the pixels 111 in the second row and even columns are connected to the wiring COM to which a positive voltage is supplied. [3] is electrically connected. A voltage having a polarity opposite to the polarity of the video signal written to the pixel 111 in the second row is supplied to the wiring COM [2] and the wiring COM [3]. Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T3]
In the period T3, the L potential is supplied to the wiring GL [2] and the H potential is supplied to the wiring GL [3] (see FIG. 10A). Then, the pixel 111 in the third row, first column to the second row, fifth column is selected, and a video signal is written to each pixel 111 through the wiring SL. In the period T3, a negative video signal is written to the pixels 111 in the third row and odd columns, and a positive video signal is written to the pixels 111 in the third row and even columns. Further, a positive voltage is supplied to the wiring COM [5], and a negative voltage is supplied to the wiring COM [1].

The pixels 111 in the third row and odd columns are electrically connected to the wiring COM [3] to which a positive voltage is supplied, and the pixels 111 in the third row and even columns are connected to the wiring COM to which a negative voltage is supplied. [4] is electrically connected. A voltage having a polarity opposite to the polarity of the video signal written to the pixel 111 in the third row is supplied to the wiring COM [3] and the wiring COM [4]. Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T4]
In the period T4, the L potential is supplied to the wiring GL [3] and the H potential is supplied to the wiring GL [4] (see FIG. 10B). Then, the pixels 111 in the 4th row, the 1st column to the 4th row, the 5th column are selected, and a video signal is written to each pixel 111 through the wiring SL. In the period T4, a positive video signal is written to the pixels 111 in the fourth row and odd columns, and a negative video signal is written to the pixels 111 in the fourth row and even columns. Further, a positive voltage is supplied to the wiring COM [2].

The pixels 111 in the 4th row and odd columns are electrically connected to the wiring COM [4] to which a negative voltage is supplied, and the pixels 111 in the 4th and even columns are connected to the wiring COM to which a positive voltage is supplied. [5] is electrically connected. A voltage having a polarity opposite to the polarity of the video signal written to the pixels 111 in the fourth row is supplied to the wiring COM [4] and the wiring COM [5]. Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

In this way, the rewriting operation of the pixel 111 in the k-th frame can be performed. Note that the polarity of the voltage supplied to the wiring COM [1] and the wiring COM [5] is reversed in the period T3. Note that inversion of the polarity of the voltage supplied to the wiring COM [1] may be performed in the period T4 instead of in the period T3 (see FIG. 13A).

Next, the rewriting operation of the pixel 111 in the (k + 1) th frame will be described.

[Period T5]
In the period T5, the L potential is supplied to the wiring GL [4] and the H potential is supplied to the wiring GL [1] (see FIG. 11A). Then, the pixels 111 in the first row and first column to the first row and fifth column are selected, and a video signal is written to each pixel 111 through the wiring SL. In the period T5, a positive video signal is written to the pixels 111 in the first row and odd columns, and a negative video signal is written to the pixels 111 in the first row and even columns. Further, a negative voltage is supplied to the wiring COM [3].

The pixels 111 in the first row and odd columns are electrically connected to the wiring COM [1] to which the negative voltage is supplied, and the pixels 111 in the first row and even columns are connected to the wiring COM to which the positive voltage is supplied. [2] is electrically connected. A voltage having a polarity opposite to the polarity of the video signal written to the pixel 111 in the first row is supplied to the wiring COM [1] and the wiring COM [2]. Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T6]
In the period T6, the L potential is supplied to the wiring GL [1] and the H potential is supplied to the wiring GL [2] (see FIG. 11B). Then, the pixels 111 in the second row, first column to the second row, fifth column are selected, and a video signal is written to each pixel 111 through the wiring SL. In the period T 6, a negative video signal is written to the pixels 111 in the second row and odd columns, and a positive video signal is written to the pixels 111 in the second row and even columns. Further, a positive voltage is supplied to the wiring COM [4].

The pixels 111 in the second row and odd columns are electrically connected to the wiring COM [2] to which a positive voltage is supplied, and the pixels 111 in the second row and even columns are connected to the wiring COM to which a negative voltage is supplied. [3] is electrically connected. A voltage having a polarity opposite to the polarity of the video signal written to the pixel 111 in the second row is supplied to the wiring COM [2] and the wiring COM [3]. Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T7]
In the period T7, the L potential is supplied to the wiring GL [2] and the H potential is supplied to the wiring GL [3] (see FIG. 12A). Then, the pixel 111 in the third row, first column to the second row, fifth column is selected, and a video signal is written to each pixel 111 through the wiring SL. In the period T7, a positive video signal is written to the pixels 111 in the third row and odd columns, and a negative video signal is written to the pixels 111 in the third row and even columns. Further, a negative voltage is supplied to the wiring COM [5], and a positive voltage is supplied to the wiring COM [1].

The pixels 111 in the third row and odd columns are electrically connected to the wiring COM [3] to which the negative voltage is supplied, and the pixels 111 in the third row and even columns are connected to the wiring COM to which the positive voltage is supplied. [4] is electrically connected. A voltage having a polarity opposite to the polarity of the video signal written to the pixel 111 in the third row is supplied to the wiring COM [3] and the wiring COM [4]. Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T8]
In the period T8, the L potential is supplied to the wiring GL [3] and the H potential is supplied to the wiring GL [4] (see FIG. 12B). Then, the pixels 111 in the 4th row, the 1st column to the 4th row, the 5th column are selected, and a video signal is written to each pixel 111 through the wiring SL. In the period T8, a negative video signal is written to the pixels 111 in the fourth row and odd columns, and a positive video signal is written to the pixels 111 in the fourth row and even columns. Further, a negative voltage is supplied to the wiring COM [2].

The pixels 111 in the fourth row and odd columns are electrically connected to the wiring COM [4] to which a positive voltage is supplied, and the pixels 111 in the fourth row and even columns are connected to the wiring COM to which a negative voltage is supplied. [5] is electrically connected. A voltage having a polarity opposite to the polarity of the video signal written to the pixels 111 in the fourth row is supplied to the wiring COM [4] and the wiring COM [5]. Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

In this way, the rewriting operation of the pixel 111 in the (k + 1) th frame can be performed. Note that the polarity of the voltage supplied to the wiring COM [1] and the wiring COM [5] is reversed in the period T7. Note that inversion of the polarity of the voltage supplied to the wiring COM [1] may be performed in the period T8 instead of in the period T7 (see FIG. 13B).

By reversing the polarity of the voltage supplied to the wiring COM connected to the row before rewriting the video signal of a certain row, accurate rewriting of the video signal can be realized.

In other words, accurate video can be obtained by inverting the polarity of the voltage supplied to the (p + 2) -th wiring COM during the period when the p-th row (p is an integer between 1 and m−1) is selected. Signal rewriting can be realized. The polarity of the voltage supplied to the first wiring COM is inverted during the period when the (m-1) th row or the mth row is selected. Further, the reversal of the polarity of the voltage supplied to the second wiring COM is performed during the period when the m-th row is selected.

According to one embodiment of the present invention, polarity inversion of the common voltage is performed for each row, so that common voltage writing shortage (insufficient shortage) hardly occurs.

Further, according to one embodiment of the present invention, the output load of the peripheral driver circuit can be reduced; thus, power consumption of the display device can be reduced. Alternatively, good display quality can be realized even in a display device with 8K resolution or higher. Alternatively, a good display quality can be realized even in a display device having a screen size of 60 inches diagonal or more and further 120 inches diagonal or more. Alternatively, a display device that can operate at high speed can be realized. For example, good display quality can be realized even when the frame frequency of the display device is 120 Hz or more, or 240 Hz or more.

(Embodiment 3)
In this embodiment, a display device 200 including a plurality of source lines per pixel column is described with reference to drawings. The display device 200 has many parts in common with the display device 100. In order to reduce repetition of the description, other embodiments and the like are referred to for matters not described in this embodiment and items common to the display device 100, and detailed description in this embodiment is omitted.

<Configuration example>
FIG. 14A is a block diagram for explaining a configuration example of the display device 200. FIG. 14B is a block diagram illustrating part of the display portion 210. Similar to the display unit 110, the display unit 210 includes a plurality of pixels 111. 14A and 14B, a display device having two source lines per pixel column is shown as the display device 200. FIG.

The display unit 210 includes a plurality of pixels 111 arranged in a matrix of m rows and n columns. The display device 200 includes two lines SL (source lines) per pixel column. Therefore, the display device 200 includes 2 × n lines SL. Note that three or more wirings SL may be provided per column of pixels. When g wirings SL (g is an integer of 2 or more) are provided per pixel column, g × n wirings SL are connected to the signal line driver circuit 131 and the signal line driver circuit 132.

In this embodiment mode, two wirings SL corresponding to the pixels in the first column are denoted as wirings SL ₁ [1] and wirings SL ₂ [1], respectively. In addition, the two wirings SL corresponding to the pixels in the j-th column are denoted as a wiring SL ₁ [j] or a wiring SL ₂ [j], respectively. In addition, the two wirings SL corresponding to the pixels in the n-th column are denoted as a wiring SL ₁ [n] or a wiring SL ₂ [n], respectively. Note that different signals can be supplied to the different wirings SL. For example, different signals can be supplied to the wiring SL ₁ (j) and the wiring SL ₂ (j).

Display device 200 has a n wirings SL ₁ and n wirings SL _2. Note that in this specification and the like, the wiring SL ₁ may be referred to as "first wiring SL" or "first video signal line". Further, the wiring SL ₂ may be referred to as "second line SL" or the "second video signal line". Therefore, it can be said that the display device 200 has n first video signal lines and n second video signal lines.

The wiring SL ₁ [j] is electrically connected to one of an odd-numbered row pixel and an even-numbered row pixel. The wiring SL ₂ [j] is electrically connected to the other of the pixels in the odd rows or the pixels in the even rows. FIG. 14B illustrates a connection relationship between the pixel 111 and the wiring SL in the case where the i-row is an even-numbered row.

In FIG. 14B, the pixel 111 in the i-th row and j-th column is electrically connected to the i + 1-th wiring COM, and the pixel 111 in the i-th row j + 1 column is electrically connected to the i-th wiring COM. A block diagram of the configuration is shown. However, the configuration is not limited to this, and the pixel 111 in the i-th row and j-th column is electrically connected to the i-th wiring COM, and the pixel 111 in the i-th row j + 1 column is electrically connected to the i + 1-th wiring COM. But you can.

FIG. 15A and FIG. 15B are block diagrams of the display device 200. 15A and 15B are different in the connection configuration of the wiring GL. As described above, the display device 200 has two lines SL per pixel column. Therefore, a selection signal can be simultaneously supplied to two adjacent gate lines, and a video signal can be simultaneously written to the pixels 111 in two adjacent rows.

15 In (A), the scanning line driving circuit 121 has a plurality of wirings GL ₀ electrically connected. In this specification and the like, the e-th wiring GL _{0 is referred} to as a wiring GL ₀ [e]. e is an integer of 1 or more. In FIG. 15A, the wiring GL ₀ [e] is electrically connected to the two wirings GL (the wiring GL [i] and the wiring GL [i + 1]). Therefore, the same selection signal is given to these two wirings GL. The wiring GL ₀ also has a function as a gate line like the wiring GL.

By providing two source lines in one column of pixels and simultaneously supplying a selection signal to two corresponding gate lines, one horizontal period can be made longer than in the prior art. In the display device 200, the length of one horizontal period can be doubled that of the display device 100. Further, by providing three source lines in one pixel column and simultaneously supplying selection signals to the corresponding three gate lines, the length of one horizontal period can be tripled. Furthermore, since the number of pixels 111 electrically connected to one source line is reduced, the output load of the signal line driver circuit can be reduced.

Accordingly, even a display device with extremely high resolution such as 4K or 8K can be operated using a transistor with low field-effect mobility. Needless to say, a display device having a resolution exceeding 8K (eg, 10K, 12K, or 16K) can be operated by using one embodiment of the present invention. One embodiment of the present invention can also be applied to a large display device having a screen size of 50 inches diagonal, 60 inches diagonal, or 70 inches diagonal.

In addition, since a plurality of rows of pixels 111 can be selected simultaneously, the frame frequency of the display device can be increased.

Further, as shown in FIG. 15 (B), without providing the interconnection GL _0, the scanning line driving circuit 121 may be connected to wiring GL.

(Embodiment 4)
In this embodiment, an example of a method for driving the display device 200 is described with reference to drawings. As an example, a driving method example of a liquid crystal display device using a liquid crystal element as a display element will be described.

<Driving method example>
An example of a method for driving the display device 200 of one embodiment of the present invention is described. In this embodiment mode, the display device 200 includes a display portion 210 in which 32 pixels 111 are provided in a matrix of 8 rows and 4 columns, and the wiring SL ₁ is electrically connected to the pixels 111 in the odd rows. for if the wiring SL ₂ is to connect the pixel 111 electrically even rows, the description of the driving method.

16 and 17 are timing charts for explaining the driving method. In the present embodiment, a driving method example of the display device 200 will be described by illustrating the kth frame and the (k + 1) th frame. One frame has four periods. In this embodiment, the four periods of the kth frame are denoted as periods T1 to T4. In addition, four periods included in the (k + 1) th frame are denoted as periods T5 to T8.

18 to 27 are diagrams for explaining the operation state of the display unit 210 for each period. When an H potential is supplied to the wiring GL, the pixels 111 in the first to fourth columns are selected in the row to which the wiring GL is connected, and a video signal is written to each pixel 111 through the wiring SL. When the L potential is supplied to the wiring GL, the pixels 111 in the first to fourth columns are not selected in the row to which the wiring GL is connected, and the video signal is not written.

In FIGS. 18 to 27, “H” is attached to the wiring GL to which the H potential is supplied, and “L” is attached to the wiring GL to which the L potential is supplied. When there is a change in the potential supplied to the wiring GL, “H” or “L” is used as an enclosing character. Further, “+” is attached to the wiring COM to which the positive voltage is supplied, and “−” is attached to the wiring COM to which the negative voltage is supplied. When there is a change in the polarity of the voltage supplied to the wiring COM, “+” or “−” is enclosed.

In FIG. 18 to FIG. 27, the pixel 111 to which the video signal is supplied is hatched. Further, “+” is added to the pixel 111 supplied with the positive video signal, and “−” is added to the pixel 111 supplied with the negative video signal.

As an initial state, it is assumed that a positive video signal is written to the odd-numbered and odd-numbered pixels 111 and a negative-polarity video signal is written to the even-numbered and even-numbered pixels 111 in the period T0. Further, an L potential is supplied to the wirings GL [1] to GL [6], and an H potential is supplied to the wirings GL [7] and GL [8]. Further, a positive voltage is supplied to the wiring COM [1], the wiring COM [3], the wiring COM [4], the wiring COM [6], and the wiring COM [8], and the wiring COM [2] and the wiring COM [ 5], a negative voltage is supplied to the wiring COM [7] and the wiring COM [9].

[Period T1]
In the period T1, the L potential is supplied to the wiring GL [7] and the wiring GL [8], and the H potential is supplied to the wiring GL [1] and the wiring GL [2] (see FIG. 18A). Then, the pixels 111 in the first row, first column to the second row, fourth column are selected, and a video signal is written to each pixel 111 via the wiring SL.

In the period T1, a negative video signal is written to the pixels 111 in the first row and odd columns, and a positive video signal is written to the pixels 111 in the first row and even columns. Also, a positive video signal is written to the pixels 111 in the second row and odd columns, and a negative video signal is written to the pixels 111 in the second row and even columns. Further, a negative voltage (common voltage) is supplied to the wiring COM [4], and a positive voltage is supplied to the wiring COM [5].

The pixels 111 in the first row and odd columns are electrically connected to the wiring COM [1] to which a positive voltage is supplied, and the pixels 111 in the first row and even columns are connected to the wiring COM to which a negative voltage is supplied. [2] is electrically connected. The pixels 111 in the second row and odd columns are electrically connected to the wiring COM [2] to which a negative voltage is supplied, and the pixels 111 in the second row and even columns are connected to the wiring COM to which a positive voltage is supplied. [3] is electrically connected.

The wiring COM [1], the wiring COM [2], and the wiring COM [3] are supplied with a voltage having a polarity opposite to the polarity of the video signal written to the pixels 111 in the first and second rows. . Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T2]
In the period T2, the L potential is supplied to the wiring GL [1] and the wiring GL [2], and the H potential is supplied to the wiring GL [3] and the wiring GL [4] (see FIG. 19). Then, the pixels 111 in the third row, first column to the fourth row, fourth column are selected, and a video signal is written to each pixel 111 through the wiring SL.

In the period T2, a negative video signal is written in the pixels 111 in the third row and odd columns, and a positive video signal is written in the pixels 111 in the third row and even columns. A positive video signal is written to the pixels 111 in the 4th row and odd columns, and a negative video signal is written to the pixels 111 in the 4th row and even columns. Further, a negative voltage is supplied to the wiring COM [6], and a positive voltage is supplied to the wiring COM [7].

The pixels 111 in the third row and odd columns are electrically connected to the wiring COM [3] to which a positive voltage is supplied, and the pixels 111 in the third row and even columns are connected to the wiring COM to which a negative voltage is supplied. [4] is electrically connected. The pixels 111 in the 4th row and odd columns are electrically connected to the wiring COM [4] to which a negative voltage is supplied, and the pixels 111 in the 4th and even columns are connected to the wiring COM to which a positive voltage is supplied. [5] is electrically connected.

The wiring COM [3], the wiring COM [4], and the wiring COM [5] are supplied with a voltage having a polarity opposite to the polarity of the video signal written to the pixels 111 in the third and fourth rows. . Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T3]
In the period T3, the L potential is supplied to the wiring GL [3] and the wiring GL [4], and the H potential is supplied to the wiring GL [5] and the wiring GL [6] (see FIG. 20). Then, the pixel 111 in the fifth row, first column to the sixth row, fourth column is selected, and a video signal is written to each pixel 111 through the wiring SL.

In the period T3, a negative video signal is written to the pixels 111 in the fifth row and odd columns, and a positive video signal is written to the pixels 111 in the fifth row and even columns. Further, a positive video signal is written to the pixels 111 in the 6th row and odd columns, and a negative video signal is written to the pixels 111 in the 6th row and even columns. Further, a negative voltage (common voltage) is supplied to the wiring COM [8], a positive voltage is supplied to the wiring COM [9], and a negative voltage (common voltage) is supplied to the wiring COM [1]. Is done.

The pixels 111 in the fifth row and odd columns are electrically connected to the wiring COM [5] to which a positive voltage is supplied, and the pixels 111 in the fifth row and even columns are connected to the wiring COM to which a negative voltage is supplied. [6] is electrically connected. The pixels 111 in the sixth row and odd columns are electrically connected to the wiring COM [6] to which a negative voltage is supplied, and the pixels 111 in the sixth row and even columns are connected to the wiring COM to which a positive voltage is supplied. [7] is electrically connected.

The wiring COM [5], the wiring COM [6], and the wiring COM [7] are supplied with a voltage having a polarity opposite to the polarity of the video signal written to the pixels 111 in the fifth and sixth rows. . Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

[Period T4]
In the period T4, the L potential is supplied to the wiring GL [5] and the wiring GL [6], and the H potential is supplied to the wiring GL [7] and the wiring GL [8] (see FIG. 21). Then, the pixel 111 in the seventh row, first column to the eighth row, fourth column is selected, and a video signal is written to each pixel 111 via the wiring SL.

In the period T4, a negative video signal is written to the pixels 111 in the seventh row and odd columns, and a positive video signal is written to the pixels 111 in the seventh row and even columns. In addition, a positive video signal is written to the pixels 111 in the 8th row and odd columns, and a negative video signal is written to the pixels 111 in the 8th row and even columns. Further, a positive voltage is supplied to the wiring COM [2], and a negative voltage is supplied to the wiring COM [3].

The pixels 111 in the seventh row and odd columns are electrically connected to the wiring COM [7] to which the positive voltage is supplied, and the pixels 111 in the seventh row and even columns are connected to the wiring COM to which the negative voltage is supplied. [8] is electrically connected. The pixels 111 in the 8th row and odd columns are electrically connected to the wiring COM [8] to which a negative voltage is supplied, and the pixels 111 in the 8th and even columns are connected to the wiring COM to which a positive voltage is supplied. [9] is electrically connected.

The wiring COM [7], the wiring COM [8], and the wiring COM [9] are supplied with a voltage having a polarity opposite to the polarity of the video signal written to the pixels 111 in the seventh and eighth rows. . Therefore, the amplitude of the video signal written to each pixel 111 can be reduced.

In this way, the rewriting operation of the pixel 111 in the k-th frame can be performed. Note that the polarity of the voltage supplied to the wiring COM [1], the wiring COM [8], and the wiring COM [9] is inverted in the period T3. Among them, the polarity of the voltage supplied to the wiring COM [1] may be reversed in the period T4 instead of the period T3 (see FIG. 26).

[Period T5]
In the period T5, the L potential is supplied to the wiring GL [7] and the wiring GL [8], and the H potential is supplied to the wiring GL [1] and the wiring GL [2] (see FIG. 22). Then, the pixels 111 in the first row, first column to the second row, fourth column are selected, and a video signal is written to each pixel 111 via the wiring SL.

In the period T5, a positive video signal is written to the pixels 111 in the first row and odd columns, and a negative video signal is written to the pixels 111 in the first row and even columns. Further, a negative video signal is written to the pixels 111 in the second row and odd columns, and a positive video signal is written to the pixels 111 in the second row and even columns. Further, a positive voltage is supplied to the wiring COM [4], and a negative voltage is supplied to the wiring COM [5].

The pixels 111 in the first row and odd columns are electrically connected to the wiring COM [1] to which the negative voltage is supplied, and the pixels 111 in the first row and even columns are connected to the wiring COM to which the positive voltage is supplied. [2] is electrically connected. The pixels 111 in the second row and odd columns are electrically connected to the wiring COM [2] to which a positive voltage is supplied, and the pixels 111 in the second row and even columns are connected to the wiring COM to which a negative voltage is supplied. [3] is electrically connected.

[Period T6]
In the period T6, the L potential is supplied to the wiring GL [1] and the wiring GL [2], and the H potential is supplied to the wiring GL [3] and the wiring GL [4] (see FIG. 23). Then, the pixels 111 in the third row, first column to the fourth row, fourth column are selected, and a video signal is written to each pixel 111 through the wiring SL.

In the period T 6, a positive video signal is written to the pixels 111 in the third row and odd columns, and a negative video signal is written to the pixels 111 in the third row and even columns. Also, a negative video signal is written to the pixels 111 in the 4th row and odd columns, and a positive video signal is written to the pixels 111 in the 4th row and even columns. Further, a positive voltage is supplied to the wiring COM [6], and a negative voltage is supplied to the wiring COM [7].

The pixels 111 in the third row and odd columns are electrically connected to the wiring COM [3] to which the negative voltage is supplied, and the pixels 111 in the third row and even columns are connected to the wiring COM to which the positive voltage is supplied. [4] is electrically connected. The pixels 111 in the fourth row and odd columns are electrically connected to the wiring COM [4] to which a positive voltage is supplied, and the pixels 111 in the fourth row and even columns are connected to the wiring COM to which a negative voltage is supplied. [5] is electrically connected.

[Period T7]
In the period T7, the L potential is supplied to the wiring GL [3] and the wiring GL [4], and the H potential is supplied to the wiring GL [5] and the wiring GL [6] (see FIG. 24). Then, the pixel 111 in the fifth row, first column to the sixth row, fourth column is selected, and a video signal is written to each pixel 111 through the wiring SL.

In the period T7, a positive video signal is written to the pixels 111 in the fifth row and odd columns, and a negative video signal is written to the pixels 111 in the fifth row and even columns. Further, a negative video signal is written to the pixels 111 in the 6th row and odd columns, and a positive video signal is written to the pixels 111 in the 6th row and even columns. Further, a positive voltage (common voltage) is supplied to the wiring COM [8], a negative voltage is supplied to the wiring COM [9], and a positive voltage (common voltage) is supplied to the wiring COM [1]. Is done.

The pixels 111 in the fifth row and odd columns are electrically connected to the wiring COM [5] to which a negative voltage is supplied, and the pixels 111 in the fifth row and even columns are connected to the wiring COM to which a positive voltage is supplied. [6] is electrically connected. The pixels 111 in the sixth row and odd columns are electrically connected to the wiring COM [6] to which a positive voltage is supplied, and the pixels 111 in the sixth row and even columns are connected to the wiring COM to which a negative voltage is supplied. [7] is electrically connected.

[Period T8]
In the period T8, the L potential is supplied to the wiring GL [5] and the wiring GL [6], and the H potential is supplied to the wiring GL [7] and the wiring GL [8] (see FIG. 25). Then, the pixel 111 in the seventh row, first column to the eighth row, fourth column is selected, and a video signal is written to each pixel 111 via the wiring SL.

In the period T8, a positive video signal is written to the pixel 111 in the seventh row and odd column, and a negative video signal is written to the pixel 111 in the seventh row and even column. Further, a negative video signal is written to the pixels 111 in the 8th row and odd columns, and a positive video signal is written to the pixels 111 in the 8th row and even columns. Further, a negative voltage is supplied to the wiring COM [2], and a positive voltage is supplied to the wiring COM [3].

The pixels 111 in the 7th row and odd columns are electrically connected to the wiring COM [7] to which a negative voltage is supplied, and the pixels 111 in the 7th row and even columns are connected to the wiring COM to which a positive voltage is supplied. [8] is electrically connected. The pixels 111 in the 8th row and odd columns are electrically connected to the wiring COM [8] to which a positive voltage is supplied, and the pixels 111 in the 8th row and even columns are connected to the wiring COM to which a negative voltage is supplied. [9] is electrically connected.

In this way, the rewriting operation of the pixel 111 in the (k + 1) th frame can be performed. Note that the polarity of the voltage supplied to the wiring COM [1], the wiring COM [8], and the wiring COM [9] is inverted in the period T7. Among them, the polarity of the voltage supplied to the wiring COM [1] may be reversed in the period T8 instead of the period T7 (see FIG. 27).

In other words, the polarity of the voltage supplied to the (g + 3) th and (g + 4) th wiring COM is reversed during the period when the gth row (g is an integer of 1 to m-3) and the (g + 1) th row are selected. In this way, accurate video signal rewriting can be realized. Further, the polarity of the voltage supplied to the first wiring COM is inverted during the period in which the (m-2) th or mth row is selected. Further, the polarity of the voltage supplied to the second and third wirings COM is reversed during the period when the m-th row is selected.

(Embodiment 5)
In this embodiment, an example of a transistor that can be used for the display device and the like described in the above embodiments will be described with reference to drawings.

<Example of transistor structure>
The display device or the like of one embodiment of the present invention can be manufactured using various types of transistors such as a bottom-gate transistor and a top-gate transistor. For example, a planar transistor or a staggered transistor may be used. Therefore, the semiconductor layer material and the transistor structure to be used can be easily replaced in accordance with an existing production line.

[Bottom gate type transistor]
FIG. 28A1 is a cross-sectional view of a channel protection transistor 310 which is a kind of bottom-gate transistor. In FIG. 28A1, the transistor 310 is formed over a substrate 371. In addition, the transistor 310 includes an electrode 322 over a substrate 371 with an insulating layer 372 interposed therebetween. In addition, the semiconductor layer 324 is provided over the electrode 322 with the insulating layer 326 interposed therebetween. The electrode 322 can function as a gate electrode. The insulating layer 326 can function as a gate insulating layer.

In addition, an insulating layer 327 is provided over the channel formation region of the semiconductor layer 324. In addition, the electrode 344 a and the electrode 344 b are provided over the insulating layer 326 in contact with part of the semiconductor layer 324. The electrode 344a can function as one of a source electrode and a drain electrode. The electrode 344b can function as the other of the source electrode and the drain electrode. Part of the electrode 344 a and part of the electrode 344 b are formed over the insulating layer 327.

The insulating layer 327 can function as a channel protective layer. By providing the insulating layer 327 over the channel formation region, it is possible to prevent the semiconductor layer 324 from being exposed when the

electrodes

344a and 344b are formed. Therefore, the channel formation region of the semiconductor layer 324 can be prevented from being etched when the

electrodes

344a and 344b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.

The transistor 310 includes the insulating layer 328 over the electrode 344a, the electrode 344b, and the insulating layer 327, and the insulating layer 329 over the insulating layer 328.

In the case where a semiconductor such as silicon is used for the semiconductor layer 324, a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 324 and the electrode 344a and between the semiconductor layer 324 and the electrode 344b. A layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.

The insulating layer 329 is preferably formed using a material having a function of preventing or reducing impurity diffusion from the outside to the transistor. Note that the insulating layer 329 can be omitted as necessary.

A transistor 311 illustrated in FIG. 28A2 is different from the transistor 310 in that the transistor 311 includes an electrode 323 that can function as a back gate electrode over the insulating layer 329. The electrode 323 can be formed using a material and a method similar to those of the electrode 322.

In general, the back gate electrode is formed using a conductive layer, and the channel formation region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be a ground potential (GND potential) or an arbitrary potential. In addition, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently of the gate electrode.

Both the electrode 322 and the electrode 323 can function as gate electrodes. Therefore, each of the insulating layer 326, the insulating layer 328, and the insulating layer 329 can function as a gate insulating layer. Note that the electrode 323 may be provided between the insulating layer 328 and the insulating layer 329.

Note that when one of the electrode 322 and the electrode 323 is referred to as a “gate electrode”, the other is referred to as a “back gate electrode”. For example, in the transistor 311, when the electrode 323 is referred to as a “gate electrode”, the electrode 322 is referred to as a “back gate electrode”. In the case where the electrode 323 is used as a “gate electrode”, the transistor 311 can be regarded as a kind of top-gate transistor. In addition, either the electrode 322 or the electrode 323 may be referred to as a “first gate electrode” and the other may be referred to as a “second gate electrode”.

By providing the electrode 322 and the electrode 323 with the semiconductor layer 324 interposed therebetween, and further by setting the electrode 322 and the electrode 323 to have the same potential, a region where carriers flow in the semiconductor layer 324 becomes larger in the film thickness direction. The amount of carrier movement increases. As a result, the on-state current of the transistor 311 increases and the field effect mobility increases.

Therefore, the transistor 311 is a transistor having a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 311 can be reduced with respect to the required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Thus, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

In addition, since the gate electrode and the back gate electrode are formed using conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on a semiconductor layer in which a channel is formed (particularly, an electric field shielding function against static electricity). . Note that the electric field shielding function can be improved by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.

Since each of the gate electrode and the back gate electrode has a function of shielding an electric field from the outside, charges such as charged particles generated above and below the transistor do not affect the channel formation region of the semiconductor layer. As a result, deterioration of a stress test (for example, an NGBT (Negative Gate Bias-Temperature) stress test (also referred to as “NBT” or “NBTS”) in which a negative voltage is applied to the gate is suppressed. The back gate electrode can block the electric field generated from the drain electrode so as not to act on the semiconductor layer, and thus can suppress fluctuations in the rising voltage of the on-current due to fluctuations in the drain voltage. This effect is remarkable when a potential is supplied to the gate electrode and the back gate electrode.

In addition, a transistor having a back gate electrode has a variation in threshold voltage before and after a PGBT (Positive Gate Bias-Temperature) stress test (also referred to as “PBT” or “PBTS”) in which a positive voltage is applied to the gate. Smaller than a transistor without a back gate electrode.

Note that a BT stress test such as NGBT and PGBT is a kind of accelerated test, and a transistor characteristic change (aging) caused by long-term use can be evaluated in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the BT stress test is an important index for examining reliability. Before and after the BT stress test, the smaller the variation amount of the threshold voltage, the higher the reliability of the transistor.

In addition, since the gate electrode and the back gate electrode are provided and both have the same potential, the amount of fluctuation in the threshold voltage is reduced. For this reason, variation in electrical characteristics among a plurality of transistors is also reduced at the same time.

In addition, when light enters from the back gate electrode side, the back gate electrode is formed using a light-shielding conductive film, whereby light can be prevented from entering the semiconductor layer from the back gate electrode side. Therefore, light deterioration of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as shift of the threshold voltage of the transistor can be prevented.

According to one embodiment of the present invention, a highly reliable transistor can be realized. In addition, a highly reliable semiconductor device can be realized.

FIG. 28B1 is a cross-sectional view of a channel protection transistor 320 which is one of bottom-gate transistors. The transistor 320 has substantially the same structure as the transistor 310 except that an insulating layer 327 covers the semiconductor layer 324. In addition, the semiconductor layer 324 and the electrode 344a are electrically connected to each other in an opening formed by selectively removing a part of the insulating layer 327 overlapping with the semiconductor layer 324. The semiconductor layer 324 and the electrode 344b are electrically connected to each other in an opening formed by selectively removing part of the insulating layer 327 overlapping with the semiconductor layer 324. A region of the insulating layer 327 overlapping with a channel formation region can function as a channel protective layer.

A transistor 321 illustrated in FIG. 28B2 is different from the transistor 320 in that the transistor 321 includes an electrode 323 that can function as a back gate electrode over the insulating layer 329.

By providing the insulating layer 327, the semiconductor layer 324 can be prevented from being exposed when the electrode 344a and the electrode 344b are formed. Therefore, the semiconductor layer 324 can be prevented from being thinned when the

electrodes

344a and 344b are formed.

Further, in the transistor 320 and the transistor 321, the distance between the electrode 344 a and the electrode 322 and the distance between the electrode 344 b and the electrode 322 are longer than those in the transistor 310 and the transistor 311. Thus, parasitic capacitance generated between the electrode 344a and the electrode 322 can be reduced. In addition, parasitic capacitance generated between the electrode 344b and the electrode 322 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.

A transistor 325 illustrated in FIG. 28C1 is a channel-etched transistor which is one of bottom-gate transistors. In the transistor 325, the electrode 344a and the electrode 344b are formed without using the insulating layer 327. For this reason, part of the semiconductor layer 324 exposed when the

electrodes

344a and 344b are formed may be etched. On the other hand, since the insulating layer 327 is not provided, the productivity of the transistor can be increased.

A transistor 325 illustrated in FIG. 28C2 is different from the transistor 320 in that the transistor 325 includes an electrode 323 that can function as a back gate electrode over the insulating layer 329.

[Top gate type transistor]
FIG. 29A1 is a cross-sectional view of a transistor 330 which is a kind of top-gate transistor. The transistor 330 includes a semiconductor layer 324 over the insulating layer 372, and an electrode 344a in contact with part of the semiconductor layer 324 and an electrode 344b in contact with part of the semiconductor layer 324 over the semiconductor layer 324 and the insulating layer 372. An insulating layer 326 is provided over the semiconductor layer 324, the electrode 344a, and the electrode 344b, and an electrode 322 is provided over the insulating layer 326.

The transistor 330 reduces the parasitic capacitance generated between the electrode 322 and the electrode 344a and the parasitic capacitance generated between the electrode 322 and the electrode 344b because the electrode 322 and the electrode 344a and the electrode 322 and the electrode 344b do not overlap with each other. be able to. Further, after the electrode 322 is formed, the impurity region can be formed in the semiconductor layer 324 in a self-alignment manner by introducing the impurity 255 into the semiconductor layer 324 using the electrode 322 as a mask ( (See FIG. 29A3). According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.

Note that the impurity 255 can be introduced using an ion implantation apparatus, an ion doping apparatus, or a plasma treatment apparatus.

As the impurity 255, for example, at least one element of a Group 13 element or a Group 15 element can be used. In the case where an oxide semiconductor is used for the semiconductor layer 324, at least one element of a rare gas, hydrogen, and nitrogen can be used as the impurity 255.

A transistor 331 illustrated in FIG. 29A2 is different from the transistor 330 in that the transistor 331 includes an electrode 323 and an insulating layer 227. The transistor 331 includes the electrode 323 formed over the insulating layer 372 and the insulating layer 227 formed over the electrode 323. The electrode 323 can function as a back gate electrode. Thus, the insulating layer 227 can function as a gate insulating layer. The insulating layer 227 can be formed using a material and a method similar to those of the insulating layer 326.

Similar to the transistor 311, the transistor 331 is a transistor having a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 331 can be reduced with respect to the required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Thus, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

A transistor 340 illustrated in FIG. 29B1 is one of top-gate transistors. The transistor 340 is different from the transistor 330 in that the semiconductor layer 324 is formed after the

electrodes

344a and 344b are formed. A transistor 341 illustrated in FIG. 29B2 is different from the transistor 340 in that the transistor 341 includes an electrode 323 and an insulating layer 227. In the transistor 340 and the transistor 341, part of the semiconductor layer 324 is formed over the electrode 344a, and the other part of the semiconductor layer 324 is formed over the electrode 344b.

Similar to the transistor 311, the transistor 341 is a transistor having a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 341 can be reduced with respect to the required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Thus, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

A transistor 342 illustrated in FIG. 30A1 is one of top-gate transistors. The transistor 342 is different from the

transistors

330 and 340 in that the electrode 344a and the electrode 344b are formed after the insulating layer 329 is formed. The

electrodes

344 a and 344 b are electrically connected to the semiconductor layer 324 through openings formed in the insulating

layers

328 and 329.

Further, part of the insulating layer 326 that does not overlap with the electrode 322 is removed, and the impurity 255 is introduced into the semiconductor layer 324 using the electrode 322 and the remaining insulating layer 326 as a mask, so that self-alignment in the semiconductor layer 324 ( Impurity regions can be formed in a self-aligning manner (see FIG. 30A3). The transistor 342 includes a region where the insulating layer 326 extends beyond the end portion of the electrode 322. When the impurity 255 is introduced into the semiconductor layer 324, the impurity concentration of the region into which the impurity 255 is introduced through the insulating layer 326 of the semiconductor layer 324 is higher than that in the region into which the impurity 255 is introduced without passing through the insulating layer 326. Get smaller. Therefore, in the semiconductor layer 324, an LDD (Lightly Doped Drain) region is formed in a region that does not overlap with the electrode 322.

A transistor 343 illustrated in FIG. 30A2 is different from the transistor 342 in that the electrode 323 is provided. The transistor 343 includes an electrode 323 formed over the substrate 371 and overlaps with the semiconductor layer 324 with the insulating layer 372 interposed therebetween. The electrode 323 can function as a back gate electrode.

Further, as in the transistor 344 illustrated in FIG. 30B1 and the transistor 345 illustrated in FIG. 30B2, the insulating layer 326 which does not overlap with the electrode 322 may be removed. Further, the insulating layer 326 may be left as in the transistor 346 illustrated in FIG. 30C1 and the transistor 347 illustrated in FIG.

The transistors 342 to 347 can also form an impurity region in the semiconductor layer 324 in a self-aligned manner by introducing the impurity 255 into the semiconductor layer 324 using the electrode 322 as a mask after the electrode 322 is formed. . According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. According to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

[substrate]
There is no major limitation on the material used for the substrate. Depending on the purpose, it may be determined in consideration of the presence or absence of translucency and heat resistance enough to withstand heat treatment. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Further, a semiconductor substrate, a flexible substrate (flexible substrate), a bonded film, a base film, or the like may be used.

Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. . The semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

Further, as the substrate, for example, 6th generation (1500 mm × 1850 mm), 7th generation (1870 mm × 2200 mm), 8th generation (2200 mm × 2400 mm), 9th generation (2400 mm × 2800 mm), 10th generation (2950 mm × 3400 mm) ) And the like can be used. Thus, a large display device can be manufactured. Further, by increasing the size of the substrate, more display devices can be produced from one substrate, and the production cost can be reduced.

In order to increase the flexibility of the display device, a flexible substrate (flexible substrate), a bonded film, a base film, or the like may be used as the substrate.

Examples of materials such as a flexible substrate, a laminated film, and a base film include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, and polymethyl methacrylate. Resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polychlorinated resin Vinylidene resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, and the like can be used.

By using the above material as the substrate, a lightweight display device can be provided. In addition, by using the above material as the substrate, a display device that is resistant to impact can be provided. In addition, by using the above material for the substrate, a display device which is not easily damaged can be provided.

The flexible substrate used for the substrate is preferably as the linear expansion coefficient is low because deformation due to the environment is suppressed. For the flexible substrate used for the substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a flexible substrate.

[Conductive layer]
In addition to the gate, source, and drain of the transistor, conductive materials that can be used for conductive layers such as various wirings and electrodes constituting the display device include aluminum (Al), chromium (Cr), copper (Cu), and silver. (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium Metal elements selected from (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), alloys containing the above metal elements, or alloys combining the above metal elements Etc. can be used. Alternatively, a semiconductor typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used. There is no particular limitation on the method for forming the conductive material, and various formation methods such as an evaporation method, a CVD method, a sputtering method, and a spin coating method can be used.

Further, a Cu—X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied as the conductive material. Since the layer formed of the Cu—X alloy can be processed by a wet etching process, the manufacturing cost can be suppressed. Alternatively, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.

As a conductive material that can be used for the conductive layer, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin containing titanium oxide, or the like can be used. A conductive material containing oxygen such as oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a conductive material containing nitrogen such as titanium nitride, tantalum nitride, or tungsten nitride can be used. Alternatively, the conductive layer can have a stacked structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above metal element are combined as appropriate.

For example, the conductive layer is a single layer structure of an aluminum layer containing silicon, a two layer structure in which a titanium layer is stacked on an aluminum layer, a two layer structure in which a titanium layer is stacked on a titanium nitride layer, and a tungsten layer on a titanium nitride layer. A two-layer structure in which layers are stacked, a two-layer structure in which a tungsten layer is stacked on a tantalum nitride layer, or a three-layer structure in which a titanium layer and an aluminum layer are stacked on the titanium layer, and a titanium layer is further stacked on the titanium layer. .

A plurality of conductive layers formed using the above conductive materials may be stacked. For example, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

For example, a conductive layer is formed by laminating a conductive layer containing copper on a conductive layer containing at least one of indium or zinc and oxygen, and further laminating a conductive layer containing at least one of indium or zinc and oxygen on the conductive layer. It may be a three-layer structure. In this case, the side surface of the conductive layer containing copper is also preferably covered with a conductive layer containing at least one of indium or zinc and oxygen. Further, for example, a plurality of conductive layers containing oxygen and at least one of indium or zinc may be used as the conductive layer.

[Insulation layer]
Each insulating layer is made of aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide A material selected from neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like is used as a single layer or a stacked layer. Alternatively, a material obtained by mixing a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

Note that in this specification, a nitrided oxide refers to a compound having a higher nitrogen content than oxygen. Further, oxynitride refers to a compound having a higher oxygen content than nitrogen. In addition, content of each element can be measured using Rutherford backscattering method (RBS: Rutherford Backscattering Spectrometry) etc., for example.

In particular, the insulating layer 372 and the insulating layer 329 are preferably formed using an insulating material which does not easily transmit impurities. For example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, in a single layer, or What is necessary is just to use it by lamination | stacking. Examples of insulating materials that are difficult to transmit impurities include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, Examples thereof include silicon nitride.

By using an insulating material that does not easily transmit impurities for the insulating layer 372, diffusion of impurities from the substrate 371 side can be suppressed and the reliability of the transistor can be improved. By using an insulating material that does not easily transmit impurities for the insulating layer 329, diffusion of impurities from above the insulating layer 329 can be suppressed, and the reliability of the transistor can be improved.

Alternatively, an insulating layer that can function as a planarization layer may be used as the insulating layer. As the insulating layer that can function as a planarization layer, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that a plurality of insulating layers formed using these materials may be stacked.

Note that the siloxane resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. In the siloxane resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used as a substituent. The organic group may have a fluoro group.

Further, a CMP process may be performed on the surface of the insulating layer or the like. By performing the CMP treatment, unevenness on the surface of the sample can be reduced, and the coverage of the insulating layer and the conductive layer to be formed thereafter can be improved.

[Semiconductor layer]
As a semiconductor material used for the semiconductor layer of the transistor, any of an amorphous semiconductor and a crystalline semiconductor (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor having part of a crystalline region) can be used. Good.

For example, silicon, germanium, or the like can be used as a semiconductor material used for a semiconductor layer of the transistor. Alternatively, a compound semiconductor such as silicon carbide, gallium arsenide, metal oxide, or nitride semiconductor, or an organic semiconductor can be used.

For example, amorphous silicon (amorphous silicon) can be used as a semiconductor material used for the transistor. In particular, amorphous silicon is excellent in mass productivity and can be easily provided on a substrate having a large area. Note that in general, amorphous silicon used for a transistor contains a large amount of hydrogen. For this reason, amorphous silicon containing a large amount of hydrogen may be referred to as “hydrogenated amorphous silicon” or “a-Si: H”. In addition, since amorphous silicon can be formed at a lower temperature than polycrystalline silicon, the maximum temperature during the manufacturing process can be lowered. Therefore, a material having low heat resistance can be used for the substrate, the conductive layer, the insulating layer, and the like.

Further, as a semiconductor material used for the transistor, silicon having crystallinity such as microcrystalline silicon, polycrystalline silicon, or single crystal silicon can be used. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.

As a semiconductor material used for the transistor, an oxide semiconductor which is a kind of metal oxide can be used. Typically, an oxide semiconductor containing indium can be used. An oxide semiconductor can realize higher field-effect mobility and higher reliability than amorphous silicon. An oxide semiconductor is excellent in mass productivity and can be easily provided over a large substrate.

An oxide semiconductor which is a kind of metal oxide has a wider band gap and lower carrier density than silicon, and thus is preferably used for a semiconductor layer of a transistor. An oxide semiconductor is preferably used for the semiconductor layer of the transistor because current flowing between the source and the drain in the off state of the transistor can be reduced.

An oxide semiconductor that is a kind of metal oxide preferably has an energy gap of 2 eV or more, and more preferably 2.5 eV or more. More preferably, it is 3 eV or more. In this manner, off-state current of a transistor can be reduced by using an oxide semiconductor with a wide energy gap.

An oxide semiconductor which is a kind of metal oxide includes, for example, at least indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It is preferable to include a material represented by —Zn-based oxide. In addition, in order to reduce variation in electrical characteristics of the transistor including the oxide semiconductor, a stabilizer is preferably included together with the transistor.

Examples of the stabilizer include the metals described in M above, and examples include gallium, tin, hafnium, aluminum, and zirconium. Other stabilizers include lanthanoids such as lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

As a metal oxide forming the semiconductor layer, for example, an In—Ga—Zn-based oxide, an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, an In—Hf—Zn-based oxide, an In— La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm -Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al- Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn acid Things, can be used In-Hf-Al-Zn-based oxide.

Note that here, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Note that a metal oxide that can be used for a semiconductor layer of a transistor will be described in detail in another embodiment.

[Method for forming each layer]
Insulating layers, semiconductor layers, conductive layers for forming electrodes and wirings are formed by sputtering, chemical vapor deposition (CVD), vacuum vapor deposition, pulse laser deposition (PLD), or pulse laser deposition (PLD). In addition, it can be formed by using an atomic layer deposition (ALD) method or the like. The CVD method may be a plasma enhanced chemical vapor deposition (PECVD) method or a thermal CVD method. As an example of the thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method may be used.

In addition, insulating layers, semiconductor layers, conductive layers for forming electrodes and wiring, etc. that constitute display devices include spin coating, dip, spray coating, ink jet, dispensing, screen printing, offset printing, slit coating, roll coating, You may form by methods, such as a curtain coat and a knife coat.

The PECVD method can obtain a high quality film at a relatively low temperature. When a film formation method that does not use plasma at the time of film formation, such as an MOCVD method, an ALD method, or a thermal CVD method, damage to the formation surface is unlikely to occur. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, since plasma damage during film formation does not occur, a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.

When a layer (thin film) included in the display device is processed, the layer can be processed using a photolithography method or the like. Alternatively, the island-shaped layer may be formed by a film formation method using a shielding mask. Alternatively, the layer may be processed by a nanoimprint method, a sand blast method, a lift-off method, or the like. As a photolithography method, a resist mask is formed over a layer (thin film) to be processed, a part of the layer (thin film) is selectively removed using the resist mask as a mask, and then the resist mask is removed. And a method of forming a layer having photosensitivity and then performing exposure and development to process the layer into a desired shape.

When light is used in the photolithography method, light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure may be performed by an immersion exposure technique. Further, extreme ultraviolet light (EUV: Extreme-violet) or X-rays may be used as light used for exposure. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

For removal (etching) of the layer (thin film), a dry etching method, a wet etching method, a sand blasting method, or the like can be used. Moreover, you may use combining these etching methods.

(Embodiment 6)
In this embodiment, a metal oxide that can be used for a semiconductor layer of a transistor will be described.

<Composition of metal oxide>
In this section, one of the metal oxides that can be used for a semiconductor device such as a transistor disclosed in one embodiment of the present invention, which is a CAC-OS (Cloud-Aligned Composite-Oxide Semiconductor), or CAC (Cloud-) The configuration of (Aligned Composite) -metal oxide will be described.

In addition, in this specification etc., it may describe as CAC and CAAC (c-axis aligned crystal). In this case, CAC represents an example of a function or material configuration, and CAAC represents an example of a structure.

CAC-OS or CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where CAC-OS or CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is an electron serving as carriers. It is a function that does not flow. A function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Therefore, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

Note that in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).

<Structure of metal oxide>
In this section, a structure of a metal oxide that can be used for a semiconductor device such as a transistor disclosed in one embodiment of the present invention will be described.

Metal oxides are classified into metal oxides made of a single crystal material and metal oxides made of a non-single crystal material. The single crystal material has a single crystal structure. The non-single-crystal material has one or more of an amorphous structure, a microcrystalline structure, and a polycrystalline structure.

Moreover, as one of the non-single crystal materials, a material called a semi-crystalline material can be given. The semi-crystalline material has an intermediate structure between a single crystal structure and an amorphous structure.

A single crystal of a metal oxide has a structure in which oxygen polyhedrons having a metal atom at the center are connected with specific regularity. Specifically, in a single crystal of InGaZnO ₄ , an oxygen octahedron having an In atom at the center and a trigonal bipyramid of oxygen having Ga or Zn at the center are connected with a specific regularity. Thus, it has a layered crystal structure.

On the other hand, the semi-crystalline material has a plurality of oxygen polyhedrons in which a metal atom is present at the center, and the polyhedrons are connected to each other without having a specific regularity. The polyhedron that the semicrystalline material has is a polyhedron that is not observed in the single crystal, in which the polyhedron of the single crystal structure is significantly broken. Note that the semicrystalline material may have a part of a single crystal structure such as a polyhedron that the single crystal structure has or a region where the polyhedrons that the single crystal structure has have regularity.

The semi-crystalline material has a stable structure as compared with a so-called amorphous material by connecting polyhedrons to each other without having a specific regularity.

For example, when the metal oxide is an oxide semiconductor, the metal oxide is divided into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, for example, a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

For example, as a semicrystalline oxide semiconductor, an oxide semiconductor having a CAAC structure and a CAC structure (hereinafter also referred to as CAAC / CAC) is given.

The CAAC-OS is an oxide semiconductor that has a c-axis orientation and a CAAC structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.

The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when a part of the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when a part of indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the CAAC-OS are stable. Therefore, the CAAC-OS is resistant to heat and has high reliability.

The nc-OS is an oxide semiconductor having a structure in which atomic arrangement is periodic in a very small region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

Oxide semiconductors have various structures and different properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

(Embodiment 7)
In this embodiment, an example of a transistor that can be used for the display device and the like described in the above embodiments will be described with reference to drawings. In particular, an example of a transistor structure which is preferably used for an OS transistor will be described.

<Example of transistor structure>
[Configuration example 1]
First, as an example of a transistor structure, a transistor 500a will be described with reference to FIGS. FIG. 31A is a top view of the transistor 500a. 31B corresponds to a cross-sectional view of a cross-sectional surface taken along the dashed-dotted line X1-X2 in FIG. 31A, and FIG. 31C is between the dashed-dotted line Y1-Y2 shown in FIG. This corresponds to a cross-sectional view of the cut surface in FIG. Note that for easy understanding of the drawing, some components (such as an insulating layer functioning as a gate insulating layer) of the transistor 500a are omitted in FIG. In the following description, the alternate long and short dash line X1-X2 direction may be referred to as a channel length direction, and the alternate long and short dash line Y1-Y2 direction may be referred to as a channel width direction. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 31A.

The transistor 500a includes a conductive layer 521 over the insulating layer 524, an insulating layer 511 over the insulating layer 524 and the conductive layer 521, a semiconductor layer 531 over the insulating layer 511, and a conductive layer over the semiconductor layer 531 and the insulating layer 511. A layer 522a, a conductive layer 522b over the semiconductor layer 531 and the insulating layer 511, an insulating layer 512 over the semiconductor layer 531, the conductive layer 522a, and the conductive layer 522b, a conductive layer 523 over the insulating layer 512, Have

Note that the insulating layer 524 may be a substrate. In the case where the insulating layer 524 is used as a substrate, the substrate can be a substrate including a material similar to that of the substrate 371 described in the above embodiment.

For the conductive layer 521 and the conductive layer 523, for example, a material similar to that of the electrode 322 described in the above embodiment can be included. As the insulating layer 511, for example, a material similar to that of the insulating layer 326 described in the above embodiment can be included. For example, the conductive layer 522a and the conductive layer 522b can include a material similar to that of the electrode 344a and the electrode 344b described in the above embodiment. The insulating layer 512 can include a material similar to that of the insulating layer 328 described in the above embodiment.

For example, the semiconductor layer 531 can include a material similar to that of the semiconductor layer 324 described in the above embodiment. In this embodiment, the semiconductor layer 531 is described as a semiconductor layer containing a metal oxide.

The insulating layer 511 and the insulating layer 512 have an opening 535. The conductive layer 523 is electrically connected to the conductive layer 521 through the opening 535.

Here, the insulating layer 511 functions as a first gate insulating layer of the transistor 500a, and the insulating layer 512 functions as a second gate insulating layer of the transistor 500a. In the transistor 500a, the conductive layer 521 functions as a first gate, the conductive layer 522a functions as one of a source and a drain, and the conductive layer 522b serves as the other of the source and the drain. It has the function of. In the transistor 500a, the conductive layer 523 functions as a second gate.

Note that the transistor 500a is a so-called channel etch transistor and has a dual-gate structure.

The transistor 500a can be formed without the conductive layer 523. In this case, the transistor 500a is a so-called channel etch type transistor and has a bottom gate structure.

As shown in FIGS. 31B and 31C, the semiconductor layer 531 is positioned so as to face the conductive layer 521 and the conductive layer 523, and is sandwiched between conductive layers having functions of two gates. The length of the conductive layer 523 in the channel length direction and the length of the conductive layer 523 in the channel width direction are longer than the length of the semiconductor layer 531 in the channel length direction and the length of the semiconductor layer 531 in the channel width direction, respectively. The entire semiconductor layer 531 is covered with the conductive layer 523 with the insulating layer 512 interposed therebetween.

In other words, the conductive layer 521 and the conductive layer 523 have a region which is connected to the opening 535 provided in the insulating layer 511 and the insulating layer 512 and located outside the side end portion of the semiconductor layer 531.

With such a structure, the semiconductor layer 531 included in the transistor 500a can be electrically surrounded by the electric fields of the conductive layer 521 and the conductive layer 523. A device structure of a transistor that electrically surrounds a semiconductor layer in which a channel formation region is formed by an electric field of a first gate and a second gate as in the transistor 500a is referred to as a surround channel (s-channel) structure. Can do.

Since the transistor 500a has an s-channel structure, an electric field for inducing a channel by the conductive layer 521 having the function of the first gate can be effectively applied to the semiconductor layer 531, so that the current of the transistor 500a The driving capability is improved and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 500a can be miniaturized.

Further, since the transistor 500a has a structure in which the semiconductor layer 531 is surrounded by the conductive layer 521 having a first gate function and the conductive layer 523 having a second gate function, the mechanical strength of the transistor 500a is increased. Can be increased.

Since the transistor 500a having an s-channel structure has high field-effect mobility and high driving capability, the transistor 500a is used in a driver circuit, typically a scan line driver circuit. A display device can be provided.

[Configuration example 2]
Next, as an example of the structure of the transistor, the transistor 500b will be described with reference to FIGS. FIG. 32A is a top view of the transistor 500b. 32B corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line X1-X2 in FIG. 32A, and FIG. 32C is between the dashed-dotted line Y1-Y2 shown in FIG. This corresponds to a cross-sectional view of the cut surface in FIG.

The transistor 500b is different from the transistor 500a in that the semiconductor layer 531, the conductive layer 522a, the conductive layer 522b, and the insulating layer 512 have a stacked structure.

The insulating layer 512 includes the insulating layer 512a over the semiconductor layer 531, the conductive layer 522a, and the conductive layer 522b, and the insulating layer 512b over the insulating layer 512a. The insulating layer 512 has a function of supplying oxygen to the semiconductor layer 531. That is, the insulating layer 512 includes oxygen. The insulating layer 512a is an insulating layer that can transmit oxygen. Note that the insulating layer 512a also functions as a damage reducing film for the semiconductor layer 531 when the insulating layer 512b to be formed later is formed.

As the insulating layer 512a, silicon oxide, silicon oxynitride, or the like with a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm can be used.

The insulating layer 512a preferably has a small amount of defects. Typically, the ESR measurement shows that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 3 × 10 ¹⁷ spins / It is preferable that it is cm ³ or less. This is because when the density of defects included in the insulating layer 512a is large, oxygen is bonded to the defects and oxygen permeability in the insulating layer 512a is reduced.

Note that in the insulating layer 512a, some oxygen that enters the insulating layer 512a from the outside does not move to the outside of the insulating layer 512a but remains in the insulating layer 512a. Further, oxygen enters the insulating layer 512a and oxygen contained in the insulating layer 512a moves to the outside of the insulating layer 512a, so that oxygen may move in the insulating layer 512a. When an oxide insulating layer that can transmit oxygen is formed as the insulating layer 512a, oxygen released from the insulating layer 512b provided over the insulating layer 512a is transferred to the semiconductor layer 531 through the insulating layer 512a. Can do.

The insulating layer 512a can be formed using an oxide insulating layer having a low level density due to nitrogen oxides. Note that the level density attributed to the nitrogen oxide may be formed between the energy at the upper end of the valence band of the metal oxide and the energy at the lower end of the conduction band of the metal oxide. As the oxide insulating layer, a silicon oxynitride film with a low emission amount of nitrogen oxide, an aluminum oxynitride film with a low emission amount of nitrogen oxide, or the like can be used.

Note that a silicon oxynitride film with a small amount of released nitrogen oxide is a film having a larger amount of released ammonia than a released amount of nitrogen oxide in a thermal desorption gas analysis (TDS) method. Specifically, the released amount of ammonia is 1 × 10 ¹⁸ / cm ³ or more and 5 × 10 ¹⁹ / cm ³ or less. Note that the amount of ammonia released is the amount released by heat treatment at a film surface temperature of 50 ° C. to 650 ° C., preferably 50 ° C. to 550 ° C.

Nitrogen oxide (NO _x , x is larger than 0 and 2 or less, preferably 1 or more and 2 or less), typically NO ₂ or NO forms a level in the insulating layer 512a or the like. The level is located in the energy gap of the semiconductor layer 531. Therefore, when nitrogen oxide diffuses to the interface between the insulating layer 512a and the semiconductor layer 531, the level may trap electrons on the insulating layer 512a side. As a result, trapped electrons remain in the vicinity of the interface between the insulating layer 512a and the semiconductor layer 531, and the threshold voltage of the transistor is shifted in the positive direction.

Nitrogen oxide reacts with ammonia and oxygen in heat treatment. Since nitrogen oxide contained in the insulating layer 512d reacts with ammonia contained in the insulating layer 512b in the heat treatment, nitrogen oxide contained in the insulating layer 512a is reduced. Therefore, electrons are not easily trapped at the interface between the insulating layer 512a and the semiconductor layer 531.

By using the oxide insulating layer as the insulating layer 512a, a shift in threshold voltage of the transistor can be reduced, and fluctuation in electric characteristics of the transistor can be reduced.

The oxide insulating layer has a nitrogen concentration of 6 × 10 ²⁰ atoms / cm ³ or less as measured by SIMS.

By forming the oxide insulating layer using a PECVD method using silane and dinitrogen monoxide with a substrate temperature of 220 ° C. or higher and 350 ° C. or lower, a dense and high hardness film is formed. be able to.

The insulating layer 512b is an oxide insulating layer containing more oxygen than oxygen that satisfies the stoichiometric composition. Part of oxygen is released from the oxide insulating layer by heating. Note that in TDS, the above oxide insulating layer has a region where the amount of released oxygen is 1.0 × 10 ¹⁹ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The amount of released oxygen is the total amount when the temperature of the heat treatment in TDS is 50 ° C. or higher and 650 ° C. or lower, or 50 ° C. or higher and 550 ° C. or lower. The amount of released oxygen is the total amount in terms of oxygen atoms in TDS.

As the insulating layer 512b, silicon oxide, silicon oxynitride, or the like with a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm can be used.

The insulating layer 512b preferably has a small amount of defects. Typically, the ESR measurement shows that the spin density of a signal appearing at g = 2.001 derived from dangling bonds in silicon is 1.5 × 10 ^18. It is preferably less than spins / cm ³ and more preferably 1 × 10 ¹⁸ spins / cm ³ or less. Note that since the insulating layer 512b is farther from the semiconductor layer 531 than the insulating layer 512a, the defect density may be higher than that of the insulating layer 512a.

In addition, since the insulating layer 512 can be formed using the same kind of insulating layer, an interface between the insulating layer 512a and the insulating layer 512b may not be clearly confirmed. Therefore, in this embodiment, the interface between the insulating layer 512a and the insulating layer 512b is illustrated by a broken line. Note that although a two-layer structure of the insulating layer 512a and the insulating layer 512b has been described in this embodiment mode, the present invention is not limited thereto, and for example, a single-layer structure of the insulating layer 512a or a stacked structure of three or more layers may be used. Good.

In the transistor 500b, the semiconductor layer 531 includes a semiconductor layer 531_1 over the insulating layer 511 and a semiconductor layer 531_2 over the semiconductor layer 531_1. Note that the semiconductor layer 531_1 and the semiconductor layer 531_2 each have the same element. For example, the semiconductor layer 531_1 and the semiconductor layer 531_2 preferably each independently include the element included in the semiconductor layer 531 described above.

The semiconductor layer 531_1 and the semiconductor layer 531_2 preferably each independently have a region in which the atomic ratio of In is larger than the atomic ratio of M. As an example, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 531_1 and the semiconductor layer 531_2 is preferably in the vicinity of In: M: Zn = 4: 2: 3. Here, in the vicinity, when In is 4, M is 1.5 or more and 2.5 or less, and Zn is 2 or more and 4 or less. Alternatively, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 531_1 and the semiconductor layer 531_2 is preferably in the vicinity of In: M: Zn = 5: 1: 6. In this manner, when the semiconductor layer 531_1 and the semiconductor layer 531_2 have substantially the same composition, the same sputtering target can be used, so that manufacturing cost can be reduced. In the case where the same sputtering target is used, the semiconductor layer 531_1 and the semiconductor layer 531_2 can be formed continuously in a vacuum in the same chamber; thus, impurities are incorporated into the interface between the semiconductor layer 531_1 and the semiconductor layer 531_2. Can be suppressed.

Here, the semiconductor layer 531_1 may have a region with lower crystallinity than the semiconductor layer 531_2. Note that the crystallinity of the semiconductor layer 531_1 and the semiconductor layer 531_2 is analyzed using, for example, X-ray diffraction (XRD: X-Ray Diffraction), or using a transmission electron microscope (TEM). It can be analyzed by analyzing.

A region with low crystallinity of the semiconductor layer 531_1 serves as an excess oxygen diffusion path, and excess oxygen can be diffused into the semiconductor layer 531_2 with higher crystallinity than the semiconductor layer 531_1. In this manner, a highly reliable transistor can be provided by using a stacked structure of semiconductor layers having different crystal structures and using a region with low crystallinity as an excess oxygen diffusion path.

In addition, since the semiconductor layer 531_2 includes a region having higher crystallinity than the semiconductor layer 531_1, impurities that can be mixed into the semiconductor layer 531 can be suppressed. In particular, by increasing the crystallinity of the semiconductor layer 531_2, damage when the

conductive layers

522a and 522b are processed can be suppressed. The surface of the semiconductor layer 531, that is, the surface of the semiconductor layer 531 _ 2 is exposed to an etchant or an etching gas when the

conductive layers

522 a and 522 b are processed. However, when the semiconductor layer 531_2 has a region with high crystallinity, the semiconductor layer 531_2 has excellent etching resistance as compared with the semiconductor layer 531_1 with low crystallinity. Therefore, the semiconductor layer 531_2 functions as an etching stopper.

In addition, since the semiconductor layer 531_1 includes a region having lower crystallinity than the semiconductor layer 531_2, the carrier density may be increased.

Further, when the carrier density of the semiconductor layer 531_1 is increased, the Fermi level may be relatively higher than the conduction band of the semiconductor layer 531_1. Accordingly, the lower end of the conduction band of the semiconductor layer 531_1 is lowered, and the energy difference between the lower end of the conduction band of the semiconductor layer 531_1 and the trap level that can be formed in the gate insulating layer (here, the insulating layer 511) is increased. There is a case. When the energy difference is increased, the charge trapped in the gate insulating layer is reduced, and the variation in threshold voltage of the transistor may be reduced in some cases. Further, when the carrier density of the semiconductor layer 531_1 is increased, the field-effect mobility of the semiconductor layer 531 can be increased.

Note that although an example in which the semiconductor layer 531 has a two-layer structure is shown in the transistor 500b, the present invention is not limited to this, and a structure in which three or more layers are stacked may be employed.

The conductive layer 522a included in the transistor 500b includes a conductive layer 522a_1, a conductive layer 522a_2 over the conductive layer 522a_1, and a conductive layer 522a_3 over the conductive layer 522a_2. The conductive layer 522b included in the transistor 500b includes a conductive layer 522b_1, a conductive layer 522b_2 over the conductive layer 522b_1, and a conductive layer 522b_3 over the conductive layer 522b_2.

For example, the conductive layer 522a_1, the conductive layer 522b_1, the conductive layer 522a_3, and the conductive layer 522b_3 include one or more selected from titanium, tungsten, tantalum, molybdenum, indium, gallium, tin, and zinc. It is preferable. The conductive layer 522a_2 and the conductive layer 522b_2 preferably include any one or more selected from copper, aluminum, and silver.

More specifically, an In—Sn oxide or an In—Zn oxide is used for the conductive layer 522a_1, the conductive layer 522b_1, the conductive layer 522a_3, and the conductive layer 522b_3, and copper is used for the conductive layer 522a_2 and the conductive layer 522b_2. it can.

In addition, the end portion of the conductive layer 522a_1 has a region located outside the end portion of the conductive layer 522a_2, and the conductive layer 522a_3 covers a top surface and side surfaces of the conductive layer 522a_2 and is in contact with the conductive layer 522a_1. Have. In addition, an end portion of the conductive layer 522b_1 has a region located outside the end portion of the conductive layer 522b_2, and the conductive layer 522b_3 covers a top surface and a side surface of the conductive layer 522b_2 and is in contact with the conductive layer 522b_1. Have.

The above structure is preferable because the wiring resistance of the

conductive layers

522a and 522b can be reduced and the diffusion of copper into the semiconductor layer 531 can be suppressed.

[Configuration example 3]
Next, as an example of the structure of the transistor, a transistor 500c will be described with reference to FIGS. FIG. 33A is a top view of the transistor 500c. 33B corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line X1-X2 in FIG. 33A, and FIG. 33C is between the dashed-dotted line Y1-Y2 shown in FIG. This corresponds to a cross-sectional view of the cut surface in FIG.

The transistor 500c includes a conductive layer 521 over the insulating layer 524, an insulating layer 511 over the conductive layer 521 and the insulating layer 524, a semiconductor layer 531 over the insulating layer 511, and an insulating layer over the semiconductor layer 531 and the insulating layer 511. Layer 516, conductive layer 522a over semiconductor layer 531 and insulating layer 516, conductive layer 522b over semiconductor layer 531 and insulating layer 516, and insulating layer over insulating layer 516, conductive layer 522a, and conductive layer 522b 512 and a conductive layer 523 over the insulating layer 512.

The insulating layer 511, the insulating layer 516, and the insulating layer 512 have an opening 535. The conductive layer 521 having a function as the first gate of the transistor 500c is electrically connected to the conductive layer 523 having a function as the second gate of the transistor 500c through the opening 535. The insulating layer 516 includes an opening 538a and an opening 538b. The conductive layer 522a functioning as one of the source and the drain of the transistor 500c is electrically connected to the semiconductor layer 531 through the opening 538a. The conductive layer 522b functioning as the other of the source and the drain of the transistor 500c is electrically connected to the semiconductor layer 531 through the opening 538b.

The insulating layer 516 functions as a channel protective layer of the transistor 500c. In the case where the insulating layer 516 is not provided, the channel formation region of the semiconductor layer 531 may be damaged when the conductive layer 522a and the conductive layer 522b are formed by an etching method or the like. As a result, the electrical characteristics of the transistor may become unstable. A semiconductor layer is formed by forming an insulating layer 516, forming an opening 538a and an opening 538b, forming a conductive layer, and processing the conductive layer by an etching method or the like to form the conductive layer 522a and the conductive layer 522b. Damage to the channel formation region of the layer 531 can be suppressed. Thereby, the electrical characteristics of the transistor can be stabilized and a highly reliable transistor can be realized.

The insulating layer 516 can include a material similar to that of the insulating layer 512, for example.

The insulating layer 516 preferably has an excess oxygen region. When the insulating layer 516 has an excess oxygen region, oxygen can be supplied to the channel formation region of the semiconductor layer 531. Accordingly, oxygen vacancies formed in the channel formation region can be filled with excess oxygen; thus, a highly reliable display device can be provided.

In addition, an impurity element is preferably added to the semiconductor layer 531 after the opening 538a and the opening 538b are formed. Specifically, an element that forms oxygen vacancies or an element that bonds with oxygen vacancies is preferably added. Accordingly, although described in detail later, the conductivity of the semiconductor layer 531 in the region overlapping with the conductive layer 522a (one of the source region or the drain region) and the region overlapping with the conductive layer 522b (the other of the source region or the drain region) are increased. Can be high. Accordingly, the current driving capability of the transistor 500c is improved, and high on-current characteristics can be obtained.

Note that the transistor 500c is a so-called channel protection transistor and has a dual-gate structure.

The transistor 500c has an s-channel structure similarly to the

transistors

500a and 500b. With such a structure, the semiconductor layer 531 included in the transistor 500c can be electrically surrounded by the electric fields of the conductive layer 521 and the conductive layer 523.

Since the transistor 500c has an s-channel structure, an electric field for inducing a channel by the conductive layer 521 or the conductive layer 523 can be effectively applied to the semiconductor layer 531. Accordingly, the current driving capability of the transistor 500f is improved, and high on-current characteristics can be obtained. In addition, since the on-state current can be increased, the transistor 500c can be miniaturized. Further, since the transistor 500c has a structure in which the semiconductor layer 531 is surrounded by the conductive layer 521 and the conductive layer 523, the mechanical strength of the transistor 500f can be increased.

Note that the transistor 500c can be formed without the conductive layer 523. In this case, the transistor 500c is a so-called channel protection transistor and has a bottom gate structure.

[Configuration example 4]
Next, an example of the structure of the transistor will be described with reference to FIGS. 34 (A), (B), (C), and (D).

34A and 34B are cross-sectional views of the transistor 500d, and FIGS. 34C and 34D are cross-sectional views of the transistor 500e. Note that the transistor 500d is a modification of the transistor 500b described above, and the transistor 500e is a modification of the transistor 500c described above. Accordingly, in FIGS. 34A, 34B, 34C, and 34D, portions having functions similar to those of the transistor 500b and the transistor 500c are denoted by the same reference numerals, and detailed description thereof is omitted.

Note that FIG. 34A is a cross-sectional view in the channel length direction of the transistor 500d, and FIG. 34B is a cross-sectional view in the channel width direction of the transistor 500d. FIG. 34C is a cross-sectional view of the transistor 500e in the channel length direction, and FIG. 34D is a cross-sectional view of the transistor 500e in the channel width direction.

A transistor 500d illustrated in FIGS. 34A and 34B is not provided with the conductive layer 523 and the opening 535 as compared with the transistor 500b. The transistor 500d is different from the transistor 500b in the structures of the insulating layer 512, the conductive layer 522a, and the conductive layer 522b.

In the transistor 500d, the insulating layer 512 includes an insulating layer 512c and an insulating layer 512d over the insulating layer 512c. The insulating layer 512c has a function of supplying oxygen to the semiconductor layer 531 and a function of suppressing entry of impurities (typically, water, hydrogen, and the like). As the insulating layer 512c, an aluminum oxide film, an aluminum oxynitride film, or an aluminum nitride oxide film can be used. In particular, the insulating layer 512c is preferably an aluminum oxide film formed by a reactive sputtering method. In addition, as an example of a method for forming an aluminum oxide film by a reactive sputtering method, the following method can be given.

First, a mixed gas of an inert gas (typically Ar gas) and oxygen gas is introduced into the sputtering chamber. Subsequently, an aluminum oxide film can be formed by applying a voltage to the aluminum target disposed in the sputtering chamber. In addition, as a power supply which applies a voltage to an aluminum target, DC power supply, AC power supply, or RF power supply is mentioned. In particular, use of a DC power source is preferable because productivity is improved.

The insulating layer 512d has a function of suppressing entry of impurities (typically water, hydrogen, and the like). As the insulating layer 512d, a silicon nitride film, a silicon nitride oxide film, or a silicon oxynitride film can be used. In particular, the insulating layer 512d is preferably a silicon nitride film formed by PECVD. A silicon nitride film formed by PECVD is preferable because a high film density can be easily obtained. Note that a silicon nitride film formed by PECVD may have a high hydrogen concentration in the film.

In the transistor 500d, since the insulating layer 512c is disposed below the insulating layer 512d, hydrogen contained in the insulating layer 512d does not diffuse or hardly diffuses to the semiconductor layer 531 side.

Note that the transistor 500d is a single-gate transistor, unlike the transistor 500b. By using a single gate transistor, the number of masks can be reduced, so that productivity can be increased.

A transistor 500e illustrated in FIGS. 34C and 34D is different in structure of the insulating layer 516 and the insulating layer 512 from the transistor 500c. Specifically, the transistor 500e includes an insulating layer 516a instead of the insulating layer 516, and includes an insulating layer 512d instead of the insulating layer 512.

The insulating layer 516a has a function similar to that of the insulating layer 512c.

With the structure of the transistor 500d and the transistor 500e, the structure can be manufactured using an existing production line without much capital investment. For example, a hydrogenated amorphous silicon manufacturing plant can be easily replaced with an oxide semiconductor manufacturing plant.

[Configuration example 5]
Next, as an example of the structure of the transistor, a transistor 500f will be described with reference to FIGS. FIG. 35A is a top view of the transistor 500f. 35B corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line X1-X2 in FIG. 35A, and FIG. 35C is between the dashed-dotted line Y1-Y2 shown in FIG. This corresponds to a cross-sectional view of the cut surface in FIG.

35A, 35B, and 35C includes a conductive layer 521 over the insulating layer 524, an insulating layer 511 over the conductive layer 521 and the insulating layer 524, and a semiconductor over the insulating layer 511. The insulating layer 512 over the semiconductor layer 531, the conductive layer 523 over the insulating layer 512, and the insulating layer 515 over the insulating layer 511, the semiconductor layer 531, and the conductive layer 523 are included. Note that the semiconductor layer 531 includes a channel formation region 531 i overlapping with the conductive layer 523, a source region 531 s in contact with the insulating layer 515, and a drain region 531 d in contact with the insulating layer 515.

The insulating layer 515 includes nitrogen or hydrogen. When the insulating layer 515 is in contact with the source region 531s and the drain region 531d, nitrogen or hydrogen in the insulating layer 515 is added to the source region 531s and the drain region 531d. In the source region 531 s and the drain region 531 d, the carrier density is increased by adding nitrogen or hydrogen.

The transistor 500f may include a conductive layer 522a electrically connected to the source region 531s through an opening 536a provided in the insulating layer 515. The transistor 500f may include a conductive layer 522b electrically connected to the drain region 531d through an opening 536b provided in the insulating layer 515.

The insulating layer 511 functions as a first gate insulating layer, and the insulating layer 512 functions as a second gate insulating layer. The insulating layer 515 functions as a protective insulating layer.

The insulating layer 512 has an excess oxygen region. When the insulating layer 512 includes the excess oxygen region, excess oxygen can be supplied to the channel formation region 531 i included in the semiconductor layer 531. Accordingly, oxygen vacancies that can be formed in the channel formation region 531i can be filled with excess oxygen; thus, a highly reliable display device can be provided.

Note that in order to supply excess oxygen into the semiconductor layer 531, excess oxygen may be supplied to the insulating layer 511 formed below the semiconductor layer 531. In this case, excess oxygen contained in the insulating layer 511 can be supplied to the source region 531s and the drain region 531d included in the semiconductor layer 531. When excess oxygen is supplied into the source region 531s and the drain region 531d, the resistance of the source region 531s and the drain region 531d may increase.

On the other hand, with the structure in which excess oxygen is included in the insulating layer 512 formed over the semiconductor layer 531, excess oxygen can be selectively supplied only to the channel formation region 531i. Alternatively, after excess oxygen is supplied to the channel formation region 531i, the source region 531s, and the drain region 531d, the carrier density of the source region 531s and the train region 531d is selectively increased, so that the source region 531s and the drain region 531d are increased. It is possible to suppress the increase in resistance.

The source region 531s and the drain region 531d included in the semiconductor layer 531 each preferably include an element that forms oxygen vacancies or an element that bonds to oxygen vacancies. As an element that forms oxygen vacancies or an element that combines with oxygen vacancies, typically, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like can be given. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. In the case where one or more elements that form oxygen vacancies are included in the insulating layer 515, they diffuse from the insulating layer 515 into the source region 531s and the drain region 531d, and / or the source region 531s is formed by impurity addition treatment, and It is added into the drain region 531d.

When the impurity element is added to the metal oxide, the bond between the metal element in the metal oxide and oxygen is cut, and oxygen vacancies are formed. Alternatively, when the impurity element is added to the metal oxide, oxygen bonded to the metal element in the metal oxide is bonded to the impurity element, oxygen is released from the metal element, and oxygen vacancies are formed. As a result, in the metal oxide, the carrier density is increased and the conductivity is increased.

The conductive layer 521 has a function as a first gate, the conductive layer 523 has a function as a second gate, the conductive layer 522a has a function as a source, and the conductive layer 522b Has a function as a drain.

As shown in FIG. 35C, the insulating layer 511 and the insulating layer 512 are provided with an opening 537. In addition, the conductive layer 521 is electrically connected to the conductive layer 523 through the opening 537. Therefore, the same potential is applied to the conductive layer 521 and the conductive layer 523. Note that different potentials may be applied to the conductive layer 521 and the conductive layer 523 without providing the opening 537. Alternatively, the conductive layer 521 may be used as a light-blocking film without providing the opening 537. For example, when the conductive layer 521 is formed using a light-blocking material, light from below irradiated to the channel formation region 531i can be suppressed.

As shown in FIGS. 35B and 35C, the semiconductor layer 531 includes a conductive layer 521 having a function as a first gate and a conductive layer 523 having a function as a second gate. It is located so as to face each other, and is sandwiched between conductive layers that function as two gates.

Similarly to the

transistors

500a, 500b, and 500c, the transistor 500f has an s-channel structure. With such a structure, the semiconductor layer 531 included in the transistor 500f is electrically connected to the conductive layer 521 having a function as a first gate and the electric field of the conductive layer 523 having a function as a second gate. Can be surrounded.

Since the transistor 500f has an s-channel structure, an electric field for inducing a channel by the conductive layer 521 or the conductive layer 523 can be effectively applied to the semiconductor layer 531. Accordingly, the current driving capability of the transistor 500f is improved, and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 500f can be miniaturized. In addition, since the transistor 500f has a structure in which the semiconductor layer 531 is surrounded by the conductive layer 521 and the conductive layer 523, the mechanical strength of the transistor 500f can be increased.

Note that the transistor 500f may be referred to as a TGSA (Top Gate Self Align) FET because of the position of the conductive layer 523 with respect to the semiconductor layer 531 or the formation method of the conductive layer 523.

Note that the transistor 500f may have a structure in which two or more semiconductor layers 531 are stacked as in the transistor 500b.

In the transistor 500f, the insulating layer 512 is provided only in a portion where the insulating layer 512 overlaps with the conductive layer 523; however, the present invention is not limited to this, and the insulating layer 512 can cover the semiconductor layer 531. Alternatively, the conductive layer 521 may be omitted.

Further, an aluminum oxide layer may be provided between the insulating layer 512 and the conductive layer 523. By providing the aluminum oxide layer, excess oxygen contained in the insulating layer 512 can be hardly diffused to the conductive layer 523 side.

In addition, the conductive layer 523 is preferably formed of a material in which at least a region in contact with the insulating layer 512 is difficult to diffuse oxygen. Examples of such materials include aluminum and molybdenum. For example, the conductive layer 523 may have a two-layer structure in which aluminum is provided on the insulating layer 512 side and titanium is provided thereover. Alternatively, the conductive layer 523 may have a three-layer structure in which molybdenum is provided on the insulating layer 512 side and aluminum and titanium are provided thereover.

This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 8)
In this embodiment, a structure example of a display device using a liquid crystal element and a structure example of a display device using an EL element will be described. 36A, a sealant 4005 is provided so as to surround the display portion 115 provided over the first substrate 4001, and the display portion 115 is sealed with the sealant 4005 and the second substrate 4006. .

The display portion 115 has a structure similar to that of the display portion 110 or the display portion 210 described in the above embodiment.

In FIG. 36A, the scan line driver circuit 121a, the signal line driver circuit 131a, the signal line driver circuit 132a, and the common line driver circuit 141a each include a plurality of integrated circuits 4042 provided over the printed board 4041. The integrated circuit 4042 is formed using a single crystal semiconductor or a polycrystalline semiconductor. The signal line driver circuit 131a and the signal line driver circuit 132a function in the same manner as the signal line driver circuit 131 described in the above embodiment. The scan line driver circuit 121a functions in the same manner as the scan line driver circuit 121 described in the above embodiment. The common line driver circuit 141a functions similarly to the common line driver circuit 141 described in the above embodiment.

Various signals and potentials supplied to the scan line driver circuit 121a, the common line driver circuit 141a, the signal line driver circuit 131a, and the signal line driver circuit 132a are supplied via an FPC (FPC: Flexible printed circuit) 4018.

An integrated circuit 4042 included in the scan line driver circuit 121 a and the common line driver circuit 141 a has a function of supplying a selection signal to the display portion 115. The integrated circuit 4042 included in the signal line driver circuit 131 a and the signal line driver circuit 132 a has a function of supplying a video signal to the display portion 115. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealant 4005 on the first substrate 4001 by a TAB (Tape Automated Bonding) method.

Note that a connection method of the integrated circuit 4042 is not particularly limited, and a wire bonding method, a COG (Chip On Glass) method, a TCP (Tape Carrier Package) method, a COF (Chip On Film) method, or the like can be used. it can.

FIG. 36B illustrates an example in which the integrated circuit 4042 included in the signal line driver circuit 131a and the signal line driver circuit 132a is mounted by a COG method. Further, with the use of the transistor described in any of the above embodiments, part or the whole of a driver circuit can be formed over the same substrate as the display portion 115 to form a system-on-panel.

FIG. 36B illustrates an example in which the scan line driver circuit 121a and the common line driver circuit 141a are formed over the same substrate as the display portion 115. By forming the driver circuit at the same time as the pixel circuit in the display portion 115, the number of components can be reduced. Therefore, productivity can be improved.

In FIG. 36B, a sealant 4005 is provided so as to surround the display portion 115 provided over the first substrate 4001, the scan line driver circuit 121a, and the common line driver circuit 141a. In addition, a second substrate 4006 is provided over the display portion 115, the scan line driver circuit 121a, and the common line driver circuit 141a. Therefore, the display portion 115, the scan line driver circuit 121a, and the common line driver circuit 141a are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006.

FIG. 36B illustrates an example in which the signal line driver circuit 131a and the signal line driver circuit 132a are separately formed and mounted on the first substrate 4001, but the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

In some cases, the display device includes a panel in which the display element is sealed, and a module in which an IC including a controller or the like is mounted on the panel.

The display portion and the scan line driver circuit provided over the first substrate include a plurality of transistors. The transistor described in any of the above embodiments can be used as the transistor.

The transistor included in the peripheral driver circuit and the transistor included in the pixel circuit in the display portion may have the same structure or different structures. The transistors included in the peripheral driver circuit may all have the same structure, or two or more structures may be used in combination. Similarly, the transistors included in the pixel circuit may all have the same structure, or two or more structures may be used in combination.

37A and 37B are cross-sectional views of a portion indicated by a chain line N1-N2 in FIG. 36B. The display device illustrated in FIGS. 37A and 37B includes an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019. In FIGS. 37A and 37B, the electrode 4015 is electrically connected to the wiring 4014 in the opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

The electrode 4015 is formed using the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed using the same conductive layer as the source electrode and the drain electrode of the transistor 4010 and the transistor 4011.

In addition, the display portion 115 and the scan line driver circuit 121a provided over the first substrate 4001 include a plurality of transistors, which are included in the display portion 115 in FIGS. 37A and 37B. The transistor 4010 and the transistor 4011 included in the scan line driver circuit 121a are illustrated. Note that FIGS. 37A and 37B illustrate bottom-gate transistors as the transistor 4010 and the transistor 4011.

In FIGS. 37A and 37B, the insulating layer 4112 is provided over the

transistors

4010 and 4011. In FIG. 37B, a partition wall 4510 is formed over the insulating layer 4112.

In addition, the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. In addition, the transistor 4010 and the transistor 4011 include an electrode 4017 formed over the insulating layer 4111. The electrode 4017 can function as a back gate electrode.

As the transistor 4010 and the transistor 4011, any of the transistors described in the above embodiments can be used.

In addition, the display device illustrated in FIGS. 37A and 37B includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same step as the gate electrode of the transistor 4010 and an electrode formed in the same step as the source electrode and the drain electrode. Each electrode overlaps with the insulating layer 4103 interposed therebetween.

In general, the capacitance of a capacitor provided in the pixel portion of the display device is set so that charge can be held for a predetermined period in consideration of leakage current of a transistor arranged in the pixel portion. The capacity of the capacitor may be set in consideration of the off-state current of the transistor.

The transistor 4010 provided in the display portion 115 is electrically connected to the display element. FIG. 37A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 37A, a liquid crystal element 4013 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 interposed therebetween.

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Yes. A spherical spacer may be used.

If necessary, an optical member (optical substrate) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source. Further, a micro LED or the like may be used as the backlight and the sidelight.

In the display device illustrated in FIG. 37A, a light-blocking layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the substrate 4006 and the second electrode layer 4031.

Examples of the material that can be used for the light-shielding layer include carbon black, titanium black, metal, metal oxide, and composite oxide containing a solid solution of a plurality of metal oxides. The light shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. Alternatively, a stacked film of a film containing a material for the colored layer can be used for the light shielding layer. For example, a stacked structure of a film including a material used for a colored layer that transmits light of a certain color and a film including a material used for a colored layer that transmits light of another color can be used. It is preferable to use a common material for the coloring layer and the light-shielding layer because the apparatus can be shared and the process can be simplified.

Examples of materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, and the like. The method for forming the light shielding layer and the colored layer may be performed in the same manner as the method for forming each layer described above. For example, the ink jet method may be used.

In addition, the display device illustrated in FIGS. 37A and 37B includes an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, insulating layers that hardly transmit an impurity element are used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, entry of impurities from the outside can be prevented.

Alternatively, a light-emitting element utilizing electroluminescence (also referred to as an “EL element”) can be used as a display element included in the display device. An EL element includes a layer containing a light-emitting compound (also referred to as an “EL layer”) between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the light-emitting substance contained in the EL layer emits light.

The EL element is distinguished depending on whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage, electrons from one electrode and holes from the other electrode are injected into the EL layer. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

Note that in addition to the light-emitting compound, the EL layer includes a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, or a bipolar layer. Material (a material having a high electron transporting property and a high hole transporting property) may be included.

The EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes may be transparent. Then, a transistor and a light emitting element are formed over the substrate, and a top emission structure that extracts light from a surface opposite to the substrate, a bottom emission structure that extracts light from a surface on the substrate side, There is a light emitting element having a dual emission structure in which light emission is extracted from both sides, and any light emitting element having an emission structure can be applied.

FIG. 37B illustrates an example of a light-emitting display device (also referred to as an “EL display device”) using a light-emitting element as a display element. A light-emitting element 4513 which is a display element is electrically connected to a transistor 4010 provided in the display portion 115. Note that the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031; however, the structure is not limited to this structure. The structure of the light-emitting element 4513 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4513, or the like.

A partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material and form an opening on the first electrode layer 4030 so that the side surface of the opening is an inclined surface formed with a continuous curvature.

The light emitting layer 4511 may be composed of a single layer or a plurality of layers stacked.

The light emission color of the light emitting element 4513 can be changed to white, red, green, blue, cyan, magenta, yellow, or the like depending on the material forming the light emitting layer 4511.

As a method for realizing color display, there are a method in which a light emitting element 4513 having a white emission color and a colored layer are combined, and a method in which a light emitting element 4513 having a different emission color is provided for each pixel. The former method is more productive than the latter method. On the other hand, in the latter method, since it is necessary to make a light emitting layer 4511 for each pixel, productivity is inferior to the former method. However, in the latter method, it is possible to obtain an emission color with higher color purity than in the former method. In addition to the latter method, the color purity can be further increased by providing the light-emitting element 4513 with a microcavity structure.

Note that the light-emitting layer 4511 may include an inorganic compound such as a quantum dot. For example, a quantum dot can be used for a light emitting layer to function as a light emitting material.

A protective layer may be formed over the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 4513. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed. In addition, a filler 4514 is provided and sealed in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. As described above, it is preferable to package (enclose) the protective film with a protective film (bonded film, ultraviolet curable resin film, or the like) or a cover material that has high hermeticity and little degassing so as not to be exposed to the outside air.

As the filler 4514, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon. PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB ( Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Further, the filler 4514 may contain a desiccant.

As the sealant 4005, a glass material such as glass frit, or a resin material such as a two-component mixed resin, a curable resin that cures at normal temperature, a photocurable resin, or a thermosetting resin can be used. Further, the sealing material 4005 may contain a desiccant.

Further, if necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the emission surface of the light emitting element. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

In addition, when the light-emitting element has a microcavity structure, light with high color purity can be extracted. Further, by combining the microcavity structure and the color filter, the reflection can be reduced and the visibility of the display image can be improved.

In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, and the like) that apply a voltage to the display element, a direction of light to be extracted, a place where the electrode layer is provided, and What is necessary is just to select translucency and reflectivity by the pattern structure of an electrode layer.

The first electrode layer 4030 and the second electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide. A light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

The first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). , Chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) and other metals, or alloys thereof, or One or more metal nitrides can be used.

Alternatively, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

In addition, since the transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the driving circuit. The protection circuit is preferably configured using a non-linear element.

(Embodiment 9)
In this embodiment, electronic devices to which the display system of one embodiment of the present invention can be applied will be described with reference to FIGS.

An example of an electronic device will be described with reference to FIGS. According to one embodiment of the present invention, good display quality and high visibility can be realized even with a display device that is large and / or high definition. Therefore, it can be suitably used for a television device, digital signage, a portable electronic device, a wearable electronic device (wearable device), an electronic book terminal, and the like. It can also be used for VR (Virtual Reality) devices and AR (Augmented Reality) devices.

An electronic device using the display system of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using non-contact power transmission.

Secondary batteries include, for example, lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) using gel electrolyte, nickel metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel A zinc battery, a silver zinc battery, etc. are mentioned.

An electronic device using the display system of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit. In the case where the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

An electronic device using the display system of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness , Electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, or infrared measurement function).

An electronic device using the display system of one embodiment of the present invention can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication A function, a function of reading a program or data recorded on a recording medium, and the like can be provided.

By using the display system of one embodiment of the present invention, display quality or the like of an electronic device can be improved.

Further, in an electronic apparatus having a plurality of display units, a function that displays image information mainly on one display unit and mainly displays character information on another display unit, or parallax is considered in the plurality of display units. By displaying an image, a function of displaying a stereoscopic image can be provided. Furthermore, in an electronic device having an image receiving unit, a function for capturing a still image or a moving image, a function for automatically or manually correcting the captured image, and a function for saving the captured image in a recording medium (externally or incorporated in the electronic device) A function of displaying the photographed image on the display portion can be provided. Note that the functions of the electronic device of one embodiment of the present invention are not limited thereto, and the electronic device can have various functions.

FIG. 38A illustrates a television device 1810 using the display system of one embodiment of the present invention. A television device 1810 includes a display portion 1811, a housing 1812, a speaker 1813, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.

The television device 1810 can be operated by a remote controller 1814.

Examples of broadcast radio waves that can be received by the television device 1810 include ground waves or radio waves transmitted from satellites. As broadcast radio waves, there are analog broadcasts, digital broadcasts, etc., and video and audio, or audio-only broadcasts. For example, broadcast radio waves transmitted in a specific frequency band in the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received. In addition, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. Accordingly, an image having a resolution exceeding full high-definition can be displayed on the display unit 1831. For example, an image having a resolution of 4K, 8K, 16K, or higher can be displayed.

A configuration for generating an image to be displayed on the display unit 1831 using broadcast data transmitted by a data transmission technique via a computer network such as the Internet, a LAN (Local Area Network), or Wi-Fi (registered trademark). It is good. At this time, the television device 1810 may not have a tuner.

FIG. 38B illustrates a digital signage 1820 using the display system of one embodiment of the present invention. The digital signage 1820 is attached to a cylindrical column 1822. The digital signage 1820 has a display portion 1821.

As the display portion 1821 is wider, the amount of information that can be provided at a time can be increased. Moreover, the wider the display portion 1821 is, the easier it is to be noticed by humans. For example, the advertising effect of advertisement can be enhanced.

It is preferable to use a touch panel for the display portion 1821 because not only an image or a moving image can be displayed on the display portion 1821 but also a user can operate intuitively. In addition, when it is used for providing information such as route information or traffic information, usability can be improved by an intuitive operation.

FIG. 38C illustrates a laptop personal computer 1830 using the display system of one embodiment of the present invention. The personal computer 1830 includes a display portion 1831, a housing 1832, a touch pad 1833, a connection port 1834, and the like.

The touch pad 1833 functions as an input unit such as a pointing device or a pen tablet, and can be operated with a finger, a stylus, or the like.

In addition, a display element is incorporated in the touch pad 1833. As shown in FIG. 38C, by displaying the input key 1835 on the surface of the touch pad 1833, the touch pad 1833 can be used as a keyboard. At this time, when the input key 1835 is touched, a vibration module may be incorporated in the touch pad 1833 in order to realize tactile sensation by vibration.

FIG. 38D illustrates an example of a portable information terminal using the display system of one embodiment of the present invention. A portable information terminal 1840 illustrated in FIG. 38D includes a housing 1841, a display portion 1842, operation buttons 1843, an external connection port 1844, a speaker 1845, a microphone 1846, a camera 1847, and the like.

The portable information terminal 1840 includes a touch sensor in the display unit 1842. Any operation such as making a call or inputting characters can be performed by touching the display portion 1842 with a finger, a stylus, or the like.

Further, by operating the operation button 1843, the power ON / OFF operation and the type of image displayed on the display unit 1842 can be switched. For example, the mail creation screen can be switched to the main menu screen.

Further, by providing a detection device such as a gyro sensor or an acceleration sensor inside the portable information terminal 1840, the orientation (portrait or landscape) of the portable information terminal 1840 is determined, and the screen display orientation of the display unit 1842 is determined. It can be switched automatically. The screen display direction can also be switched by touching the display portion 1842, operating the operation buttons 1843, or inputting voice using the microphone 1846.

The portable information terminal 1840 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. The portable information terminal 1840 can execute various applications such as mobile phone, electronic mail, text browsing and creation, music playback, video playback, Internet communication, and games.

FIGS. 38E and 38F illustrate an example of a portable information terminal 1850 using the display system of one embodiment of the present invention. The portable information terminal 1850 includes a housing 1851, a housing 1852, a display portion 1853, a display portion 1854, a hinge portion 1855, and the like.

The housing 1851 and the housing 1852 are connected by a hinge portion 1855. The portable information terminal 1850 can open the housing 1851 and the housing 1852 as illustrated in FIG. 38F from the folded state as illustrated in FIG.

For example, document information can be displayed on the display portion 1853 and the display portion 1854 and can also be used as an electronic book terminal. In addition, a still image or a moving image can be displayed on the display portion 1853 and the display portion 1854.

Thus, since the portable information terminal 1850 can be folded when being carried, it is excellent in versatility.

Note that the housing 1851 and the housing 1852 may include a power button, an operation button, an external connection port, a speaker, a microphone, and the like.

FIG. 39A illustrates an appearance of a camera 1860 using the display system of one embodiment of the present invention with the viewfinder 1861 attached.

The camera 1860 includes a housing 1869, a display portion 1862, operation buttons 1863, a shutter button 1864, and the like. In addition, a detachable lens 1865 is attached to the camera 1860.

Although the lens 1865 can be removed from the housing 1869 and replaced as the camera 1860 here, the lens 1865 and the housing may be integrated.

The camera 1860 can capture an image by pressing a shutter button 1864. Further, the display portion 1862 has a function as a touch panel, and can be imaged by touching the display portion 1862.

A housing 1869 of the camera 1860 includes a mount having electrodes, and can connect a stroboscopic device or the like in addition to the finder 1861.

The viewfinder 1861 includes a housing 1866, a display portion 1867, a button 1868, and the like. The display system of one embodiment of the present invention may be used for the viewfinder 1861.

The housing 1866 has a mount that engages with the mount of the camera 1860, and the finder 1861 can be attached to the camera 1860. Further, the mount includes an electrode, and an image received from the camera 1860 through the electrode can be displayed on the display portion 1867.

The button 1868 has a function as a power button. A button 1868 can switch on / off the display of the display portion 1867.

The display device of one embodiment of the present invention can be applied to the display portion 1862 of the camera 1860 and the display portion 1867 of the viewfinder 1861.

Note that in FIG. 39A, the camera 1860 and the viewfinder 1861 are separate electronic devices and can be attached and detached. However, the housing 1869 of the camera 1860 includes the display device of one embodiment of the present invention. A finder may be built in.

FIG. 39B illustrates the appearance of a head mounted display 1870 using the display system of one embodiment of the present invention.

The head mounted display 1870 includes a mounting portion 1871, a lens 1872, a main body 1873, a display portion 1874, a cable 1875, and the like. In addition, a battery 1876 is built in the mounting portion 1871.

The cable 1875 supplies power from the battery 1876 to the main body 1873. The main body 1873 includes a wireless receiver and the like, and can display video information such as received image data on the display portion 1874. In addition, it is possible to use the user's line of sight as an input unit by capturing the movement of the user's eyeball or eyelid with a camera provided in the main body 1873 and calculating the coordinates of the user's line of sight based on the information. it can.

In addition, the mounting portion 1871 may be provided with a plurality of electrodes at a position where the user touches the user. The main body 1873 may have a function of recognizing the user's line of sight by detecting a current flowing through the electrode in accordance with the movement of the user's eyeball. Moreover, you may have a function which monitors a user's pulse by detecting the electric current which flows into the said electrode. The mounting portion 1871 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 1874. Further, the movement of the user's head or the like may be detected, and the video displayed on the display unit 1874 may be changed in accordance with the movement.

FIGS. 39C and 39D illustrate the appearance of a head mounted display 1880 using the display system of one embodiment of the present invention.

The head mounted display 1880 includes a housing 1881, two display portions 1882, operation buttons 1883, and a band-shaped fixture 1884.

The head mounted display 1880 includes two display units in addition to the functions of the head mounted display 1870.

By having two display portions 1882, the user can see one display portion for each eye. Thereby, even when performing three-dimensional display using parallax or the like, a high-resolution video can be displayed. In addition, the display unit 1882 is curved in an arc shape with the user's eyes roughly at the center. Thereby, since the distance from the user's eyes to the display surface of the display unit is constant, the user can see a more natural image. Even if the luminance and chromaticity of the light from the display unit changes depending on the viewing angle, the user's eyes are positioned in the normal direction of the display surface of the display unit, The effect can be ignored. Therefore, a more realistic image can be displayed.

The operation button 1883 has a function as a power button or the like. In addition to the operation buttons 1883, buttons may be provided.

In addition, as shown in FIG. 39E, a lens 1885 may be provided between the display portion 1882 and the position of the user's eyes. The lens 1885 allows the user to enlarge the display portion 1882, so that a sense of reality is further enhanced. At this time, as shown in FIG. 39E, a dial 1886 for changing the position of the lens for diopter adjustment may be provided.

The display device of one embodiment of the present invention can be applied to the display portion 1882. Since the display device of one embodiment of the present invention has extremely high definition, even if the display device is enlarged using the lens 1885 as illustrated in FIG. 39E, the pixel is not visually recognized by the user and more realistic. High video can be displayed.

FIG. 39F illustrates an example of a television device using the display system of one embodiment of the present invention. In the television device 1890, a display portion 1892 is incorporated in a housing 1891. Here, a structure in which the housing 1891 is supported by a stand 1893 is shown.

Operation of the television device 1890 illustrated in FIG. 39F can be performed with an operation switch included in the housing 1891 or a separate remote controller 1894. Alternatively, the display portion 1892 may be provided with a touch sensor, and may be operated by touching the display portion 1892 with a finger or the like. The remote controller 1894 may include a display unit that displays information output from the remote controller 1894. Channels and volume can be operated with an operation key or a touch panel included in the remote controller 1894, and an image displayed on the display portion 1892 can be operated.

Note that the television set 1890 is provided with a receiver, a modem, and the like. A general television broadcast can be received by the receiver. In addition, by connecting to a wired or wireless communication network via a modem, information communication is performed in one direction (from the sender to the receiver) or in two directions (between the sender and the receiver or between the receivers). It is also possible.

DESCRIPTION OF SYMBOLS 100 Display apparatus 110

Display part

111, 112 Pixel 121 Scan

line drive circuit

131, 132 Signal line drive circuit 141 Common

line drive circuit

227, 326, 327, 328, 329 Insulating layer 255

Impurity

310, 311, 320, 321

Transistor

322, 323 Electrode 324 Semiconductor layer 325 Transistor

Claims

a plurality of pixels arranged in m rows and n columns (m and n are each an integer of 2 or more);
m rows of scanning lines, n columns of video signal lines, and m + 1 common lines,
The m + 1 common lines extend in a direction substantially parallel to the m rows of scanning lines,
Each of the plurality of pixels includes a transistor and a display element,
The pixel in the x-th row and the j-th column (x is an integer of 1 to m-1 and j is an integer of 1 to n)
electrically connected to the scan line in the x-th row, the video signal line in the j-th column, and the x-th common line;
The pixel in the x row, j + 1 column is
Electrically connected to the scanning line of the x-th row, the video signal line of the (j + 1) th column, and the x + 1-th common line;
The pixel in the m-th row and the j-th column is
electrically connected to the m-th scanning line, the j-th column video signal line, and the m-th common line;
The pixel in the m-th row j + 1-th column is
A display device, wherein the display device is electrically connected to the m-th scanning line, the j + 1-th column video signal line, and the m + 1-th common line.
a plurality of pixels arranged in m rows and n columns (m and n are each an integer of 2 or more);
m rows of scanning lines, n columns of video signal lines, and m + 1 common lines,
The m + 1 common lines extend in a direction substantially parallel to the m rows of scanning lines,
Each of the plurality of pixels includes a transistor and a display element,
The pixel in the x-th row and the j-th column (x is an integer of 1 to m-1 and j is an integer of 1 to n)
electrically connected to the scanning line in the x-th row, the video signal line in the j-th column, and the x + 1-th common line;
The pixel in the x row, j + 1 column is
Electrically connected to the scanning line of the x-th row, the video signal line of the (j + 1) th column, and the x-th common line;
The pixel in the m-th row and the j-th column is
electrically connected to the scanning line in the m-th row, the video signal line in the j-th column, and the m + 1-th common line;
The pixel in the m-th row j + 1-th column is
The display device is electrically connected to the m-th scanning line, the (j + 1) -th column video signal line, and the m-th common line.
a plurality of pixels arranged in m rows and n columns (m and n are each an integer of 4 or more);
m rows of scanning lines;
n first video signal lines, n second video signal lines,
m + 1 common lines, and
The m + 1 common lines extend in a direction substantially parallel to the m rows of scanning lines,
Each of the plurality of pixels includes a transistor and a display element,
The pixel in the x-th row and the j-th column (x is an integer from 1 to m-2, j is an integer from 1 to n)
electrically connected to the scan line in the x-th row, the first video signal line in the j-th row, and the common line in the x-th row;
The pixel in the (x + 1) th row and jth column is
electrically connected to the scan line of the x + 1th row, the jth second video signal line, and the x + 1th common line;
The pixel in the x row, j + 1 column is
electrically connected to the scanning line in the x-th row, the j + 1-th first video signal line, and the x + 1-th common line;
The pixel in the x + 1 row j + 1 column is
electrically connected to the scan line in the (x + 1) th row, the second video signal line in the (j + 1) th row, and the common line in the (x + 2) th row,
The pixel in the (m−1) th row and jth column is
electrically connected to the (m-1) th scanning line, the jth first video signal line, and the (m-1) th common line;
The pixel in the m-th row and the j-th column is
electrically connected to the m-th scanning line, the j-th second video signal line, and the m-th common line;
The pixel in the (m−1) th row j + 1th column is
electrically connected to the (m-1) th scanning line, the (j + 1) th first video signal line, and the mth common line;
The pixel in the m-th row j + 1-th column is
A display device, wherein the display device is electrically connected to the m-th scanning line, the j + 1-th second video signal line, and the m + 1-th common line.
a plurality of pixels arranged in m rows and n columns (m and n are each an integer of 4 or more);
m rows of scanning lines;
n first video signal lines, n second video signal lines,
m + 1 common lines, and
The m + 1 common lines extend in a direction substantially parallel to the m rows of scanning lines,
Each of the plurality of pixels includes a transistor and a display element,
The pixel in the x-th row and the j-th column (x is an integer from 1 to m-2, j is an integer from 1 to n)
electrically connected to the scan line in the x-th row, the first video signal line in the j-th row, and the common line in the x + 1-th row,
The pixel in the (x + 1) th row and jth column is
electrically connected to the scan line in the x + 1th row, the jth second video signal line, and the x + 2 common line;
The pixel in the x row, j + 1 column is
electrically connected to the scanning line in the x-th row, the first video signal line in the (j + 1) th row, and the common line in the xth row,
The pixel in the x + 1 row j + 1 column is
electrically connected to the scan line in the x + 1th row, the j + 1th second video signal line, and the x + 1th common line;
The pixel in the (m−1) th row and jth column is
electrically connected to the (m-1) th scanning line, the jth first video signal line, and the mth common line;
The pixel in the m-th row and the j-th column is
electrically connected to the m-th scanning line, the j-th second video signal line, and the m + 1-th common line;
The pixel in the (m−1) th row j + 1th column is
electrically connected to the (m-1) th scanning line, the (j + 1) th first video signal line, and the (m-1) th common line,
The pixel in the m-th row j + 1-th column is
A display device, wherein the display device is electrically connected to the m-th scanning line, the j + 1-th second video signal line, and the m-th common line.
In any one of Claims 1 thru | or 4,
The display device, wherein the display element is a liquid crystal element.
In any one of Claims 1 thru | or 4,
In the transistor, a semiconductor layer in which a channel is formed contains silicon or a metal oxide.
In any one of Claims 1 thru | or 4,
The display device has a resolution of 8K or higher.
In any one of Claims 1 thru | or 4,
A display device having a display portion having a diagonal of 60 inches or more.
In any one of Claims 1 thru | or 4,
A display device having a frame frequency of 240 Hz or more.
A driving method of a display device according to claim 1 or 2,
During the period when the pixel in the p-th row (p is an integer of 1 to m-2) is selected,
A method for driving a display device, characterized by inverting the polarity of a voltage supplied to the p + 2 common line.
In claim 10,
During the period when the pixel in the (m-1) th row is selected,
A display device driving method, wherein the polarity of a voltage supplied to the first common line is inverted.
In claim 10,
During the period when the pixel in the m-th row is selected,
A display device driving method, wherein the polarity of a voltage supplied to the first common line is inverted.
In claim 10,
During the period when the pixel in the m-th row is selected,
A display device driving method, wherein the polarity of a voltage supplied to the second common line is inverted.
A driving method of a display device according to claim 3 or claim 4,
During the period when the pixel in the p-th row (p is an integer of 1 to m-3) is selected,
A driving method of a display device, wherein the polarity of the voltage supplied to the p + 2 common line and the polarity of the voltage supplied to the p + 3 common line are inverted.
In claim 14,
During the period in which the pixel in the (m-2) th row is selected,
A display device driving method, wherein the polarity of a voltage supplied to the first common line is inverted.
In claim 14,
During the period when the pixel in the m-th row is selected,
A display device driving method, wherein the polarity of a voltage supplied to the first common line is inverted.
In claim 14,
During the period when the pixel in the m-th row is selected,
A driving method of a display device, wherein the polarity of the voltage supplied to the second common line and the polarity of the voltage supplied to the third common line are inverted.