WO2018161431A1

WO2018161431A1 - Memory-based circuit board

Info

Publication number: WO2018161431A1
Application number: PCT/CN2017/083834
Authority: WO
Inventors: 叶勇云
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2017-03-10
Filing date: 2017-05-10
Publication date: 2018-09-13
Also published as: CN109154923A; CN206498588U

Abstract

A memory-based circuit board (1) is provided. A memory (2) is disposed on the circuit board (1). A processor (3) configured to control the memory (2) is further disposed on the circuit board (1). The memory (2) and the processor (3) both comprise at least two sets of signal lines. A line set identifier of each set of the signal lines of the memory (2) corresponds to a line set identifier of each set of the signal lines of the processor (3). Signal lines of the memory (2) and the processor (3) have no cross connection on the same layer of the circuit board. Line set identifiers of the connected memory (2) and the processor (3) do not correspond to each other. Thus, by exchanging signals between the memory (2) and the processor (3) using signal line sets as units, the arrangement of the signal lines of the memory (2) and the processor (3) is facilitated, and it is ensured that the signal lines of the two do not cross each other, such that communication quality of signals is ensured.

Description

Memory based board

Technical field

The present invention relates to memory wiring techniques, and more particularly to a memory based circuit board.

Background technique

With the rapid development of electronic technology, the size of circuit boards in electronic products, such as printed circuit boards (PCBs), has become smaller and smaller.

As a minimum system of electronic devices, a memory is usually disposed on a PCB, for example, a Double Data Rate Dynamic Random Access Memory ("DDR") and a processor that controls the operation of the memory. For a circuit board that uses a memory, the corresponding pin distribution between the processor and the memory is often difficult to achieve a one-to-one correspondence without a crossover, which causes a chaotic problem when the board is routed, and a chaotic trace is likely to cause Interference between signals affects signal quality; if you want to avoid crossover between processor and memory and reduce interference between signals, you need to extend the length of the trace on the board. The longer the trace takes up more circuits. The area of the board leads to an increase in the size of the board.

Summary of the invention

The present invention provides a memory-based circuit board for solving the technical problem of the chaos of the electrical signal between the memory on the circuit board and the processor and the signal interference caused by the prior art.

The present invention provides a memory-based circuit board on which the memory is disposed, and a processor for controlling the memory;

The memory and the processor each include at least two sets of signal lines;

a line group identifier of each group of signal lines on the memory corresponds to a line group identifier of each group of signal lines on the processor;

The signal line of the memory and the signal line of the processor are not cross-connected on the same layer circuit board; wherein the line group identifier of the connected memory and the line group identifier of the processor are Non-corresponding line group ID.

Optionally, each group of signal lines includes a data signal with a preset bit capacity, and further includes a control signal for transmitting the data signal for controlling the preset bit capacity.

Optionally, the control signal includes at least: a data synchronization signal control bit; and a data mask signal control bit.

Optionally, each bit of the data signal of the preset bit capacity in the two connected signal lines is connected to each other in an arbitrary order;

The data synchronization signal control bits in the two connected signal lines are correspondingly connected;

The data mask signal control bits in the two connected signal lines are correspondingly connected.

Optionally, the memory is a DDR chip;

The DDR chip is a DDR of a 16-bit data signal;

Correspondingly, the DDR chip and the processor both include a high 8-bit signal line and a low 8-bit signal line;

a high 8-bit signal line of the DDR chip is connected to a lower 8-bit signal line of the processor;

The lower 8-bit signal line of the DDR chip is connected to the upper 8-bit signal line of the processor.

Optionally, the low 8-bit signal line includes an 8-bit data signal of DQ0 to DQ7;

The high 8-bit signal line includes an 8-bit data signal of DQ8 to DQ15;

The data signals of the DQ0 to DQ7 of the DDR chip and the data signals of the DQ8 to DQ15 of the processor may be connected in an arbitrary order;

The data signals of the DQ8 to DQ15 of the DDR chip and the data signals of the DQ0 to DQ7 of the processor may be connected in an arbitrary order.

Optionally, the high 8-bit signal line includes a data synchronization signal control bit UDQS for controlling the DQ8 to DQ15; and a data mask signal control bit UDQM for controlling the DQ8 to DQ15;

The lower 8-bit signal line includes a data synchronization signal control bit LDQS for controlling the DQ0 to DQ7; and a data mask signal control bit LDQM for controlling the DQ0 to DQ7;

The UDQS of the DDR chip is connected to the LDQS of the processor, the UDQM of the DDR chip is connected to the LDQM of the processor; the LDQS of the DDR chip and the processing The UDQS connection of the device, the DDR chip The LDQM is coupled to the UDQM of the processor.

Optionally, the memory is any one of the following chip types: a DDR chip with a 16-bit data signal, a DDR chip with a 32-bit data signal, and a DDR chip with a 64-bit data signal.

Optionally, the memory is any one of the following chip types: DDR1, DDR2, DDR3, DDR4.

A memory-based circuit board provided by the present invention, a memory is disposed on the circuit board, and a processor for controlling the memory is further disposed; the memory and the processor each include at least two sets of signal lines; wherein each group on the memory The line group identifier of the signal line corresponds to the line group identifier of each group of signal lines on the processor; the signal line of the memory and the signal line of the processor are not cross-connected on the same layer circuit board; wherein, the line of the connected memory line The group ID and the line group ID of the processor are non-corresponding line group identifiers. Therefore, by exchanging the signal lines between the memory and the processor in units of signal lines, the routing of the signal lines between the memory and the processor is facilitated, and the signal lines between the two are not crossed, thereby ensuring the communication quality between the signals.

DRAWINGS

1 is a schematic structural diagram of a memory-based circuit board according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a memory-based circuit board according to another exemplary embodiment of the present invention; FIG.

FIG. 3 is a schematic structural diagram of a memory-based circuit board according to another exemplary embodiment of the present invention.

Reference mark:

1. Circuit board; 2. Memory/DDR chip; 3. Processor; 4. Signal line pin; 5. Line group.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the embodiments of the present invention. It should be noted that in the drawings or the description, similar or identical components use the same attached Figure mark.

FIG. 1 is a schematic structural diagram of a memory-based circuit board according to an exemplary embodiment of the present invention. As shown in FIG. 1 , a memory-based circuit board 1 is provided in the embodiment, and a memory 2 is disposed on the circuit board 1 . A processor 3 for controlling the memory 2 is also provided; the memory 2 and the processor 3 each include at least two sets of signal lines; a line group identification of each group of signal lines on the memory 2 and a line group of each set of signal lines on the processor 3. Corresponding to the identification; wherein the pins of the signal line are indicated by the numeral 4, the line group of the signal line is indicated by the numeral 5, and the identification of the different line groups is distinguished by the capital letters of A, B, C, D, ... . The signal line of the memory 2 and the signal line of the processor 3 are not cross-connected on the same layer circuit board; wherein the line group identifier of the connected memory 2 and the line group identifier of the processor 3 are non-corresponding line group identifiers.

Specifically, the circuit board 1 in FIG. 1 may be a printed circuit board (PCB), a flexible printed circuit board (FPC), a single-panel, a double-panel, a multi-layer circuit board, etc. This is not specifically limited, and those skilled in the art can select the corresponding circuit board according to the circuit characteristics. The circuit board 1 is provided with at least a memory 2, and a processor 3 that controls the memory 2 to perform an information storage operation. If the processor 3 needs to correctly deposit or retrieve information such as original data, program, intermediate operation result, final running result, etc., it is necessary to put each signal line pin 4 on the memory 2 chip and the processor 3 chip. Corresponding connection of each signal line pin 4, that is, as shown in FIG. 1, each data signal pin 4 in the line group 5 (A) of the memory 2 and the line group 5 (A) of the processor 3 The respective data signal pins 4 are correspondingly connected, thereby ensuring that the processor 3 can store the data information in the correct position in the memory 2, and can accurately extract the data information from the exact position in the memory 2. Therefore, as shown in FIG. 1, the line group identification of each group of signal lines on the memory 2 corresponds to the line group identification of each group of signal lines on the processor 3, for example, the line group 5 (A) on the memory 2 corresponds to processing. Line group 5 (A) on device 3, line group 5 (B) on memory 2 corresponds to line group 5 (B) on processor 3, line group 5 (C) on memory 2 corresponds to processor 3 Line group 5 (C), line group 5 (D) on memory 2 corresponds to line group 5 (D) on processor 3. Only four sets of line sets 5 are shown in FIG. 1, which are not limited to the number of line sets 5 included in the circuit board 1 in this embodiment. Both the memory 2 and the processor 3 in this embodiment include two sets. Or more than two sets of signal line groups 5. Assume that the layout of the line group 5 is as shown in FIG. 1, and if the shortest path is used, the line groups 5 (A), 5 (B), 5 (C), 5 (D) and the processor 3 on the memory 2 are used. Line group 5 (A), 5 (B), When 5(C) and 5(D) are connected, the line crossover will occur, causing interference between signals and degrading signal quality. Therefore, the line group 5 of the memory 2 and the line group 5 of the processor 3 can be grouped and grouped while ensuring that the signal line of the memory 2 and the signal line of the processor 3 are not cross-connected on the same layer circuit board 1. The signal exchange between them is to facilitate the routing of the board 1 to the utmost extent. As shown in the layout of FIG. 1, the line group 5 (B) of the memory 2 can be connected to the line group 5 (C) of the processor, the line group 5 (C) of the memory 2 and the line group 5 of the processor (B) ), the line group 5 (A) of the memory 2 is still connected to the line group 5 (A) of the processor, and the line group 5 (D) of the memory 2 is still connected to the line group 5 (D) of the processor, ensuring the memory The signal connections between the 2 and the processor 3 are the shortest and do not intersect each other.

The memory-based circuit board of this embodiment is provided with a memory on the circuit board, and a processor for controlling the memory; the memory and the processor each include at least two sets of signal lines; wherein each set of signals on the memory The line group identifier of the line corresponds to the line group identifier of each group of signal lines on the processor; the signal line of the memory and the signal line of the processor are not cross-connected on the same layer circuit board; wherein, the line group of the connected memory The line group identifier that identifies the processor and the processor is a non-corresponding line group identifier. Therefore, by exchanging the signal lines between the memory and the processor in units of signal lines, the routing of the signal lines between the memory and the processor is facilitated, and the signal lines between the two are not crossed, thereby ensuring the communication quality between the signals.

FIG. 2 is a schematic structural diagram of a memory-based circuit board according to another exemplary embodiment of the present invention. On the basis of the previous embodiment, further, each group of signal lines includes a data signal with a preset bit capacity. And further comprising a control signal for controlling the data signal of the preset bit capacity for transmission.

Specifically, the preset bit capacity in each group of signal lines refers to the capacity of the binary data information contained in each group of signals of the memory 2. Preferably, the preset bit capacity may be one of every 8 bits. A byte is a basic unit, which is an integer multiple of a byte unit, for example, an 8-bit data signal is a group, or a 16-bit data signal is a group, or a 32-bit data signal is a group, and in addition, each group Control signals for performing control operations on preset bit capacity data information, such as data synchronization, clock synchronization, mask control, and the like, are also included.

Optionally, the control signal may at least include: a data synchronization signal control bit; and a data mask signal control bit. The data synchronization signal control bit is used for clock synchronization control of receiving and transmitting data signals between the memory 2 and the processor 3. Data mask signal control bits are used in The data signal is masked during the read or write operation.

Optionally, referring to FIG. 2, each bit of the data signal of the preset bit capacity in the two connected signal lines may be connected to each other in an arbitrary order, and the control signal is a data synchronization signal control bit, and the data is masked. In the case of the code signal control bit, the data synchronization signal control bits in the two connected signal lines are correspondingly connected, and the data mask signal control bits in the two connected signal lines are correspondingly connected. That is, as shown in FIG. 2, assuming that the memory 2 is a memory of a 16-bit data signal, the signal line group 5 (A) and the signal line group 5 (B) are exchanged and connected according to the current layout of FIG. It is ensured that the traces on the same layer board 1 are not crossed, and the trace length is saved. Therefore, the low eight-bit data signals DQ0 to DQ7 of the memory 2 can be connected with the high eight-bit data signals DQ8 to DQ15 of the processor 3. And each of the data signals inside the upper eight bits or the lower eight bits of the data signal can be connected in any order, and does not necessarily have to be connected in the order of high to low or low to high of the data signals. That is, as shown in FIG. 2, the DQ1 of the memory 2 does not have to be connected to the DQ9 of the processor 3, and it can be connected to the DQ 13, that is, the signal line pins 4 of the respective data signals in the signal line group 5 can be in any order. The signal line pins 4 of the respective data signals in the connected signal line group 5 are connected. However, for the control signal, such as the data synchronization signal control bit (DQS) and the data mask signal control bit (DQM) in FIG. 2, it must be connected correspondingly, that is, the lower eight bits of the data signal of the memory 2 (DQ0) The data sync signal control bit (LDQS) to DQ7) is connected to the data sync signal control bit (UDQS) of the upper eight bit data signals (DQ8 to DQ15) of the controller 3, and the lower eight bits of the data signal of the memory 2 (DQ0) The data mask signal control bit (LDQM) to DQ7) is connected to the data mask signal control bit (UDQM) of the upper eight bit data signals (DQ8 to DQ15) of the controller 3.

The memory-based circuit board of the embodiment further includes a data signal of a preset bit capacity included in each group of signal lines, and a control signal for transmitting a data signal for controlling the preset bit capacity, such as a data synchronization signal control bit. The data mask signal control bits are properly wired. For example, the data bits of the preset bit capacity of the two sets of signal lines are connected to each other in an arbitrary order, and the data synchronization signals in the two sets of signal lines are controlled. The bit corresponding connection connects the data mask signal control bits in the two sets of connected signal lines. Therefore, the wiring flexibility between the data signal lines in the group is improved, and the control signal is effective and accurate for controlling the data signals in each signal line group, thereby effectively avoiding the occurrence of each signal line. Crossing and reducing signal quality issues.

FIG. 3 is a schematic structural diagram of a memory-based circuit board according to another exemplary embodiment of the present invention. On the basis of the foregoing embodiments, the memory 2 in the foregoing embodiment may be a DDR chip, that is, a dual Double Data Rate Dynamic Random Access Memory ("DDR"). Double Rate of DDR Compared to the traditional single data rate, DDR technology implements two read/write operations in one clock cycle, that is, a read/write operation is performed on the rising and falling edges of the clock, respectively.

There are many types of DDR chips suitable for use in the present invention. Alternatively, the memory 2 can be any of the following chip types: a DDR chip with a 16-bit data signal, a DDR chip with a 32-bit data signal, and a 64-bit data signal. DDR chip.

Optionally, the memory 2 can be any one of the following chip types: DDR1, DDR2, DDR3, DDR4. Different numbers represent DDR chips with different processes, different interfaces, and different performances (for example, different speeds). For example, DDR2: IDDR2/DDR II (Double Data Rate 2) SDRAM is a new generation memory technology standard developed by JEDEC (Joint Commission for Electronic Equipment Engineering). The biggest difference from the previous generation DDR memory technology standard is that although The basic method of simultaneous data transfer on the rising/falling edge of the clock is used, but DDR2 memory has twice the pre-read capability of the previous generation DDR memory (ie, 4-bit data read prefetch). In other words, DDR2 memory can read/write data at 4 times the speed of the external bus per clock and can run at 4 times the speed of the internal control bus.

It should be noted that the memory of different numbers of bits will have different layouts of the corresponding control signals. The invention is not limited to the number of bits of the memory bus, including but not limited to 8-bit memory, 16-bit memory, 32-bit memory, 64-bit memory, 128-bit memory, 256-bit memory, 512. Bit memory, etc. For example, for a 16-bit memory, the data synchronization signal control bit can be synchronized with the data synchronization signal control bit LDQS for controlling the low eight-bit data signal as described in the above embodiment, and controlling the high eight-bit data signal for synchronous data synchronization. The signal control bit UDQS, whose data mask signal control bit can be masked by the data mask signal control bit LDQM for controlling the low eight bit data signal as described in the above embodiment, controls the high eight bit data signal The data mask signal controls the bit UDQM. For a 32-bit memory, its data synchronization signal control bit generally identifies one data synchronization signal control bit configured for each 8-bit data signal with DQS0, DQS1, DQS2, DQS3; its data mask signal The control bits typically identify a data mask signal control bit for each 8-bit data signal with DQM0, DQM1, DQM2, DQM3. The DQS0 bit of the memory can be connected to any of the DQS1, DQS2, DQS3 bits in the processor. For example, the DQS0 of the memory is connected to the DQS1 of the processor, the DQM0 of the memory is connected to the DQM1 of the processor, and correspondingly, the DQS1 of the memory is The DQS0 of the processor is connected, and the DQM0 of the memory is connected to the DQM1 of the processor. In addition, for some DDR chips, there are data synchronization signal control bits (DQS) in the form of differential pairs. For example, DDR2, DDR3, DDR4 contain DQS+ and DQS- data synchronization signal control bits, then corresponding In the process of exchanging signal line groups, pay attention to the need to connect the DQS to the polarity. For example, for a DDR with a DQS differential pair, the LDQS of the memory is connected to the UDQS- of the processor, and correspondingly, the LDQS+ of the memory is connected to the UDQS+. For different types of DDR chips 2, the DDR with DDR chip 2 as a 16-bit data signal is taken as an example. For the 16-bit DDR chip 2, the DDR chip 2 and the processor 3 processing the DDR chip 2 are both Contains a high 8-bit signal line and a low 8-bit signal line; the upper 8-bit signal line of DDR chip 2 is connected to the lower 8-bit signal line of processor 3; the lower 8-bit signal line of DDR chip 2 is higher than processor 3. 8-bit signal line connection.

Optionally, the low 8-bit signal line includes an 8-bit data signal of DQ0 to DQ7; the upper 8-bit signal line includes an 8-bit data signal of DQ8 to DQ15; and the data signal of the DQ0 to DQ7 of the DDR chip 2 is The data signals of DQ8 to DQ15 of processor 3 can be connected in any order. The data signals of DQ8 to DQ15 of the DDR chip 2 and the data signals of DQ0 to DQ7 of the processor 3 can be connected in an arbitrary order. DQ0 of DDR chip 2 shown in FIG. 3 is connected to DQ11 of processor 3, DQ1 of DDR chip 2 is connected to DQ13 of processor 3; and DQ9 of DDR chip 2 is connected to DQ2 of processor 3, DQ10 of DDR chip 2 is connected. DQ7 of processor 3.

Optionally, the high 8-bit signal line includes a data synchronization signal control bit UDQS for controlling the DQ8 to DQ15; and a data mask signal control bit UDQM for controlling DQ8 to DQ15; the lower 8-bit signal line includes control The data synchronization signal control bit LDQS of DQ0 to DQ7; further includes a data mask signal control bit LDQM for controlling DQ0 to DQ7; wherein the UDQS of the DDR chip 2 is connected to the LDQS of the processor 3, and the UDQM of the DDR chip 2 and the processor 3 LDQM connection; LDQS of DDR chip 2 is connected to UDQS of processor 3, LDQM of DDR chip 2 is connected with UDQM of processor 3. That is, when DDR After the high 8-bit signal line in chip 2 and the lower 8-bit signal line are exchanged for signal line group 5, the upper UDQS in DDR chip 2 must be connected to the lower LDQS of processor 3; the lower LDQS in DDR chip 2 It must be connected to the upper UDQS of the processor 3; similarly, the upper UDQM in the DDR chip 2 must be connected to the lower LDQM of the processor 3, and the lower LDQM in the DDR chip 2 must be connected to the upper UDQM of the processor 3.

The memory-based circuit board of this embodiment is defined by specifically routing a DDR chip of a 16-bit data signal, such as connecting a high 8-bit signal line of the DDR chip to a low 8-bit signal line of the processor, and a low 8-bit signal. The line is connected to the upper 8-bit signal line of the processor; and the low 8-bit, high 8-bit data signals in the DDR chip and the processor can be connected in any order; UDQS, LDQS in the DDR chip and LDQS of the processor respectively UDQS and LDQM of the DDR chip are connected to the LDQM and UDQM of the processor respectively. Thereby, the flexibility of signal connection between the DDR chip and the processor is improved, the communication quality of the signal between the two is ensured, and the wiring between the DDR chip and each data signal line in each signal group of the processor is also improved. The quality also ensures the control effectiveness and accuracy of the control signal for the data signals in each signal line group, thereby effectively avoiding the problem of crossover between the signal lines and reducing the signal quality.

It should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently substituted; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention.

Claims

A memory based circuit board characterized in that

The memory board is provided with the memory, and a processor for controlling the memory is further provided;

The memory and the processor each include at least two sets of signal lines;

a line group identifier of each group of signal lines on the memory corresponds to a line group identifier of each group of signal lines on the processor;

The signal line of the memory and the signal line of the processor are not cross-connected on the same layer circuit board; wherein the line group identifier of the connected memory is non-corresponding to the line group identifier of the processor Line group ID.
A memory-based circuit board according to claim 1, wherein

Each set of signal lines includes a data signal of a preset bit capacity, and further includes a control signal for transmitting the data signal for controlling the preset bit capacity.
A memory-based circuit board according to claim 2, wherein

The control signal includes at least: a data synchronization signal control bit; a data mask signal control bit.
A memory-based circuit board according to claim 3, wherein

Connecting respective bits of the data signal of the preset bit capacity in the two connected signal lines to each other in an arbitrary order;

The data synchronization signal control bits in the two connected signal lines are correspondingly connected;

The data mask signal control bits in the two connected signal lines are correspondingly connected.
A memory-based circuit board according to any one of claims 1 to 4, characterized in that

The memory is a DDR chip;

The DDR chip is a DDR of a 16-bit data signal;

Correspondingly, the DDR chip and the processor both include a high 8-bit signal line and a low 8-bit signal line;

a high 8-bit signal line of the DDR chip is connected to a lower 8-bit signal line of the processor;

The lower 8-bit signal line of the DDR chip is connected to the upper 8-bit signal line of the processor.
A memory-based circuit board according to claim 5, wherein

The low 8-bit signal line includes an 8-bit data signal of DQ0 to DQ7;

The high 8-bit signal line includes an 8-bit data signal of DQ8 to DQ15;

The data signals of the DQ0 to DQ7 of the DDR chip and the data signals of the DQ8 to DQ15 of the processor may be connected in an arbitrary order;

The data signals of the DQ8 to DQ15 of the DDR chip and the data signals of the DQ0 to DQ7 of the processor may be connected in an arbitrary order.
A memory based circuit board according to claim 6 wherein:

The high 8-bit signal line includes a data synchronization signal control bit UDQS for controlling the DQ8 to DQ15; and a data mask signal control bit UDQM for controlling the DQ8 to DQ15;

The lower 8-bit signal line includes a data synchronization signal control bit LDQS for controlling the DQ0 to DQ7; and a data mask signal control bit LDQM for controlling the DQ0 to DQ7;

The UDQS of the DDR chip is connected to the LDQS of the processor, the UDQM of the DDR chip is connected to the LDQM of the processor; the LDQS of the DDR chip and the processing The UDQS connection of the DDR chip, the LDQM of the DDR chip is connected to the UDQM of the processor.
A memory-based circuit board according to any one of claims 1 to 4, characterized in that

The memory is any one of the following chip types: a DDR chip of a 16-bit data signal, a DDR chip of a 32-bit data signal, and a DDR chip of a 64-bit data signal.
A memory-based circuit board according to any one of claims 1 to 4, characterized in that

The memory is any one of the following chip types: DDR1, DDR2, DDR3, DDR4.