CN206498588U - Circuit board based on memory - Google Patents
Circuit board based on memory Download PDFInfo
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- CN206498588U CN206498588U CN201720232640.4U CN201720232640U CN206498588U CN 206498588 U CN206498588 U CN 206498588U CN 201720232640 U CN201720232640 U CN 201720232640U CN 206498588 U CN206498588 U CN 206498588U
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- 230000015654 memory Effects 0.000 title claims abstract description 131
- 230000000873 masking effect Effects 0.000 claims description 23
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- 238000004891 communication Methods 0.000 abstract description 3
- 238000012545 processing Methods 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 2
- 229910002056 binary alloy Inorganic materials 0.000 description 1
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- 239000004744 fabric Substances 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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Abstract
The utility model provides a kind of circuit board based on memory, and memory is provided with the board, the processor for controlling the memory is additionally provided with；Memory and processor include at least two groups signal wires；Wherein, the line group mark of every group of signal wire is corresponding with the line group mark of every group of signal wire on processor on memory；The signal wire of memory and the signal wire of processor, without interconnection on same layer circuit board；Wherein, the line group that the line group mark for the memory being connected and the line group of processor are designated non-corresponding is identified.So as to by using signal line group as the signal wire between unit swapping memory and processor, facilitating the cabling of the signal wire between memory and processor, it is ensured that signal wire between the two does not intersect, and then ensure the communication quality between signal.
Description
Technical field
The utility model is related to memory wiring technique, more particularly to a kind of circuit board based on memory.
Background technology
With the rapid development of electronic technology, the circuit board in electronic product, such as printing board PCB (Printed
Circuit Board) volume become less and less.
As the minimum system of electronic device, memory is usually provided with pcb board, for example, Double Data Rate synchronous dynamic
Random access memory (Double Data Rate Dynamic Random Access Memory, referred to as " DDR ") and control should
The processor of memory operation.For making memory-aided circuit board, the respective pins distribution between processor and memory is logical
It is difficult often to accomplish that no intersection connects one to one, the problem of easily being caused confusion when this results in circuit board trace, chaotic walks
Line easily causes the interference between signal, influences signal quality；To avoid cabling between processor and memory from intersecting, signal is reduced
Between interference, it is necessary to extension track lengths on circuit boards, cabling lengthens the area for occupying more circuit boards, led
Cause the volume increase of circuit board.
The content of the invention
The utility model provides a kind of circuit board based on memory, for solving circuit board present in prior art
Electric signal cabling confusion and the technical problem of signal interference by its initiation between upper memory and processor.
The utility model provides and is provided with the memory on a kind of circuit board based on memory, the circuit board, also
It is provided with the processor for controlling the memory；
The memory and the processor include at least two groups signal wires；
The line group mark and the line group of every group of signal wire on the processor of every group of signal wire identify phase on the memory
Correspondence；
The signal wire of the signal wire of the memory and the processor, without interconnection on same layer circuit board；Wherein,
The line group that the line group mark for the memory being connected and the line group of the processor are designated non-corresponding is identified.
Optionally, the data-signal of predetermined bit capacity is included in every group of signal wire, also includes control described default
The control signal that the data-signal of bit capacity is transmitted.
Optionally, the control signal at least includes：Data synchronizing signal control bit；Data masking signals control bit.
Optionally, each bit of the data-signal of the predetermined bit capacity in two groups of signal wires being connected it
Between be connected with each other with random order；
Data synchronizing signal control bit correspondence in two groups of signal wires being connected is connected；
Data masking signals control bit correspondence in two groups of signal wires being connected is connected.
Optionally, the memory is DDR chips；
The DDR chips are the DDR of 16 data-signals；
Accordingly, most-significant byte signal wire and least-significant byte signal wire are included on the DDR chips and the processor；
The most-significant byte signal wire of the DDR chips is connected with the least-significant byte signal wire of the processor；
The least-significant byte signal wire of the DDR chips is connected with the most-significant byte signal wire of the processor.
Optionally, DQ0 to DQ7 8 data-signals are included in the least-significant byte signal wire；
Include DQ8 to DQ15 8 data-signals in the most-significant byte signal wire；
The data of the DQ0 to DQ7 of DDR chips data-signal and the DQ8 to DQ15 of the processor
Signal can be attached in any order；
The data of the DQ8 to DQ15 of DDR chips data-signal and the DQ0 to DQ7 of the processor
Signal can be attached in any order.
Optionally, the data synchronizing signal control bit for controlling the DQ8 to DQ15 is included in the most-significant byte signal wire
UDQS；Also include the data masking signals control bit UDQM for controlling the DQ8 to DQ15；
Include the data synchronizing signal control bit LDQS for controlling the DQ0 to DQ7 in the least-significant byte signal wire；Also wrap
Contain the data masking signals control bit LDQM for controlling the DQ0 to DQ7；
The UDQS of the DDR chips is connected with the LDQS of the processor, the UDQM of the DDR chips
It is connected with the LDQM of the processor；The LDQS of the DDR chips is connected with the UDQS of the processor, institute
The LDQM of DDR chips is stated to be connected with the UDQM of the processor.
Optionally, the memory is any one in following chip type：The DDR chips of 16 data-signals, 32
DDR chips, the DDR chips of 64 data-signals of position data-signal.
Optionally, the memory is any one in following chip type：DDR1、DDR2、DDR3、DDR4.
Circuit board provided by the utility model based on memory, is provided with memory, also sets up on the board
There is the processor for controlling the memory；Memory and processor include at least two groups signal wires；Wherein, on memory
The line group mark of every group of signal wire is corresponding with the line group mark of every group of signal wire on processor；The signal wire of memory and processing
The signal wire of device, without interconnection on same layer circuit board；Wherein, the line group mark and the line of processor for the memory being connected
Group is designated the line group mark of non-corresponding.So as to by using signal line group as the signal between unit swapping memory and processor
Line, facilitates the cabling of the signal wire between memory and processor, it is ensured that signal wire between the two does not intersect, and then ensures signal
Between communication quality.
Brief description of the drawings
Fig. 1 is a kind of structural representation of circuit board based on memory shown in the exemplary embodiment of the utility model one
Figure；
Fig. 2 is a kind of structural representation of circuit board based on memory shown in the utility model another exemplary embodiment
Figure；
Fig. 3 is a kind of structural representation of circuit board based on memory shown in the utility model another exemplary embodiment
Figure.
Reference：
1st, circuit board；2nd, memory/DDR chips；3rd, processor；4th, signal wire pin；5th, line group.
Embodiment
It is new below in conjunction with this practicality to make the purpose, technical scheme and advantage of the utility model embodiment clearer
Type embodiment, the technical scheme in the utility model embodiment is clearly and completely described.It should be noted that attached
In figure or specification, similar or identical element all uses identical reference.
Fig. 1 is a kind of structural representation of circuit board based on memory shown in the exemplary embodiment of the utility model one
Figure, as shown in figure 1, being provided with memory 2 on the circuit board 1 based on memory that the present embodiment is provided, circuit board 1, also sets up
There is the processor 3 for control memory 2；Memory 2 and processor 3 include at least two groups signal wires；It is every on memory 2
The line group mark of group signal wire is corresponding with the line group mark of every group of signal wire on processor 3；Wherein, the pin of signal wire is to mark
Numbers 4 signals, the line group of signal wire is illustrated with label 5, and not collinear group of mark carries out area with A, B, C, D...... capitalization
Point.The signal wire of memory 2 and the signal wire of processor 3, without interconnection on same layer circuit board；Wherein, what is be connected deposits
The line group that the line group mark of reservoir 2 and the line group of processor 3 are designated non-corresponding is identified.
Specifically, the circuit board 1 in Fig. 1 can be printing board PCB (Printed Circuit Board), flexibility
Wiring board FPC (Flexible Printed Circuit board), single sided board, dual platen, multilayer circuit board etc., the present embodiment
This is not especially limited, those skilled in the art can carry out the selection of corresponding circuit board according to circuit characteristic.Circuit board 1
On at least provided with memory 2, and control the memory 2 enter row information storage operation processor 3.Processor 3 is to right
The information such as initial data, program, middle operation result, final operation result be correctly stored in or take out, then are needed
By the connection corresponding with each signal wire pin 4 on the chip of processor 3 of each signal wire pin 4 on the chip of memory 2,
Be exactly it is as shown in Figure 1, each data signal pin 4 in the line group 5 (A) of memory 2 with the line group 5 (A) of processor 3
Each data signal pin 4 correspondence connect so that ensure processor 3 can will data message be stored in memory 2 in it is correct
Position, and data message can be taken out from the accurate location in memory 2 exactly.Therefore, it is as shown in Figure 1, memory 2
The line group mark of upper every group of signal wire is corresponding with the line group mark of every group of signal wire on processor 3, for example, on memory 2
The line group 5 (B) on (B) alignment processing of line group 5 device 3 on line group 5 (A) on (A) alignment processing of line group 5 device 3, memory 2, is deposited
The line on (D) alignment processing of line group 5 device 3 on the line group 5 (C) on (C) alignment processing of line group 5 device 3 on reservoir 2, memory 2
5 (D) of group.Four groups of line groups 5 are only shown, its number not to the line group 5 included in circuit board in the present embodiment 1 in Fig. 1
Limit, include two groups or more signal wire line group 5 on the memory 2 and processor 3 in the present embodiment.It is assumed that
Line group 5 is laid out as shown in figure 1, then according to shortest path cabling, then line group 5 (A) on memory 2,5 (B), 5 (C), 5 (D)
When connection corresponding with the line group 5 (A) on processor 3,5 (B), 5 (C), 5 (D), the situation of crossing elimination certainly will occur, from
And the interference between signal is caused, signal quality declines.It therefore, it can in the signal wire and the signal of processor 3 for ensureing memory 2
Line on same layer circuit board 1 without interconnection in the case of, by the carry out group of line group 5 of the line group 5 of memory 2 and processor 3 with
Signal exchange between group, so as to farthest facilitate the cabling of circuit board 1.Layout as shown in Figure 1, can use will storage
The line group 5 (B) of device 2 is connected with the line group 5 (C) of processor, and the line group 5 (C) of memory 2 is connected with the line group 5 (B) of processor,
The line group 5 (A) of memory 2 is still connected with the line group 5 (A) of processor, the line of the line group 5 (D) of memory 2 still with processor
Group 5 (D) connections, it is ensured that the signal link between memory 2 and processor 3 is most short and does not intersect each other.
The circuit board based on memory of the present embodiment, is provided with memory on the board, is additionally provided with for controlling
Make the processor of the memory；Memory and processor include at least two groups signal wires；Wherein, every group of signal on memory
The line group mark of line is corresponding with the line group mark of every group of signal wire on processor；The signal wire of memory and the signal of processor
Line, without interconnection on same layer circuit board；Wherein, the line group mark and the line group of processor for the memory being connected are designated
The line group mark of non-corresponding.It is convenient so as to by using signal line group as the signal wire between unit swapping memory and processor
It is logical between the cabling of signal wire between memory and processor, it is ensured that signal wire between the two does not intersect, and then guarantee signal
Believe quality.
Fig. 2 is a kind of structural representation of circuit board based on memory shown in the utility model another exemplary embodiment
Figure, on the basis of a upper embodiment, further, includes the data-signal of predetermined bit capacity in every group of signal wire, also
Include the control signal for controlling the data-signal of the predetermined bit capacity to be transmitted.
Specifically, the predetermined bit capacity in every group of signal wire refers to the binary system accommodated in every group of signal of memory 2
The capacity of data message, it is preferred that the byte (byte) that predetermined bit capacity can be constituted with every 8 positions (bit) is
Base unit, it is the integral multiple of byte unit, for example, 8 data-signals are one group, or 16 data-signals are one group, or
32 data-signals are one group, and operation, example are controlled to predetermined bit capacity data information in addition, also including in each group
Such as, the control signal of synchronous, mask control of data syn-chronization, clock etc..
Optionally, the control signal can at least include：Data synchronizing signal control bit；Data masking signals control bit.
Wherein, data synchronizing signal control bit be used for the data-signal between memory 2 and processor 3 is received, send when
Clock Synchronization Control.Data masking signals control bit is used to carry out mask control during data-signal carries out read or write
System.
Optionally, each ratio of the data-signal of the predetermined bit capacity in refer to the attached drawing 2, two groups of signal wires being connected
It can be connected with each other between special position with random order, be data synchronizing signal control bit, data masking signals based on control signal
Data synchronizing signal control bit correspondence in the situation of control bit, two groups of signal wires being connected is connected, two groups of letters being connected
Data masking signals control bit correspondence in number line is connected.Situation namely as shown in Figure 2, it is assumed that memory 2 is 16 digits
It is believed that number memory, then according to Fig. 2 current arrangements, after signal line group 5 (A) and signal line group 5 (B) are swapped connect
It can ensure that the cabling on same layer circuit board 1 does not intersect, and save track lengths, therefore, it can the low by eight of memory 2
Position data-signal DQ0 to DQ7 and processor 3 high eight-bit data-signal DQ8 to DQ15 are attached, and high eight-bit or low eight
Each data-signal inside data-signal can be attached with random order, it is not necessary to necessarily according to data-signal from high to low
Or order from low to high is attached.Namely as shown in Fig. 2 the DQ1 of memory 2 not necessarily have to be with processor 3 DQ9
Connection, it can be connected with DQ13, i.e. the signal wire pin 4 of each data-signal in signal line group 5 can be with random order
It is attached with the signal wire pin 4 of each data-signal in the signal line group 5 being connected.But, for control signal, such as
Data synchronizing signal control bit (DQS), data masking signals control bit (DQM) in Fig. 2, then must correspond to and connect, that is,
Say, the data synchronizing signal control bit (LDQS) of the data-signal of low eight (DQ0 to DQ7) of memory 2 and the height of controller 3
Data synchronizing signal control bit (UDQS) connection of the data-signal (DQ8 to DQ15) of eight, the data of low eight of memory 2
(DQ8 is extremely for the data-signal of the data masking signals control bit (LDQM) of signal (DQ0 to DQ7) and the high eight-bit of controller 3
DQ15 data masking signals control bit (UDQM) connection).
The circuit board based on memory of the present embodiment, further to the predetermined bit capacity included in every group of signal wire
Data-signal, and the control signal for controlling the data-signal of the predetermined bit capacity to be transmitted, such as data synchronizing signal
Control bit, data masking signals control bit etc. carry out reasonable line arrangement, such as by the data of the predetermined bit capacity in two groups of signal wires
It is connected with each other between each bit of signal with random order, by the data synchronizing signal control bit correspondence in two groups of signal wires
Connection, the data masking signals control bit correspondence in be connected two groups of signal wires is connected.So as to i.e. improve group in each
Wiring flexibility between data signal line, while also assures that control of the control signal to the data-signal in each signal line group
Validity and accuracy, and then efficiently avoid the problem of occurring to intersect and reduce signal quality between each signal wire.
Fig. 3 is a kind of structural representation of circuit board based on memory shown in the utility model another exemplary embodiment
Figure, on the basis of above-described embodiment, further, the memory 2 in previous embodiment can be DDR chips, i.e. double-speed
Rate synchronous DRAM (Double Data Rate Dynamic Random Access Memory, referred to as
“DDR”).DDR Double Data Rate is compared with traditional single data rate, and DDR technologies, which are realized, carries out two in a clock cycle
Secondary read/write operation, i.e., perform a read/write operation respectively in the rising edge and trailing edge of clock.
Species suitable for DDR chips of the present utility model is a lot, and optionally, the memory 2 can be following chip class
Any one in type：The DDR chips of 16 data-signals, the DDR chips of 32 data-signals, the DDR of 64 data-signals
Chip.
Optionally, the memory 2 can be any one in following chip type：DDR1、DDR2、DDR3、DDR4.No
Same numbering represents different process, distinct interface, the DDR chips of different performance (for example, speed is different).For example, DDR2：
IDDR2/DDR II (Double Data Rate 2) SDRAM is opened by JEDEC (EEE electronic equipment engineering joint committee)
The memory techniques standard of new generation of hair, the difference of it and previous generation DDR memory techniques standard maximums is exactly, although be both to employ
The basic mode carried out data transmission simultaneously on the rise/fall edge of clock, but DDR2 internal memories possess twice previous generation DDR
Internal memory pre-read ability is (i.e.：4bit data are read to prefetch).In other words, each clock of DDR2 internal memories can be with 4 times of external bus
Speed read/write data, and can be run with the speed of 4 times of Internal Control Bus IBC.
It should be noted that the not memory of isotopic number, the layout of the control signal corresponding to it also can be different.This practicality
The new digit for being not limited to memory bus, applicable memory include but is not limited to 8 memory, the storage of 16
Device, the memory of 32, the memory of 64, the memory of 128, the memory of 256,512 memory etc..Example
Such as, the memory for 16, its data synchronizing signal control bit can be such as the low eight-digit number of the control described in above-mentioned embodiment
It is believed that the data syn-chronization letter that number data synchronizing signal control bit LDQS synchronized, control high eight-bit data-signal are synchronized
Number control bit UDQS, its data masking signals control bit can enter such as the low eight bit data signal of the control described in above-mentioned embodiment
Data masking signals control bit LDQM, the control high eight-bit data-signal of the operation of row mask carry out the data mask letter of mask operation
Number control bit UDQM.For the memory of 32, its data synchronizing signal control bit is general to be marked with DQS0, DQS1, DQS2, DQS3
Know the data synchronizing signal control bit that every 8 data-signals are configured；Its data masking signals control bit it is general with DQM0,
DQM1, DQM2, DQM3 identify the data masking signals control bit that every 8 data-signals are configured.The DQS0 positions of memory
It can be attached with DQS1, DQS2, DQS3 any bit in processor, for example, the DQS0 and the DQS1 of processor of memory
Connection, the DQM0 and processor of memory DQM1 connections, accordingly, the DQS1 and processor of memory DQS0 connections are deposited
The DQM0 and processor of reservoir DQM1 connections.In addition, for some DDR chips, there is data synchronizing signal control bit
(DQS) presented in the form of differential pair, for example, including DQS+ and DQS- data synchronizing signal control in DDR2, DDR3, DDR4
Position processed, then accordingly, during signal line group is swapped, note needing DQS is carried out into the corresponding connection of polarity.Example
Such as, for the DDR of the differential pair containing DQS, by the UDQS- connections of the LDQS- alignment processing devices of memory, accordingly, memory
LDQS+ correspondence UDQS+ connections.For different types of DDR chips 2, below with DDR of the DDR chips 2 for 16 data-signals
Exemplified by illustrate, for 16 DDR chips 2, the DDR chips 2 and handle the DDR chips 2 processor 3 on include
There are most-significant byte signal wire and least-significant byte signal wire；The most-significant byte signal wire of DDR chips 2 is connected with the least-significant byte signal wire of processor 3；
The least-significant byte signal wire of DDR chips 2 is connected with the most-significant byte signal wire of processor 3.
Optionally, DQ0 to DQ7 8 data-signals are included in least-significant byte signal wire；Include in most-significant byte signal wire
DQ8 to DQ15 8 data-signals；The number of DQ0 to DQ7 of DDR chips 2 data-signal and the DQ8 to DQ15 of processor 3
It is believed that number can be attached in any order.The DQ8 of DDR chips 2 to DQ15 data-signal and the DQ0 of processor 3 are extremely
DQ7 data-signal can be attached in any order.The DQ0 connections processor 3 of DDR chips 2 as shown in Figure 3
The DQ13 of the DQ1 connections processor 3 of DQ11, DDR chip 2；For another example DQ2, DDR chip of the DQ9 connections processor 3 of DDR chips 2
The DQ7 of 2 DQ10 connections processor 3.
Optionally, control DQ8 to DQ15 data synchronizing signal control bit UDQS is included in most-significant byte signal wire；Also
Include control DQ8 to DQ15 data masking signals control bit UDQM；Include control DQ0 in least-significant byte signal wire to DQ7's
Data synchronizing signal control bit LDQS；Also include control DQ0 to DQ7 data masking signals control bit LDQM；Wherein, DDR
The UDQS of chip 2 is connected with the LDQS of processor 3, and the UDQM of DDR chips 2 is connected with the LDQM of processor 3；DDR chips 2
LDQS is connected with the UDQS of processor 3, and the LDQM of DDR chips 2 is connected with the UDQM of processor 3.That is, when DDR chips 2
In most-significant byte signal wire and least-significant byte signal wire enter after the exchanging of row signal line line group 5, the high-order UDQS in DDR chips 2 is necessary
Connection corresponding with the low level LDQS of processor 3；Low level LDQS in DDR chips 2 corresponding with the high-order UDQS of processor 3 must connect
Connect；Similarly, the high-order UDQM in DDR chips 2 corresponding with the low level LDQM of processor 3 must be connected, the low level in DDR chips 2
LDQM must connection corresponding with the high-order UDQM of processor 3.
The circuit board based on memory of the present embodiment, by specifically carrying out cloth to the DDR chips of 16 data-signals
Line is limited, and such as connects the least-significant byte signal wire of the most-significant byte signal wire of DDR chips and processor, least-significant byte signal wire and processor
Most-significant byte signal wire connection；And least-significant byte, the most-significant byte data-signal in DDR chips and processor can enter in any order
Row connection；UDQS, LDQS connection corresponding with LDQS, UDQS of processor, UDQM, LDQM of DDR chips respectively in DDR chips
Connection corresponding with LDQM, UDQM of processor respectively.So as to improve the flexible of signal link between DDR chips and processor
Property, it is ensured that the communication quality of signal between the two；Meanwhile, also improve each in DDR chips and processor each signal group
Wiring flexibility between individual data signal line, while also assures that control of the control signal to the data-signal in each signal line group
Validity and accuracy processed, and then efficiently avoid the problem of occurring to intersect and reduce signal quality between each signal wire.
Finally it should be noted that：Various embodiments above is only limited to illustrate the technical solution of the utility model, rather than to it
System；Although the utility model is described in detail with reference to foregoing embodiments, one of ordinary skill in the art should manage
Solution：It can still modify to the technical scheme described in foregoing embodiments, or to which part or whole skills
Art feature carries out equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from the utility model
Each embodiment technical scheme scope.
Claims (9)
1. a kind of circuit board based on memory, it is characterised in that
The memory is provided with the circuit board, the processor for controlling the memory is additionally provided with；
The memory and the processor include at least two groups signal wires；
The line group mark of every group of signal wire is corresponding with the line group mark of every group of signal wire on the processor on the memory；
The signal wire of the signal wire of the memory and the processor, without interconnection on same layer circuit board；Wherein, it is connected
The line group that the line group mark of the memory connect and the line group of the processor are designated non-corresponding is identified.
2. the circuit board according to claim 1 based on memory, it is characterised in that
Include the data-signal of predetermined bit capacity in every group of signal wire, also include the number for controlling the predetermined bit capacity
It is believed that number control signal being transmitted.
3. the circuit board according to claim 2 based on memory, it is characterised in that
The control signal at least includes：Data synchronizing signal control bit；Data masking signals control bit.
4. the circuit board according to claim 3 based on memory, it is characterised in that
With any suitable between each bit of the data-signal of the predetermined bit capacity in two groups of signal wires being connected
Sequence is connected with each other；
Data synchronizing signal control bit correspondence in two groups of signal wires being connected is connected；
Data masking signals control bit correspondence in two groups of signal wires being connected is connected.
5. according to the circuit board according to any one of claims 1 to 4 based on memory, it is characterised in that
The memory is DDR chips；
The DDR chips are the DDR of 16 data-signals；
Accordingly, most-significant byte signal wire and least-significant byte signal wire are included on the DDR chips and the processor；
The most-significant byte signal wire of the DDR chips is connected with the least-significant byte signal wire of the processor；
The least-significant byte signal wire of the DDR chips is connected with the most-significant byte signal wire of the processor.
6. the circuit board according to claim 5 based on memory, it is characterised in that
Include DQ0 to DQ7 8 data-signals in the least-significant byte signal wire；
Include DQ8 to DQ15 8 data-signals in the most-significant byte signal wire；
The data-signal of the DQ0 to DQ7 of DDR chips data-signal and the DQ8 to DQ15 of the processor
It can be attached in any order；
The data-signal of the DQ8 to DQ15 of DDR chips data-signal and the DQ0 to DQ7 of the processor
It can be attached in any order.
7. the circuit board according to claim 6 based on memory, it is characterised in that
Include the data synchronizing signal control bit UDQS for controlling the DQ8 to DQ15 in the most-significant byte signal wire；Also include
Control the DQ8 to DQ15 data masking signals control bit UDQM；
Include the data synchronizing signal control bit LDQS for controlling the DQ0 to DQ7 in the least-significant byte signal wire；Also include
Control the DQ0 to DQ7 data masking signals control bit LDQM；
The UDQS of the DDR chips is connected with the LDQS of the processor, the UDQM of the DDR chips and institute
State the LDQM connections of processor；The LDQS of the DDR chips is connected with the UDQS of the processor, described
The LDQM of DDR chips is connected with the UDQM of the processor.
8. according to the circuit board according to any one of claims 1 to 4 based on memory, it is characterised in that
The memory is any one in following chip type：The DDR chips of 16 data-signals, 32 data-signals
The DDR chips of DDR chips, 64 data-signals.
9. according to the circuit board according to any one of claims 1 to 4 based on memory, it is characterised in that
The memory is any one in following chip type：DDR1、DDR2、DDR3、DDR4.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720232640.4U CN206498588U (en) | 2017-03-10 | 2017-03-10 | Circuit board based on memory |
| CN201780030651.7A CN109154923A (en) | 2017-03-10 | 2017-05-10 | Circuit board based on memory |
| PCT/CN2017/083834 WO2018161431A1 (en) | 2017-03-10 | 2017-05-10 | Memory-based circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720232640.4U CN206498588U (en) | 2017-03-10 | 2017-03-10 | Circuit board based on memory |
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| Publication Number | Publication Date |
|---|---|
| CN206498588U true CN206498588U (en) | 2017-09-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201720232640.4U Expired - Fee Related CN206498588U (en) | 2017-03-10 | 2017-03-10 | Circuit board based on memory |
| CN201780030651.7A Pending CN109154923A (en) | 2017-03-10 | 2017-05-10 | Circuit board based on memory |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780030651.7A Pending CN109154923A (en) | 2017-03-10 | 2017-05-10 | Circuit board based on memory |
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| CN (2) | CN206498588U (en) |
| WO (1) | WO2018161431A1 (en) |
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| KR20070033714A (en) * | 2005-09-22 | 2007-03-27 | 삼성전자주식회사 | Data transmission line wiring method |
| CN101217468A (en) * | 2007-12-28 | 2008-07-09 | 华为技术有限公司 | A routing table look-up system, tristate content addressing memory and network processor |
| CN101727970B (en) * | 2009-11-03 | 2012-11-21 | 深圳市共进电子股份有限公司 | Method for reducing radiation generated by synchronous dynamic random access memory (SDRAM) |
| CN103885919B (en) * | 2014-03-20 | 2017-01-04 | 北京航空航天大学 | A kind of many DSP and FPGA parallel processing system (PPS)s and implementation method |
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- 2017-03-10 CN CN201720232640.4U patent/CN206498588U/en not_active Expired - Fee Related
- 2017-05-10 CN CN201780030651.7A patent/CN109154923A/en active Pending
- 2017-05-10 WO PCT/CN2017/083834 patent/WO2018161431A1/en active Application Filing
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| Publication number | Publication date |
|---|---|
| WO2018161431A1 (en) | 2018-09-13 |
| CN109154923A (en) | 2019-01-04 |
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