WO2018161283A1 - 用于处理报文的方法和装置 - Google Patents

用于处理报文的方法和装置 Download PDF

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Publication number
WO2018161283A1
WO2018161283A1 PCT/CN2017/075996 CN2017075996W WO2018161283A1 WO 2018161283 A1 WO2018161283 A1 WO 2018161283A1 CN 2017075996 W CN2017075996 W CN 2017075996W WO 2018161283 A1 WO2018161283 A1 WO 2018161283A1
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WIPO (PCT)
Prior art keywords
processor
binary file
virtual machine
code
message
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PCT/CN2017/075996
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English (en)
French (fr)
Inventor
夏阳
刘珺
田太徐
王中震
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华为技术有限公司
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Priority to CN201780087658.2A priority Critical patent/CN110352400B/zh
Priority to PCT/CN2017/075996 priority patent/WO2018161283A1/zh
Publication of WO2018161283A1 publication Critical patent/WO2018161283A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Definitions

  • the present application relates to the field of network technologies and, more particularly, to a method and apparatus for processing messages.
  • Enabling the processor to perform a processing operation requires loading a binary file on the processor that defines the processing operation. For example, the processor can discard, modify, or forward the message.
  • the processor can discard, modify, or forward the message.
  • Different types of processors have different instruction sets, that is, different types of processors can recognize different codes. That is, the binary files loaded on different processors are different in order to enable different processors to perform the same processing operation.
  • binary files loaded on different types of processors are generated by compiling source code described in different programming languages. That is to say, the binary files loaded on different types of processors have a corresponding relationship with the programming language of the source code, that is, the processor has a corresponding relationship with the programming language of the source code.
  • a binary file loaded on a Network Processor (NP) is generated by compiling source code described in Assembly Language (AL). That is, the programming language of the source code corresponding to NP is AL.
  • a binary file loaded on a Field Programmable Gate Array (FPGA) is generated by compiling source code described in a Hardware Description Language (HDL). That is, the programming language of the source code corresponding to the FPGA is HDL.
  • HDL Hardware Description Language
  • the source code of the programming language corresponding to the compiling processor generates a technical solution for loading the binary file on the processor, which is not flexible enough and costly.
  • the embodiment of the present application provides a method and apparatus for processing a message, and compiling a source code of a high-level programming language to generate object code that can be executed by a virtual machine, and the binary file loaded on the processor is generated by converting the target code.
  • the program has a high degree of flexibility.
  • a method for processing a message comprising: a first processor compiling a source code of a high-level programming language description to generate object code executable by a virtual machine, the source code defining message processing
  • the first processor converts the target code to generate a binary file; the second processor that loads the binary file processes the message according to the message processing operation.
  • the binary file to be loaded is generated by the source code described in the programming language corresponding to the compiler processor.
  • the programming language of the source code is related to the type of the processor.
  • the user needs to describe the source code in a different programming language.
  • the object code is between the source code of the high-level programming language description and the binary file loaded on the processor, and is used to implement the conversion of the source code of the high-level programming language description into the binary file loaded on the processor.
  • Programmers can describe source code in a high-level programming language. The programmer does not need to use a programming language that corresponds to the type of processor. Therefore, the program has a high degree of flexibility.
  • the first processor may convert the target code into different binary files and load different binary files into different second processors, respectively. That is to say, the above scheme helps to generate binary files of different processors according to the source code described in the high-level programming language, which helps to reduce development costs.
  • the first processor is a general-purpose processor
  • the second processor is At least one of a general purpose processor and a special purpose processor.
  • first processor and the second processor are both general purpose processors, the first processor and the second processor may be the same processor or different processors.
  • the second processor includes at least one of a reconfigurable logic device, an NP, a CPU, and a multi-core system-on-chip Soc.
  • the reconfigurable logic device comprises a field programmable gate array FPGA and a complex programmable logic device CPLD.
  • the high level programming language comprises Java, C++, C, pascal, Python, Lisp, Prolog or FoxPro.
  • the high-level programming language includes a variety of languages, and the user can flexibly select the corresponding language to describe the source code, which is beneficial for loading the binary file on the second processor, thereby facilitating the second processor to perform message processing.
  • the packet processing operation is used to process an L2 layer service of a data communication network, an L3 layer service of a data communication network, an L4 layer service of a data communication network, and an L5 layer service of a data communication network. At least one of an L6 layer service of a data communication network and an L7 layer service of a data communication network.
  • the user can load a binary file defining the operation of the corresponding message processor on the second processor to meet the requirement for the user to process the message through the second processor.
  • the virtual machine is a Java virtual machine
  • the instruction in the target code is an instruction in a Java virtual machine instruction set
  • the virtual machine is a Berkeley message filter BPF virtual machine.
  • the instruction in the target code is an instruction in the BPF virtual machine instruction set; or the virtual machine is an extended Berkeley message filter eBPF virtual machine, and the instruction in the target code is an instruction in the eBPF virtual machine instruction set.
  • the virtual machine has its own instruction set, which facilitates the accurate conversion of the target code into a binary file loaded on the second processor.
  • the converting, by the first processor, the target code to generate a binary file comprising: the first processor disassembling the target code, and generating a computer program described by the AL; The first processor generates the binary file according to the computer program described by the AL.
  • AL corresponds to a different instruction set. That is, for the same processing operation, different devices have different ALs, that is, AL and devices have corresponding relationships.
  • the AL generated by disassembling the object code is the AL corresponding to the virtual machine. This scheme facilitates the conversion of the object code into a binary file.
  • the AL is a first AL; the first processor generates the binary file according to the computer program described by the AL, including: the first processor: The computer program described by the first AL is converted into a computer program described by the second AL; the first processor assembles the computer program described by the second AL to generate the binary file.
  • the first AL is an AL corresponding to the virtual machine
  • the second AL is an AL corresponding to the second processor.
  • the scheme is simple and easy to implement, and is beneficial for converting the target code into a binary file loaded on the second processor.
  • the second processor may be an NP or a central processing unit CPU.
  • the method further includes: saving the binary file into an instruction memory, the second processor is coupled to the instruction memory; and the second processor loading the binary file is The message processing operation, the processing of the message includes: the second processor acquiring the binary by accessing the instruction memory a file; the second processor processes the message by executing a sequence of instructions in the binary file.
  • the first processor generates the binary file according to the computer program described by the AL, including: the first processor converting the computer program described by the AL into an HDL Decoded code; the first processor synthesizes the code described by the HDL to generate a gate level description; the first processor converts the gate level description to generate the binary file.
  • the scheme is simple and easy to implement, and is beneficial for converting the target code into a binary file loaded on the second processor. Further, if the second processor is a reconfigurable logic device.
  • the HDL may include: a super high speed integrated circuit hardware description language VHDL or a Verilog language.
  • the gate level description may include an electronic design exchange format EDIF netlist.
  • the method further comprises: loading the binary file to the second processor via a joint test behavior organization JTAG interface of the second processor, the processor being reconfigurable logic Device, the binary file is a bit configuration file.
  • the reconfigurable logic device includes an FPGA, and the bit configuration file is specifically a bitstream file.
  • a bitstream file can be represented as: *.bit.
  • the reconfigurable logic device includes a CPLD
  • the bit configuration file is specifically a solid state technology association is a leading standard organization JEDEC file of the microelectronics industry.
  • a JEDEC file can be expressed as: *.jed.
  • the second processor is for network function virtualization NFV acceleration.
  • the second processor may be a hardware accelerator.
  • the user can flexibly load the binary file on the hardware accelerator as needed to enable the hardware accelerator to perform corresponding operations, thereby facilitating the improvement of the NFV. Handling the efficiency of the business, the method is flexible and operability.
  • the acceleration unit chip of the hardware accelerator may include at least one of an embedded neural network processor NPU chip, an FPGA, and a Soc.
  • an apparatus for processing a message for performing a method in a first aspect or any possible implementation of a first party may comprise means for performing the first aspect or the first A unit of a method in any of the possible implementations.
  • an apparatus for processing a message comprising a processor configured to support the apparatus to perform a corresponding function of the above method.
  • the device can also include a memory coupled to the processor that holds the program instructions and data necessary for the device.
  • a computer readable medium for storing computer software instructions for use in the first processor and/or the second processor described above, comprising a program designed to perform the above aspects.
  • a computer program product comprising: computer program code, when the computer program code is run by a first processing unit and/or a second processing unit of a device for message processing Having the apparatus perform the method of the above-described implementation; or when the computer program code is executed by the first processor and/or the second processor of the device for message processing, causing the device to perform the above implementation Methods.
  • the method, device and device for processing a message provided by the embodiment of the present application convert the source code to the target code by the high-level programming language, and then convert from the target code to the binary file.
  • the solution has high flexibility and compatibility, which is beneficial for loading binary files on the processor and facilitating the processor to perform message processing.
  • FIG. 1 is a schematic flowchart of an example of a method for processing a message according to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of another example of a method for processing a message according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of still another example of a method for processing a message according to an embodiment of the present application.
  • FIG. 4 is a schematic block diagram of an apparatus for processing a message in accordance with an embodiment of the present application.
  • FIG. 5 is a schematic block diagram of an apparatus for processing a message according to an embodiment of the present application.
  • the enabling processor performs a certain processing operation, and the user needs to use the programming language corresponding to the processor to describe the source code that defines the processing operation, and compile the source code to generate (can) the binary loaded on the processor.
  • the file, the processor loaded with the binary file can be processed according to the processing operation, which is not conducive to loading the binary file on the processor, thereby being disadvantageous for the processor to perform corresponding processing.
  • the method has limitations.
  • the processor has a corresponding relationship with a programming language that describes the source code, such that the source code described by a certain programming language can only be loaded on some specific types of processors.
  • HDL for example, Verilog language
  • the "HDL description defines the source code of the processing operation A” as “Source Code C A (HDL) " Compile the source code C A (HDL) to generate the binary file C FPGA-A loaded on the FPGA .
  • the source code C A (HDL) cannot be converted to the binary file C NP-A loaded on the NP .
  • the source code C A(AL) of the AL corresponding to the NP can be converted to the binary file C NP-A but cannot be converted to C NP-A . This method has limitations.
  • the user needs to describe a plurality of source codes in a one-to-one correspondence using a plurality of programming languages. For example, assuming that the FPGA and NP are enabled to perform processing operation A, the user needs to separately describe the source code C A (HDL) and the source code C A (AL) , which can result in wasted human resources.
  • HDL source code C A
  • AL source code C A
  • the binary file loaded on the processor can be understood as: the processor can recognize the binary file, and after the processor acquires the binary file, the processing operation defined by the binary file can be performed.
  • the method requires a high level of development environment.
  • the source code development environment is processor dependent.
  • the processor is an FPGA produced by Xilinx
  • the source code development environment is the ISE development environment.
  • the user needs to describe the source code in the ISE development environment using the Verilog language (ie, using the ISE software to describe the source code in the Verilog language).
  • the processor is an FPGA produced by Altera
  • the user needs to describe the source code in the Verilog language in the quartus development environment, which requires a high development environment.
  • this method requires a higher level of professional competence of the user.
  • FPGAs require a professional developer with logic circuit development capabilities to describe the Verilog code. Often, users do not have the ability to develop logic circuits, which is not conducive to loading binary files on the processor.
  • the embodiment of the present application provides a method for processing a message, which is convenient for loading a binary file on a processor, thereby facilitating processing of the message by the processor according to a processing operation defined by the binary file.
  • a high-level programming language a programming language based on human everyday language, expressed in words that are easily accepted by the average person (such as Chinese characters, irregular English or other foreign languages), making the description easier and higher. Readability. Java, C++, C, pascal, Python, Lisp, Prolog, FoxPro, etc. are all high-level programming languages.
  • Assembly language AL is a low-level language for electronic computers, microprocessors, microcontrollers, or other programmable devices.
  • assembly language replace the opcode of the machine instruction with a Mnemonics, and replace the address of the instruction or operand with an address symbol (Label) or label (Label).
  • assembly language corresponds to different machine language instruction sets, which are converted into machine instructions through assembly process.
  • the specific assembly language and the specific machine language instruction set are in one-to-one correspondence. That is, different devices correspond to different assembly languages.
  • Source Code refers to an uncompiled text file described in accordance with a certain business design language specification and is a series of human-readable computer language instructions.
  • the source code (or source program) cannot be directly recognized by the machine (for example, a computer), and the compiled binary file is required, and the binary file can be recognized by the machine.
  • source code the code described by the developer (or user) in the programming language.
  • Compilation is the process of "translating" one language into another before the application source code is executed.
  • a high-level programming language (source code) is translated into a machine language (object code) that a computer can recognize.
  • Object Code refers to the code generated by the compiler or assembler in computer science after processing the source code. It is generally composed of machine code or code close to machine language.
  • Binaries also called Object Files, are files used to record object code. Binaries contain object code and data that the code uses at runtime, such as relocation information, such as business symbols (names of variables and functions) for linking or debugging, and other debugging information.
  • relocation information such as business symbols (names of variables and functions) for linking or debugging, and other debugging information.
  • a binary file is a file that a machine (which should be understood to be a physical machine or a virtual machine) that can be recognized. Generate the corresponding binary file by compiling the source code. For example, compiling the source code described in the Verilog language generates binary files that are loaded on the FPGA. The source code of the AL description corresponding to the compiled NP generates a binary file loaded on the NP.
  • FIG. 1 is a schematic flowchart of a method 100 for processing a message according to an embodiment of the present application. It should be understood that FIG. 1 shows detailed steps or operations of a method for processing a message, but these steps or operations are merely examples, and other embodiments of the present application may perform other operations or variations of various operations in FIG. .
  • the method 100 involves a first processor and a second processor.
  • the first processor can be understood as a processor capable of converting source code of a high-level programming language description into a binary file.
  • the second processor can be understood as a processor that enables the message processing operation defined by the binary file (ie, the processor to load the binary file).
  • the first processor is a general purpose processor.
  • general-purpose processors are Turing-complete", that is, the general-purpose processor has the same computing power as a general Turing machine, and can calculate Turing.
  • the result of the function can be calculated (everything that can be calculated can be calculated).
  • the second processor can be a general purpose processor or a dedicated processor.
  • the dedicated processor or coprocessor
  • the NP of the embodiment of the present application is a dedicated processor.
  • the second processor may include at least one of a reconfigurable logic device, a CPU, an NP, and a multi-core system on chip (Soc).
  • the reconfigurable logic device may include at least one of an FPGA and a Complex Programmable Logic Device (CPLD).
  • first processor and the second processor are both general purpose processors, the first processor and the second processor may be the same processor or different processors.
  • the first processor and the second processor are the same central processing unit (CPU), and the CPU generates a binary file, and the CPU loads the binary file and processes the message according to the binary file definition, The message is processed.
  • CPU central processing unit
  • the first processor is a first CPU
  • the second processor is a second CPU
  • the first CPU is different from the second CPU
  • the first processor and the second processor can also be different processors.
  • the first processor is a CPU
  • the second processor is an NP
  • the CPU generates a binary file
  • the NP loads a binary file generated by the CPU
  • the NP processes the packet according to a packet processing operation defined by the binary file.
  • the method 100 can include S110, S120, and S130.
  • the first processor compiles the source code of the high-level programming language description to generate object code that can be executed by the virtual machine, the source code defining a message processing operation.
  • a virtual machine refers to a complete system that runs through a software and has a complete hardware system function and runs in a completely isolated environment.
  • the virtual system of the virtual machine generates a completely new virtual image of the existing operating system. It has the same functions as the Windows operating system, the Linux operating system or other operating systems. After entering the virtual system, all operations are in this brand new independent virtual. It can be installed in the system, can install and run software independently, save data, has its own independent desktop, does not have any impact on the real system, and has a kind of operating system that can flexibly switch between the existing system and the virtual image.
  • the virtual machine may include multiple types of virtual machines.
  • the virtual machine can be a Java virtual machine
  • the instructions in the object code are instructions in a Java virtual machine instruction set.
  • the virtual machine may be a Berkeley Packet Filter (BPF) virtual machine
  • the instruction in the target code is an instruction in a BPF virtual machine instruction set.
  • BPF Berkeley Packet Filter
  • the virtual machine may be an extended Bertenley Packet Filter (eBPF) virtual machine, and the instruction in the target code is an instruction in the eBPF virtual machine instruction set.
  • eBPF extended Bertenley Packet Filter
  • the virtual machine can be other types of virtual machines such as a Microsoft virtual machine and a Linux virtual machine.
  • the Java virtual machine, the BPF virtual machine, and the eBPF virtual machine have an instruction set, which is beneficial for subsequent conversion of the target code to generate a binary file.
  • the packet processing operation may be: performing a forwarding operation on the packet, performing a modification operation on the packet, calculating a checksum (English: checksum), decrementing the value of the lifetime, and performing a counting operation on the packet.
  • the forwarding operation may be a Layer 3 virtual private network (L3VPN) forwarding, and a layer 2 virtual private network (L2VPN) may be forwarded.
  • Virtual private LAN service (English: virtual private LAN service, VPLS for short) forwarding, multiprotocol label switching (English: multiprotocol label switching, MPLS for short) forwarding, IP forwarding or layer 2 switching (English: layer 2 switching).
  • processing operations are defined by different source code. For example, suppose that the source code defining the message processing operation A and the source code defining the message processing operation B are described by a high-level programming language, and the source code of the definition message processing operation A is different from the source code defining the message processing operation B. .
  • the source code, the object code generated by compiling the source code, and the binary file generated by converting the object code described below, the three defined message processing is the same.
  • the source code written in the high-level language defines the message processing operation A
  • converting The object code generates a binary file that defines the message processing operation A.
  • source code C C source code
  • target code C VIR target code executable by the virtual machine
  • the object code C VIR is independent of the second processor.
  • the "the object code C VIR is independent of the second processor" can be understood as: regardless of the type of processor of the second processor, the binary file loaded on the second processor can convert the target code C by VIR generation.
  • the S110 may include:
  • the source code C C is compiled (eg, statically compiled) by Ahead Of Time (AOT) to generate the object code C VIR .
  • AOT Ahead Of Time
  • the first processor converts the target code to generate a binary file.
  • the second processor that loads the binary file processes the packet according to the packet processing operation.
  • the first processor converts the target code to generate a binary file
  • the first processor converts the target code to generate a binary file loaded on the second processor.
  • the first processor converts the target code to obtain a different binary file.
  • the first processor is a CPU, FPGA second processor
  • the CPU can convert the generated target code C VIR loaded on the FPGA binary C FPGA
  • the FPGA is loaded binary C FPGA can perform the binary file C FPGA defined message processing operations.
  • the CPU can convert the target code C VIR to generate a binary file C NP that can be loaded on the NP , and the NP loaded with the binary file C NP can execute the The message processing operation defined by the binary file C NP .
  • the S120 may specifically include: a first processor, Just In Time (JIT), compiling the target The code generates a binary file.
  • JIT Just In Time
  • the first processor can identify the type of the second processor if the first processor is connected to the second processor.
  • the first processor may also install driver software of the second processor, the first processor JIT compiling the object code to generate a binary file loaded on the second processor.
  • the second processor is an FPGA
  • the first processor can identify the FPGA and JIT compile the target code C VIR to generate a binary file loaded on the FPGA, assuming the second processing
  • the device is NP.
  • the first processor can identify the NP and JIT compiles the object code C VIR to generate a binary file loaded on the NP.
  • the first processor may convert the target code C VIR to generate a binary file in a plurality of manners.
  • the S120 may include:
  • the first processor disassembles the target code to generate a computer program described by the AL.
  • the first processor generates the binary file according to the computer program described by the AL.
  • the AL is an AL corresponding to the virtual machine, and for convenience of explanation, the "AL corresponding to the virtual machine” is referred to as "first AL".
  • the first processor may generate the binary file according to at least a computer program described by the first AL in the following manner.
  • FIG. 2 is a schematic flowchart of another example of a method for packet processing according to an embodiment of the present application.
  • the S122 may include:
  • the second AL is an AL corresponding to the second processor.
  • the second processor is an NP and the second AL is an AL corresponding to the NP.
  • the first processor assembles the computer program described by the second AL language to generate the binary file.
  • FIG. 3 is a schematic flowchart of another example of a method for packet processing according to an embodiment of the present application.
  • the S122 may include:
  • the HDL may comprise a VHDL or Verilog language.
  • the first processor synthesizes the code of the HDL to generate a gate level description
  • the gate level description may be an Electronic Design Interchange Format (EDIF) netlist.
  • EDIF Electronic Design Interchange Format
  • the first processor converts the gate level description to generate the binary file.
  • the method 100 can also include:
  • the first processor loads the binary file onto the second processor. Further, the first processor can load the binary file onto the second processor in a plurality of manners.
  • the first processor saves the binary file into an instruction memory
  • the second processor is coupled to the instruction memory.
  • the S130 may include: the second processor acquiring the binary file by accessing the instruction memory; and the second processor processing the message by executing a sequence of instructions in the binary file.
  • the first processor loads the binary file to the second processor via a Joint Test Action Group (JTAG) interface of the second processor, where the second processor is A reconfigurable logical device, the binary file being a bit configuration file.
  • JTAG Joint Test Action Group
  • the reconfigurable logic device includes an FPGA, and the bit configuration file is specifically a bitstream file.
  • a bitstream file can be represented as: *.bit.
  • the reconfigurable logic device includes a CPLD, and the bit profile is specifically a Solid Electron Device Engineering Council (JEDEC) document.
  • JEDEC Solid Electron Device Engineering Council
  • a JEDEC file can be expressed as: *.jed.
  • the first processor may encapsulate the binary file through an application programming interface (API) for loading, by the first processor, the binary file into the second processor.
  • API application programming interface
  • the first processor compiles the source code of the high-level programming language description to generate target code that can be executed by the virtual machine, and the binary file loaded on the processor is generated by converting the target code, and the target code is used as
  • the process code which is used to implement the conversion of the source code of the high-level programming language description to the binary file loaded on the processor, helps to save human resources.
  • the high-level programming language is simple and easy to operate compared to other programming languages (such as HDL), and the high-level programming language has an open development environment, which can save the cost of enabling the second processor to perform processing operations.
  • the method has high compatibility, flexibility and simple operation, and is beneficial for loading a binary file on the second processor, thereby facilitating processing of the message by the second processor.
  • the second processor is used for network function virtualization (NFV) acceleration.
  • the second processor may be a hardware accelerator, and the acceleration unit chip of the hardware accelerator may include an embedded Network Processing Unit (NPU) chip, an FPGA, or a Soc.
  • NPU Network Processing Unit
  • the hardware accelerator can be applied to a variety of device configurations.
  • the hardware accelerator can be the latest Peripheral Component Interconnect Express (PCIE) network card or an accelerated resource pool device.
  • PCIE Peripheral Component Interconnect Express
  • the method of the embodiment of the present application is described from a holistic perspective, wherein the first processor can implement conversion of source code-object code-binary file. Further, the first processor can implement conversion of the source code-object code-binary file by software running on the first processor.
  • the method of the embodiment of the present application is described in detail by taking some software as an example. It should be noted that the software involved below is merely an example and should not be construed as limiting the application.
  • the S110 may specifically include:
  • the first processor generates source code executable by the virtual machine by compiling the source code of the high-level programming language by the first compiler running on the first processor.
  • the first compiler is a C compiler
  • the source code is described using a JAVA language
  • the first compiler is JAVA compiler
  • the first compiler corresponding to each high level programming language may include multiple types of compilers.
  • the first compiler may include a C language compiler such as Turbo C, Borland C++, or Low Level Virtual Machine (LLVM).
  • LLVM Low Level Virtual Machine
  • the method 100 may further include:
  • the first processor acquires the source code C C .
  • the first processor acquires the source code C C by using programming software running on the first processor, wherein the programming software is used by a developer (or a user) to describe the source code, the first compiler This source code can be obtained by the programming software.
  • the programming software may include C language programming software such as Microsoft Visual C++, Microsoft Visual Studio, DEV C++, or Watcom C++.
  • the first compiler and the programming software run on a virtual machine on the first processor.
  • the user can open programming software for a virtual machine running on the first processor, which can be Microsoft Visual C++ software.
  • the user defines the source code C CA of the message processing operation A through the software description.
  • the first compiler of the virtual machine is an LLVM compiler, which can acquire the source code C CA and compile the source code C CA to generate the object code C VIR-A .
  • the S120 may specifically include:
  • the first processor converts the target code to generate a binary file by a second compiler running on the first processor
  • the second compiler belongs to a compiler of a software system running on the first processor, the software system being independent of the virtual machine.
  • second processors correspond to different second compilers.
  • the second compiler is an FPGA-compatible compiler
  • the second compiler is an NP-compatible compiler
  • the first processor can identify the second processor Type, and call the second compiler corresponding to the second processor to convert the target code C VIR to generate a binary file loaded on the second processor.
  • the first processor can identify the NP and call the second compiler corresponding to the NP to compile the binary file C VIR JIT to be on the NP. Loaded binary file.
  • FIG. 4 The apparatus 300 shown in FIG. 4 and the apparatus 400 shown in FIG. 5 are capable of executing the methods shown in FIGS. 1 through 3.
  • FIGS. 1 through 3 Regarding the specific implementation of the device 300 and the device 400, reference may be made to the description of the corresponding embodiment of FIGS. 1 to 3.
  • the apparatus 300 includes a first processing unit 310 and a second processing unit 320.
  • the first processing unit 310 the source code for compiling the high-level programming language description generates object code executable by the virtual machine, the source code defines a message processing operation, and the first processing unit 310 is further configured to convert the aims
  • the code generates a binary file; the second processing unit 320 that loads the binary file is configured to process the message according to the message processing operation.
  • the virtual machine is a Java virtual machine
  • the instruction in the target code is an instruction in a Java virtual machine instruction set
  • the virtual machine is a Berkeley message filter BPF virtual machine, in the target code
  • the instruction is an instruction in the BPF virtual machine instruction set
  • the virtual machine is an extended Berkeley message filter eBPF virtual machine
  • the instruction in the target code is an instruction in the eBPF virtual machine instruction set.
  • the first processing unit 310 is specifically configured to: disassemble the target code, generate a computer program of the AL description, and generate the binary file according to the computer program described by the AL.
  • the AL is a first AL
  • the first processing unit 310 is specifically configured to: convert the computer program of the first AL description into a computer program of a second AL description; describe the second AL
  • the computer program is assembled to generate the binary file.
  • the first processing unit 310 is specifically configured to: after the first processing unit 310 converts the target code to generate a binary file, and the second processing unit 320 that loads the binary file according to the The message processing operation saves the binary file to an instruction memory before the message is processed, and the second processing unit 320 is coupled to the instruction memory.
  • the second processing unit 320 is specifically configured to: acquire the binary file by accessing the instruction memory; and process the message by executing an instruction sequence in the binary file.
  • the first processing unit 310 is specifically configured to: convert the computer program described by the AL into a code described by an HDL; synthesize the code described by the HDL, and generate a gate level description; The description is converted to generate the binary file.
  • the first processing unit 310 is specifically configured to: after converting the target code to generate a binary file, and the second processing unit 320 that loads the binary file according to the packet processing operation, Before the message is processed, the binary file is loaded into the second processing unit 320 via the joint test behavior of the second processing unit 320, and the second processing unit 320 is reconfigurable logic.
  • the binary file is a bit configuration file.
  • the apparatus 300 herein is embodied in the form of a functional unit.
  • the device 300 is used to perform various processes and/or steps in the foregoing method embodiments. To avoid repetition, details are not described herein again.
  • the device 400 includes a memory 410, a first processor 420, and a second processor 430.
  • the first processor 420 and the second processor 430 may be the same processor or different processors.
  • the memory 410 can be integrated in the first processor 420 or can be independent of the first processor 420.
  • the first processor 420 and the memory 410 can communicate with one another via internal connection paths to communicate control and/or data signals.
  • the memory 410 can be used to store instructions (specifically, the memory 410 stores a compiler, the compiler including the first compiler and the second compiler above), the first processor 420 is configured to execute the memory 410 storage The instructions, and the operations performed by the first processor 420 of the foregoing embodiment of the present application.
  • the first processor 420 is configured to: the first processor compiles the source code of the high-level programming language description to generate object code that can be executed by the virtual machine, where the source code defines a message processing operation;
  • the first processor converts the target code to generate a binary file
  • the second processor 430 that loads the binary file is configured to: process the message according to the message processing operation.
  • the device 400 may further include a network interface, if the first processor 420 and the second processor 430 are different processors, the network interface is used to connect the first processor 420 and the second processor 430.
  • each step of the foregoing method embodiment may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method.
  • the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (Erasable PROM, EPROM), or an electric Erase programmable read only memory (EEPROM) or flash memory.
  • the volatile memory can be a Random Access Memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM).
  • SDRAM Double Data Rate SDRAM
  • DDR SDRAM Double Data Rate SDRAM
  • ESDRAM Enhanced Synchronous Dynamic Random Access Memory
  • SLDRAM Synchronous Connection Dynamic Random Access Memory
  • DR RAM direct memory bus random access memory
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices, and methods may It is achieved in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

本申请实施例提供一种用于处理报文的方法和装置，该方法具有灵活性以及兼容性，有利于在处理器上加载定义报文处理操作的二进制文件，从而有利于处理器进行报文处理。该方法包括：第一处理器编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，该源代码定义了报文处理操作；该第一处理器转换该目标代码生成二进制文件；加载了该二进制文件的第二处理器根据该报文处理操作，对报文进行处理。

Description

用于处理报文的方法和装置 技术领域
本申请涉及网络技术领域，并且更具体地，涉及一种用于处理报文的方法和装置。
背景技术
使能处理器执行某个处理操作，需要在处理器上加载定义该处理操作的二进制文件。例如，处理器可以对报文进行丢弃、修改或者转发。不同类型的处理器对应的指令集不同，即不同类型的处理器能够识别的代码不同。也就是说，为使得不同的处理器能够执行同一个处理操作，在不同处理器上加载的二进制文件是不同的。
现有技术中，在不同类型的处理器上加载的二进制文件是通过编译不同的编程语言描述的源代码生成的。也就是说，在不同类型的处理器上加载的二进制文件与源代码的编程语言具有对应关系，也就是说，处理器与源代码的编程语言具有对应关系。例如，在网络处理器(Network Processor，NP)上加载的二进制文件是通过编译汇编语言(Assembly Language，AL)描述的源代码生成的。即NP对应的源代码的编程语言为AL。又例如，在现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)上加载的二进制文件是通过编译硬件描述语言(Hardware Description Language，HDL)描述的源代码生成的。即FPGA对应的源代码的编程语言为HDL。
编译处理器对应的编程语言描述的源代码生成在该处理器上加载的二进制文件的技术方案不够灵活，成本比较高。
发明内容
本申请实施例提供一种用于处理报文的方法和装置，编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，在处理器上加载的二进制文件是通过转换该目标代码生成的，能够实现高级编程语言描述的源代码到在处理器上加载的二进制文件的转化。该方案具有较高的灵活性。
第一方面，提供一种用于处理报文的方法，该方法包括：第一处理器编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，所述源代码定义了报文处理操作；所述第一处理器转换所述目标代码生成二进制文件；加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理。
在现有技术中，待加载的二进制文件是通过编译处理器对应的编程语言描述的源代码生成的。其中，该源代码的编程语言与处理器的类型相关。对于不同类型的处理器，用户需要使用不同的编程语言描述源代码。而在本申请中，目标代码介于高级编程语言描述的源代码和加载在处理器上的二进制文件之间，用于实现高级编程语言描述的源代码到加载在处理器上的二进制文件的转化。程序员可以使用高级编程语言描述源代码。程序员不需要使用与处理器的类型对应的编程语言。因此，该方案具有较高的灵活性。另外，所述第一处理器可以将所述目标代码转换为不同的二进制文件，并分别将不同的二进制文件加载到不同的第二处理器中。也就是说，上述方案有助于根据高级编程语言描述的源代码生成不同处理器的二进制文件，有助于降低开发成本。
可选地，在第一方面可能的实现方式中，第一处理器为通用处理器，第二处理器为 通用处理器和专用处理器中的至少一种。
应理解，若第一处理器和第二处理器均为通用处理器，该第一处理器和第二处理器可以为同一个处理器也可以为不同的处理器。
可选地，在第一方面可能的实现方式中，第二处理器包括可重配的逻辑设备、NP、CPU以及多核系统级芯片Soc中的至少一种。
可选地，在第一方面可能的实现方式中，可重配的逻辑设备包括现场可编程逻辑门阵列FPGA以及复杂可编程逻辑器件CPLD。
可选地，在第一方面可能的实现方式中，该高级编程语言包括Java、C++、C、pascal、Python、Lisp，Prolog或FoxPro。
高级编程语言包括的语言种类多，用户可以灵活地选择相应语言进行源代码的描述，有利于在第二处理器上加载二进制文件，从而有利于第二处理器进行报文处理。
在第一方面可能的实现方式中，所述报文处理操作用于处理数据通信网络的L2层业务、数据通信网络的L3层业务、数据通信网络的L4层业务、数据通信网络的L5层业务、数据通信网络的L6层业务和数据通信网络的L7层业务中的至少一种。
该方案中，用户可以在第二处理器上加载定义相应报文处理器操作的二进制文件，以满足用户通过第二处理器进行报文处理的需求。
在第一方面可能的实现方式中，所述虚拟机为Java虚拟机，所述目标代码中的指令为Java虚拟机指令集中的指令；或者所述虚拟机为伯克利报文过滤器BPF虚拟机，所述目标代码中的指令为BPF虚拟机指令集中的指令；或者所述虚拟机为扩展的伯克利报文过滤器eBPF虚拟机，所述目标代码中的指令为eBPF虚拟机指令集中的指令。
在该方案中，虚拟机具有自己的指令集，有利于目标代码准确地转化成为加载在第二处理器上的二进制文件。
在第一方面可能的实现方式中，所述第一处理器转换所述目标代码生成二进制文件，包括：所述第一处理器对所述目标代码进行反汇编，生成AL描述的计算机程序；所述第一处理器根据所述AL描述的计算机程序，生成所述二进制文件。
应理解，对于不同的设备，AL对应不同的指令集。即，对于同一个处理操作，不同的设备对应的AL不同，也就是说，AL和设备具有对应关系。该通过对目标代码进行反汇编生成的AL为虚拟机对应的AL。该方案有利于将该目标代码转化为二进制文件。
在第一方面可能的实现方式中，所述AL为第一AL；所述第一处理器根据所述AL描述的计算机程序，生成所述二进制文件，包括：所述第一处理器将所述第一AL描述的计算机程序转换为第二AL描述的计算机程序；所述第一处理器对所述第二AL描述的计算机程序进行汇编，生成所述二进制文件。
该第一AL为虚拟机对应的AL，该第二AL为第二处理器对应的AL。该方案操作简单易于实现，有利于将目标代码转化为在第二处理器上加载的二进制文件。进一步地，该第二处理器可以为NP或中央处理器CPU。
在第一方面可能的实现方式中，所述第一处理器转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理之前，所述方法还包括：将所述二进制文件保存到指令存储器中，所述第二处理器与所述指令存储器耦合；所述加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理包括：所述第二处理器通过访问所述指令存储器获取所述二进制 文件；所述第二处理器通过执行所述二进制文件中的指令序列，对所述报文进行处理。
在第一方面可能的实现方式中，所述第一处理器根据所述AL描述的计算机程序，生成所述二进制文件，包括：所述第一处理器将所述AL描述的计算机程序转换为HDL描述的代码；所述第一处理器对所述HDL描述的代码进行综合，生成门级描述；所述第一处理器对所述门级描述进行转换，生成所述二进制文件。
该方案操作简单易于实现，有利于将目标代码转化为在第二处理器上加载的二进制文件。进一步地，若该第二处理器可以为可重配的逻辑设备。
可选地，在第一方面可能的实现方式中，该HDL可以包括：超高速集成电路硬件描述语言VHDL或Verilog语言。
可选地，该门级描述可以包括电子设计交换格式EDIF网表(netlist)。
在第一方面可能的实现方式中，所述第一处理器转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理之前，所述方法还包括：经由所述第二处理器的联合测试行为组织JTAG接口，将所述二进制文件加载到所述第二处理器，所述处理器为可重配的逻辑设备，所述二进制文件为比特配置文件。
可选地，在第一方面可能的实现方式中，所述可重配的逻辑设备包括FPGA，该比特配置文件具体为比特流文件(bitstream file)。例如，一个比特流文件可以表示为：*.bit。
可选地，在第一方面可能的实现方式中，所述可重配的逻辑设备包括CPLD，该比特配置文件具体为固态技术协会是微电子产业的领导标准机构JEDEC文件。例如，一个JEDEC文件可以表示为：*.jed。
在第一方面可能的实现方式中，所述第二处理器用于网络功能虚拟化NFV加速。
例如，该第二处理器可以为硬件加速器，采用本申请实施例的方法，用户可以根据需要灵活地在硬件加速器上加载二进制文件，以用于使该硬件加速器执行相应的操作，有利于提高NFV处理业务的效率，该方法灵活性高，可操作性强。
可选地，该硬件加速器的加速单元芯片可以包括嵌入式神经网络处理器NPU芯片、FPGA以及Soc中的至少一种。
第二方面，提供一种用于处理报文的装置，用于执行第一方面或第一方任意的可能实现方式中的方法，具体地，该装置可以包括用于执行第一方面或第一方面任意可能的实现方式中的方法的单元。
第三方面，提供一种用于处理报文的设备，该设备包括处理器，该处理器被配置为支持该设备执行上述方法中相应的功能。该设备还可以包括存储器，该存储器与处理器耦合，该存储器保存该设备必要的程序指令和数据。
第四方面，提供了一种计算机可读介质，用于储存为上述第一处理器和/或第二处理器所用的计算机软件指令，其包含用于执行上述方面所设计的程序。
第五方面，提供一种计算机程序产品，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码被用于报文处理的装置的第一处理单元和/或第二处理单元运行时，使得该装置执行上述实现方式中的方法；或当所述计算机程序代码被用于报文处理的设备的第一处理器和/或第二处理器运行时，使得该设备执行上述实现方式中的方法。
基于以上技术方案，本申请实施例提供的用于处理报文的方法、装置和设备，通过高级编程语言描述的源代码到目标代码的转化，进而从目标代码到二进制文件的转换， 该方案具有较高的灵活性以及兼容性，有利于在处理器上加载二进制文件，有利于使能处理器进行报文处理。
附图说明
图1是根据本申请实施例用于处理报文的方法的一例的示意性流程图。
图2是根据本申请实施例用于处理报文的方法的另一例的示意性流程图。
图3是根据本申请实施例的用于处理报文的方法的又一例的示意性流程图。
图4是根据本申请实施例的用于处理报文的装置的示意性框图。
图5是根据本申请实施例的用于处理报文的设备的示意性框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
应理解，本申请实施例中的方式的划分仅是为了描述的方便，不应构成特别的限定，各种方式中的特征在不矛盾的情况下可以相结合。
还应理解，申请实施例中的“第一”以及“第二”仅为了区分，不应对本申请构成任何限定。
现有技术中，使能处理器执行某个处理操作，用户需要使用该处理器对应的编程语言描述定义该处理操作的源代码，编译该源代码生成(能够)在该处理器上加载的二进制文件，加载了该二进制文件的处理器能够根据该处理操作进行相应处理，该方法不利于在处理器上加载二进制文件，从而不利于处理器进行相应处理。
首先，该方法具有局限性。
具体地，在该方法中，处理器与描述源代码的编程语言具有对应关系，导致通过某种编程语言描述的源代码只能加载在某些特定类型的处理器上。
例如，使能FPGA执行处理操作A，用户需要使用HDL(例如，Verilog语言)描述定义该处理操作A的源代码，为了便于说明，将“HDL描述的定义该处理操作A的源代码”记为“源代码CA(HDL)”编译该源代码CA(HDL)能够生成在FPGA上加载的二进制文件CFPGA-A。但是，该源代码CA(HDL)无法转换为在NP上加载的二进制文件CNP-A。同理，NP对应的AL描述的源代码CA(AL)能够转换为二进制文件CNP-A但是无法转换为CNP-A。该方法具有局限性。
进一步地，若多种类型的处理器有执行同一个处理操作的需求，用户需要使用多种编程语言一一对应描述多种源代码。例如，假设使能FPGA和NP执行处理操作A，用户需要使用分别描述源代码CA(HDL)以及源代码CA(AL)，该方法会导致人力资源浪费。
需要说明是，在处理器上加载的二进制文件可以理解为：该处理器能够识别该二进制文件，该处理器获取该二进制文件之后，能够执行该二进制文件定义的处理操作。
其次，该方法对开发环境要求较高。
通常情况下，源代码的开发环境与处理器相关。例如，假设处理器为赛灵思(Xilinx)公司生产的FPGA，该源代码的开发环境为ISE开发环境。具体地，用户需要在ISE开发环境下使用Verilog语言描述源代码(即使用ISE软件通过Verilog语言描述源代码)。又例如，假设处理器为拓朗半导体(Altera)公司生产的FPGA，用户需要在quartus开发环境下使用Verilog语言描述源代码，该方法对开发环境要求较高。
进一步地，该方式对用户的专业能力要求较高。
例如，FPGA需要具有逻辑电路开发能力的专业开发人员进行Verilog代码的描述。通常情况下，用户不具有逻辑电路开发能力，从而不利于在处理器上加载二进制文件。
通过以上分析可以发现，现有技术中在处理器上加载二进制文件的方法存在局限性、开发环境要求高以及专业性强等缺点，不利于在处理器上加载二进制文件，从而不利于处理器对数据进行处理。
因此，本申请实施例提供一种用于处理报文的方法，该方法有利于在处理器上加载二进制文件，从而有利于处理器根据该二进制文件定义的处理操作对报文进行处理。
为便于理解本申请实施例，在描述本申请实施例的用于处理报文的方法之前，首先对本申请实施例涉及到的相关概念作简单介绍。
高级编程语言，是以人类的日常语言为基础的一种编程语言，使用一般人易于接受的文字来表示(例如汉字、不规则英文或其他外语)，从而使描述更容易，亦有较高的可读性。Java、C++、C、pascal、Python、Lisp，Prolog，FoxPro等都属于高级编程语言。
汇编语言AL，是一种用于电子计算机、微处理器、微控制器或其他可编程器件的低级语言。在汇编语言中，用助记符(Mnemonics)代替机器指令的操作码，用地址符号(Symbol)或标号(Label)代替指令或操作数的地址。在不同的设备中，汇编语言对应着不同的机器语言指令集，通过汇编过程转换成机器指令，特定的汇编语言和特定的机器语言指令集是一一对应的。也就是说，不同的设备对应不同的汇编语言。
源代码(Source Code)，是指未编译的按照一定的业务设计语言规范描述的文本文件，是一系列人类可读的计算机语言指令。源代码(或源程序)不能直接被机器(例如，计算机)识别，需要经过编译生成的二进制文件，二进制文件可以能被机器识别。
需要说明是的，在本申请中，将开发人员(或用户)通过编程语言描述的代码记为“源代码”。
编译(Compilation)，是指在应用源代码执行之前，将一种语言“翻译”成另外一种语言的过程。例如，将高级编程语言(源代码)翻译成计算机可以识别的机器语言(目标代码)。
目标代码(Object Code)，指计算机科学中编译器或汇编器处理源代码后所生成的代码，它一般由机器代码或接近于机器语言的代码组成。
二进制文件(Binaries)，也叫“目标文件(Object File)”是用于记录目标代码的文件。二进制文件包含着目标代码以及代码在运行时使用的数据，如重定位信息，如用于链接或调试的业务符号(变量和函数的名字)，此外还包括其他调试信息。
二进制文件是机器(应理解，该机器可以是实体机器也可以是虚拟机)可以识别的文件。通过编译源代码生成对应的二进制文件。例如，编译Verilog语言描述的源代码生成在FPGA上加载的二进制文件。编译NP对应的AL描述的源代码生成在NP上加载的二进制文件。
以下，结合图1、图2和图3，详细说明根据本申请实施例用于处理报文的方法的详细过程。
图1是根据本申请实施例的用于处理报文的方法100的示意性流程图。应理解，图1示出了用于处理报文的方法的详细的步骤或操作，但这些步骤或操作仅是示例，本申请实施例还可以执行其它操作或者图1中的各种操作的变形。
如图1所示，该方法100涉及第一处理器和第二处理器。
在这里，该第一处理器可以理解为能够将高级编程语言描述的源代码转换为二进制文件的处理器。该第二处理器可以理解为使能执行该二进制文件定义的报文处理操作的处理器(即待加载二进制文件的处理器)。
具体地，该第一处理器为通用处理器。其中，对于通用处理器并没有严格的定义，目前最广泛的概念是“通用处理器是图灵完备的”，也就是说，通用处理器计算能力与一个通用图灵机相当，能计算出图灵可计算函数的结果(一切可计算的问题都能计算)。
第二处理器可以为通用处理器也可以为专用处理器。其中，专用处理器(或者协处理器)在计算一些特定任务时很快，但是无法计算其之外的其它应用。例如，本申请实施例的NP就是一种专用处理器。可选地，该第二处理器可以包括可重配的逻辑设备、CPU、NP以及多核系统级芯片(System on Chip，Soc)中的至少一种。其中，该可重配的逻辑设备可以包括FPGA、复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)中的至少一种。
若第一处理器和第二处理器均为通用处理器，该第一处理器和第二处理器可以为同一个处理器也可以为不同的处理器。
例如，第一处理器和第二处理器为同一个中央处理器(Central Processing Unit，CPU)，该CPU生成二进制文件，该CPU加载该二进制文件并根据该二进制文件定义的报文处理操作，对报文进行处理。
又例如，该第一处理器为第一CPU，该第二处理器为第二CPU，该第一CPU和第二CPU不同。
该第一处理器和第二处理器还可以为不同的处理器。例如，第一处理器为CPU，第二处理器为NP，该CPU生成二进制文件，该NP加载该CPU生成的二进制文件，该NP根据该二进制文件定义的报文处理操作，对报文进行处理。
具体地，该方法100可以包括S110、S120以及S130。
S110、第一处理器编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，所述源代码定义了报文处理操作。
其中，虚拟机指通过软件模拟的具有完整硬件系统功能的、运行在一个完全隔离环境中的完整系统。虚拟机的虚拟系统通过生成现有操作系统的全新虚拟镜像，它具有windows操作系统、linux操作系统或其他操作系统完全一样的功能，进入虚拟系统后，所有操作都是在这个全新的独立的虚拟系统里面进行，可以独立安装运行软件，保存数据，拥有自己的独立桌面，不会对真正的系统产生任何影响，而且具有能够在现有系统与虚拟镜像之间灵活切换的一类操作系统。
可选地，该虚拟机可以包括多种类型的虚拟机，
例如，所述虚拟机可以为Java虚拟机，所述目标代码中的指令为Java虚拟机指令集中的指令。
又例如，所述虚拟机可以为伯克利报文过滤器(Berkeley Packet Filter，BPF)虚拟机，所述目标代码中的指令为BPF虚拟机指令集中的指令。
再例如，所述虚拟机可以为扩展的伯克利报文过滤器(Extend Berkeley Packet Filter，eBPF)虚拟机，所述目标代码中的指令为eBPF虚拟机指令集中的指令。该虚拟机可以是微软虚拟机、Linux虚拟机等其他类型的虚拟机。
其中，Java虚拟机、BPF虚拟机以及eBPF虚拟机具有指令集，有利于后续转换目标代码生成二进制文件。
可选地，该报文处理操作可以是对报文执行转发操作，对报文执行修改操作，计算校验和(英文：checksum)，对生存时间的值减一，对报文执行计数操作，对报文执行服务质量(英文：quality of service，简称：QoS)操作，或者对报文执行访问控制操作以及对报文执行丢弃操作。
举例来说，所述转发操作可以是三层虚拟专用网(英文：layer 3 virtual private network，简称：L3VPN)转发，二层虚拟专用网(英文：layer 2 virtual private network，简称：L2VPN)转发，虚拟专用局域网业务(英文：virtual private LAN service，简称：VPLS)转发，多协议标签交换(英文：multiprotocol label switching，简称：MPLS)转发，IP转发或者二层交换(英文：layer 2 switching)。
应理解，不同的处理操作通过不同的源代码进行定义。例如，假设定义报文处理操作A的源代码和定义报文处理操作B的源代码均通过高级编程语言描述，该定义报文处理操作A的源代码与定义报文处理操作B的源代码不同。
还应理解，源代码、编译该源代码生成的目标代码以及下文描述的转换该目标代码生成的二进制文件，三者定义的报文处理相同。例如，使能第二处理器执行报文处理操作A，高级语言编写的源代码定义该报文处理操作A，编译该源代码生成目标代码，该目标代码定义该报文处理操作A，以及转换该目标代码生成二进制文件，该二进制文件定义该报文处理操作A。
以下，为了便于说明，将“高级编程语言描述的源代码”记为“源代码CC”，将“能够被虚拟机执行的目标代码”记为“目标代码CVIR”。
该目标代码CVIR与第二处理器无关。其中，该“该目标代码CVIR与第二处理器无关”可以理解为：不论第二处理器为何种类型的处理器，在第二处理器上加载的二进制文件均能够通过转换该目标代码CVIR生成。
进一步地，在本申请实施例中，该S110可以包括：
提前(Ahead Of Time，AOT)编译(例如，静态编译)所述源代码CC，生成所述目标代码CVIR。
S120、所述第一处理器转换所述目标代码生成二进制文件。
S130、加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理。
应理解，“所述第一处理器转换所述目标代码生成二进制文件”可以理解为所述第一处理器转换所述目标代码生成在第二处理器上加载的二进制文件。对于不同类型的第二处理器，第一处理器转换该目标代码得到的二进制文件不同。
例如，假设第一处理器为CPU，第二处理器为FPGA，该CPU可以转换该目标代码CVIR生成在FPGA上加载的二进制文件CFPGA，加载了二进制文件CFPGA的FPGA可以执行该二进制文件CFPGA定义的报文处理操作。
又例如，假设第一处理器为CPU，第二处理器为NP，该CPU可以转换该目标代码CVIR生成能够在NP上加载的二进制文件CNP，加载了二进制文件CNP的NP可以执行该二进制文件CNP定义的报文处理操作。
可选地，该S120具体可以包括：第一处理器即时(Just In Time，JIT)编译该目标 代码生成二进制文件。
假设第一处理器和第二处理器为不同的处理器，在第一处理器与第二处理器相连的情况下，该第一处理器可以识别该第二处理器的类型。该第一处理器还可以安装该第二处理器的驱动软件，该第一处理器JIT编译该目标代码生成在该第二处理器上加载的二进制文件。
例如，假设第二处理器为FPGA，该FPGA与第一处理器相连后，该第一处理器可以识别该FPGA并JIT编译该目标代码CVIR生成在FPGA上加载的二进制文件，假设第二处理器为NP，该NP与第一处理器相连后，该第一处理器可以识别该NP并JIT编译该目标代码CVIR生成在NP上加载的二进制文件。
在本申请实施例中，第一处理器可以通过多种方式，转换该目标代码CVIR生成二进制文件。
图2和图3是根据本申请实施例的方法的示意性流程图。如图2和图3所示，作为可选地一例，该S120可以包括：
S121、所述第一处理器对所述目标代码进行反汇编，生成AL描述的计算机程序；
S122、所述第一处理器根据所述AL描述的计算机程序，生成所述二进制文件。
应理解，该AL为虚拟机对应的AL，为了便于说明，将该“虚拟机对应的AL”记为“第一AL”。
具体地，该第一处理器至少可以通过以下几种方式根据第一AL描述的计算机程序，生成所述二进制文件。
方式一、
图2是根据本申请实施例的用于报文处理的方法的另一例的示意性流程图，如图2所示，可选地，该S122可以包括：
S122a1、所述第一处理器将所述第一AL描述的计算机程序转换为第二AL语言描述的计算机程序；
其中，该第二AL为该第二处理器对应的AL。例如，假设第二处理器为NP，该第二AL为NP对应的AL。
S122a2、所述第一处理器对所述第二AL语言描述的计算机程序进行汇编，生成所述二进制文件.
方式二、
图3是根据本申请实施例的用于报文处理的方法的另一例的示意性流程图，如图3所示，可选地，该S122可以包括：
S122b1、所述第一处理器将所述第一AL语言描述的计算机程序转换为HDL描述的代码；
可选地，该HDL可以包括VHDL或Verilog语言。
S122b2、所述第一处理器对所述HDL的代码进行综合，生成门级描述；
可选地，该门级描述可以是电子设计交换格式(Electronic Design Interchange Format，EDIF)网表(netlist)。
S122b3、所述第一处理器对所述门级描述进行转换，生成所述二进制文件。
作为可选地一例，所述第一处理器转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理之前， 该方法100还可以包括：
第一处理器将该二进制文件加载到第二处理器上。进一步地，该第一处理器可以通过多种方式将该二进制文件加载到第二处理器上。
例如，第一处理器将所述二进制文件保存到指令存储器中，所述第二处理器与所述指令存储器耦合。该S130可以包括：所述第二处理器通过访问所述指令存储器获取所述二进制文件；所述第二处理器通过执行所述二进制文件中的指令序列，对所述报文进行处理。
又例如，第一处理器经由所述第二处理器的联合测试行为组织(Joint Test Action Group，JTAG)接口，将所述二进制文件加载到所述第二处理器，所述第二处理器为可重配的逻辑设备，所述二进制文件为比特配置文件。
作为可选地一例，所述可重配的逻辑设备包括FPGA，该比特配置文件具体为比特流文件(bitstream file)。例如，一个比特流文件可以表示为：*.bit。
作为可选地另一例，所述可重配的逻辑设备包括CPLD，该比特配置文件具体为固态技术协会是微电子产业的领导标准机构(Joint Electron Device Engineering Council，JEDEC)文件。例如，一个JEDEC文件可以表示为：*.jed。
进一步地，第一处理器可以通过应用程序编程接口(Application Programming Interface，API)对该二进制文件进行封装，以用于第一处理器将该二进制文件加载至第二处理器中。
在本申请实施例中，第一处理器编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，加载在处理器上的二进制文件是通过转换该目标代码生成的，该目标代码作为过程码，用于实现高级编程语言描述的源代码到加载在处理器上的二进制文件的转化，有利于节约人力资源。进一步地，相较于其他编程语言(例如HDL)，高级编程语言简单易操作，且高级编程语言具有开放的开发环境，能够节省使能第二处理器执行处理操作的成本。更进一步地，高级编程语言的种类较多，开发人员的选择性大。该方法具有较高的兼容性、灵活性且操作简单，有利于在第二处理器上加载二进制文件，从而有利于第二处理器对报文进行处理。
可选地，该第二处理器用于网络功能虚拟化(Network Function Virtualization，NFV)加速。例如，该第二处理器可以为硬件加速器，该硬件加速器的加速单元芯片可以包括嵌入式神经网络处理器(Network Processing Unit，NPU)芯片、FPGA或Soc等。该硬件加速器可以应用在多种设备形态上，例如，该硬件加速器可以是最新的总线和接口标准(Peripheral Component Interconnect Express，PCIE)网卡或加速资源池设备等。
以上，从整体角度描述本申请实施例的方法，其中，第一处理器能够实现源代码-目标代码-二进制文件的转换。进一步地，第一处理器可以通过运行在该第一处理器上的软件，实现源代码-目标代码-二进制文件的转换。以下，以一些软件为例，详细说明本申请实施例的方法，需要说明是，下文涉及的软件仅为示例不应对本申请构成任何限定。
作为可选地一例，该S110具体可以包括：
第一处理器通过运行在该第一处理器上的第一编译器编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码。
应理解，不同的高级编程语言对应不同的第一编译器。例如，若使用C语言描述源代码，该第一编译器为C语言编译器；若使用JAVA语言描述源代码，该第一编译器为 JAVA编译器。
还应理解，每一种高级编程语言对应的第一编译器可以包括多种类型的编译器。例如，假设源代码CC是通过C语言描述的，该第一编译器可以包括：Turbo C、Borland C++或底层虚拟机(Low Level Virtual Machine，LLVM)等C语言编译器。
可选地，该方法100还可以包括：
第一处理器获取该源代码CC。
具体地，该第一处理器通过运行在第一处理器上的编程软件获取该源代码CC，其中，该编程软件用于开发人员(或用户)进行源代码的描述，该第一编译器可以通过该编程软件获取该源代码。
应理解，不同的高级编程语言对应不同的编程软件。例如，若使用C语言描述源代码A，该编程软件可以包括Microsoft Visual C++、Microsoft Visual Studio、DEV C++或Watcom C++等C语言编程软件。
进一步地，该第一编译器和该编程软件运行在第一处理器上的虚拟机上。
例如，用户可以打开在第一处理器上运行的虚拟机的编程软件，该编程软件可以为Microsoft Visual C++软件。用户通过该软件描述定义报文处理操作A的源代码CC-A。该虚拟机的第一编译器为LLVM编译器，该LLVM编译器可以获取该源代码CC-A，并编译该源代码CC-A生成目标代码CVIR-A。
作为可选地一例，该S120具体可以包括：
第一处理器通过运行在该第一处理器上的第二编译器转换所述目标代码生成二进制文件
应理解，该第二编译器属于运行在第一处理器上的软件系统的编译器，该软件系统与虚拟机相互独立。
还应理解，不同的第二处理器对应不同的第二编译器。例如，若第二处理器为FPGA，该第二编译器为FPGA对应的编译器，若的第二处理器为NP，该第二编译器为NP对应的编译器。
若第一处理器和第二处理器不是同一个处理器，第一处理器和第二处理器相连之后，该第一处理器(第一处理通过内部的软件)可以识别该第二处理器的类型，并调用该第二处理器对应的第二编译器转换该目标代码CVIR生成在该第二处理器上加载的二进制文件。
例如，假设第二处理器为NP，该NP与第一处理器相连后，该第一处理器可以识别该NP并调用NP对应的第二编译器将该二进制文件CVIRJIT编译为在NP上加载的二进制文件。
以上，结合图1至图3详细说明了本申请实施例的用于处理报文的方法。以下，结合图4和图5详细说明本申请实施例的用于处理报文的装置和设备。图4所示的装置300以及图5所示的设备400能够执行图1至图3所示的方法。关于装置300以及设备400的具体实现方式，可以参考图1至图3对应的实施例的描述。
图4是根据本申请实施例的用于处理报文的装置的示意性框图。如图4所示，该装置300包括第一处理单元310以及第二处理单元320。
第一处理单元310，用于编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，所述源代码定义了报文处理操作，所述第一处理单元310还用于转换所述目标 代码生成二进制文件；加载了所述二进制文件的第二处理单元320，用于根据所述报文处理操作，对报文进行处理。
可选地，所述虚拟机为Java虚拟机，所述目标代码中的指令为Java虚拟机指令集中的指令；或者所述虚拟机为伯克利报文过滤器BPF虚拟机，所述目标代码中的指令为BPF虚拟机指令集中的指令；或者所述虚拟机为扩展的伯克利报文过滤器eBPF虚拟机，所述目标代码中的指令为eBPF虚拟机指令集中的指令。
可选地，所述第一处理单元310具体用于：对所述目标代码进行反汇编，生成AL描述的计算机程序；根据所述AL描述的计算机程序，生成所述二进制文件。
可选地，所述AL为第一AL；所述第一处理单元310具体用于：将所述第一AL描述的计算机程序转换为第二AL描述的计算机程序；对所述第二AL描述的计算机程序进行汇编，生成所述二进制文件。
可选地，所述第一处理单元310具体用于：在所述第一处理单元310转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理单元320根据所述报文处理操作，对报文进行处理之前，将所述二进制文件保存到指令存储器中，所述第二处理单元320与所述指令存储器耦合。
所述第二处理单元320具体用于：通过访问所述指令存储器获取所述二进制文件；通过执行所述二进制文件中的指令序列，对所述报文进行处理。
可选地，所述第一处理单元310具体用于：将所述AL描述的计算机程序转换为HDL描述的代码；对所述HDL描述的代码进行综合，生成门级描述；对所述门级描述进行转换，生成所述二进制文件。
可选地，所述第一处理单元310具体用于：在转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理单元320根据所述报文处理操作，对报文进行处理之前，经由所述第二处理单元320的联合测试行为组织JTAG接口，将所述二进制文件加载到所述第二处理单元320，所述第二处理单元320为可重配的逻辑设备，所述二进制文件为比特配置文件。
应理解，这里的装置300以功能单元的形式体现。该装置300用于执行上述方法实施例中的各个流程和/或步骤，为了避免重复，在此不再赘述。
图4是根据本申请实施例的用于处理报文的设备的示意性框图。如图4所示，该设备400包括：存储器410、第一处理器420和第二处理器430。其中第一处理器420和第二处理器430可以为同一个处理器，也可以为不同的处理器。该存储器410可以集成在第一处理器420中，也可以独立于第一处理器420。该第一处理器420和存储器410可以通过内部连接通路互相通信，传递控制和/或数据信号。
该存储器410可以用于存储指令(具体地，该存储器410存储编译器，该编译器包括上文中的第一编译器以及第二编译器)，该第一处理器420用于执行该存储器410存储的指令，并实现本申请前述实施例第一处理器420执行的操作。
具体地，第一处理器420用于：第一处理器编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，所述源代码定义了报文处理操作；
所述第一处理器转换所述目标代码生成二进制文件；
加载了该二进制文件的第二处理器430用于：根据所述报文处理操作，对报文进行处理。
可选地，该设备400还可以包括网络接口，若该第一处理器420和第二处理器430为不同的处理器，该网络接口用于连接第一处理器420和第二处理器430.
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的装置300和设备400的更具体实现以及描述，可以参考前述方法实施例的对应过程，为了简洁，在此不再赘述。
应注意，本申请上述方法实施例可以应用于处理器中，或者由处理器实现。处理器可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。
可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
可理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以 通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式。熟悉本技术领域的技术人员在本申请揭露的技术范围内，可想到变化或替换。

Claims (14)

  1. 一种用于处理报文的方法，其特征在于，所述方法包括：
    第一处理器编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，所述源代码定义了报文处理操作；
    所述第一处理器转换所述目标代码生成二进制文件；
    加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理。
  2. 根据权利要求1所述的方法，其特征在于，所述虚拟机为Java虚拟机，所述目标代码中的指令为Java虚拟机指令集中的指令；或者
    所述虚拟机为伯克利报文过滤器BPF虚拟机，所述目标代码中的指令为BPF虚拟机指令集中的指令；或者
    所述虚拟机为扩展的伯克利报文过滤器eBPF虚拟机，所述目标代码中的指令为eBPF虚拟机指令集中的指令。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第一处理器转换所述目标代码生成二进制文件，包括：
    所述第一处理器对所述目标代码进行反汇编，生成汇编语言描述的计算机程序；
    所述第一处理器根据所述汇编语言描述的计算机程序，生成所述二进制文件。
  4. 根据权利要求3所述的方法，其特征在于，所述汇编语言为第一汇编语言；
    所述第一处理器根据所述汇编语言描述的计算机程序，生成所述二进制文件，包括：
    所述第一处理器将所述第一汇编语言描述的计算机程序转换为第二汇编语言描述的计算机程序；
    所述第一处理器对所述第二汇编语言描述的计算机程序进行汇编，生成所述二进制文件。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述第一处理器转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理之前，所述方法还包括：
    所述第一处理器将所述二进制文件保存到指令存储器中，所述第二处理器与所述指令存储器耦合；
    所述加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理包括：
    所述第二处理器通过访问所述指令存储器获取所述二进制文件；
    所述第二处理器通过执行所述二进制文件中的指令序列，对所述报文进行处理。
  6. 根据权利要求3所述的方法，其特征在于，所述第一处理器根据所述汇编语言描述的计算机程序，生成所述二进制文件，包括：
    所述第一处理器将所述汇编语言描述的计算机程序转换为硬件描述语言描述的代码；
    所述第一处理器对所述硬件描述语言描述的代码进行综合，生成门级描述；
    所述第一处理器对所述门级描述进行转换，生成所述二进制文件。
  7. 根据权利要求1、2、3或6所述的方法，其特征在于，所述第一处理器转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理器根据所述报文处理操作，对报文进行处理之前，所述方法还包括：
    经由所述第二处理器的联合测试行为组织JTAG接口，将所述二进制文件加载到所述第二处理器，所述第二处理器为可重配的逻辑设备，所述二进制文件为比特配置文件。
  8. 一种用于处理报文的装置，其特征在于，所述装置包括：
    第一处理单元，用于编译高级编程语言描述的源代码生成能够被虚拟机执行的目标代码，所述源代码定义了报文处理操作，所述第一处理单元还用于转换所述目标代码生成二进制文件；
    加载了所述二进制文件的第二处理单元，用于根据所述报文处理操作，对报文进行处理。
  9. 根据权利要求7所述的装置，其特征在于，所述虚拟机为Java虚拟机，所述目标代码中的指令为Java虚拟机指令集中的指令；或者
    所述虚拟机为伯克利报文过滤器BPF虚拟机，所述目标代码中的指令为BPF虚拟机指令集中的指令；或者
    所述虚拟机为扩展的伯克利报文过滤器eBPF虚拟机，所述目标代码中的指令为eBPF虚拟机指令集中的指令。
  10. 根据权利要求8或9所述的装置，其特征在于，所述第一处理单元具体用于：
    对所述目标代码进行反汇编，生成汇编语言描述的计算机程序；
    根据所述汇编语言描述的计算机程序，生成所述二进制文件。
  11. 根据权利要求10所述的装置，其特征在于，所述汇编语言为第一汇编语言；
    所述第一处理单元具体用于：
    将所述第一汇编语言描述的计算机程序转换为第二汇编语言描述的计算机程序；
    对所述第二汇编语言描述的计算机程序进行汇编，生成所述二进制文件。
  12. 根据权利要求8至11中任一项所述的装置，其特征在于，所述第一处理单元具体用于：
    在所述第一处理单元转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理单元根据所述报文处理操作，对报文进行处理之前，
    将所述二进制文件保存到指令存储器中，所述第二处理单元与所述指令存储器耦合；
    所述第二处理单元具体用于：
    通过访问所述指令存储器获取所述二进制文件；
    通过执行所述二进制文件中的指令序列，对所述报文进行处理。
  13. 根据权利要求10所述的装置，其特征在于，所述第一处理单元具体用于：
    将所述汇编语言描述的计算机程序转换为硬件描述语言HDL描述的代码；
    对所述硬件描述语言描述的代码进行综合，生成门级描述；
    对所述门级描述进行转换，生成所述二进制文件。
  14. 根据权利要求8、9、10或13所述的装置，其特征在于，所述第一处理单元具体用于：
    在转换所述目标代码生成二进制文件之后，以及所述加载了所述二进制文件的第二处理单元根据所述报文处理操作，对报文进行处理之前，
    经由所述第二处理单元的联合测试行为组织JTAG接口，将所述二进制文件加载到所述第二处理单元，所述第二处理单元为可重配的逻辑设备，所述二进制文件为比特配置文件。
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