WO2018151029A1 - Capacitor - Google Patents

Capacitor Download PDF

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Publication number
WO2018151029A1
WO2018151029A1 PCT/JP2018/004530 JP2018004530W WO2018151029A1 WO 2018151029 A1 WO2018151029 A1 WO 2018151029A1 JP 2018004530 W JP2018004530 W JP 2018004530W WO 2018151029 A1 WO2018151029 A1 WO 2018151029A1
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Prior art keywords
capacitor
metal
cavity
substrate
dielectric layer
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PCT/JP2018/004530
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French (fr)
Japanese (ja)
Inventor
晃 白鳥
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株式会社村田製作所
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Publication of WO2018151029A1 publication Critical patent/WO2018151029A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 

Definitions

  • the present invention relates to a capacitor.
  • Patent Document 1 has a conductive metal base material having a porous portion, a dielectric layer located on the porous portion, and an upper electrode located on the dielectric layer.
  • a capacitor having a capacitance forming portion only on one main surface side is disclosed.
  • ⁇ Capacitors as described above are usually manufactured as a collective substrate and divided into individual elements. At this time, if a metal part is present in the cut part, the upper electrode and the lower electrode may be short-circuited due to flash generated by the cutting. Further, since the metal has high ductility and viscosity, it is easily stretched in the cutting direction during cutting. The extended metal may cause a short circuit between the upper electrode and the lower electrode at the end face of the capacitor.
  • a conductive metal base material is a main constituent member, and a collective substrate is manufactured from a single metal substrate. Therefore, this metal substrate exists on the cut surface. Therefore, there is a problem that the short circuit between the upper electrode and the lower electrode is likely to occur.
  • an object of the present invention is to provide a capacitor that has a high capacitance and can be easily separated from the collective substrate.
  • the present inventors have found that a capacitor made of a conductive material such as metal is not disposed at a location where the material is cut from the collective substrate.
  • the present inventors have found that a short circuit at the end face of the film can be suppressed, and have reached the present invention.
  • the present invention An insulating substrate; A conductive porous substrate having a porous portion; A dielectric layer located on the porous portion; An upper electrode located on the dielectric layer; A capacitor in which the insulating substrate has a cavity, and the conductive porous substrate, the dielectric layer, and the upper electrode are provided in the cavity. To do.
  • a capacitor comprising an insulating substrate, a conductive porous substrate having a porous part, a dielectric layer located on the porous part, and an upper electrode located on the dielectric layer
  • FIG. 1 is a schematic cross-sectional view of a capacitor 1a according to one embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of the capacitance forming portion 4 of the capacitor 1a shown in FIG.
  • FIG. 3 is a schematic plan view of the insulating sheet 21 used for manufacturing the capacitor 1a.
  • FIG. 4 is a schematic plan view of one surface of the insulating sheet 22 used for manufacturing the capacitor 1a.
  • FIG. 5 is a schematic plan view of another surface of the insulating sheet 22 used for manufacturing the capacitor 1a.
  • FIG. 6 is a schematic plan view of the insulating sheet 23 used for manufacturing the capacitor 1a.
  • FIG. 1 is a schematic cross-sectional view of a capacitor 1a according to one embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of the capacitance forming portion 4 of the capacitor 1a shown in FIG.
  • FIG. 3 is a schematic plan view of the insulating sheet 21 used for manufacturing the capacitor 1
  • FIG. 7 is a schematic cross-sectional view of the substrate before the capacitance forming portion 4 is formed in the cavity 3 of the insulating base 2.
  • FIG. 8 is a view showing a cutting part of the collective substrate 29.
  • FIG. 9 is a schematic cross-sectional view of a capacitor 1b according to another embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view for explaining the state of the substrate during firing.
  • the capacitor 1 a includes an insulating base 2 and a capacitance forming portion 4 provided in the cavity 3 of the insulating base 2.
  • a first external electrode 5 is provided on the capacitance forming portion 4.
  • a cavity electrode 6 is provided at the bottom of the cavity 3.
  • a second external electrode 7 is provided on the bottom surface of the insulating substrate 2, and a metal layer 8 is provided on the second external electrode 7.
  • a via 9 is provided between the cavity electrode 6 and the second external electrode 7 so as to penetrate the insulating substrate 2 and electrically connect them.
  • the capacitance forming unit 4 includes a conductive porous substrate 11 functioning as a lower electrode, a dielectric layer 12 positioned on the conductive porous substrate 11, and an upper electrode 13 positioned on the dielectric layer 12. Consists of The first external electrode 5 is provided on the upper electrode 13. No metal material is present at the end of the capacitor 1a, and the capacitor 1a is entirely composed of the insulating substrate 2. In the capacitor 1 a, by applying a voltage between the first external electrode 5 and the metal layer 8, a voltage is applied between the lower electrode, that is, the conductive porous substrate 11 and the upper electrode 13, and the dielectric layer 12 is applied. Charge can be accumulated.
  • the capacitor 1a as described above is manufactured as follows, for example.
  • insulating sheets 21, 22, 23, and 24 constituting the insulating base 2 are prepared.
  • the insulating sheet 21 has a plurality of openings 25 corresponding to the cavities 3 of the capacitor 1a.
  • the insulating sheet 22 has a metal layer 26 corresponding to the cavity electrode 6 of the capacitor 1 a on one main surface and a through metal layer 27 corresponding to the via 9.
  • the insulating sheet 23 has a through metal layer 27 corresponding to the via 9 of the capacitor 1a, as shown in FIG.
  • the insulating sheet 24 is the same as the insulating sheet 22 except that the cavity electrode 6 is replaced with the second external electrode 7, and has a metal layer 26 corresponding to the second external electrode 7 on one main surface, and a via 9 has a through metal layer 27 corresponding to 9.
  • each insulating sheet is not particularly limited as long as it is an insulating material, and examples thereof include various ceramic materials, glass ceramic materials, resin materials, and the like.
  • the insulating material is preferably a ceramic material, particularly a glass ceramic material.
  • Examples of the ceramic material include alumina and zirconia.
  • Examples of the glass ceramic material include a mixture of CaO—Al 2 O 3 —SiO 2 glass and alumina.
  • glass ceramic materials include CaO—Al 2 O 3 —SiO 2 —B 2 O 3 glass, Na 2 O—SiO 2 glass, Na 2 O—CaO—SiO 2 glass, Na 2 O—CaO. —SiO 2 —Al 2 O 3 glass, Na 2 O—CaO—SiO 2 —Al 2 O 3 —B 2 O 3 glass, Na 2 O—B 2 O 3 —SiO 2 glass, Na 2 O— Examples thereof include B 2 O 3 —CaO—SiO 2 glass, B 2 O 3 —Al 2 O 3 —SiO 2 glass, and the like.
  • the resin material is preferably a heat-resistant resin, and examples thereof include polyimide, polybenzoxazole, polyethylene terephthalate, benzocyclobutene resin, and epoxy resin.
  • the resin material may contain a filler for adjusting the linear expansion coefficient, such as a Si filler.
  • each insulating sheet is not particularly limited, but may be, for example, 1 ⁇ m or more and 1.0 mm or less, preferably 10 ⁇ m or more and 200 ⁇ m or less, for example, 20 ⁇ m or more and 100 ⁇ m or less.
  • the material constituting the cavity electrode 6 is not particularly limited, and examples thereof include metals such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and alloys thereof.
  • the material constituting the cavity electrode 6 is Cu.
  • the thickness of the cavity electrode 6 is not particularly limited, but is preferably 0.1 ⁇ m to 100 ⁇ m, more preferably 0.5 ⁇ m to 50 ⁇ m, still more preferably 0.5 ⁇ m to 10 ⁇ m, for example, 1 ⁇ m to 5 ⁇ m. .
  • the material constituting the via 9 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu. Preferably, the material constituting the via 9 is Cu.
  • the material constituting the second external electrode 7 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu. Preferably, the material constituting the second external electrode 7 is Cu.
  • the thickness of the second external electrode 7 is not particularly limited, but is preferably 0.1 ⁇ m or more and 100 ⁇ m or less, more preferably 0.5 ⁇ m or more and 50 ⁇ m or less, further preferably 0.5 ⁇ m or more and 10 ⁇ m or less, for example, 1 ⁇ m or more and 5 ⁇ m or less. possible.
  • the insulating sheets 21, 22, 23, and 24 are laminated as shown in FIG. 7 and integrated by thermocompression bonding or the like to obtain a laminated body 28.
  • the number of each insulating sheet is not specifically limited, It can set suitably according to the size etc. of a desired capacitor
  • the laminate 28 is fired.
  • the firing is performed while applying pressure in the thickness direction.
  • the cavity 3 is filled with a ceramic slurry 33 (for example, Al 2 O 3 slurry), and further separately prepared green sheets 31 and 32 (for example, Al 2 O 3 green sheets). Are disposed on the upper and lower surfaces of the insulating substrate 2.
  • the green sheets 31 and 32 are fired while a pressure is applied.
  • the magnitude of the pressure may be, for example, from 0.1 MPa to 10 MPa, preferably from 0.3 MPa to 1 MPa.
  • the sintered body in the cavity 3 and the layers derived from the green sheets 31 and 32 are removed.
  • a metal layer 8 is formed on the second external electrode 7.
  • the material constituting the metal layer 8 is not particularly limited, and examples thereof include metals such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and alloys thereof.
  • the material constituting the metal layer 8 is Cu.
  • the method for forming the metal layer 8 is not particularly limited, and for example, chemical vapor deposition (CVD: Chemical Vapor Deposition), electrolytic plating, electroless plating, vapor deposition, sputtering, conductive paste baking, or the like can be used. Electroless plating, vapor deposition, sputtering and the like are preferable. Moreover, you may use combining these methods. By using electrolytic plating, electroless plating, vapor deposition, or sputtering, a dense metal layer 8 can be obtained.
  • CVD Chemical Vapor Deposition
  • electrolytic plating electroless plating
  • vapor deposition vapor deposition
  • sputtering conductive paste baking
  • the metal layer 8 By forming the metal layer 8 as a dense layer, when the dielectric layer 12 and the upper electrode 13 are later formed by a vapor phase method, the upper electrode 13 penetrates the via 9 and the like and is exposed to the bottom surface of the capacitor, It is possible to prevent a short circuit between the upper electrode and the lower surface of the capacitor.
  • the thickness of the metal layer 8 is not particularly limited, but is preferably 0.1 ⁇ m to 100 ⁇ m, more preferably 0.5 ⁇ m to 50 ⁇ m, and even more preferably 0.5 ⁇ m to 10 ⁇ m, for example, 1 ⁇ m to 5 ⁇ m. .
  • the conductive porous substrate 11 is formed in the cavity 3 of the laminate 28.
  • the conductive porous substrate 11 is a metal sintered body.
  • the metal sintered body can be obtained by firing one or more metal powders.
  • the metal sintered body may be formed by firing metal powder in the cavity 3, or a metal sintered body obtained by separately firing metal powder may be placed in the cavity 3.
  • the metal sintered body is formed by firing metal powder in the cavity 3.
  • the metal powder added into the cavity may be either liquid phase synthetic powder or gas phase synthetic powder.
  • the said metal powder can be added to a cavity as a dispersion liquid, and this dispersion liquid may contain the 1 type (s) or 2 or more types of dispersing agent, a plasticizer, a solvent, and a binder component.
  • metal powder in the present specification means an aggregate of metal particles, which means that the particle size distribution substantially shows one peak. That is, even metal powders made of the same constituent element, such as Ni, are regarded as different metal powders if their particle size distributions are different.
  • the shape of the metal powder is not particularly limited, and may be spherical, elliptical, needle-like, rod-like, wire-like, or the like. Further, the metal powder may be subjected to a treatment for increasing the surface area.
  • the metal material constituting the metal powder is not particularly limited as long as it is conductive.
  • Al, Ti, Ta, Nb, Ni, Cu, W, Mo, Au, Ir, Ag, Rh, Ru, Co, Fe or an alloy thereof may be used.
  • the metal material constituting the metal powder is Ni, Cu, W, Mo, Au, Ir, Ag, Rh, Ru, Co or Fe.
  • the equivalent series resistance of the sintered metal body can be reduced.
  • these materials have a low specific resistance and a high melting point, they can be annealed at a high temperature, and a high-quality dielectric film can be obtained in the following steps.
  • the average particle diameter of the metal powder is not particularly limited, but may be, for example, 10 nm to 600 nm, preferably 30 nm to 400 nm, and more preferably 50 nm to 200 nm. By setting the average particle size within this range, the effective area that functions as a capacitor can be increased.
  • the metal sintered body can be obtained by mixing and firing at least two kinds of metal powders.
  • strength can be obtained, and high electrostatic capacitance density and high intensity
  • the mixture of metal powders includes at least 2, for example, 2, 3, or 4 metal powders having different average particle sizes.
  • the “average particle size” of the metal powder means the average particle size D50 (particle size equivalent to a volume-based cumulative percentage of 50%).
  • the average particle diameter D50 can be measured by, for example, a dynamic light scattering particle size analyzer (manufactured by Nikkiso Co., Ltd., UPA).
  • the average particle size of the sintered metal is obtained by processing the sintered metal into a thin piece by focused ion beam (FIB) processing, and a predetermined region (for example, 5 ⁇ m ⁇ 5 ⁇ m) of the thin piece sample, It can be obtained by photographing using a transmission electron microscope (TEM) and analyzing the obtained image.
  • FIB focused ion beam
  • TEM transmission electron microscope
  • the mixture of metal powders includes at least two metal powders having different melting points, such as two, three, or four metal powders.
  • the combination of the metal powder that is the main component of the metal sintered body and the metal powder having a low melting point is not particularly limited, and examples thereof include a combination of Ni and Cu.
  • the metal sintered body has a high gap.
  • the porosity of the sintered metal body may be preferably 30% or more, more preferably 40% or more.
  • 90% or less is preferable and 80% or less is more preferable.
  • porosity means the ratio of voids in the porous portion.
  • the porosity can be measured as follows.
  • the voids in the porous portion can be finally filled with a dielectric layer and an upper electrode in the process of manufacturing a capacitor.
  • the “porosity” does not take into account the material filled in this way.
  • the filled portion is also calculated as a void.
  • the porous portion is processed into a thin piece by focused ion beam (FIB) processing.
  • a predetermined region for example, 5 ⁇ m ⁇ 5 ⁇ m
  • TEM transmission electron microscope
  • the thickness of the metal sintered body, that is, the conductive porous substrate is not particularly limited and can be appropriately selected according to the purpose.
  • the thickness is 5 ⁇ m or more and 200 ⁇ m or less, preferably 10 ⁇ m or more and 100 ⁇ m or less, more preferably 20 ⁇ m or more. It can be 100 ⁇ m or less.
  • the thickness of the conductive porous substrate means the thickness of the porous portion when it is assumed that all the pores are filled.
  • the dielectric layer 12 and the upper electrode 13 are formed on the conductive porous substrate 11.
  • the material for forming the dielectric layer 12 is not particularly limited as long as it is insulative, but preferably, AlO x (eg, Al 2 O 3 ), SiO x (eg, SiO 2 ), AlTiO x , SiTiO x , HfO x, TaO x, ZrO x , LaO x, HfSiO x, ZrSiO x, TiZrO x, TiZrWO x, TiO x, SrTiO x, PbTiO x, BaTiO x, BaSrTiO x, BaCaTiO x, metal oxides such as SiAlO x; Metal nitrides such as AlN x , SiN x , AlScN x ; or metal oxynitrides such as AlO x N y , SiO x N y , HfSiO x N y , SiC x O
  • x, y, and z attached to O and N may be any value greater than 0, and the abundance ratio of each element including a metal element is arbitrary. Further, a layered compound composed of a plurality of layers having different dielectric layers may be used.
  • the thickness of the dielectric layer 12 is not particularly limited, but is preferably 3 nm to 100 nm, for example, and more preferably 5 nm to 50 nm. By setting the thickness of the dielectric layer to 3 nm or more, it is possible to increase the insulation and to reduce the leakage current. Further, by setting the thickness of the dielectric layer to 100 nm or less, it is possible to obtain a larger capacitance.
  • the dielectric layer 12 may be a single layer or a multilayer.
  • the dielectric layer 12 is preferably formed by a vapor phase method such as a vacuum evaporation method, a CVD method, a sputtering method, an atomic layer deposition method (ALD), a pulsed laser deposition method (PLD: Pulsed Laser Deposition), or the like. It is formed by a method using a supercritical fluid.
  • the ALD method is more preferable because a more uniform and dense film can be formed in the fine pores of the high porosity portion.
  • the material constituting the upper electrode 13 is not particularly limited as long as it is conductive, but Ni, Cu, Al, W, Ti, Ag, Au, Pt, Zn, Sn, Pb, Fe, Cr, Mo, Ru, Pd, Ta and alloys thereof such as CuNi, AuNi, AuSn, and metal nitrides such as TiN, TiAlN, TiON, TiAlON, and TaN, metal oxynitrides, conductive polymers (eg, PEDOT (poly (3,4) -Ethylenedioxythiophene))), polypyrrole, polyaniline) and the like, and TiN and TiON are preferred.
  • PEDOT poly (3,4) -Ethylenedioxythiophene
  • the thickness of the upper electrode 13 is not particularly limited, but is preferably 3 nm or more, for example, and more preferably 10 nm or more. By setting the thickness of the upper electrode to 3 nm or more, the resistance of the upper electrode itself can be reduced.
  • the upper electrode 13 may be a single layer or a multilayer.
  • the upper electrode 13 may be formed by an ALD method. By using the ALD method, the capacitance of the capacitor can be increased.
  • the top electrode may be coated by a method such as CVD, plating, bias sputtering, Sol-Gel method, or conductive polymer filling that can cover the dielectric layer and substantially fill the pores of the substrate. It may be formed.
  • a conductive film is formed on the dielectric layer by the ALD method, and the upper electrode is formed by filling the pores with a conductive material, preferably a substance having a lower electrical resistance, by another method. May be. With such a configuration, a higher capacity density and a lower equivalent series resistance (ESR: Equivalent Series Resistance) can be obtained efficiently.
  • ESR Equivalent Series Resistance
  • the first external electrode 5 is formed on the upper electrode 13.
  • the material constituting the first external electrode 5 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and conductive polymers.
  • the material constituting the first external electrode 5 is Cu.
  • the method for forming the first external electrode 5 is not particularly limited, and for example, CVD, electrolytic plating, electroless plating, vapor deposition, sputtering, baking of conductive paste, and the like can be used. Electrolytic plating, electroless plating, vapor deposition Sputtering or the like is preferable. Moreover, you may use combining these methods.
  • the thickness of the first external electrode 5 is not particularly limited, but it is preferably 0.1 ⁇ m or more and 100 ⁇ m or less, more preferably 0.5 ⁇ m or more and 50 ⁇ m or less, and still more preferably 0.00 on the basis of the upper surface of the conductive porous substrate. It may be 5 ⁇ m or more and 10 ⁇ m or less, for example, 1 ⁇ m or more and 5 ⁇ m or less.
  • the collective substrate 29 including the plurality of capacitors 1a is manufactured by the above process.
  • the collective substrate 29 is divided into each element.
  • the collective substrate 29 can be cut along a straight line indicated by x and y and divided into each element. That is, in the capacitor of the present invention, at least one of the side surfaces, preferably the entire side surface may be a cut surface.
  • the division of the aggregate substrate can be performed using a scriber, a dicing blade, various laser devices, various blades, and a mold.
  • the capacitor of the present invention can be manufactured as a collective substrate, the size and capacitance of the entire capacitor can be easily adjusted by adjusting the size of each block.
  • FIG. 9 shows a schematic cross-sectional view of a capacitor 1b according to another embodiment of the present invention.
  • the capacitor 1 b of the present embodiment is characterized in that the cavity 43 of the insulating base 42 is provided so as to penetrate the insulating base 42.
  • the capacitor 1b includes an insulating base 42 having a through-cavity 43, a cavity electrode 46 that seals the bottom of the through-cavity 43, a capacitance forming portion 44 provided in the cavity, and capacitance formation.
  • a first external electrode 45 on the portion 44 is provided.
  • the capacitance forming portion 44 includes a conductive porous substrate that functions as a lower electrode, a dielectric layer positioned on the conductive porous substrate, and a dielectric And an upper electrode located on the layer.
  • the capacitor 1b by applying a voltage between the first external electrode 45 and the cavity electrode 46, a voltage is applied between the conductive porous substrate of the capacitance forming portion 44 and the upper electrode, and the dielectric layer is applied to the dielectric layer. Charge can be accumulated.
  • the thickness of the capacitor can be reduced.
  • the capacitor of the present invention has been described based on the capacitors 1a and 1b.
  • the capacitor of the present invention is not limited to the above-described embodiment and manufacturing method, and the design can be changed without departing from the gist of the present invention. is there.
  • the capacitor 1a has a cavity electrode at the bottom of the cavity
  • the capacitor of the present invention may not have a cavity electrode.
  • the conductive porous substrate and the via are directly electrically connected.
  • the capacitor 1a has three vias 9.
  • the number of vias may be one or two, or four or more. Increasing the number of vias increases the contact area between the via, the cavity electrode, and the second external electrode, and reduces the ESR of the capacitor. Further, contact failure between the via, the cavity electrode, and the second external electrode can be suppressed.
  • the opening of the cavity extends over the entire cavity.
  • the opening may be a part of the bottom of the cavity.
  • the capacitors 1a and 1b have only one capacitance forming portion, but the present invention is not limited to this.
  • the number of capacitance forming units may be two or more, for example, two, three, or four.
  • the capacitance can be easily adjusted.
  • the strength of the capacitor can be increased.
  • the cavity electrode or via of the capacitor of the present invention may have a dense structure or a coarse structure.
  • the dense structure means a dense structure in which a gas, for example, a gas used when manufacturing a dielectric layer or an upper electrode by a vapor phase method does not penetrate
  • the coarse structure means a coarse structure through which the gas penetrates. To do.
  • the strength of the capacitor can be increased.
  • the cavity electrode or the via can also function as the capacitance forming portion, and the capacitance of the entire capacitor can be increased.
  • the method of manufacturing the capacitor aggregate substrate of the present invention is not limited to the above.
  • the insulating substrate does not need to be obtained as a laminate, and the cavity or the through hole may be formed by scraping the insulating substrate with a laser or the like.
  • Examples of the conductive porous substrate include a conductive porous substrate in addition to the above-described sintered metal.
  • the conductive porous substrate has a porous structure, and its material and configuration are not limited as long as the surface is conductive.
  • examples of the conductive porous substrate include a porous metal substrate, a substrate in which a conductive layer is formed on the surface of a porous silica material, a porous carbon material, or a porous ceramic sintered body.
  • the conductive porous substrate is a porous metal substrate.
  • the metal constituting the porous metal substrate examples include aluminum, tantalum, nickel, copper, titanium, niobium and iron metals, and alloys such as stainless steel and duralumin.
  • the porous metal substrate is an aluminum porous substrate.
  • a separately manufactured capacitor may be incorporated in the cavity.
  • Such a capacitor is not particularly limited, and various capacitors can be used.
  • a multilayer capacitor, a winding capacitor, a film capacitor, an electrolytic capacitor, or the like can be used.
  • a glass ceramic powder obtained by mixing a CaO—Al 2 O 3 —SiO 2 —B 2 O 3 glass powder (50 wt%) and an Al 2 O 3 powder (50 wt%) as a glass ceramic raw material powder.
  • a body was prepared (average particle size: about 2 ⁇ m).
  • a dioxyl phthalate plasticizer, an acrylic resin binder, and a solvent are added to the glass ceramic powder, and the mixture is thoroughly kneaded to prepare a slurry having a viscosity of 2,000 mPa ⁇ s.
  • the thickness is 0.1 mm by the doctor blade method.
  • a glass ceramic green sheet was formed.
  • the glass ceramic green sheet was processed into a predetermined shape using a punching machine.
  • a plurality of via holes (0.3 mm ⁇ ) were punched and formed at predetermined positions, and each via hole was filled with Cu paste.
  • Cu paste was screen-printed in the predetermined location.
  • the obtained glass ceramic green sheets were laminated as shown in FIG. 7 to obtain a green sheet laminate.
  • the obtained green sheet laminate was integrated by thermocompression bonding under conditions of 110 ° C. and 10 MPa.
  • the outer dimensions of the obtained green sheet laminate were 100 ⁇ 100 mm square, and the dimensions of the cavity were 1.4 ⁇ 0.6 mm.
  • the green sheet laminate had 6438 cavities.
  • Al 2 O 3 powder having an average particle size of about 0.3 [mu] m was added a mixture of ethyl cellulose resin dissolved in alcohol, Al 2 O 3 solid content of the powder is 69% Al 2 O A paste containing 3 powders was prepared.
  • an organic solvent, an acrylic binder, a plasticizer, and a dispersant are added to the Al 2 O 3 powder, mixed with a ball mill to form a slurry, and this slurry is used to form an Al 2 O 3 green sheet by a doctor blade method. Formed.
  • the obtained Al 2 O 3 green sheets were arranged on both the upper and lower surfaces of the green sheet laminate (see FIG. 10).
  • the green sheet laminate and the Al 2 O 3 and Al 2 O 3 green sheets in the cavity were used in an electric continuous belt furnace. Then, it was calcined by holding at 900 ° C. for 20 minutes in the reduction. Next, the Al 2 O 3 powder on the upper and lower surfaces of the obtained sintered laminate was removed by blasting glass beads. As a result, a multilayer substrate having a structure as shown in FIG. 7 was obtained.
  • a Cu layer was formed by electroless plating so as to cover the second external electrode of the obtained multilayer substrate.
  • Ni metal powder having an average particle diameter of 200 nm was dispersed in a ball mill using 1 mm ⁇ zirconia balls in ethanol.
  • Polyvinyl alcohol was added to this dispersion to prepare a metal powder slurry.
  • This slurry was added into each cavity using a dispenser and dried.
  • the thickness of the metal powder layer after drying was about 30 ⁇ m.
  • the metal substrate on which the metal powder layer was formed in the cavity was degreased at 200 to 300 ° C. in a firing furnace and then heat-treated at 300 to 650 ° C. for 5 minutes in an N 2 atmosphere to obtain a sintered metal body.
  • an ALD method was used to form an AlOx film (25 nm) on the metal sintered body to form a dielectric layer.
  • a Ru film (20 nm) was formed by ALD to form an upper electrode.
  • a first external electrode was formed on the upper electrode by Cu plating. As a result, a capacitor aggregate substrate of the present invention was obtained.
  • the capacitor of the present invention has a high capacitance, it is suitably used for various electronic devices.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

The present invention provides a capacitor which is configured to comprise an insulating substrate, a conductive porous base material that has a porous part, a dielectric layer that is positioned on the porous part, and an upper electrode that is positioned on the dielectric layer. The insulating substrate is provided with a cavity; and the conductive porous base material, the dielectric layer and the upper electrode are provided within the cavity.

Description

コンデンサCapacitor
　本発明は、コンデンサに関する。 The present invention relates to a capacitor.
　近年、電子機器の高密度実装化に伴って、より高静電容量を有するコンデンサが求められている。このようなコンデンサとして、例えば、特許文献１には、多孔部を有する導電性金属基材と、該多孔部上に位置する誘電体層と、該誘電体層上に位置する上部電極とを有してなり、一方の主面側にのみ静電容量形成部を有するコンデンサが開示されている。 In recent years, a capacitor having a higher electrostatic capacity has been demanded as electronic devices are mounted with higher density. As such a capacitor, for example, Patent Document 1 has a conductive metal base material having a porous portion, a dielectric layer located on the porous portion, and an upper electrode located on the dielectric layer. Thus, a capacitor having a capacitance forming portion only on one main surface side is disclosed.
国際公開第２０１６／１８１８６５号International Publication No. 2016/181865
　上記のようなコンデンサは、通常集合基板として製造され、個別の素子に分割される。その際、切断部に金属部が存在すると、切断により生じたばりにより、上部電極と下部電極が短絡する場合がある。また、金属は延性および粘性が高いので、切断時に切断方向に引き延ばされやすい。この引き延ばされた金属により、コンデンサの端面において、上部電極と下部電極が短絡する場合がある。 ¡Capacitors as described above are usually manufactured as a collective substrate and divided into individual elements. At this time, if a metal part is present in the cut part, the upper electrode and the lower electrode may be short-circuited due to flash generated by the cutting. Further, since the metal has high ductility and viscosity, it is easily stretched in the cutting direction during cutting. The extended metal may cause a short circuit between the upper electrode and the lower electrode at the end face of the capacitor.
　特許文献１のコンデンサは、導電性金属基材が主たる構成部材であり、一の金属基板から集合基板を製造するので、切断面にこの金属基板が存在する。従って、上記のような上部電極と下部電極の短絡が生じ易いという問題がある。 In the capacitor of Patent Document 1, a conductive metal base material is a main constituent member, and a collective substrate is manufactured from a single metal substrate. Therefore, this metal substrate exists on the cut surface. Therefore, there is a problem that the short circuit between the upper electrode and the lower electrode is likely to occur.
　従って、本発明の目的は、高静電容量を有し、かつ、集合基板からの個片化が容易なコンデンサを提供することである。 Therefore, an object of the present invention is to provide a capacitor that has a high capacitance and can be easily separated from the collective substrate.
　本発明者らは、上記の問題を解決するために鋭意検討した結果、集合基板からの個片化の際に切断される箇所に金属のような導電性材料の部材を配置しないことにより、コンデンサの端面における短絡を抑制できることを見出し、本発明に至った。 As a result of intensive investigations to solve the above problems, the present inventors have found that a capacitor made of a conductive material such as metal is not disposed at a location where the material is cut from the collective substrate. The present inventors have found that a short circuit at the end face of the film can be suppressed, and have reached the present invention.
　従って、本発明は、
　絶縁性基体と、
　多孔部を有する導電性多孔基材と、
　多孔部上に位置する誘電体層と、
　誘電体層上に位置する上部電極と、
を有して成るコンデンサであって、前記絶縁性基体がキャビティを有し、該キャビティ内に、前記導電性多孔基材、前記誘電体層、および前記上部電極が設けられている、コンデンサ
を提供する。 Therefore, the present invention
An insulating substrate;
A conductive porous substrate having a porous portion;
A dielectric layer located on the porous portion;
An upper electrode located on the dielectric layer;
A capacitor in which the insulating substrate has a cavity, and the conductive porous substrate, the dielectric layer, and the upper electrode are provided in the cavity. To do.
　本発明によれば、絶縁性基体と、多孔部を有する導電性多孔基材と、多孔部上に位置する誘電体層と、誘電体層上に位置する上部電極とを有して成るコンデンサにおいて、前記絶縁性基体にキャビティを形成し、該キャビティ内に導電性多孔基材、誘電体層および上部電極を配置することにより、コンデンサ端面における短絡を防止することができる。 According to the present invention, in a capacitor comprising an insulating substrate, a conductive porous substrate having a porous part, a dielectric layer located on the porous part, and an upper electrode located on the dielectric layer By forming a cavity in the insulating substrate and disposing the conductive porous substrate, the dielectric layer and the upper electrode in the cavity, it is possible to prevent a short circuit on the capacitor end face.
図１は、本発明の１つの実施形態におけるコンデンサ１ａの概略断面図である。FIG. 1 is a schematic cross-sectional view of a capacitor 1a according to one embodiment of the present invention. 図２は、図１に示すコンデンサ１ａの静電容量形成部４の概略断面図である。FIG. 2 is a schematic cross-sectional view of the capacitance forming portion 4 of the capacitor 1a shown in FIG. 図３は、コンデンサ１ａの製造に用いる絶縁シート２１の概略平面図である。FIG. 3 is a schematic plan view of the insulating sheet 21 used for manufacturing the capacitor 1a. 図４は、コンデンサ１ａの製造に用いる絶縁シート２２の一の面の概略平面図である。FIG. 4 is a schematic plan view of one surface of the insulating sheet 22 used for manufacturing the capacitor 1a. 図５は、コンデンサ１ａの製造に用いる絶縁シート２２の他の面の概略平面図である。FIG. 5 is a schematic plan view of another surface of the insulating sheet 22 used for manufacturing the capacitor 1a. 図６は、コンデンサ１ａの製造に用いる絶縁シート２３の概略平面図である。FIG. 6 is a schematic plan view of the insulating sheet 23 used for manufacturing the capacitor 1a. 図７は、絶縁性基体２のキャビティ３中に静電容量形成部４を形成する前の基板の概略断面図である。FIG. 7 is a schematic cross-sectional view of the substrate before the capacitance forming portion 4 is formed in the cavity 3 of the insulating base 2. 図８は、集合基板２９の切断部を示す図である。FIG. 8 is a view showing a cutting part of the collective substrate 29. 図９は、本発明の別の実施形態におけるコンデンサ１ｂの概略断面図である。FIG. 9 is a schematic cross-sectional view of a capacitor 1b according to another embodiment of the present invention. 図１０は、焼成時の基板の状態を説明するための概略断面図である。FIG. 10 is a schematic cross-sectional view for explaining the state of the substrate during firing.
　本発明のコンデンサについて、以下、図面を参照しながら詳細に説明する。但し、下記実施形態のコンデンサおよび各構成要素の形状および配置等は、図示する例に限定されない。 Hereinafter, the capacitor of the present invention will be described in detail with reference to the drawings. However, the shape and arrangement of the capacitors and the constituent elements of the following embodiments are not limited to the illustrated examples.
（実施形態１）
　本実施形態のコンデンサ１ａの断面図を図１に、静電容量形成部４の拡大断面図を図２に模式的に示す。図１および図２に示されるように、本実施形態のコンデンサ１ａは、絶縁性基体２と、絶縁性基体２のキャビティ３内に設けられた静電容量形成部４を有してなる。静電容量形成部４上には第一外部電極５が設けられている。上記キャビティ３の底部には、キャビティ電極６が設けられている。また、絶縁性基体２の底面上には、第二外部電極７が設けられ、さらに第二外部電極７上には金属層８が設けられている。上記キャビティ電極６と第二外部電極７の間には、絶縁性基体２を貫通してこれらを電気的に接続するビア９が設けられている。上記静電容量形成部４は、下部電極として機能する導電性多孔基材１１と、導電性多孔基材１１上に位置する誘電体層１２と、誘電体層１２上に位置する上部電極１３とから構成される。上部電極１３上には、上記第一外部電極５が設けられている。コンデンサ１ａの端部には、金属材料は存在せず、すべて絶縁性基体２により構成される。コンデンサ１ａにおいて、第一外部電極５および金属層８間に電圧を印加することにより、下部電極、即ち導電性多孔基材１１と上部電極１３との間に電圧が印加され、誘電体層１２に電荷を蓄積することができる。 (Embodiment 1)
A sectional view of the capacitor 1a of this embodiment is schematically shown in FIG. 1, and an enlarged sectional view of the capacitance forming portion 4 is schematically shown in FIG. As shown in FIGS. 1 and 2, the capacitor 1 a according to this embodiment includes an insulating base 2 and a capacitance forming portion 4 provided in the cavity 3 of the insulating base 2. A first external electrode 5 is provided on the capacitance forming portion 4. A cavity electrode 6 is provided at the bottom of the cavity 3. A second external electrode 7 is provided on the bottom surface of the insulating substrate 2, and a metal layer 8 is provided on the second external electrode 7. A via 9 is provided between the cavity electrode 6 and the second external electrode 7 so as to penetrate the insulating substrate 2 and electrically connect them. The capacitance forming unit 4 includes a conductive porous substrate 11 functioning as a lower electrode, a dielectric layer 12 positioned on the conductive porous substrate 11, and an upper electrode 13 positioned on the dielectric layer 12. Consists of The first external electrode 5 is provided on the upper electrode 13. No metal material is present at the end of the capacitor 1a, and the capacitor 1a is entirely composed of the insulating substrate 2. In the capacitor 1 a, by applying a voltage between the first external electrode 5 and the metal layer 8, a voltage is applied between the lower electrode, that is, the conductive porous substrate 11 and the upper electrode 13, and the dielectric layer 12 is applied. Charge can be accumulated.
（製造方法１）
　上記のようなコンデンサ１ａは、例えば以下のようにして製造される。 (Manufacturing method 1)
The capacitor 1a as described above is manufactured as follows, for example.
　まず、絶縁性基体２を構成する絶縁シート２１，２２，２３，２４を準備する。 First, insulating sheets 21, 22, 23, and 24 constituting the insulating base 2 are prepared.
　絶縁シート２１は、図３に示されるように、コンデンサ１ａのキャビティ３に対応する開口部２５を複数有する。 As shown in FIG. 3, the insulating sheet 21 has a plurality of openings 25 corresponding to the cavities 3 of the capacitor 1a.
　絶縁シート２２は、図４および図５に示されるように、一の主表面上にコンデンサ１ａのキャビティ電極６に対応する金属層２６を有し、ビア９に対応する貫通金属層２７を有する。 As shown in FIGS. 4 and 5, the insulating sheet 22 has a metal layer 26 corresponding to the cavity electrode 6 of the capacitor 1 a on one main surface and a through metal layer 27 corresponding to the via 9.
　絶縁シート２３は、図６に示されるように、コンデンサ１ａのビア９に対応する貫通金属層２７を有する。 The insulating sheet 23 has a through metal layer 27 corresponding to the via 9 of the capacitor 1a, as shown in FIG.
　絶縁シート２４は、キャビティ電極６を第二外部電極７に置き換えた以外は、絶縁シート２２と同様であり、一の主表面上に第二外部電極７に対応する金属層２６を有し、ビア９に対応する貫通金属層２７を有する。 The insulating sheet 24 is the same as the insulating sheet 22 except that the cavity electrode 6 is replaced with the second external electrode 7, and has a metal layer 26 corresponding to the second external electrode 7 on one main surface, and a via 9 has a through metal layer 27 corresponding to 9.
　各絶縁シートを構成する材料としては、絶縁性材料であれば特に限定されず、各種セラミック材料、ガラスセラミック材料、樹脂材料等が挙げられる。上記絶縁性材料は、好ましくはセラミック材料、特にガラスセラミック材料が好ましい。 The material constituting each insulating sheet is not particularly limited as long as it is an insulating material, and examples thereof include various ceramic materials, glass ceramic materials, resin materials, and the like. The insulating material is preferably a ceramic material, particularly a glass ceramic material.
　上記セラミック材料としては、例えば、アルミナ、ジルコニアなどが挙げられる。ガラスセラミック材料としては、例えば、ＣａＯ－Ａｌ２Ｏ３－ＳｉＯ２系ガラスとアルミナの混合物などが挙げられる。 Examples of the ceramic material include alumina and zirconia. Examples of the glass ceramic material include a mixture of CaO—Al 2 O 3 —SiO 2 glass and alumina.
　ガラスセラミック材料としては、他にＣａＯ－Ａｌ２Ｏ３－ＳｉＯ２－Ｂ２Ｏ３系ガラス、Ｎａ２Ｏ－ＳｉＯ２系ガラス、Ｎａ２Ｏ－ＣａＯ－ＳｉＯ２系ガラス、Ｎａ２Ｏ－ＣａＯ－ＳｉＯ２－Ａｌ２Ｏ３系ガラス、Ｎａ２Ｏ－ＣａＯ－ＳｉＯ２－Ａｌ２Ｏ３－Ｂ２Ｏ３系ガラス、Ｎａ２Ｏ－Ｂ２Ｏ３－ＳｉＯ２系ガラス、Ｎａ２Ｏ－Ｂ２Ｏ３－ＣａＯ－ＳｉＯ２系ガラス、Ｂ２Ｏ３－Ａｌ２Ｏ３－ＳｉＯ２系ガラスなどが挙げられる。 Other glass ceramic materials include CaO—Al 2 O 3 —SiO 2 —B 2 O 3 glass, Na 2 O—SiO 2 glass, Na 2 O—CaO—SiO 2 glass, Na 2 O—CaO. —SiO 2 —Al 2 O 3 glass, Na 2 O—CaO—SiO 2 —Al 2 O 3 —B 2 O 3 glass, Na 2 O—B 2 O 3 —SiO 2 glass, Na 2 O— Examples thereof include B 2 O 3 —CaO—SiO 2 glass, B 2 O 3 —Al 2 O 3 —SiO 2 glass, and the like.
　上記樹脂材料としては、耐熱性樹脂が好ましく、例えば、ポリイミド、ポリベンゾオキサゾール、ポリエチレンテレフタラート、ベンゾシクロブテン樹脂、エポキシ樹脂等が挙げられる。樹脂材料は、線膨張係数を調整するためのフィラー、例えばＳｉフィラー等を含んでいてもよい。 The resin material is preferably a heat-resistant resin, and examples thereof include polyimide, polybenzoxazole, polyethylene terephthalate, benzocyclobutene resin, and epoxy resin. The resin material may contain a filler for adjusting the linear expansion coefficient, such as a Si filler.
　各絶縁シートの厚みは、特に限定されないが、例えば、１μｍ以上１．０ｍｍ以下であり、好ましくは１０μｍ以上２００μｍ以下、例えば２０μｍ以上１００μｍ以下であり得る。 The thickness of each insulating sheet is not particularly limited, but may be, for example, 1 μm or more and 1.0 mm or less, preferably 10 μm or more and 200 μm or less, for example, 20 μm or more and 100 μm or less.
　上記キャビティ電極６を構成する材料としては、特に限定されないが、例えば、Ａｕ、Ｐｂ、Ｐｄ、Ａｇ、Ｓｎ、Ｎｉ、Ｃｕ等の金属および合金などが挙げられる。好ましくは、キャビティ電極６を構成する材料は、Ｃｕである。 The material constituting the cavity electrode 6 is not particularly limited, and examples thereof include metals such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and alloys thereof. Preferably, the material constituting the cavity electrode 6 is Cu.
　上記キャビティ電極６の厚みは、特に限定されないが、好ましくは０．１μｍ以上１００μｍ以下、より好ましくは０．５μｍ以上５０μｍ以下、さらに好ましくは０．５μｍ以上１０μｍ以下、例えば１μｍ以上５μｍ以下であり得る。 The thickness of the cavity electrode 6 is not particularly limited, but is preferably 0.1 μm to 100 μm, more preferably 0.5 μm to 50 μm, still more preferably 0.5 μm to 10 μm, for example, 1 μm to 5 μm. .
　上記ビア９を構成する材料としては、特に限定されないが、例えば、Ａｕ、Ｐｂ、Ｐｄ、Ａｇ、Ｓｎ、Ｎｉ、Ｃｕ等の金属および合金などが挙げられる。好ましくは、ビア９を構成する材料は、Ｃｕである。 The material constituting the via 9 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu. Preferably, the material constituting the via 9 is Cu.
　上記第二外部電極７を構成する材料としては、特に限定されないが、例えば、Ａｕ、Ｐｂ、Ｐｄ、Ａｇ、Ｓｎ、Ｎｉ、Ｃｕ等の金属および合金などが挙げられる。好ましくは、第二外部電極７を構成する材料は、Ｃｕである。 The material constituting the second external electrode 7 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu. Preferably, the material constituting the second external electrode 7 is Cu.
　上記第二外部電極７の厚みは、特に限定されないが、好ましくは０．１μｍ以上１００μｍ以下、より好ましくは０．５μｍ以上５０μｍ以下、さらに好ましくは０．５μｍ以上１０μｍ以下、例えば１μｍ以上５μｍ以下であり得る。 The thickness of the second external electrode 7 is not particularly limited, but is preferably 0.1 μm or more and 100 μm or less, more preferably 0.5 μm or more and 50 μm or less, further preferably 0.5 μm or more and 10 μm or less, for example, 1 μm or more and 5 μm or less. possible.
　上記絶縁シート２１，２２，２３，２４を図７に示すように積層し、熱圧着等により一体化して、積層体２８を得る。尚、各絶縁シートの数は、特に限定されず、所望のコンデンサのサイズなどに応じて適宜設定することができる。 The insulating sheets 21, 22, 23, and 24 are laminated as shown in FIG. 7 and integrated by thermocompression bonding or the like to obtain a laminated body 28. In addition, the number of each insulating sheet is not specifically limited, It can set suitably according to the size etc. of a desired capacitor | condenser.
　一の態様において、例えば、上記絶縁シートを構成する材料がセラミック材料である場合、積層体２８を焼成する。好ましい態様において、かかる焼成は、厚み方向に圧力を加えながら行われる。このように焼成することにより、焼成による各材料の面方向（水平方向）の収縮を抑制し、収縮を厚み方向に集中させることができ、収縮による絶縁基体の反りを抑制することができる。 In one embodiment, for example, when the material constituting the insulating sheet is a ceramic material, the laminate 28 is fired. In a preferred embodiment, the firing is performed while applying pressure in the thickness direction. By firing in this way, shrinkage in the surface direction (horizontal direction) of each material due to firing can be suppressed, the shrinkage can be concentrated in the thickness direction, and warping of the insulating substrate due to shrinkage can be suppressed.
　具体的には、図１０に示すように、キャビティ３をセラミックスラリー３３（例えば、Ａｌ２Ｏ３スラリー）で充填し、さらに、別途調製したグリーンシート３１，３２（例えば、Ａｌ２Ｏ３グリーンシート）を、絶縁性基体２の上下面に配置する。次いで、上記グリーンシート３１および３２間に圧力を負荷しながら焼成する。上記圧力の大きさは、例えば、０．１ＭＰａ以上１０ＭＰａ以下、好ましくは０．３ＭＰａ以上１ＭＰａ以下であり得る。焼成後、キャビティ３内の焼結体およびグリーンシート３１および３２に由来する層は除去される。 Specifically, as shown in FIG. 10, the cavity 3 is filled with a ceramic slurry 33 (for example, Al 2 O 3 slurry), and further separately prepared green sheets 31 and 32 (for example, Al 2 O 3 green sheets). Are disposed on the upper and lower surfaces of the insulating substrate 2. Next, the green sheets 31 and 32 are fired while a pressure is applied. The magnitude of the pressure may be, for example, from 0.1 MPa to 10 MPa, preferably from 0.3 MPa to 1 MPa. After firing, the sintered body in the cavity 3 and the layers derived from the green sheets 31 and 32 are removed.
　次に、第二外部電極７上に、金属層８を形成する。 Next, a metal layer 8 is formed on the second external electrode 7.
　上記金属層８を構成する材料は、特に限定されないが、例えば、Ａｕ、Ｐｂ、Ｐｄ、Ａｇ、Ｓｎ、Ｎｉ、Ｃｕ等の金属および合金などが挙げられる。好ましくは、金属層８を構成する材料は、Ｃｕである。 The material constituting the metal layer 8 is not particularly limited, and examples thereof include metals such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and alloys thereof. Preferably, the material constituting the metal layer 8 is Cu.
　上記金属層８の形成方法は、特に限定されず、例えば化学蒸着（ＣＶＤ：Chemical Vapor Deposition）、電解めっき、無電解めっき、蒸着、スパッタ、導電性ペーストの焼き付け等を用いることができ、電解めっき、無電解めっき、蒸着、スパッタ等が好ましい。また、これらの方法を組み合わせて用いてもよい。電解めっき、無電解めっき、蒸着またはスパッタを用いることにより、緻密な金属層８を得ることができる。金属層８を緻密な層とすることにより、後に誘電体層１２および上部電極１３を気相法により形成する場合に、上部電極１３がビア９等を貫通してコンデンサの底面に露出して、上部電極とコンデンサの下面の間が短絡することを防止することができる。 The method for forming the metal layer 8 is not particularly limited, and for example, chemical vapor deposition (CVD: Chemical Vapor Deposition), electrolytic plating, electroless plating, vapor deposition, sputtering, conductive paste baking, or the like can be used. Electroless plating, vapor deposition, sputtering and the like are preferable. Moreover, you may use combining these methods. By using electrolytic plating, electroless plating, vapor deposition, or sputtering, a dense metal layer 8 can be obtained. By forming the metal layer 8 as a dense layer, when the dielectric layer 12 and the upper electrode 13 are later formed by a vapor phase method, the upper electrode 13 penetrates the via 9 and the like and is exposed to the bottom surface of the capacitor, It is possible to prevent a short circuit between the upper electrode and the lower surface of the capacitor.
　上記金属層８の厚みは、特に限定されないが、好ましくは０．１μｍ以上１００μｍ以下、より好ましくは０．５μｍ以上５０μｍ以下、さらに好ましくは０．５μｍ以上１０μｍ以下、例えば１μｍ以上５μｍ以下であり得る。 The thickness of the metal layer 8 is not particularly limited, but is preferably 0.1 μm to 100 μm, more preferably 0.5 μm to 50 μm, and even more preferably 0.5 μm to 10 μm, for example, 1 μm to 5 μm. .
　次に、積層体２８のキャビティ３内に、導電性多孔基材１１を形成する。本実施形態においては、導電性多孔基材１１は、金属焼結体である。 Next, the conductive porous substrate 11 is formed in the cavity 3 of the laminate 28. In the present embodiment, the conductive porous substrate 11 is a metal sintered body.
　上記金属焼結体は、１種または２種以上の金属粉を焼成することにより、得ることができる。金属焼結体は、キャビティ３において金属粉を焼成して形成してもよく、別途金属粉を焼成して得られた金属焼結体をキャビティ３に設置してもよい。好ましくは、金属焼結体は、キャビティ３において金属粉を焼成して形成される。金属焼結体を、キャビティ３内において形成することにより、金属焼結体とキャビティ電極６とが金属結合で接合され、コンデンサの強度が向上し、また、コンデンサの等価直列抵抗（ＥＳＲ：Equivalent Series Resistance）を低減することができる。 The metal sintered body can be obtained by firing one or more metal powders. The metal sintered body may be formed by firing metal powder in the cavity 3, or a metal sintered body obtained by separately firing metal powder may be placed in the cavity 3. Preferably, the metal sintered body is formed by firing metal powder in the cavity 3. By forming the metal sintered body in the cavity 3, the metal sintered body and the cavity electrode 6 are joined by metal bonding, the strength of the capacitor is improved, and the equivalent series resistance (ESR: Equivalent Series) of the capacitor. Resistance) can be reduced.
　また、キャビティ内に加えられる金属粉は、液相合成粉または気相合成粉のいずれであってもよい。また、当該金属粉は、分散液としてキャビティに加えることができ、かかる分散液は、１種または２種以上の分散剤、可塑剤、溶媒、バインダー成分を含んでいてもよい。 Further, the metal powder added into the cavity may be either liquid phase synthetic powder or gas phase synthetic powder. Moreover, the said metal powder can be added to a cavity as a dispersion liquid, and this dispersion liquid may contain the 1 type (s) or 2 or more types of dispersing agent, a plasticizer, a solvent, and a binder component.
　上記のような金属焼結体からなる多孔部を用いたコンデンサは、表面積が非常に大きいことから、より高い静電容量密度を得ることができる。 Since a capacitor using a porous portion made of a metal sintered body as described above has a very large surface area, a higher capacitance density can be obtained.
　ここに、本明細書において「金属粉」とは、金属粒子の集合物であり、粒度分布が実質的に１つのピークを示すものを意味する。即ち、同じ構成元素、例えばＮｉから成る金属粉であっても、粒度分布が異なれば、異なる金属粉とみなす。また、金属粉の形状は、特に限定されず、球状、楕円状、針状、棒状、ワイヤー状等であってもよい。また、金属粉は、表面積を大きくするための処理が施されていてもよい。 Here, “metal powder” in the present specification means an aggregate of metal particles, which means that the particle size distribution substantially shows one peak. That is, even metal powders made of the same constituent element, such as Ni, are regarded as different metal powders if their particle size distributions are different. The shape of the metal powder is not particularly limited, and may be spherical, elliptical, needle-like, rod-like, wire-like, or the like. Further, the metal powder may be subjected to a treatment for increasing the surface area.
　金属粉を構成する金属材料としては、導電性であれば特に限定されないが、例えば、Ａｌ、Ｔｉ、Ｔａ、Ｎｂ、Ｎｉ、Ｃｕ、Ｗ、Ｍｏ、Ａｕ、Ｉｒ、Ａｇ、Ｒｈ、Ｒｕ、Ｃｏ、Ｆｅ、またはこれらの合金が挙げられる。 The metal material constituting the metal powder is not particularly limited as long as it is conductive. For example, Al, Ti, Ta, Nb, Ni, Cu, W, Mo, Au, Ir, Ag, Rh, Ru, Co, Fe or an alloy thereof may be used.
　好ましくは、金属粉を構成する金属材料は、Ｎｉ、Ｃｕ、Ｗ、Ｍｏ、Ａｕ、Ｉｒ、Ａｇ、Ｒｈ、Ｒｕ、ＣｏまたはＦｅである。このような材料を用いることにより、金属焼結体の等価直列抵抗を低減することができる。また、これらの材料は、比抵抗が低く、高融点であることから、高温でのアニール処理が可能であり、下記の工程において高品質の誘電体膜を得ることができる。 Preferably, the metal material constituting the metal powder is Ni, Cu, W, Mo, Au, Ir, Ag, Rh, Ru, Co or Fe. By using such a material, the equivalent series resistance of the sintered metal body can be reduced. Further, since these materials have a low specific resistance and a high melting point, they can be annealed at a high temperature, and a high-quality dielectric film can be obtained in the following steps.
　上記金属粉の平均粒径は、特に限定されないが、例えば１０ｎｍ以上６００ｎｍ以下、好ましくは３０ｎｍ以上４００ｎｍ以下、さらに好ましくは５０ｎｍ以上２００ｎｍ以下であり得る。平均粒径をこの範囲とすることにより、コンデンサとして機能する有効面積を大きくすることができる。 The average particle diameter of the metal powder is not particularly limited, but may be, for example, 10 nm to 600 nm, preferably 30 nm to 400 nm, and more preferably 50 nm to 200 nm. By setting the average particle size within this range, the effective area that functions as a capacitor can be increased.
　好ましい態様において、金属焼結体は、少なくとも２種の金属粉を混合して焼成することにより得ることができる。このように２種以上の金属粉を混合して焼成することにより、高い強度を有する多孔部を得ることができ、高静電容量密度および高強度を両立することができる。 In a preferred embodiment, the metal sintered body can be obtained by mixing and firing at least two kinds of metal powders. Thus, by mixing and baking 2 or more types of metal powder, the porous part which has high intensity | strength can be obtained, and high electrostatic capacitance density and high intensity | strength can be made compatible.
　一の態様において、金属粉の混合物は、平均粒径が異なる少なくとも２種、例えば２種、３種または４種の金属粉を含む。平均粒径が異なる金属粉を用いることにより、より低温で焼成した場合であっても焼結体の強度が向上する。 In one embodiment, the mixture of metal powders includes at least 2, for example, 2, 3, or 4 metal powders having different average particle sizes. By using metal powders having different average particle sizes, the strength of the sintered body is improved even when fired at a lower temperature.
　ここに、金属粉の「平均粒径」とは、平均粒径Ｄ５０（体積基準の累積百分率５０％相当粒径）を意味する。かかる平均粒径Ｄ５０は、例えば動的光散乱式粒度分析計（日機装株式会社製、ＵＰＡ）により測定することができる。 Here, the “average particle size” of the metal powder means the average particle size D50 (particle size equivalent to a volume-based cumulative percentage of 50%). The average particle diameter D50 can be measured by, for example, a dynamic light scattering particle size analyzer (manufactured by Nikkiso Co., Ltd., UPA).
　また、金属焼結体における平均粒径は、金属焼結体を集束イオンビーム（ＦＩＢ：Focused Ion Beam）加工で薄片に加工し、この薄片試料の所定の領域（例えば、５μｍ×５μｍ）を、透過型電子顕微鏡（ＴＥＭ：Transmission Electron Microscope）を用いて撮影し、得られた画像を画像解析することにより求めることができる。 The average particle size of the sintered metal is obtained by processing the sintered metal into a thin piece by focused ion beam (FIB) processing, and a predetermined region (for example, 5 μm × 5 μm) of the thin piece sample, It can be obtained by photographing using a transmission electron microscope (TEM) and analyzing the obtained image.
　別の態様において、金属粉の混合物は、融点が異なる少なくとも２種、例えば２種、３種または４種の金属粉を含む。融点が異なる金属粉を用いることにより、より低温で焼成した場合であっても焼結体の強度が向上する。 In another aspect, the mixture of metal powders includes at least two metal powders having different melting points, such as two, three, or four metal powders. By using metal powders having different melting points, the strength of the sintered body is improved even when firing at a lower temperature.
　上記金属焼結体の主成分となる金属粉と、低融点の金属粉の組み合わせは、特に限定されないが、例えば、ＮｉとＣｕの組み合わせが挙げられる。 The combination of the metal powder that is the main component of the metal sintered body and the metal powder having a low melting point is not particularly limited, and examples thereof include a combination of Ni and Cu.
　上記金属焼結体は、高い空隙部を有する。金属焼結体の空隙率は、比表面積を大きくして、コンデンサの容量をより大きくする観点から、好ましくは３０％以上、より好ましくは４０％以上であり得る。また、機械的強度を高める観点から、９０％以下が好ましく、８０％以下がより好ましい。 The metal sintered body has a high gap. From the viewpoint of increasing the specific surface area and increasing the capacity of the capacitor, the porosity of the sintered metal body may be preferably 30% or more, more preferably 40% or more. Moreover, from a viewpoint of improving mechanical strength, 90% or less is preferable and 80% or less is more preferable.
　本明細書において、「空隙率」とは、多孔部において空隙が占める割合を言う。当該空隙率は、下記のようにして測定することができる。尚、上記多孔部の空隙は、コンデンサを作製するプロセスにおいて、最終的に誘電体層および上部電極などで充填され得るが、上記「空隙率」は、このように充填された物質は考慮せず、充填された箇所も空隙とみなして算出する。 In this specification, “porosity” means the ratio of voids in the porous portion. The porosity can be measured as follows. The voids in the porous portion can be finally filled with a dielectric layer and an upper electrode in the process of manufacturing a capacitor. However, the “porosity” does not take into account the material filled in this way. In addition, the filled portion is also calculated as a void.
　まず、多孔部を、集束イオンビーム（ＦＩＢ：Focused Ion Beam）加工で薄片に加工する。この薄片試料の所定の領域（例えば、５μｍ×５μｍ）を、透過型電子顕微鏡（ＴＥＭ：Transmission Electron Microscope）を用いて撮影する。得られた画像を画像解析することにより、多孔部の金属が存在する面積を求める。そして、下記等式から空隙率を計算することができる。
　　空隙率（％）＝（（測定面積－基材の金属が存在する面積）／測定面積）×１００ First, the porous portion is processed into a thin piece by focused ion beam (FIB) processing. A predetermined region (for example, 5 μm × 5 μm) of the thin sample is photographed using a transmission electron microscope (TEM). By analyzing the obtained image, the area where the metal in the porous portion exists is obtained. And the porosity can be calculated from the following equation.
Porosity (%) = ((measurement area−area where base metal exists) / measurement area) × 100
　上記金属焼結体、即ち導電性多孔基材の厚みは、特に限定されず、目的に応じて適宜選択することができ、例えば５μｍ以上２００μｍ以下、好ましくは１０μｍ以上１００μｍ以下、より好ましくは２０μｍ以上１００μｍ以下であり得る。尚、導電性多孔基材の厚みとは、細孔がすべて埋まっていると仮定した場合の多孔部の厚みを意味する。 The thickness of the metal sintered body, that is, the conductive porous substrate is not particularly limited and can be appropriately selected according to the purpose. For example, the thickness is 5 μm or more and 200 μm or less, preferably 10 μm or more and 100 μm or less, more preferably 20 μm or more. It can be 100 μm or less. In addition, the thickness of the conductive porous substrate means the thickness of the porous portion when it is assumed that all the pores are filled.
　次に、上記導電性多孔基材１１上に、誘電体層１２および上部電極１３を形成する。 Next, the dielectric layer 12 and the upper electrode 13 are formed on the conductive porous substrate 11.
　上記誘電体層１２を形成する材料は、絶縁性であれば特に限定されないが、好ましくは、ＡｌＯｘ（例えば、Ａｌ２Ｏ３）、ＳｉＯｘ（例えば、ＳｉＯ２）、ＡｌＴｉＯｘ、ＳｉＴｉＯｘ、ＨｆＯｘ、ＴａＯｘ、ＺｒＯｘ、ＬａＯｘ、ＨｆＳｉＯｘ、ＺｒＳｉＯｘ、ＴｉＺｒＯｘ、ＴｉＺｒＷＯｘ、ＴｉＯｘ、ＳｒＴｉＯｘ、ＰｂＴｉＯｘ、ＢａＴｉＯｘ、ＢａＳｒＴｉＯｘ、ＢａＣａＴｉＯｘ、ＳｉＡｌＯｘ等の金属酸化物；ＡｌＮｘ、ＳｉＮｘ、ＡｌＳｃＮｘ等の金属窒化物；またはＡｌＯｘＮｙ、ＳｉＯｘＮｙ、ＨｆＳｉＯｘＮｙ、ＳｉＣｘＯｙＮｚ等の金属酸窒化物が挙げられ、ＡｌＯｘ、ＳｉＯｘ、ＳｉＯｘＮｙ、ＨｆＳｉＯｘが好ましい。なお、上記の式は、単に材料の構成を表現するものであり、組成を限定するものではない。即ち、ＯおよびＮに付されたｘ、ｙおよびｚは０より大きい任意の値であってもよく、金属元素を含む各元素の存在比率は任意である。また、誘電体層が異なる複数の層からなる層状化合物であっても構わない。 The material for forming the dielectric layer 12 is not particularly limited as long as it is insulative, but preferably, AlO x (eg, Al 2 O 3 ), SiO x (eg, SiO 2 ), AlTiO x , SiTiO x , HfO x, TaO x, ZrO x , LaO x, HfSiO x, ZrSiO x, TiZrO x, TiZrWO x, TiO x, SrTiO x, PbTiO x, BaTiO x, BaSrTiO x, BaCaTiO x, metal oxides such as SiAlO x; Metal nitrides such as AlN x , SiN x , AlScN x ; or metal oxynitrides such as AlO x N y , SiO x N y , HfSiO x N y , SiC x O y Nz, and AlO x , SiO x , SiO x N y , and HfSiO x are preferable. Note that the above formula merely represents the structure of the material and does not limit the composition. That is, x, y, and z attached to O and N may be any value greater than 0, and the abundance ratio of each element including a metal element is arbitrary. Further, a layered compound composed of a plurality of layers having different dielectric layers may be used.
　上記誘電体層１２の厚みは、特に限定されないが、例えば３ｎｍ以上１００ｎｍ以下が好ましく、５ｎｍ以上５０ｎｍ以下がより好ましい。誘電体層の厚みを３ｎｍ以上とすることにより、絶縁性を高めることができ、漏れ電流を小さくすることが可能になる。また、誘電体層の厚みを１００ｎｍ以下とすることにより、より大きな静電容量を得ることが可能になる。 The thickness of the dielectric layer 12 is not particularly limited, but is preferably 3 nm to 100 nm, for example, and more preferably 5 nm to 50 nm. By setting the thickness of the dielectric layer to 3 nm or more, it is possible to increase the insulation and to reduce the leakage current. Further, by setting the thickness of the dielectric layer to 100 nm or less, it is possible to obtain a larger capacitance.
　上記誘電体層１２は、単層であっても、多層であってもよい。 The dielectric layer 12 may be a single layer or a multilayer.
　上記誘電体層１２は、好ましくは、気相法、例えば真空蒸着法、ＣＶＤ法、スパッタ法、原子層堆積法（ＡＬＤ：Atomic Layer Deposition）、パルスレーザー堆積法（ＰＬＤ：Pulsed Laser Deposition）等または超臨界流体を用いる方法により形成される。高空隙率部の細孔の細部にまでより均質で緻密な膜を形成できることから、ＡＬＤ法がより好ましい。 The dielectric layer 12 is preferably formed by a vapor phase method such as a vacuum evaporation method, a CVD method, a sputtering method, an atomic layer deposition method (ALD), a pulsed laser deposition method (PLD: Pulsed Laser Deposition), or the like. It is formed by a method using a supercritical fluid. The ALD method is more preferable because a more uniform and dense film can be formed in the fine pores of the high porosity portion.
　上記上部電極１３を構成する材料は、導電性であれば特に限定されないが、Ｎｉ、Ｃｕ、Ａｌ、Ｗ、Ｔｉ、Ａｇ、Ａｕ、Ｐｔ、Ｚｎ、Ｓｎ、Ｐｂ、Ｆｅ、Ｃｒ、Ｍｏ、Ｒｕ、Ｐｄ、Ｔａおよびそれらの合金、例えばＣｕＮｉ、ＡｕＮｉ、ＡｕＳｎ、ならびにＴｉＮ、ＴｉＡｌＮ、ＴｉＯＮ、ＴｉＡｌＯＮ、ＴａＮ等の金属窒化物、金属酸窒化物、導電性高分子（例えば、ＰＥＤＯＴ（ポリ（３，４－エチレンジオキシチオフェン））、ポリピロール、ポリアニリン）などが挙げられ、ＴｉＮ、ＴｉＯＮが好ましい。 The material constituting the upper electrode 13 is not particularly limited as long as it is conductive, but Ni, Cu, Al, W, Ti, Ag, Au, Pt, Zn, Sn, Pb, Fe, Cr, Mo, Ru, Pd, Ta and alloys thereof such as CuNi, AuNi, AuSn, and metal nitrides such as TiN, TiAlN, TiON, TiAlON, and TaN, metal oxynitrides, conductive polymers (eg, PEDOT (poly (3,4) -Ethylenedioxythiophene))), polypyrrole, polyaniline) and the like, and TiN and TiON are preferred.
　上記上部電極１３の厚みは、特に限定されないが、例えば３ｎｍ以上が好ましく、１０ｎｍ以上がより好ましい。上部電極の厚みを３ｎｍ以上とすることにより、上部電極自体の抵抗を小さくすることができる。 The thickness of the upper electrode 13 is not particularly limited, but is preferably 3 nm or more, for example, and more preferably 10 nm or more. By setting the thickness of the upper electrode to 3 nm or more, the resistance of the upper electrode itself can be reduced.
　上記上部電極１３は、単層であっても、多層であってもよい。 The upper electrode 13 may be a single layer or a multilayer.
　上記上部電極１３は、ＡＬＤ法により形成してもよい。ＡＬＤ法を用いることにより、コンデンサの容量をより大きくすることができる。別法として、誘電体層を被覆し、基材の細孔を実質的に埋めることのできる、ＣＶＤ、めっき、バイアススパッタ、Ｓｏｌ－Ｇｅｌ法、導電性高分子充填などの方法で、上部電極を形成してもよい。好ましくは、誘電体層上にＡＬＤ法で導電性膜を形成し、その上から他の手法により、導電性材料、好ましくはより電気抵抗の小さな物質で細孔を充填して上部電極を形成してもよい。このような構成とすることにより、効率的により高い容量密度および低い等価直列抵抗（ＥＳＲ：Equivalent Series Resistance）を得ることができる。 The upper electrode 13 may be formed by an ALD method. By using the ALD method, the capacitance of the capacitor can be increased. Alternatively, the top electrode may be coated by a method such as CVD, plating, bias sputtering, Sol-Gel method, or conductive polymer filling that can cover the dielectric layer and substantially fill the pores of the substrate. It may be formed. Preferably, a conductive film is formed on the dielectric layer by the ALD method, and the upper electrode is formed by filling the pores with a conductive material, preferably a substance having a lower electrical resistance, by another method. May be. With such a configuration, a higher capacity density and a lower equivalent series resistance (ESR: Equivalent Series Resistance) can be obtained efficiently.
　次に、上部電極１３上に、第一外部電極５を形成する。 Next, the first external electrode 5 is formed on the upper electrode 13.
　上記第一外部電極５を構成する材料は、特に限定されないが、例えば、Ａｕ、Ｐｂ、Ｐｄ、Ａｇ、Ｓｎ、Ｎｉ、Ｃｕ等の金属および合金、ならびに導電性高分子などが挙げられる。好ましくは、第一外部電極５を構成する材料は、Ｃｕである。 The material constituting the first external electrode 5 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and conductive polymers. Preferably, the material constituting the first external electrode 5 is Cu.
　上記第一外部電極５の形成方法は、特に限定されず、例えばＣＶＤ、電解めっき、無電解めっき、蒸着、スパッタ、導電性ペーストの焼き付け等を用いることができ、電解めっき、無電解めっき、蒸着、スパッタ等が好ましい。また、これらの方法を組み合わせて用いてもよい。 The method for forming the first external electrode 5 is not particularly limited, and for example, CVD, electrolytic plating, electroless plating, vapor deposition, sputtering, baking of conductive paste, and the like can be used. Electrolytic plating, electroless plating, vapor deposition Sputtering or the like is preferable. Moreover, you may use combining these methods.
　上記第一外部電極５の厚みは、特に限定されないが、導電性多孔基材の上面を基準として、好ましくは０．１μｍ以上１００μｍ以下、より好ましくは０．５μｍ以上５０μｍ以下、さらに好ましくは０．５μｍ以上１０μｍ以下、例えば１μｍ以上５μｍ以下であり得る。 The thickness of the first external electrode 5 is not particularly limited, but it is preferably 0.1 μm or more and 100 μm or less, more preferably 0.5 μm or more and 50 μm or less, and still more preferably 0.00 on the basis of the upper surface of the conductive porous substrate. It may be 5 μm or more and 10 μm or less, for example, 1 μm or more and 5 μm or less.
　上記の工程により、複数のコンデンサ１ａを含む集合基板２９が製造される。 The collective substrate 29 including the plurality of capacitors 1a is manufactured by the above process.
　次いで、集合基板２９を、各素子に分割する。例えば、図８に示すように、集合基板２９を、ｘおよびｙで示す直線で切断し、各素子に分割することができる。即ち、本発明のコンデンサは、側面の少なくとも１つ、好ましくは側面全体が切断面であり得る。 Next, the collective substrate 29 is divided into each element. For example, as shown in FIG. 8, the collective substrate 29 can be cut along a straight line indicated by x and y and divided into each element. That is, in the capacitor of the present invention, at least one of the side surfaces, preferably the entire side surface may be a cut surface.
　集合基板の分割は、スクライバー、ダイシングブレード、各種レーザー装置、各種刃物、金型を用いて行うことができる。 The division of the aggregate substrate can be performed using a scriber, a dicing blade, various laser devices, various blades, and a mold.
　本発明のコンデンサは、上記の切断部（ｘおよびｙ）に、導電性物質が存在せず、絶縁性基体のみが存在することから、切断に伴うばりが発生しても、コンデンサの端面における短絡は生じない。 In the capacitor according to the present invention, since no conductive substance is present in the cut portions (x and y) and only the insulating substrate is present, even if a flash occurs due to cutting, a short circuit occurs at the end face of the capacitor. Does not occur.
　また、本願発明のコンデンサは、集合基板として製造することができるので、各ブロックのサイズを調整することにより、コンデンサ全体の大きさおよび静電容量を容易に調節することができる。 In addition, since the capacitor of the present invention can be manufactured as a collective substrate, the size and capacitance of the entire capacitor can be easily adjusted by adjusting the size of each block.
（実施形態２）
　本発明の別の実施形態のコンデンサ１ｂの概略断面図を図９に示す。 (Embodiment 2)
FIG. 9 shows a schematic cross-sectional view of a capacitor 1b according to another embodiment of the present invention.
　図９に示されるように、本実施形態のコンデンサ１ｂは、絶縁性基体４２のキャビティ４３が、絶縁性基体４２を貫通して設けられていることを特徴とする。具体的には、コンデンサ１ｂは、貫通キャビティ４３を有する絶縁性基体４２と、貫通キャビティ４３の底を封じるキャビティ電極４６と、キャビティ内に設けられた静電容量形成部４４と、静電容量形成部４４上の第一外部電極４５を有して成る。静電容量形成部４４は、上記コンデンサ１ａの静電容量形成部４と同様に、下部電極として機能する導電性多孔基材と、導電性多孔基材上に位置する誘電体層と、誘電体層上に位置する上部電極とから構成される。コンデンサ１ｂにおいて、第一外部電極４５およびキャビティ電極４６間に電圧を印加することにより、静電容量形成部４４の導電性多孔基材と上部電極との間に電圧が印加され、誘電体層に電荷を蓄積することができる。 As shown in FIG. 9, the capacitor 1 b of the present embodiment is characterized in that the cavity 43 of the insulating base 42 is provided so as to penetrate the insulating base 42. Specifically, the capacitor 1b includes an insulating base 42 having a through-cavity 43, a cavity electrode 46 that seals the bottom of the through-cavity 43, a capacitance forming portion 44 provided in the cavity, and capacitance formation. A first external electrode 45 on the portion 44 is provided. Similar to the capacitance forming portion 4 of the capacitor 1a, the capacitance forming portion 44 includes a conductive porous substrate that functions as a lower electrode, a dielectric layer positioned on the conductive porous substrate, and a dielectric And an upper electrode located on the layer. In the capacitor 1b, by applying a voltage between the first external electrode 45 and the cavity electrode 46, a voltage is applied between the conductive porous substrate of the capacitance forming portion 44 and the upper electrode, and the dielectric layer is applied to the dielectric layer. Charge can be accumulated.
　このようにキャビティ電極を絶縁性基体から露出させることにより、コンデンサの厚みを小さくすることができる。 Thus, by exposing the cavity electrode from the insulating substrate, the thickness of the capacitor can be reduced.
　以上、本発明のコンデンサを、コンデンサ１ａおよび１ｂに基づいて説明したが、本発明のコンデンサは、上記の実施形態および製造方法に限定されず、本発明の要旨を逸脱しない範囲で設計変更可能である。 As described above, the capacitor of the present invention has been described based on the capacitors 1a and 1b. However, the capacitor of the present invention is not limited to the above-described embodiment and manufacturing method, and the design can be changed without departing from the gist of the present invention. is there.
　例えば、上記コンデンサ１ａは、キャビティの底部にキャビティ電極を有するが、本発明のコンデンサには、キャビティ電極は存在しなくてもよい。この場合、導電性多孔基材とビアは、直接電気的に接続される。 For example, although the capacitor 1a has a cavity electrode at the bottom of the cavity, the capacitor of the present invention may not have a cavity electrode. In this case, the conductive porous substrate and the via are directly electrically connected.
　上記コンデンサ１ａは、ビア９が３つ形成されているが、本発明のコンデンサにおいては、ビアは１つまたは２つであってもよく、あるいは４つ以上であってもよい。ビアの数を多くすることにより、ビアとキャビティ電極および第二外部電極間の接触面積が大きくなり、コンデンサのＥＳＲが小さくなる。また、ビアとキャビティ電極および第二外部電極間の接触不良を抑制することができる。 The capacitor 1a has three vias 9. However, in the capacitor of the present invention, the number of vias may be one or two, or four or more. Increasing the number of vias increases the contact area between the via, the cavity electrode, and the second external electrode, and reduces the ESR of the capacitor. Further, contact failure between the via, the cavity electrode, and the second external electrode can be suppressed.
　上記コンデンサ１ｂは、キャビティの開口部がキャビティ全体にわたっているが、本発明のコンデンサにおいては、開口部はキャビティの底部の一部であってもよい。 In the capacitor 1b, the opening of the cavity extends over the entire cavity. However, in the capacitor of the present invention, the opening may be a part of the bottom of the cavity.
　上記コンデンサ１ａおよび１ｂは、静電容量形成部を１つだけ有するが、本発明はこれに限定されない。例えば、静電容量形成部は、２つ以上、例えば２つ、３つ、または４つであってもよい。静電容量形成部の数を調整することにより、静電容量を容易に調整することができる。また、静電容量形成部を複数形成し、各静電容量形成部の周囲を絶縁性基体で囲むことにより、コンデンサの強度を高めることができる。 The capacitors 1a and 1b have only one capacitance forming portion, but the present invention is not limited to this. For example, the number of capacitance forming units may be two or more, for example, two, three, or four. By adjusting the number of capacitance forming portions, the capacitance can be easily adjusted. In addition, by forming a plurality of capacitance forming portions and surrounding each capacitance forming portion with an insulating substrate, the strength of the capacitor can be increased.
　本発明のコンデンサのキャビティ電極またはビアは、緻密構造または粗構造のいずれであってもよい。ここに緻密構造とは、気体、例えば誘電体層または上部電極を気相法により製造する際に用いる気体が貫通しない密な構造であり、粗構造とは、上記気体が貫通する粗い構造を意味する。緻密構造を採用することにより、コンデンサの強度を高くすることができる。粗構造を採用することにより、キャビティ電極またはビアも静電容量形成部として機能することが可能となり、コンデンサ全体の静電容量を高くすることができる。 The cavity electrode or via of the capacitor of the present invention may have a dense structure or a coarse structure. Here, the dense structure means a dense structure in which a gas, for example, a gas used when manufacturing a dielectric layer or an upper electrode by a vapor phase method does not penetrate, and the coarse structure means a coarse structure through which the gas penetrates. To do. By adopting a dense structure, the strength of the capacitor can be increased. By adopting the rough structure, the cavity electrode or the via can also function as the capacitance forming portion, and the capacitance of the entire capacitor can be increased.
　また、本発明のコンデンサの集合基板の製造方法は、上記に限定されない。例えば、絶縁性基体は、積層体として得る必要はなく、絶縁性基板をレーザー等により削ることにより、キャビティまたは貫通孔を形成してもよい。 Also, the method of manufacturing the capacitor aggregate substrate of the present invention is not limited to the above. For example, the insulating substrate does not need to be obtained as a laminate, and the cavity or the through hole may be formed by scraping the insulating substrate with a laser or the like.
　上記導電性多孔基材としては、上記した金属焼結体の他、導電性多孔基材が挙げられる。 Examples of the conductive porous substrate include a conductive porous substrate in addition to the above-described sintered metal.
　上記導電性多孔基材は、多孔構造を有し、表面が導電性であれば、その材料および構成は限定されない。例えば、導電性多孔基材としては、多孔質金属基材、または、多孔質シリカ材料、多孔質炭素材料もしくは多孔質セラミック焼結体の表面に導電性の層を形成した基材等が挙げられる。好ましい態様において、導電性多孔基材は、多孔質金属基材である。 The conductive porous substrate has a porous structure, and its material and configuration are not limited as long as the surface is conductive. For example, examples of the conductive porous substrate include a porous metal substrate, a substrate in which a conductive layer is formed on the surface of a porous silica material, a porous carbon material, or a porous ceramic sintered body. . In a preferred embodiment, the conductive porous substrate is a porous metal substrate.
　上記多孔質金属基材を構成する金属としては、例えば、アルミニウム、タンタル、ニッケル、銅、チタン、ニオブおよび鉄の金属、ならびにステンレス、ジュラルミン等の合金等が挙げられる。好ましくは、多孔質金属基材は、アルミニウム多孔基材である。 Examples of the metal constituting the porous metal substrate include aluminum, tantalum, nickel, copper, titanium, niobium and iron metals, and alloys such as stainless steel and duralumin. Preferably, the porous metal substrate is an aluminum porous substrate.
　別の態様において、上記キャビティ内に別途製造したコンデンサを組み入れてもよい。 In another embodiment, a separately manufactured capacitor may be incorporated in the cavity.
　このようなコンデンサとしては、特に限定されず種々のコンデンサを用いることができ、例えば積層コンデンサ、巻回コンデンサ、フィルムコンデンサ、電解コンデンサ等を用いることができる。 Such a capacitor is not particularly limited, and various capacitors can be used. For example, a multilayer capacitor, a winding capacitor, a film capacitor, an electrolytic capacitor, or the like can be used.
　まず、絶縁シート２１～２４に対応するセラミックシートを製造する。 First, ceramic sheets corresponding to the insulating sheets 21 to 24 are manufactured.
　具体的には、ガラスセラミックの原料粉末として、ＣａＯ－Ａｌ２Ｏ３－ＳｉＯ２－Ｂ２Ｏ３系のガラス粉末（５０ｗｔ％）およびＡｌ２Ｏ３粉末（５０ｗｔ％）を混合したガラスセラミック粉体を準備した（平均粒径：約２μｍ）。 Specifically, a glass ceramic powder obtained by mixing a CaO—Al 2 O 3 —SiO 2 —B 2 O 3 glass powder (50 wt%) and an Al 2 O 3 powder (50 wt%) as a glass ceramic raw material powder. A body was prepared (average particle size: about 2 μm).
　上記のガラスセラミック粉体に、ジオキシルフタレートの可塑剤、アクリル樹脂のバインダ、および溶剤を加え、十分に混練して粘度２，０００ｍＰａ・ｓのスラリーを作製し、ドクターブレード法によって０．１ｍｍ厚のガラスセラミックグリーンシートを形成した。 A dioxyl phthalate plasticizer, an acrylic resin binder, and a solvent are added to the glass ceramic powder, and the mixture is thoroughly kneaded to prepare a slurry having a viscosity of 2,000 mPa · s. The thickness is 0.1 mm by the doctor blade method. A glass ceramic green sheet was formed.
　上記ガラスセラミックグリーンシートを、パンチングマシーンを用いて、所定の形状に加工した。また、ビアを有するシートについては、所定位置に複数のビアホール（０．３ｍｍφ）を打ち抜き形成し、各ビアホールにＣｕペーストを充填した。表面に金属層（電極）を有するシートについては、所定の箇所に、Ｃｕペーストをスクリーン印刷した。 The glass ceramic green sheet was processed into a predetermined shape using a punching machine. For the sheet having vias, a plurality of via holes (0.3 mmφ) were punched and formed at predetermined positions, and each via hole was filled with Cu paste. About the sheet | seat which has a metal layer (electrode) on the surface, Cu paste was screen-printed in the predetermined location.
　得られたガラスセラミックグリーンシートを、図７に記載のように積層して、グリーンシート積層体を得た。得られたグリーンシート積層体を、１１０℃、１０ＭＰａの条件で熱圧着して一体化した。得られたグリーンシート積層体の外形寸法は１００×１００ｍｍ角、キャビティの寸法は１．４×０．６ｍｍであった。グリーンシート積層体は６４３８個のキャビティを有していた。 The obtained glass ceramic green sheets were laminated as shown in FIG. 7 to obtain a green sheet laminate. The obtained green sheet laminate was integrated by thermocompression bonding under conditions of 110 ° C. and 10 MPa. The outer dimensions of the obtained green sheet laminate were 100 × 100 mm square, and the dimensions of the cavity were 1.4 × 0.6 mm. The green sheet laminate had 6438 cavities.
　次に、別途、平均粒径が約０．３μｍのＡｌ２Ｏ３粉末に、エチルセルロース樹脂をアルコールで溶解した混合液を加え、Ａｌ２Ｏ３粉末の固形分比率が６９％となるＡｌ２Ｏ３粉末を含有するペーストを作製した。 Then, separately, the Al 2 O 3 powder having an average particle size of about 0.3 [mu] m, was added a mixture of ethyl cellulose resin dissolved in alcohol, Al 2 O 3 solid content of the powder is 69% Al 2 O A paste containing 3 powders was prepared.
　次に、グリーンシート積層体のキャビティ内にＡｌ２Ｏ３粉末を含有するペーストをスクリーン印刷により充填し、乾燥させた。 Next, a paste containing Al 2 O 3 powder was filled into the cavities of the green sheet laminate by screen printing and dried.
　次に、別途、Ａｌ２Ｏ３粉末に有機溶媒、アクリルバインダ、可塑剤および分散剤を添加し、ボールミルにて混合してスラリーとし、このスラリーを用いてドクターブレード法によりＡｌ２Ｏ３グリーンシートを形成した。得られたＡｌ２Ｏ３グリーンシートを、グリーンシート積層体の上下両面に配置した（図１０参照）。 Next, separately, an organic solvent, an acrylic binder, a plasticizer, and a dispersant are added to the Al 2 O 3 powder, mixed with a ball mill to form a slurry, and this slurry is used to form an Al 2 O 3 green sheet by a doctor blade method. Formed. The obtained Al 2 O 3 green sheets were arranged on both the upper and lower surfaces of the green sheet laminate (see FIG. 10).
　次に、グリーンシート積層体の上下面に０．５ＭＰａの圧力を負荷しながら、グリーンシート積層体およびキャビティ内のＡｌ２Ｏ３、およびＡｌ２Ｏ３グリーンシートを電気式連続ベルト炉を使用して、還元中で９００℃で２０分間保持して焼成した。次いで、得られた焼結積層体の上下面のＡｌ２Ｏ３粉末をガラスビーズのブラスト処理により除去した。これにより図７に示すような構造を有する積層基板を得た。 Next, while applying a pressure of 0.5 MPa to the upper and lower surfaces of the green sheet laminate, the green sheet laminate and the Al 2 O 3 and Al 2 O 3 green sheets in the cavity were used in an electric continuous belt furnace. Then, it was calcined by holding at 900 ° C. for 20 minutes in the reduction. Next, the Al 2 O 3 powder on the upper and lower surfaces of the obtained sintered laminate was removed by blasting glass beads. As a result, a multilayer substrate having a structure as shown in FIG. 7 was obtained.
　次に、得られた積層基板の第二外部電極を覆うにように、無電解めっきによりＣｕ層を形成した。 Next, a Cu layer was formed by electroless plating so as to cover the second external electrode of the obtained multilayer substrate.
　次いで、平均粒径２００ｎｍのＮｉ金属粉を、エタノール中にて１ｍｍφのジルコニアボールを用いて、ボールミルにて分散した。この分散液に、ポリビニルアルコールを加えて、金属粉スラリーを作製した。このスラリーを、ディスペンサを用いて各キャビティ内に加え、乾燥した。乾燥後の金属粉の層の厚みは、約３０μｍであった。キャビティ内に金属粉層が形成された金属基板を、焼成炉にて２００～３００℃で脱脂後、Ｎ２雰囲気下３００～６５０℃で５分間熱処理し、金属焼結体を得た。 Next, Ni metal powder having an average particle diameter of 200 nm was dispersed in a ball mill using 1 mmφ zirconia balls in ethanol. Polyvinyl alcohol was added to this dispersion to prepare a metal powder slurry. This slurry was added into each cavity using a dispenser and dried. The thickness of the metal powder layer after drying was about 30 μm. The metal substrate on which the metal powder layer was formed in the cavity was degreased at 200 to 300 ° C. in a firing furnace and then heat-treated at 300 to 650 ° C. for 5 minutes in an N 2 atmosphere to obtain a sintered metal body.
　次に、ＡＬＤ法により、金属焼結体上に、ＡｌＯｘ膜（２５ｎｍ）を形成し、誘電体層とした。この誘電体層の上に、ＡＬＤにより、Ｒｕ膜（２０ｎｍ）を形成し、上部電極とした。 Next, an ALD method was used to form an AlOx film (25 nm) on the metal sintered body to form a dielectric layer. On this dielectric layer, a Ru film (20 nm) was formed by ALD to form an upper electrode.
　次に、上部電極上に、Ｃｕめっきにより第一外部電極を形成した。これにより、本発明のコンデンサの集合基板が得られた。 Next, a first external electrode was formed on the upper electrode by Cu plating. As a result, a capacitor aggregate substrate of the present invention was obtained.
　次に、得られた集合基板を、スクライバーを用いて、各コンデンサに分割し、図１に示すような実施例１のコンデンサを得た。 Next, the obtained collective substrate was divided into capacitors using a scriber to obtain a capacitor of Example 1 as shown in FIG.
　本発明のコンデンサは、高い静電容量を有するので、種々の電子機器に好適に用いられる。 Since the capacitor of the present invention has a high capacitance, it is suitably used for various electronic devices.
１ａ，１ｂ…コンデンサ、２…絶縁性基体、３…キャビティ、
４…静電容量形成部、５…第一外部電極、６…キャビティ電極、
７…第二外部電極、８…金属層、９…ビア、
１１…導電性多孔基材、１２…誘電体層、１３…上部電極、
２１…絶縁シート、２２…絶縁シート、２３…絶縁シート、２４…絶縁シート、
２５…開口部、２６…金属層、２７…貫通金属層、
２８…積層体、２９…集合基板、
３１…グリーンシート、３２…グリーンシート、３３…セラミックスラリー、
４２…絶縁性基体、４３…貫通キャビティ、４４…静電容量形成部、
４５…第一外部電極、４６…キャビティ電極 1a, 1b ... capacitor, 2 ... insulating substrate, 3 ... cavity,
4 ... electrostatic capacity forming part, 5 ... first external electrode, 6 ... cavity electrode,
7 ... Second external electrode, 8 ... Metal layer, 9 ... Via,
11 ... conductive porous substrate, 12 ... dielectric layer, 13 ... upper electrode,
21 ... Insulating sheet, 22 ... Insulating sheet, 23 ... Insulating sheet, 24 ... Insulating sheet,
25 ... opening, 26 ... metal layer, 27 ... penetrating metal layer,
28 ... laminate, 29 ... collective substrate,
31 ... Green sheet, 32 ... Green sheet, 33 ... Ceramic slurry,
42 ... Insulating substrate, 43 ... Through cavity, 44 ... Capacitance forming part,
45 ... first external electrode, 46 ... cavity electrode

Claims (6)

  1. 　絶縁性基体と、
    　多孔部を有する導電性多孔基材と、
    　多孔部上に位置する誘電体層と、
    　誘電体層上に位置する上部電極と、
    を有して成るコンデンサであって、前記絶縁性基体がキャビティを有し、該キャビティ内に、前記導電性多孔基材、前記誘電体層、および前記上部電極が設けられている、コンデンサ。     An insulating substrate;
    A conductive porous substrate having a porous portion;
    A dielectric layer located on the porous portion;
    An upper electrode located on the dielectric layer;
    A capacitor having the insulating base has a cavity, and the conductive porous substrate, the dielectric layer, and the upper electrode are provided in the cavity.
  2. 　前記キャビティが前記絶縁性基体を貫通しており、貫通孔の一方が金属層により封じられ、該金属層上に前記導電性多孔基材、前記誘電体層、および前記上部電極が順に配置されている、請求項１に記載のコンデンサ。 The cavity penetrates the insulating substrate, one of the through holes is sealed with a metal layer, and the conductive porous substrate, the dielectric layer, and the upper electrode are sequentially disposed on the metal layer. The capacitor according to claim 1.
  3. 　前記キャビティが底部を有し、該底部上に金属層を有しており、該金属層上に前記導電性多孔基材、前記誘電体層、および前記上部電極が順に配置されている、請求項１に記載のコンデンサ。 The cavity has a bottom, and has a metal layer on the bottom, and the conductive porous substrate, the dielectric layer, and the upper electrode are sequentially disposed on the metal layer. 1. The capacitor according to 1.
  4. 　前記キャビティが底部を有し、該底部上に、前記導電性多孔基材、前記誘電体層、および前記上部電極が順に配置されている、請求項１に記載のコンデンサ。 The capacitor according to claim 1, wherein the cavity has a bottom portion, and the conductive porous substrate, the dielectric layer, and the upper electrode are sequentially disposed on the bottom portion.
  5. 　前記キャビティが底部から絶縁性基体の下面まで貫通するビアを有する、請求項３または４に記載のコンデンサ。 The capacitor according to claim 3 or 4, wherein the cavity has a via penetrating from the bottom to the lower surface of the insulating substrate.
  6. 　前記導電性多孔基材が、金属焼結体である、請求項１～５のいずれかにコンデンサ。 The capacitor according to any one of claims 1 to 5, wherein the conductive porous substrate is a sintered metal.
PCT/JP2018/004530 2017-02-14 2018-02-09 Capacitor WO2018151029A1 (en)

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Publication number Priority date Publication date Assignee Title
CN115039190A (en) * 2020-03-24 2022-09-09 株式会社村田制作所 Capacitor with a capacitor element

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JP2001203455A (en) * 1999-11-12 2001-07-27 Matsushita Electric Ind Co Ltd Capacitor-mounted metal foil and its manufacturing method, and circuit board and its manufacturing method
US20090122460A1 (en) * 2007-11-12 2009-05-14 Alexander Gschwandtner Semiconductor Device and Method for Producing the Same
US20100283122A1 (en) * 2009-05-05 2010-11-11 Pulugurtha Markondeyaraj Systems and methods for providing high-density capacitors
US20150028449A1 (en) * 2013-07-25 2015-01-29 International Business Machines Corporation Nanoparticles for making supercapacitor and diode structures

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JP2001203455A (en) * 1999-11-12 2001-07-27 Matsushita Electric Ind Co Ltd Capacitor-mounted metal foil and its manufacturing method, and circuit board and its manufacturing method
US20090122460A1 (en) * 2007-11-12 2009-05-14 Alexander Gschwandtner Semiconductor Device and Method for Producing the Same
US20100283122A1 (en) * 2009-05-05 2010-11-11 Pulugurtha Markondeyaraj Systems and methods for providing high-density capacitors
US20150028449A1 (en) * 2013-07-25 2015-01-29 International Business Machines Corporation Nanoparticles for making supercapacitor and diode structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115039190A (en) * 2020-03-24 2022-09-09 株式会社村田制作所 Capacitor with a capacitor element
CN115039190B (en) * 2020-03-24 2023-08-25 株式会社村田制作所 Capacitor with a capacitor body

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