JP7215459B2 - Multilayer electronic component - Google Patents

Description

This disclosure relates to laminated electronic components.

In recent years, multilayer electronic components such as multilayer ceramic capacitors have been applied to electronic devices such as in-vehicle devices that require high reliability. The reliability of multilayer electronic components can be evaluated, for example, by the length of time required for insulation resistance to decrease to a predetermined value in a high temperature load test (hereinafter sometimes simply referred to as life).

As an example of a multilayer electronic component, there is a multilayer ceramic capacitor described in Japanese Patent Application Laid-Open No. 2017-228590 (Patent Document 1). A multilayer ceramic capacitor described in Patent Document 1 includes dielectric layers containing a ceramic material and nickel (Ni), and internal electrode layers containing Ni.

Insulation resistance when a high electric field is applied to dielectric layers of a multilayer ceramic capacitor as in a high temperature load test tends to be governed by grain boundaries of crystal grains forming the dielectric layers. Patent Literature 1 discloses a technique for suppressing variations in insulation resistance by incorporating Ni, which has diffused from internal electrode layers and non-uniformly existed at grain boundaries, into crystal grains.

JP 2017-228590 A

Patent Literature 1 does not mention at all a structure for taking Ni, which is non-uniformly present at grain boundaries, into crystal grains and holding it within crystal grains. An object of this disclosure is to provide a multilayer electronic component that can have high reliability.

A multilayer electronic component according to this disclosure comprises a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers. The multiple dielectric layers have multiple crystal grains. At least some of the plurality of crystal grains have trap portions within the crystal grains. The crystal grains having trap portions contain at least one element selected from the group consisting of Ni, Cu, Pt, Sn, Pd and Ag. The element is unevenly distributed in the trap portion.

A multilayer electronic component according to this disclosure can have high reliability.

1 is a cross-sectional view showing an example of a laminated ceramic capacitor that is an embodiment of a laminated electronic component according to this disclosure; FIG. FIG. 2 is a cross-sectional view for explaining a sample prepared for investigating the fine structure of crystal grains in dielectric layers of the multilayer ceramic capacitor shown in FIG. 1; 3 is a high-resolution transmission electron microscope (hereinafter sometimes abbreviated as HRTEM) observation image of the dielectric layer in the central region of FIG. 2 ; 4 is a mapping image of Ni in the region shown in FIG. 3 by energy dispersive X-ray analysis (hereinafter sometimes abbreviated as EDX). 4 is an HRTEM observation image in which the area indicated by the dashed line in FIG. 3 is enlarged. It is the line analysis result of Ni and Ba by EDX in the analysis area indicated by the dashed line in FIG. 1 is a schematic diagram of the crystal structure of BaTiO _3. FIG.

Features of this disclosure will be described with reference to the drawings. In the embodiments of the laminated electronic component described below, the same or common parts are denoted by the same reference numerals in the drawings, and the description thereof may not be repeated.

A multilayer ceramic capacitor, which is one embodiment of a multilayer electronic component according to this disclosure, will be described with reference to FIGS. 1 to 7. FIG.

<Structure of Multilayer Ceramic Capacitor>
FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor 100. FIG. A multilayer ceramic capacitor 100 includes a laminate 10 . The laminate 10 has a first main surface and a second main surface facing in the lamination direction, a first side surface and a second side surface facing in the width direction orthogonal to the lamination direction, It has a first end face 13a and a second end face 13b facing each other in orthogonal longitudinal directions.

The laminate 10 includes a plurality of laminated dielectric layers 11 and a plurality of internal electrode layers 12 . The multiple dielectric layers 11 have an outer layer portion and an inner layer portion. The outer layer portion is formed between the first main surface of the laminate 10 and the internal electrode layer 12 closest to the first main surface, and between the second main surface and the internal electrode layer 12 closest to the second main surface. is placed between. The inner layer portion is arranged in a region sandwiched between the two outer layer portions.

The plurality of dielectric layers 11 are layers composed of dielectrics. Each of the plurality of dielectric layers 11 preferably contains at least one element selected from the group consisting of Ba, Ti, Ca, Sr and Zn. Each of the dielectric layers 11 has a plurality of crystal grains containing a perovskite compound containing Ba, for example. Examples of the above perovskite type compounds include perovskite type compounds having a basic structure of BaTiO ₃ .

The plurality of internal electrode layers 12 has first internal electrode layers 12a and second internal electrode layers 12b. The first internal electrode layer 12a has a counter electrode portion facing the second internal electrode layer 12b with the dielectric layer 11 interposed therebetween, and a lead from the counter electrode portion to the first end surface 13a of the laminate 10. and an electrode section. The second internal electrode layer 12b includes a counter electrode portion facing the first internal electrode layer 12a with the dielectric layer 11 interposed therebetween, and a lead-out portion extending from the counter electrode portion to the second end surface 13b of the laminate 10. and an electrode section.

A capacitor is formed by the first internal electrode layer 12a and the second internal electrode layer 12b facing each other with the dielectric layer 11 interposed therebetween. It can be said that the multilayer ceramic capacitor 100 is formed by connecting a plurality of capacitors in parallel via first external electrodes 14a and second external electrodes 14b, which will be described later.

The internal electrode layers 12 contain a conductive material. The conductive material forming the internal electrode layers 12 includes at least one metal selected from Ni, Cu, Pt, Sn, Pd, Ag, and the like, or an alloy containing the metal. The internal electrode layers 12 may further contain dielectric particles called common material as described later. The common material is added in order to bring the sintering shrinkage characteristics of the internal electrode layers 12 closer to the sintering shrinkage characteristics of the dielectric layers 11 when firing the laminate 10, and this effect is exhibited. The material is not particularly limited as long as it exists.

The multilayer ceramic capacitor 100 further includes a first external electrode 14a and a second external electrode 14b. The first external electrode 14a is formed on the first end face 13a of the laminate 10 so as to be electrically connected to the first internal electrode layer 12a. The first external electrode 14a extends from the first end surface 13a to the first and second main surfaces and the first and second side surfaces. The second external electrode 14b is formed on the second end surface 13b of the laminate 10 so as to be electrically connected to the second internal electrode layer 12b. The second external electrode 14b extends from the second end surface 13b to the first and second main surfaces and the first and second side surfaces.

The first external electrode 14a and the second external electrode 14b have, for example, a base electrode layer and a plated layer disposed on the base electrode layer. The base electrode layer includes, for example, at least one selected from a sintered body layer, a conductive resin layer, and a metal thin film layer.

The sintered body layer is obtained by baking a paste containing glass powder and metal powder, and includes a glass portion and a metal portion. Examples of the glass forming the glass portion include B ₂ O ₃ —SiO ₂ —BaO-based glass. Examples of the metal forming the metal portion include at least one selected from Ni, Cu, Ag, and the like, or an alloy containing the metal. The sintered body layer may be formed in multiple layers with different components. In addition, the sintered body layer may be fired simultaneously with the laminate 10 in the manufacturing method described later, or may be baked after the laminate 10 is fired.

The conductive resin layer includes conductive particles such as fine metal particles and a resin portion. Examples of the metal that constitutes the fine metal particles include at least one selected from Ni, Cu, Ag, and the like, or alloys containing such metals. Examples of the resin forming the resin portion include epoxy-based thermosetting resins. The conductive resin layer may be formed in multiple layers with different components.

The metal thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer with a thickness of 1 μm or less on which fine metal particles are deposited. Examples of the metal forming the metal thin film layer include at least one selected from Ni, Cu, Ag, Au, and the like, or an alloy containing the metal. The metal thin film layer may be formed in multiple layers with different components.

Examples of the metal forming the plating layer include at least one selected from Ni, Cu, Ag, Au, Sn, and the like, or an alloy containing the metal. The plating layer may be formed in multiple layers with different components. The plating layer preferably consists of two layers, a Ni plating layer and a Sn plating layer. The Ni plating layer can prevent the base electrode layer from being eroded by solder when the multilayer electronic component is mounted. The Sn-plated layer has good wettability with solder containing Sn, and can improve mountability when mounting the multilayer electronic component.

The first external electrode 14a and the second external electrode 14b may be plated layers directly provided on the laminate 10 and directly connected to the corresponding internal electrode layers described above. The plating layer preferably includes a first plating layer and a second plating layer provided on the first plating layer.

Examples of metals constituting the first plating layer and the second plating layer include at least one selected from Cu, Ni, Sn, Au, Ag, Pd, Zn, and the like, or alloys containing such metals. For example, when Ni is used as the metal forming the internal electrode layers 12, it is preferable to use Cu, which has good bonding properties with Ni, as the first plating layer. When Sn or the like is used as the metal forming the internal electrode layers 12, it is preferable to use a metal having solder barrier properties as the metal forming the first plating layer. Moreover, it is preferable to use Ni, which has good solder wettability, as the metal forming the second plating layer.

<Microstructure of Dielectric Layer>
In order to examine the fine structure of the crystal grains included in the dielectric layer 11 of the multilayer ceramic capacitor 100 according to this disclosure, HRTEM observation and elemental mapping by EDX attached to the HRTEM were performed. In this investigation, the dielectric layer 11 used a dielectric material in which BaTiO ₃ was the basic structure of a perovskite compound and various additives were added.

Sample preparation for HRTEM observation and EDX mapping will be described with reference to FIG. FIG. 2 is a cross-sectional view for explaining a sample prepared for investigating the fine structure of crystal grains in dielectric layer 11 of multilayer ceramic capacitor 100. As shown in FIG.

A laminated body 10 of a laminated ceramic capacitor 100 was obtained by a manufacturing method to be described later. The dielectric layer 11 in the stack 10 used in this investigation comprises a perovskite-type compound with BaTiO ₃ as the basic structure. In addition, the internal electrode layers 12 contain Ni.

A polished body was obtained by polishing the laminate 10 from the first side and the second side so that the central portion in the width direction of the laminate 10 remained. As shown in FIG. 2, a virtual line OL was assumed to intersect perpendicularly with the internal electrode layers 12 in the vicinity of the central portion in the length direction. Then, along the imaginary line OL, a region where the dielectric layer 11, the first internal electrode layer 12a, and the second internal electrode layer 12b relating to the acquisition of the capacitance of the polishing body are stacked is 3 or so in the stacking direction. It was divided into 3 regions: upper region, middle region and lower region. In FIG. 2, the upper, middle and lower regions are indicated by dashed lines.

An upper region, a central region and a lower region were cut out from the polishing body and thinned to obtain three thin film samples from each region. The three thin film samples each include dielectric layer 11 . For the three thin film samples of the upper region, the central region and the lower region of the laminate 10 obtained as described above, HRTEM observation and elemental mapping by EDX attached to the HRTEM were performed.

The results of HRTEM observation and elemental mapping by EDX are shown in FIGS. FIG. 3 is an HRTEM observation image of the dielectric layer in the central region of FIG. FIG. 4 is an EDX mapping image of Ni in the region shown in FIG. FIG. 5 is an HRTEM observation image in which the area indicated by the dashed line in FIG. 3 is enlarged. Note that the magnification of the HRTEM observation image and the EDX elemental mapping image does not need to be such that 20 or more crystal grains fit in one field of view. Also, HRTEM observation and EDX elemental mapping may be based on images captured in multiple fields of view. In this case, each image may have an area in the range of 1 μm or less by 1 μm or less.

HRTEM observation images and EDX mapping images showed no significant difference between the upper and lower regions and the central region. Therefore, the results obtained from the central region described below are regarded as the microstructure of the crystal grains included in the dielectric layer 11 of the multilayer ceramic capacitor 100 according to this disclosure.

The dielectric layer 11 has a thickness of about 1.5 μm, and the average grain size of the crystal grains obtained as the average value of equivalent circular diameters by image analysis is about 0.13 μm. The grain boundaries GB of the crystal grains G were visually determined from the HRTEM observation image.

As shown in FIG. 3, some of the multiple crystal grains G have multiple linear portions within the crystal grain G. As shown in FIG. As can be seen from FIG. 4, Ni is contained in the crystal grains G having a plurality of linear portions, and Ni is unevenly distributed in these linear portions. It is presumed that this Ni is diffused from the Ni contained in the internal electrode layers 12 . That is, these linear portions function to trap Ni diffused from the internal electrode layer 12 and incorporate it into the crystal grains G. As shown in FIG. Therefore, these linear portions can be called trap portions TP in the crystal grains G. As shown in FIG. The linear trap portion has a longitudinal length of 20 nm or more.

Further, as shown in FIG. 5, there is no change in the lattice images on the left and right sides of the trap portion TP, confirming that the trap portion TP is not the grain boundary GB between two different crystal grains G. That is, the trap part TP is a part where the crystallinity has changed in the crystal grain G, and since the electron beam is diffracted there, it appears as a linear part in the HRTEM observation image. It was also confirmed that the site where the crystallinity changed was parallel to the lines seen in the lattice image. Since the line visible in this lattice image represents one of the crystal planes, it is presumed that the portion where the crystallinity has changed contains a planar defect parallel to this crystal plane within the crystal grain G.

As shown in FIG. 3, a plurality of plane defects exist within the crystal grain G. As shown in FIG. Now, consider a virtual plane that intersects with each of a plurality of planar defects. In this investigation, the virtual plane can be the viewing plane of the HRTEM (the plane represented as FIG. 3). The lines of intersection between this virtual plane and the plurality of plane defects are parallel to each other. That is, on the HRTEM observation plane, a plurality of surface defects appear as linear portions parallel to each other.

Since these multiple surface defects are parallel to each other, they are generated with a certain regularity. That is, it is presumed that these multiple planar defects are planar defects that have a low energy for existing on the above-mentioned crystal plane and tend to exist stably. Planar defects can exist more stably by being paired close to each other. This can also be understood from the fact that even a plane defect that looks like a single line in FIG. 3 is confirmed as two adjacent plane defects in FIG.

FIG. 6 shows the result of further research on the structure of this trap part TP. FIG. 6 shows line analysis results of Ni and Ba by EDX in the analysis region indicated by the dashed line in FIG. 5, that is, around the trap portion TP. It can be seen from the line analysis results in FIG. 6 that Ni is unevenly distributed in the trap portion TP. Also, it can be seen that the amount of Ba is smaller in the trap portion TP than in the portions other than the trap portion TP.

Here, a schematic diagram of the crystal structure of BaTiO ₃ is shown in FIG. As described above, there is a difference in the amount of Ba between the trap portion TP and the other portions. That is, the trap part TP is presumed to be a defect in the plane composed of Ba ²⁺ in the perovskite compound having a basic structure of BaTiO ₃ composing the crystal grain G.

As shown in FIG. 7, since the plane formed by Ba ²⁺ in BaTiO ₃ is the (111) plane, the trap part TP is presumed to be a plane defect of the (111) plane.

As described above, the insulation resistance when a high electric field is applied to the dielectric layers of a multilayer ceramic capacitor tends to be governed by grain boundaries of crystal grains forming the dielectric layers. In the multilayer ceramic capacitor 100 according to this disclosure, Ni diffused from the internal electrode layers 12 is taken into the crystal grains G by the trap portions TP, thereby suppressing variations in insulation resistance. In addition, it is possible to improve the life and the like in a high temperature load test in which a high electric field is applied to the dielectric layer 11, and to obtain high reliability.

From the viewpoint of reliability of the multilayer ceramic capacitor 100, it is preferable that the crystal grain G having the trap portion TP has a plurality of trap portions TP within the crystal grain G. In addition, the dielectric layer 11 preferably contains more crystal grains G having trap parts TP, and more preferably contains more crystal grains G having a plurality of trap parts TP.

From this investigation, it was inferred that the trap part TP in the multilayer ceramic capacitor 100 was a plane defect of the (111) plane, but the plane defect of the (111) plane is an example of the structure of the trap part TP. is not limited to Also, with regard to the trapped element, Ni has been described as an object, but Ni is an example of an element forming the internal electrode layer, and the trapping element is not limited to this. Cu, Pt, Sn, Pd, Ag and the like are other examples of the elements unevenly distributed in the trap part TP. The element unevenly distributed in the trap part TP preferably contains at least one element selected from the group consisting of Ni, Cu, Pt, Sn, Pd and Ag. The trap part TP according to this disclosure has, for example, a structure capable of trapping an element diffused from the internal electrode layer.

The element unevenly distributed in the trap part TP may be the same kind of element as the element forming the internal electrode layer, but it is not necessarily the element diffused from the internal electrode layer. As will be described later, by using a dielectric raw material powder containing at least one element selected from the group consisting of Ni, Cu, Pt, Sn, Pd and Ag, a multilayer ceramic capacitor having a trap portion TP according to this disclosure can be obtained. You can also get

<Manufacturing method of multilayer ceramic capacitor>
Next, a method for manufacturing a multilayer ceramic capacitor 100 representing an embodiment of a multilayer electronic component according to this disclosure will be described in order of manufacturing steps. The manufacturing method of the multilayer ceramic capacitor 100 includes the following steps.

The manufacturing method of this laminated ceramic capacitor 100 includes a step of obtaining a plurality of ceramic green sheets using dielectric raw material powder. The word "green" is an expression representing "before sintering" and will be used in this sense hereinafter. The dielectric raw material powder is, for example, BaTiO ₃ powder with various additives added to its surface. The ceramic green sheets contain a binder component in addition to the dielectric raw material powder. The binder component is not particularly limited.

The above-mentioned dielectric raw material powder is obtained by, for example, adding an organic compound as an additive to the surface of the _BaTiO3 powder and calcining it to burn the organic component, so that the additive is in the form of an oxide _on the surface of the BaTiO3 powder. It can be produced so as to be in a given state. However, the present invention is not limited to this, and the dielectric raw material powder may contain an organic compound, or may contain an oxide and an organic compound. In the dielectric raw material powder, the BaTiO ₃ powder may be a BaTiO ₃ solid solution powder.

In one embodiment, the manufacturing method of the multilayer ceramic capacitor 100 includes a step of obtaining a plurality of ceramic green sheets using dielectric raw material powder, the dielectric raw material powder being Ni, Cu, Pt, Sn, Pd and Ag. A dielectric raw material powder containing at least one element selected from the group consisting of By using such a dielectric raw material powder, at least one element selected from the group consisting of Ni, Cu, Pt, Sn, Pd and Ag is unevenly distributed in the trap part of the crystal grains constituting the dielectric layer. be able to. An example of _BaTiO3 powder that can be used to form a dielectric raw material powder containing at least one element selected from the group consisting of Ni, Cu, Pt, Sn, Pd and Ag can be produced by the following method. _BaTiO3 powder containing Ni that can be used.

First, Ni is coated on BaTiO ₃ powder by plasma treatment to form Ni-coated BaTiO ₃ powder. BaTiO ₃ coated with Ni is dispersed in a solution, Ba and Ti in the form of metal alkoxides are added, and hydrolyzed to form a structure in which the coated Ni is further covered with BaTiO ₃ . By using BaTiO ₃ having such a structure, it is possible to obtain a laminated ceramic capacitor in which Ni is trapped as linear portions in the crystal grains constituting the dielectric layers.

BaTiO3 powder can be obtained _, for example _, by calcining a mixture of BaCO3 powder and _TiO2 powder. Alternatively, BaTiO ₃ powder that has already been produced by a known method such as the oxalic acid method or the hydrothermal synthesis method may be used. As described above, the material for forming the dielectric layer is not limited to BaTiO ₃ , and for example, a material based on Ca, Ti or Zr may be used.

The manufacturing method of this laminated ceramic capacitor 100 includes a step of printing an internal electrode layer pattern on a ceramic green sheet. The internal electrode layer paste contains, for example, Ni powder, BaTiO ₃ powder with various additives added to its surface (common material), and a binder component. Note that the common material is not essential in the internal electrode layers. The binder component is not particularly limited. Here, the step of printing the internal electrode layer pattern on the ceramic green sheets corresponds to the step of forming the pre-sintered internal electrode layers on the pre-sintered dielectric layers using the internal electrode layer paste.

The above common material is applied to the surface of the BaTiO ₃ powder, for example, by applying an organic compound as an additive to the surface of the BaTiO 3 powder and calcining to burn the organic component, so that the additive is applied to the surface of the BaTiO ₃ powder in the form of an oxide. It can be manufactured so as to be in a state of However, not limited to this, the common material may contain an organic compound, or may contain an oxide and an organic compound. Also, the BaTiO ₃ powder in the common material may be a BaTiO ₃ solid solution powder. The common material may be the same as or different from the dielectric raw material powder.

The manufacturing method of this laminated ceramic capacitor 100 includes a step of laminating a plurality of ceramic green sheets including ceramic green sheets having internal electrode patterns to obtain a green laminated body.

The manufacturing method of this laminated ceramic capacitor 100 includes a step of sintering a green laminated body to obtain a laminated body including a plurality of laminated dielectric layers and a plurality of internal electrode layers.

EXAMPLES Hereinafter, the invention according to this disclosure will be described more specifically by showing examples and comparative examples, but the invention according to this disclosure is not limited by these examples.

<Comparative Example 1>
A multilayer ceramic capacitor was produced by the following procedure. First, dielectric sheets and conductive paste for internal electrodes were prepared. Conductive pastes for dielectric sheets and internal electrodes contain organic binders and solvents. A dielectric sheet was produced using a dielectric raw material powder. The dielectric raw material powder includes _BaTiO3 powder.

An internal electrode pattern was formed by printing a conductive paste for internal electrodes in a predetermined pattern on the dielectric sheet. A predetermined number of dielectric sheets for outer layers on which internal electrode patterns are not printed are laminated, and dielectric sheets on which internal electrode patterns are printed are successively laminated thereon, and a predetermined number of dielectric sheets for outer layers are laminated thereon. It laminated|stacked and produced the lamination sheet. A laminated block was produced by pressing the laminated sheet in the lamination direction by an isostatic press. The laminated block was cut into a predetermined size, and laminated chips were cut out. At this time, the corners and ridges of the laminated chips were rounded by barrel polishing. A laminated body was produced by sintering the laminated chips. The sintering temperature is preferably 900 to 1300° C., although it depends on the materials of the dielectric and internal electrodes. The sintering temperature was set within this range also in this comparative example. A conductive paste for external electrodes was applied to both end surfaces of the laminated chip and baked to form a baked layer for the external electrodes. The baking temperature is preferably 700-900°C. Also in this comparative example, the baking temperature was set within this range. Plating was applied to the surface of the baking layer.

<Example 1>
(1) Preparation of Dielectric Raw Material Powder 1 A BaTiO ₃ powder and metallic Ni were simultaneously vaporized by plasma and then cooled to form a Ni-coated BaTiO ₃ powder. The thickness of Ni to be coated was set to 2 nm by adjusting the amount of Ni to be introduced. A dielectric material powder 1 was prepared in the same manner as in Comparative Example 1 except that this Ni-coated BaTiO ₃ powder was used.

The cross section of 10 particles was confirmed with a TEM, and the average thickness was taken as the thickness of the Ni coating.
(2) Fabrication of Multilayer Ceramic Capacitor A multilayer ceramic capacitor was fabricated in the same manner as in Comparative Example 1 except that the dielectric raw material powder 1 prepared in (1) above was used.

<Example 2>
(1) Preparation of Dielectric Raw Material Powder 2 Dielectric raw powder 2 was prepared in the same manner as in Example 1, except that the thickness of the Ni coating was 5 nm.

(2) Production of laminated ceramic capacitor A laminated ceramic capacitor was produced in the same manner as in Comparative Example 1 except that the dielectric raw material powder 2 prepared in (1) above was used.

<Example 3>
(1) Preparation of Dielectric Raw Material Powder 3 Dielectric raw powder 3 was prepared in the same manner as in Example 1, except that the thickness of the Ni coating was 9 nm.

(2) Production of laminated ceramic capacitor A laminated ceramic capacitor was produced in the same manner as in Comparative Example 1 except that the dielectric material powder 3 prepared in (1) above was used.

[Measurement/Evaluation]
(1) Measurement of Microstructure of Dielectric Layer A sample was prepared from the multilayer ceramic capacitor by the above-described procedure, and the central region was subjected to HRTEM observation and elemental mapping by EDX attached to HRTEM. The magnification of the HRTEM observation image and the EDX elemental mapping image was adjusted so that 20 crystal grains could fit in one field of view.

Table 1 shows the number of crystal grains having Ni trap portions among the 20 crystal grains within the field of view. Table 1 shows the number of crystal grains having two or more Ni trap portions among the 20 crystal grains within the field of view.

(2) Evaluation of Reliability The reliability of the multilayer ceramic capacitor was evaluated by the following two indexes based on the high temperature load test.

(2-1) Mean time to failure (HALT life) in high temperature load acceleration test
The mean time to failure (MTTF) was measured in a high temperature accelerated load test (HALT) in which 12 V was applied to the multilayer ceramic capacitor at 150°C. Table 1 shows the results. Failure was determined when the IR was 10 ⁴ or less.

(2-2) Number of failures after 2000 hours in high temperature load test The number of failures (per 72 pieces) after 2000 hours in a normal high temperature load test in which 6 V is applied to the multilayer ceramic capacitor at 85°C was measured. . Table 1 shows the results. Failure was determined when the IR was 10 ⁴ or less.

In Comparative Example 1, since the crystal grains of the dielectric layer do not have trap portions, the HALT life is short and the number of failures after 2000 hours in the high temperature load test is large.

On the other hand, in Examples 1 to 3, the crystal grains of the dielectric layers have trap portions where Ni is unevenly distributed, so that the reliability of the multilayer ceramic capacitors is high. From the viewpoint of reliability of the multilayer ceramic capacitor, it is preferable that the crystal grain having the trap portion has a plurality of trap portions within the crystal grain. Further, from the viewpoint of reliability of the laminated ceramic capacitor, the dielectric layer of the laminated ceramic capacitor preferably contains more crystal grains having trap portions, and more preferably contains more crystal grains having a plurality of trap portions. .

The embodiments disclosed in this specification are exemplary, and the invention according to this disclosure is not limited to the above-described embodiments. That is, the scope of the invention according to this disclosure is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope of equivalence to the scope of claims. Moreover, various applications and modifications can be made within the above range.

For example, various applications and modifications can be made within the scope of the present invention regarding the number of dielectric layers and internal electrode layers constituting the laminate, the materials of the dielectric layers and internal electrode layers, and the like. In addition, although a multilayer ceramic capacitor has been exemplified as a multilayer electronic component, the invention according to this disclosure is not limited to that, and can be applied to a capacitor element or the like formed inside a multilayer substrate.

Reference Signs List 100 laminated ceramic capacitor 10 laminate 11 dielectric layer 12 internal electrode layer 12a first internal electrode layer 12b second internal electrode layer 13a first end surface 13b second end surface 14a first external electrode, 14b second external electrode, OL virtual line, G crystal grain, GB grain boundary, TP trap portion.

Claims (7)

a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers;
The plurality of dielectric layers have a plurality of crystal grains,
At least some of the plurality of crystal grains have a trap portion within the crystal grain,
The crystal grains having the trap portion contain at least one element selected from the group consisting of Ni, Cu, Pt, Sn, Pd and Ag,
A multilayer electronic component, wherein the element is unevenly distributed in the trap portion. 2. The multilayer electronic component according to claim 1, wherein a plurality of said trap portions are present within said crystal grains. 3. The multilayer electronic component according to claim 1, wherein said unevenly distributed element includes an element constituting said internal electrode layer. 4. The multilayer electronic component according to claim 1, wherein said dielectric layer contains at least one element selected from the group consisting of Ba, Ti, Ca, Sr and Zn. 5. The multilayer electronic component according to claim 1, wherein said trap portion includes a portion where crystallinity has changed in said crystal grain. 6. The multilayer electronic component according to claim 1, wherein said crystallinity-changed portion in said crystal grain includes a planar defect in said crystal grain. There are a plurality of planar defects in the crystal grains,
7. The laminated electronic component according to claim 6, wherein in a virtual plane that intersects with each of said plurality of planar defects, lines of intersection between said plurality of planar defects and said virtual plane are parallel to each other.

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