WO2018150776A1 - Array substrate, mounted element, device comprising array substrate and method for producing array substrate - Google Patents

Array substrate, mounted element, device comprising array substrate and method for producing array substrate Download PDF

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Publication number
WO2018150776A1
WO2018150776A1 PCT/JP2018/000747 JP2018000747W WO2018150776A1 WO 2018150776 A1 WO2018150776 A1 WO 2018150776A1 JP 2018000747 W JP2018000747 W JP 2018000747W WO 2018150776 A1 WO2018150776 A1 WO 2018150776A1
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Prior art keywords
elements
array substrate
bump
mounting
main body
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PCT/JP2018/000747
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French (fr)
Japanese (ja)
Inventor
研 足立
修一 岡
周作 柳川
出穂 畑田
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
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Priority to CN201880010798.4A priority Critical patent/CN110268459A/en
Publication of WO2018150776A1 publication Critical patent/WO2018150776A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • This technology relates to a technology such as an array substrate on which a large number of elements are mounted.
  • Patent Document 1 describes a mounting method including a step of manufacturing an EL display device by transferring a TFT chip from a transfer source substrate to a mounting substrate.
  • the transfer source substrate is opposed to a mounting substrate including bumps covered with an adhesive (see FIG. 2E).
  • the connection terminal of the TET chip attached to the transfer source substrate through the release layer is pressure-bonded to the bump (see FIG. 2F).
  • a release member attached on another TFT chip also adheres to the adhesive.
  • Light is irradiated to the TFT chip through the mask (see FIG. 2G).
  • peeling of the peeling layer is induced, and the TFT chip is mounted on the mounting substrate via the adhesive (see FIG. 2H) (see, for example, paragraphs [0024] and [0025] of the specification of Patent Document 1). .)
  • Patent Document 1 since the method of Patent Document 1 includes a step of forming a release member in each region of the non-transfer chip while avoiding the region of the transfer chip, the necessary materials increase and the process becomes complicated. . Further, since the release member remains on the mounting substrate, it becomes difficult to mount the chip on the remaining portion.
  • an array substrate includes a mounting substrate and a plurality of elements.
  • the plurality of elements include two or more first elements and one or more second elements different from the first elements, and are mounted so as to be arranged in an array structure on the mounting substrate.
  • Each of the plurality of elements may have a main body and one or more bumps provided on the main body.
  • the length of one side of the main body of the second element may be shorter than that of the first element. This facilitates the mounting of the second element in the removal region after removal of the specific or arbitrary first element.
  • the mounting substrate has lands to which bumps of the plurality of elements are connected.
  • the difference between the length of one side of the main body of the second element and that of the first element may be twice or more the sum of the radius of the land and the radius of the bump of the second element.
  • the length of one side of the main body of the first element may be not less than 60 ⁇ m and not more than 2000 ⁇ m, and the length of one side of the main body of the second element may be not less than 50 ⁇ m and not more than 1990 ⁇ m.
  • the first element may have a first bump group.
  • the second element may include a second bump group having an arrangement that matches the arrangement of the first bump group.
  • the arrangement of the first bump group includes the arrangement of the second bump group. You may do it.
  • the first element may include a first bump group
  • the second element may include a second bump group having an arrangement different from the entire arrangement of the first bump group.
  • the bump height of the second element may be lower than the bump height of the first element.
  • the bumps of the second element may have at least two different heights.
  • the mounting element which concerns on one form is the said 2nd element mounted in the mounting board
  • the plurality of elements are arranged in an array structure on the mounting substrate.
  • the mounting element includes a main body configured such that the length of one side is shorter than the length of one side of the main body of the first element, and one or more bumps provided on the main body.
  • a device includes the array substrate.
  • a method for manufacturing an array substrate includes transferring and mounting a plurality of first elements arranged in an array structure on a mounting substrate. One or more first elements of the plurality of first elements are removed from the mounting substrate. One or more second elements different from the first element are mounted in the removal region on the mounting substrate where the first element is removed.
  • the plurality of first elements are mounted on the mounting substrate by transfer, and the second element is mounted in the removal region from which the first element has been removed.
  • An array substrate including elements can be easily manufactured.
  • Each of the plurality of elements may have a main body and one or more bumps provided on the main body.
  • the mounting board may have lands to which bumps of the plurality of elements are connected.
  • the height of the bump of the second element before mounting the second element is set so that the height of the main body of the first element from the mounting substrate is the same as that of the second element. You may be comprised lower than the height of the bump of an element.
  • the second element may be configured as follows. That is, after mounting the second element, the bumps of the second element before mounting the second element are at least two different heights so that the mounting substrate and the main body of the second element are parallel to each other. You may have.
  • the second element may be arranged on the mounting substrate so that a main body of the second element is inclined with respect to the mounting substrate after mounting the second element.
  • the bumps of the second element may have at least two different heights.
  • FIG. 1 is a diagram illustrating an array substrate according to an embodiment of the present technology.
  • 2A to 2E are views showing a method of manufacturing an array substrate.
  • FIG. 3 shows a state where the manufactured array substrate is cut and divided at a position indicated by a broken line to form a plurality of array substrates.
  • FIG. 4 is a diagram showing a device using an array substrate.
  • FIG. 5 is a diagram for illustrating the sizes of the first element 1 and the second element.
  • 6A to 6C are sectional views showing manufacturing steps of the array substrate shown in FIGS. 2C to 2E.
  • FIG. 7 shows a mounting example when the sizes of the first element and the second element are the same.
  • FIG. 8 is a diagram for explaining the shift amount of the second element, and is an enlarged view of a portion surrounded by a one-dot chain line in FIG. 6C.
  • 9A to 9D are diagrams showing various forms of the arrangement of the bump groups of the element.
  • FIG. 10 shows a form in which the arrangement of the second bump group is not included in the arrangement of the first bump group.
  • FIG. 11 is a cross-sectional view showing a mounting substrate having residual solder of the first bump group.
  • 12A and 12B are cross-sectional views showing a first element and a second element for explaining the height of the bump, respectively.
  • 13A and 13B show a mounting process in the case where the bump height of the first element is the same as that of the second element.
  • FIG. 14A and 14B show a mounting process in the case where the bump height of the first element is different from that of the second element.
  • FIG. 15 shows a case where the amount of residual solder on the land is different in one removal region.
  • FIG. 16 shows a form in which the bump diameter of the second element is different when the amount of residual solder on the land is different in one removal region.
  • FIG. 17 shows a form in which the bump diameter of the second element is different when the amount of residual solder on the land is the same in one removal region.
  • FIG. 1 is a diagram illustrating an array substrate 50 according to an embodiment of the present technology.
  • the array substrate 50 includes a mounting substrate 10 and a plurality of elements 15 on the mounting substrate 10.
  • the plurality of elements 15 are mounted on the mounting substrate 10 so as to be arranged in an array structure.
  • the plurality of elements 15 include two or more (plural) first elements 11 and one or more second elements 12 (mounting elements) different from the first elements 11. In the present embodiment, two or more second elements 12 are provided.
  • one element 11 is a light receiving element
  • the second element 12 is a light emitting element
  • the array substrate 50 is used as an imaging device, for example.
  • the first element 11 is a light emitting element
  • the second element 12 is a light receiving element
  • the array substrate 50 is used as a display device, for example.
  • An example of the light receiving element is a photodiode.
  • the light emitting element include LED (Light Emitting Diode), LD (Laser Diode), and organic EL (Electro-Luminescence).
  • An array structure array is typically a matrix array along two orthogonal axes (xy axes).
  • the array structure includes, in addition to this matrix-like arrangement, a staggered arrangement, an arrangement along a straight line or a curve in two dimensions, and an arrangement having an arrangement having regularity or geometric characteristics.
  • the number of second elements 12 is smaller than the number of first elements 11.
  • the ratio of the number of the second elements 12 to the number of the first elements 11 is 1 ppm to 30%, and more practically 0.01% to 15%. .
  • the plurality of second elements 12 may be arranged adjacently and continuously in a predetermined region on the array substrate 50.
  • FIG. 2A to 2E are diagrams showing a method of manufacturing the array substrate 50.
  • a transfer source substrate 60 such as a semiconductor wafer on which a plurality of first elements 11 are formed is prepared.
  • FIG. 2B a mounting substrate 10 which is an unmounted transfer destination substrate is prepared.
  • the first elements 11 are formed in an array structure at a pitch substantially the same as the mounting pitch on the mounting substrate 10 or a suitable pitch.
  • a UBM UnderUBump Metalization
  • Lands (not shown here) configured as are formed respectively.
  • Corresponding solder bumps (not shown here) are formed on the lands of the first element 11.
  • the solder bump is simply referred to as “bump”.
  • the first element 11 is transferred from the transfer source substrate 60 to the mounting substrate 10.
  • the first elements 11 are collectively transferred to the mounting substrate 10 over the entire surface of a predetermined mounting area.
  • this transfer method for example, the transfer source substrate 60 and the mounting substrate 10 are aligned, superposed, and the first element 11 is mounted on the mounting substrate 10 by heat treatment such as reflow (of the first element 11). Bump joins to land).
  • one or more first elements 11 arranged at predetermined positions on the mounting substrate 10 are removed from the mounting substrate 10.
  • the plurality of first elements 11 are removed.
  • Examples of the removal method include known methods described in JP 2001-007508, 2010-36232, 2004-260053, 2013-21325, and the like.
  • one or more second elements 12 are mounted on the removal region 14 on the mounting substrate 10 after the first element 11 is removed.
  • the plurality of second elements 12 are mounted in the plurality of removal regions 14, respectively. Thereby, the array substrate 50 is completed.
  • a mounting method of the second element 12 for example, transfer by laser ablation may be used, or a component mounting machine may be used.
  • FIG. 3 shows a state where the array substrate 50 manufactured as described above is cut and divided at a position indicated by a broken line to form a plurality of array substrates 50 ′. In this figure, it is divided into four, but it may be divided into five or more. Thereby, a plurality of array substrates 50 ′ are formed from one array substrate 50.
  • the plurality of first elements 11 are mounted on the mounting substrate 10 simultaneously by transfer, and the second elements 12 are mounted in the removal region 14 where the first elements 11 are removed.
  • This manufacturing method does not include a complicated process, and can easily manufacture the array substrate 50 including the first element 11 and the second element 12.
  • cost reduction is realizable. Further, no extra material such as a release member is left on the completed array substrate 50.
  • a repair element having the same function as the first element 11 may be used. That is, when a specific first element 11 is defective among the plurality of first elements 11, a repair element is mounted as the second element 12 instead of the first element 11 having the defect. That is, the removal of the first element 11 and the repair process can be performed, the number of manufacturing processes of the array substrate 50 including the repair process can be reduced, and the manufacture of the array substrate 50 can be realized with a high yield.
  • the repair element is configured so that the size of the repair element (the length of one side of the main body) is different from that of the first element 11, for example.
  • FIG. 4 is a diagram showing a device using the array substrate 50. As shown in FIG. In this device 100, the flexible wiring board 13 is connected to two sides of the array substrate 50. The number of elements 15 shown in this figure is different from the number of elements 15 on the array substrate 50 shown in FIG. In FIGS. 1 to 4, the number of elements is illustrated to be easy to understand, but the actual number of elements may be several thousand to several tens of thousands or even larger.
  • Examples of devices using the array substrate 50 include the following devices in addition to the light emitting and receiving devices as in the present embodiment.
  • a mirror array device For example, a MEMS (Micro Electro Mechanical Systems) device, another sensor array device, or a device composed of a combination of at least two of them.
  • MEMS Micro Electro Mechanical Systems
  • a device composed of a combination of at least two of them By using this manufacturing method, it is possible to significantly reduce the number of steps of a device on which a large number of types of elements such as sensor array devices are mounted, and it becomes easy to manufacture a device having specific characteristics.
  • FIG. 5 is a diagram for showing the sizes of the first element 11 and the second element 12.
  • the first element 11 includes a main body 11a and bumps 11b (plural) provided on the main body 11a.
  • the second element 12 includes a main body 12a and bumps 12b (plural).
  • the main bodies 11a and 12a have a rectangular shape.
  • the length of one side of the main body 12 a of the second element 12 is shorter than that of the first element 11. In this case, the length of one side is set to the extent that there is no adverse effect on the function of the second element 12.
  • the size of one side of the main body 11a, 12a of the element 15 is not less than 50 ⁇ m and not more than 2000 ⁇ m, and a narrower range is not less than 90 ⁇ m and not more than 400 ⁇ m.
  • the length of one side of the main body 11a of the first element 11 is 60 ⁇ m or more and 2000 ⁇ m or less, 70 ⁇ m or more and 1500 ⁇ m or less as a narrower range, and 80 ⁇ m or more and 1000 ⁇ m or less as a narrower range.
  • the length of one side of the main body 12a of the second element 12 is 50 ⁇ m or more and 1990 ⁇ m or less, a narrower range is 50 ⁇ m or more and 1490 ⁇ m or less, and a narrower range is 60 ⁇ m or more and 600 ⁇ m or less.
  • each bump 12b of the second element 12 is formed on the land (the plurality of lands 16 in one removal region 14 and the residual solder 11c thereon) on the removal region 14 (see FIG. 2D) of the mounting substrate 10.
  • the second elements 12 can be mounted on the mounting substrate 10 so as to be connected to each other.
  • the number of bumps that one element 15 has is several to several tens, depending on the element size.
  • the diameters of the bumps 11a and 12b are 15 ⁇ m or more and 40 ⁇ m or less, and more narrowly 20 ⁇ m or more and 30 ⁇ m or less.
  • 6A to 6C are sectional views showing the manufacturing process of the array substrate 50 shown in FIGS. 2C to 2E.
  • the bumps 11b of the first element 11 are bonded to the lands 16 of the mounting board 10, whereby the first element 11 is mounted on the mounting board 10.
  • the bump 12b of the second element 12 is bonded to the land 16, but may be mounted in a shifted manner.
  • the length of one side of the main body 12a is short, so that the second element 12 does not contact the adjacent first element 11. Yes (easy to implement)
  • the elements 15 are arranged at a high density, the merit is great.
  • FIG. 8 is a diagram for explaining the shift amount of the second element 12, and is an enlarged view of a portion surrounded by a one-dot chain line in FIG. 6C. Since the first element 11 was originally mounted in the removal region 14, the distance between the adjacent first elements 11 (distance a in FIG. 6B) in this removal region 14 is one side of the main body 11 a of the first element 11. It is set slightly larger than the length. Since the second element 12 is smaller than the first element 11, if the second element is mounted at an exact position, the second element 12 can be accommodated in the removal region 14. Needless to say.
  • the distance d between the adjacent main bodies 11a is, for example, 10 ⁇ m or more and 30 ⁇ m or less, and more narrowly 10 ⁇ m or more and 20 ⁇ m or less, 15 ⁇ m or more and 25 ⁇ m or less, or 15 ⁇ m or more and 20 ⁇ m or less.
  • the difference between the length of one side of the main body 12a of the second element 12 and that of the first element 11 may be set to be twice or more the sum b of the radius of the land 16 (residual solder 11c) and the radius of the bump 12b. desirable.
  • the radii of the land 16 and the bump 12b are substantially the same. According to such conditions, even if the second element 12 is arranged with a deviation from the intended position in a state where the land 16 and the bump 12b are joined (electrical connection is possible), the main bodies 11a and 12a There is no contact between them.
  • “double” means that the second element 12 may be shifted to the left or right in FIG. 8 with respect to the position of the land 16.
  • the second element 12 is mounted so that the maximum deviation from the intended position occurs in a state where the land 16 and the bump 12b are bonded, the second element 12 and the adjacent element Contact with the first element 11 can be prevented.
  • the size of the second element 12 is smaller than that of the first element 11, but the size of the first element may be smaller than the size of the second element.
  • FIGS. 9A to 9D are diagrams respectively showing various forms of the arrangement of bumps (bump groups) of the element 15.
  • the uppermost drawing shows the arrangement form of the bumps (first bump group 110) of the first element 11 respectively.
  • the second drawing from the top shows the arrangement of the bumps (second bump group 120) of the second element 12, respectively.
  • the first element 11 is removed, and a part of the solder of the first bump group 110 remains in the removal region 14 (see FIG. 6B), and the second element 12 is mounted on the mounting board.
  • FIG. The lowermost figure shows a cross section taken along the broken line in the third stage.
  • FIG. 9D shows a form in which the size of the first element 11 is smaller than the size of the second element 12.
  • FIG. 9A shows a form in which the arrangement of the first bump group 110 is completely the same as the arrangement of the second bump group 120.
  • the second element 12 is mounted on the removal region 14 of the mounting substrate 10
  • the residual solder 11 c (see FIG. 6B) of the first bump group 110 remaining in the removal region 14 and the bump 12 b of the second element 12. And everything is joined.
  • An electrode in a state where the residual solder 11c and the bump 12b are fused is denoted by reference numeral 17 in FIGS. 9A and 9B.
  • FIG. 9B shows a form in which the arrangement of the second bump group 120 matches a part of the arrangement of the first bump group 110, and the arrangement of the first bump group 110 includes the arrangement of the second bump group 120. In this case, all of the second bump group 120 is bonded to a part of the residual solder 11c of the first bump group 110 remaining in the removal region 14.
  • FIG. 9C shows a form in which the arrangement of the first bump group 110 and the arrangement of the second bump group 120 do not all match, that is, all differ. Also in this case, all of the second bump group 120 is not bonded to the residual solder 11c of the first bump group 110, but is bonded to a land (not shown here) of the mounting substrate 10.
  • FIG. 9D is a diagram having the same purpose as FIG. 9C.
  • FIG. 10 shows a form in which the arrangement of the second bump group 120 is not included in the arrangement of the first bump group 110. That is, a part of the second bump group 120 overlaps with a part of the first bump group 110, but the other part does not overlap. In such a bump arrangement, mounting of the second element 12 results in an error. In this case, the non-overlapping bumps 12b of the second bump group 120 may not be joined to lands (not shown here) on the mounting substrate 10. This is because the overlapping second bump group 120 is joined to the residual solder at a position higher by the height of the residual solder of the first bump group 110.
  • the arrangement of the first bump group 110 completely matches the arrangement of the second bump group 120, or the arrangement of the first bump group 110 includes the arrangement of the second bump group 120. Occurrence of a connection failure when the element 12 is mounted can be prevented.
  • FIG. 11 is a cross-sectional view showing the mounting substrate 10 having the residual solder 11c. As described above, after removing the first element 11, a part of the solder of the bump 11 b remains on the land 16 on the mounting substrate 10.
  • 12A and 12B are cross-sectional views showing the first element 11 and the second element 12, respectively.
  • the bumps 12b of the second bump group 120 are designed so that the height (which may be a diameter or volume) is lower than the height of the bumps 11b of the first bump group 110.
  • 12A and 12B the diameter of the bump 11b of the first element 11 is X
  • the diameter of the bump 12b of the second element 12 is X- ⁇ .
  • the volume of the bump 12b is designed so that the sum of the volume of the residual solder 11c and the volume of the bump 12b of the second element 12 is substantially equal to the volume of the bump 11b of the first element 11. Specifically, in the manufacturing process of the second element 12, the diameter of the solder material forming the bump 12b is controlled using a mask (in this case, the height (thickness) is constant). The volume of the bump 12b can be controlled.
  • FIG. 13A and 13B show a mounting process (for example, a reflow process) when the height of the bump 11b of the first element 11 is the same as that of the second element 12.
  • FIG. 13B a difference occurs between the height of the main body 12a of the second element 12 after mounting (including the residual solder 11c) and the height of the main body 11a of the other first element 11.
  • the height of the bump 12b of the second element 12 when the height of the bump 12b of the second element 12 is set in advance lower than that of the first element 11, it becomes as shown in FIG. 14B. That is, the height of the bump 12b (including the residual solder 11c) after mounting the second element 12 is the same as the height of the bump 11b of the other first element 11. Thereby, the height of the main body 12a of the mounted second element 12 can be made the same as the height of the main body 11a of the first element 11. As a result, for example, the height of the entire surface of the elements 15 can be made uniform.
  • the design of the bumps 11b and 12b as shown in FIGS. 13A and 13B may be used.
  • the bumps 11b and 12b may be designed so as to make the second element 12 lower than the height of the main body 11a of the first element 11 in consideration of the amount of the residual solder 11c.
  • the height of the element 15 can be adjusted, and the process of removing the residual solder 11c can be omitted.
  • FIG. 15 shows a form in which the amount of the residual solder 11c on the land 16 is different in one removal region.
  • the second element 12 is mounted in an inclined state.
  • a second element 12 having a bump 12b having at least two different heights (which may be a diameter or a volume) is used.
  • the diameter of one bump 12b is X- ⁇
  • the diameter of the other bump 12b is X- ⁇ .
  • ⁇ ⁇ is joined to the residual solder 11c having a small residual amount
  • the bump 12b having the smaller diameter X- ⁇ is joined to the residual solder 11c having a large residual amount.
  • the second element 12 having at least two bumps 12b having different heights is mounted.
  • the main body 12 a is disposed so as to be inclined with respect to the mounting substrate 10.
  • the inclination angle of the main body 12a of the second element 12 after mounting can be controlled by controlling the diameter of the bump 12b of the second element 12 at the time of design. That is, the second element 12 that is inclined at an arbitrary angle with respect to the mounting substrate 10 can be realized by controlling only the diameter of the bump 12b.
  • first element 11 and the second element 12 have been described, but the same applies to three or more types of elements. That is, in addition to the second elements smaller than the number of the first elements 11, third elements smaller than the number of the first elements 11 may be mounted in the removed region where the first elements are removed.
  • this technique can also take the following structures.
  • a mounting board An array substrate comprising: two or more first elements; and a plurality of elements mounted to be arranged in an array structure on the mounting substrate, including one or more second elements different from the first elements .
  • Each of the plurality of elements has a main body and one or more bumps provided on the main body.
  • the array substrate according to (2) above, The length of one side of the main body of the second element is shorter than that of the first element.
  • the array substrate according to (2) or (3) The mounting substrate has lands to which bumps of the plurality of elements are connected, The difference between the length of one side of the main body of the second element and that of the first element is at least twice the sum of the radius of the land and the radius of the bump of the second element.
  • the array substrate according to any one of (2) to (4) The length of one side of the main body of the first element is 60 ⁇ m or more and 2000 ⁇ m or less, The length of one side of the main body of the second element is 50 ⁇ m or more and 1990 ⁇ m or less.
  • the array substrate according to any one of (2) to (8), The height of the bump of the second element is lower than the height of the bump of the first element.
  • the array substrate according to any one of (2) to (8), The bump of the second element has at least two different heights.
  • the second element mounted on a mounting substrate of an array substrate comprising a plurality of elements including two or more first elements and one or more second elements, The plurality of elements are arranged in an array structure on the mounting substrate, A main body configured such that the length of one side is shorter than the length of one side of the main body of the first element; A mounting element comprising one or more bumps provided on the main body.
  • the mounting element according to (11), The bump of the second element has at least two different heights.
  • a mounting board comprising: two or more first elements; and a plurality of elements mounted on the mounting substrate so as to be arranged in an array structure, including at least one second element different from the first element.
  • Device provided.
  • a plurality of first elements arranged in an array structure are transferred and mounted on a mounting substrate, Removing one or more first elements of the plurality of first elements from the mounting substrate;
  • the method of manufacturing an array substrate according to (14) Each of the plurality of elements has a main body and one or more bumps provided on the main body.
  • the mounting substrate has a land to which bumps of the plurality of elements are connected.
  • the method for manufacturing an array substrate according to (15) The height of the bump of the second element before mounting the second element is set so that the height of the main body of the first element from the mounting substrate is the same as that of the second element.
  • An array substrate manufacturing method configured to be lower than the bump height of the element.
  • the method for manufacturing an array substrate according to (15) When the lands remaining in one removal region have at least two different heights, the mounting substrate and the main body of the second element after mounting the second element are parallel to each other.
  • the method of manufacturing an array substrate, wherein the bumps of the second element before the two elements are mounted have at least two different heights.

Abstract

[Solution] An array substrate according to one embodiment of the present invention comprises a mounting substrate and a plurality of elements. The plurality of elements comprise two or more first elements and one or more second elements, which are different from the first element, and are mounted on the mounting substrate so as to be arranged in an array structure.

Description

アレイ基板、実装素子、アレイ基板を備えたデバイス、アレイ基板の製造方法Array substrate, mounting element, device including array substrate, and method of manufacturing array substrate
　本技術は、多数の素子（element）が実装されたアレイ基板等の技術に関する。 This technology relates to a technology such as an array substrate on which a large number of elements are mounted.
　特許文献１には、転写元基板から実装基板へＴＦＴチップを転写することによってＥＬ表示装置を製造する工程を含む実装方法が記載されている。例えば、接着剤で覆われたバンプを備える実装基板に転写元基板が対向させられる（図２（Ｅ）参照）。転写元基板に剥離層を介して付着したＴＥＴチップの接続端子がバンプに圧着される（図２（Ｆ）参照）。このとき、他のＴＦＴチップ（非転写のＴＦＴチップ）上に貼り付けられた離型部材も接着剤に付着する。光がマスクを介してＴＦＴチップに照射される（図２（Ｇ）参照）。これにより剥離層の剥離が誘起され、ＴＦＴチップが接着剤を介して実装基板に実装される（図２（Ｈ）参照）（例えば、特許文献１の明細書段落［００２４］、［００２５］参照。）。 Patent Document 1 describes a mounting method including a step of manufacturing an EL display device by transferring a TFT chip from a transfer source substrate to a mounting substrate. For example, the transfer source substrate is opposed to a mounting substrate including bumps covered with an adhesive (see FIG. 2E). The connection terminal of the TET chip attached to the transfer source substrate through the release layer is pressure-bonded to the bump (see FIG. 2F). At this time, a release member attached on another TFT chip (non-transfer TFT chip) also adheres to the adhesive. Light is irradiated to the TFT chip through the mask (see FIG. 2G). As a result, peeling of the peeling layer is induced, and the TFT chip is mounted on the mounting substrate via the adhesive (see FIG. 2H) (see, for example, paragraphs [0024] and [0025] of the specification of Patent Document 1). .)
特許第4244003号公報Japanese Patent No. 4424003
　しかしながら、特許文献１の方法は、転写用のチップの領域を避けて非転写用のチップの各領域に離型部材を形成する工程を含むので、必要な材料が増え、また工程が複雑になる。また、離型部材が実装基板上に残るので、引き続き、その残留箇所へのチップの実装が困難になる。 However, since the method of Patent Document 1 includes a step of forming a release member in each region of the non-transfer chip while avoiding the region of the transfer chip, the necessary materials increase and the process becomes complicated. . Further, since the release member remains on the mounting substrate, it becomes difficult to mount the chip on the remaining portion.
　本開示の目的は、複雑な工程を含まず、製造が容易なアレイ基板の製造方法を提供することにある。
　また、本開示の目的は、新規な構造を有するアレイ基板、実装素子、およびそのアレイ基板を備えたデバイスを提供することにある。 An object of the present disclosure is to provide a method of manufacturing an array substrate that does not include complicated processes and is easy to manufacture.
Another object of the present disclosure is to provide an array substrate having a novel structure, a mounting element, and a device including the array substrate.
　上記目的を達成するため、一形態に係るアレイ基板は、実装基板と、複数の素子とを具備する。
　前記複数の素子は、２以上の第１素子と、前記第１素子とは異なる１以上の第２素子とを含み、前記実装基板上にアレイ構造で配列されるように実装される。 In order to achieve the above object, an array substrate according to one embodiment includes a mounting substrate and a plurality of elements.
The plurality of elements include two or more first elements and one or more second elements different from the first elements, and are mounted so as to be arranged in an array structure on the mounting substrate.
　これにより、新規な構造を有するアレイ基板が実現される。 This realizes an array substrate having a novel structure.
　前記複数の素子は、それぞれ、本体と、前記本体に設けられた１以上のバンプとを有していてもよい。 Each of the plurality of elements may have a main body and one or more bumps provided on the main body.
　前記第２素子の本体の一辺の長さが、前記第１素子のそれより短くてもよい。
　これにより、特定または任意の第１素子の除去後、その除去領域への第２素子の実装が容易になる。 The length of one side of the main body of the second element may be shorter than that of the first element.
This facilitates the mounting of the second element in the removal region after removal of the specific or arbitrary first element.
　前記実装基板は、前記複数の素子のバンプが接続されるランドを有する。前記第２素子の本体の一辺の長さと、前記第１素子のそれとの差は、前記ランドの半径と前記第２素子のバンプの半径の和の２倍以上であってもよい。
　これにより、ランドとバンプとが接合された状態で、所期の位置から最大のずれが発生するように第２素子が実装されたとしても、第２素子とその隣の第１素子との接触を防止できる。 The mounting substrate has lands to which bumps of the plurality of elements are connected. The difference between the length of one side of the main body of the second element and that of the first element may be twice or more the sum of the radius of the land and the radius of the bump of the second element.
As a result, even if the second element is mounted so that the maximum deviation from the intended position occurs in a state where the land and the bump are joined, the contact between the second element and the first element adjacent thereto is made. Can be prevented.
　前記第１素子の本体の一辺の長さは、60μm以上2000μm以下であり、前記第２素子の本体の一辺の長さは、50μm以上1990μm以下であってもよい。 The length of one side of the main body of the first element may be not less than 60 μm and not more than 2000 μm, and the length of one side of the main body of the second element may be not less than 50 μm and not more than 1990 μm.
　前記第１素子は第１バンプ群を有していてもよい。前記第２素子は、前記第１バンプ群の配列と一致する配列を持つ第２バンプ群を有していてもよい。
　あるいは、前記第２素子は、前記第１バンプ群の配列の一部と一致する配列を持つ第２バンプ群を有する場合、前記第１バンプ群の配列が、前記第２バンプ群の配列を包含していてもよい。
　あるいは、前記第１素子は第１バンプ群を有し、前記第２素子は、前記第１バンプ群の配列の全部と異なる配列を持つ第２バンプ群を有していてもよい。
　これらの技術により、特定または任意の第１素子の除去後、その除去領域に第２素子が実装されるときの接続不具合の発生を防止できる。 The first element may have a first bump group. The second element may include a second bump group having an arrangement that matches the arrangement of the first bump group.
Alternatively, when the second element has a second bump group having an arrangement that coincides with a part of the arrangement of the first bump group, the arrangement of the first bump group includes the arrangement of the second bump group. You may do it.
Alternatively, the first element may include a first bump group, and the second element may include a second bump group having an arrangement different from the entire arrangement of the first bump group.
By these techniques, it is possible to prevent the occurrence of a connection failure when the second element is mounted in the removal region after the specific or arbitrary first element is removed.
　前記第２素子のバンプの高さは、前記第１素子のバンプの高さより低くてもよい。 The bump height of the second element may be lower than the bump height of the first element.
　前記第２素子のバンプは、少なくとも２つの異なる高さを持っていてもよい。 The bumps of the second element may have at least two different heights.
　一形態に係る実装素子は、２以上の第１素子および１以上の第２素子を含む複数の素子を備えるアレイ基板の実装基板に実装された前記第２素子である。前記複数の素子が前記実装基板上にアレイ構造で配列される。
　前記実装素子は、一辺の長さが、前記第１素子の本体の一辺の長さより短くなるように構成された本体と、前記本体に設けられた１以上のバンプとを具備する。 The mounting element which concerns on one form is the said 2nd element mounted in the mounting board | substrate of the array board | substrate provided with the several element containing 2 or more 1st elements and 1 or more 2nd elements. The plurality of elements are arranged in an array structure on the mounting substrate.
The mounting element includes a main body configured such that the length of one side is shorter than the length of one side of the main body of the first element, and one or more bumps provided on the main body.
　一形態に係るデバイスは、上記アレイ基板を備える。 A device according to one aspect includes the array substrate.
　一形態に係るアレイ基板の製造方法は、アレイ構造で配列された複数の第１素子を実装基板上に転写して実装することを含む。
　複数の第１素子のうち１以上の第１素子が、前記実装基板から除去される。
　前記実装基板上の、前記第１素子が除去された除去領域に、前記第１素子とは異なる１以上の第２素子が実装される。 A method for manufacturing an array substrate according to one aspect includes transferring and mounting a plurality of first elements arranged in an array structure on a mounting substrate.
One or more first elements of the plurality of first elements are removed from the mounting substrate.
One or more second elements different from the first element are mounted in the removal region on the mounting substrate where the first element is removed.
　この製造方法は、複数の第１素子を転写により実装基板に実装し、第１素子が除去された除去領域に第２素子を実装するので、複雑な工程を含まず、第１素子および第２素子を含むアレイ基板を容易に製造することができる。 In this manufacturing method, the plurality of first elements are mounted on the mounting substrate by transfer, and the second element is mounted in the removal region from which the first element has been removed. An array substrate including elements can be easily manufactured.
　前記複数の素子は、それぞれ、本体と、前記本体に設けられた１以上のバンプとを有していてもよい。前記実装基板は、前記複数の素子のバンプが接続されるランドを有していてもよい。 Each of the plurality of elements may have a main body and one or more bumps provided on the main body. The mounting board may have lands to which bumps of the plurality of elements are connected.
　前記実装基板からの前記第１素子の本体の高さと、前記第２素子のそれとが同じになるように、前記第２素子の実装前の当該第２素子のバンプの高さが、前記第１素子のバンプの高さより低く構成されていてもよい。 The height of the bump of the second element before mounting the second element is set so that the height of the main body of the first element from the mounting substrate is the same as that of the second element. You may be comprised lower than the height of the bump of an element.
　１つの前記除去領域に残るそれらランドが、少なくとも２つの異なる高さを持つ場合、次のように第２素子が構成されていてもよい。すなわち、前記第２素子の実装後の、前記実装基板と当該第２素子の本体とが平行になるように、前記第２素子の実装前の当該第２素子のそれらバンプが少なくとも異なる２つの高さを持っていてもよい。 When the lands remaining in one removal area have at least two different heights, the second element may be configured as follows. That is, after mounting the second element, the bumps of the second element before mounting the second element are at least two different heights so that the mounting substrate and the main body of the second element are parallel to each other. You may have.
　前記第２素子の実装後の、前記実装基板に対して前記第２素子の本体が傾斜するように前記第２素子が前記実装基板上に配置されていてもよい。 The second element may be arranged on the mounting substrate so that a main body of the second element is inclined with respect to the mounting substrate after mounting the second element.
　前記第２素子のそれらバンプは、少なくとも２つの異なる高さを持っていてもよい。 The bumps of the second element may have at least two different heights.
　以上、本技術によれば、複雑な工程を含まず、製造が容易なアレイ基板を提供することができる。 As described above, according to the present technology, it is possible to provide an array substrate that does not include a complicated process and is easy to manufacture.
　なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。 It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
図１は、本技術の一実施形態に係るアレイ基板を示す図である。FIG. 1 is a diagram illustrating an array substrate according to an embodiment of the present technology. 図２Ａ～Ｅは、アレイ基板を製造する方法を示した図である。2A to 2E are views showing a method of manufacturing an array substrate. 図３は、製造されたアレイ基板が、破線で示す位置でカットされて分割され、複数のアレイ基板が形成される様子を示す。FIG. 3 shows a state where the manufactured array substrate is cut and divided at a position indicated by a broken line to form a plurality of array substrates. 図４は、アレイ基板を利用したデバイスを示す図である。FIG. 4 is a diagram showing a device using an array substrate. 図５は、第１素子１および第２素子のサイズを示すための図である。FIG. 5 is a diagram for illustrating the sizes of the first element 1 and the second element. 図６Ａ～Ｃは、図２Ｃ～Ｅで示したアレイ基板の製造工程を断面で示す。6A to 6C are sectional views showing manufacturing steps of the array substrate shown in FIGS. 2C to 2E. 図７は、第１素子および第２素子のサイズが同じ場合の実装例を示す。FIG. 7 shows a mounting example when the sizes of the first element and the second element are the same. 図８は、第２素子のずれ量を説明するための図であり、図６Ｃにおいて一点鎖線で囲まれる部分を拡大して示す図である。FIG. 8 is a diagram for explaining the shift amount of the second element, and is an enlarged view of a portion surrounded by a one-dot chain line in FIG. 6C. 図９Ａ～Ｄは、素子のバンプ群の配列の各種の形態をそれぞれ示した図である。9A to 9D are diagrams showing various forms of the arrangement of the bump groups of the element. 図１０は、第１バンプ群の配列内に第２バンプ群の配列が包含されない形態を示す。FIG. 10 shows a form in which the arrangement of the second bump group is not included in the arrangement of the first bump group. 図１１は、第１バンプ群の残留はんだを有する実装基板を示す断面図である。FIG. 11 is a cross-sectional view showing a mounting substrate having residual solder of the first bump group. 図１２Ａ、Ｂは、バンプの高さを説明するための、第１素子、第２素子をそれぞれ示す断面図である。12A and 12B are cross-sectional views showing a first element and a second element for explaining the height of the bump, respectively. 図１３Ａ、Ｂは、第１素子のバンプの高さと、第２素子のそれとが同じである場合の実装工程を示す。13A and 13B show a mounting process in the case where the bump height of the first element is the same as that of the second element. 図１４Ａ、Ｂは、第１素子のバンプの高さと、第２素子のそれとが異なる場合の実装工程を示す。14A and 14B show a mounting process in the case where the bump height of the first element is different from that of the second element. 図１５は、１つの除去領域において、ランド上の残留はんだの量がそれぞれ異なる場合を示す。FIG. 15 shows a case where the amount of residual solder on the land is different in one removal region. 図１６は、１つの除去領域において、ランド上の残留はんだの量がそれぞれ異なる場合に、第２素子のバンプの径が異なる形態を示す。FIG. 16 shows a form in which the bump diameter of the second element is different when the amount of residual solder on the land is different in one removal region. 図１７は、１つの除去領域において、ランド上の残留はんだの量が同じである場合に、第２素子のバンプの径が異なる形態を示す。FIG. 17 shows a form in which the bump diameter of the second element is different when the amount of residual solder on the land is the same in one removal region.
　以下、本技術に係る実施形態を、図面を参照しながら説明する。 Hereinafter, embodiments of the present technology will be described with reference to the drawings.
　１．アレイ基板 1. Array substrate
　図１は、本技術の一実施形態に係るアレイ基板５０を示す図である。アレイ基板５０は、実装基板１０と、実装基板１０上に複数の素子（element）１５とを含む。複数の素子１５は、実装基板１０上にアレイ構造で配列されるように実装されている。複数の素子１５は、２以上（複数）の第１素子１１と、第１素子１１とは異なる１以上の第２素子１２（実装素子）とを含む。本実施形態では、２以上の第２素子１２が設けられている。 FIG. 1 is a diagram illustrating an array substrate 50 according to an embodiment of the present technology. The array substrate 50 includes a mounting substrate 10 and a plurality of elements 15 on the mounting substrate 10. The plurality of elements 15 are mounted on the mounting substrate 10 so as to be arranged in an array structure. The plurality of elements 15 include two or more (plural) first elements 11 and one or more second elements 12 (mounting elements) different from the first elements 11. In the present embodiment, two or more second elements 12 are provided.
　例えば、１素子１１は受光素子であり、第２素子１２は発光素子である。第１素子１１が第２素子１２より十分に多い場合、このアレイ基板５０は例えば撮像デバイスとして利用される。第１素子１１が発光素子で、第２素子１２が受光素子である場合、アレイ基板５０は例えば表示デバイスとして利用される。受光素子としては、例えばフォトダイオードが挙げられる。発光素子としては、例えばＬＥＤ（Light Emitting Diode）、ＬＤ（Laser Diode）、有機ＥＬ（Electro-Luminescence）等が挙げられる。 For example, one element 11 is a light receiving element, and the second element 12 is a light emitting element. When the first element 11 is sufficiently larger than the second element 12, the array substrate 50 is used as an imaging device, for example. When the first element 11 is a light emitting element and the second element 12 is a light receiving element, the array substrate 50 is used as a display device, for example. An example of the light receiving element is a photodiode. Examples of the light emitting element include LED (Light Emitting Diode), LD (Laser Diode), and organic EL (Electro-Luminescence).
　アレイ構造の配列とは、典型的には直交２軸（x-y軸）に沿ったマトリクス状の配列である。アレイ構造は、このマトリクス状配列の他、千鳥状配列、２次元内での直線または曲線に沿った配列など、規則性あるいは幾何学的な特性を持った配列による構造を含む。 An array structure array is typically a matrix array along two orthogonal axes (xy axes). The array structure includes, in addition to this matrix-like arrangement, a staggered arrangement, an arrangement along a straight line or a curve in two dimensions, and an arrangement having an arrangement having regularity or geometric characteristics.
　第１素子１１の数に比べ、第２素子１２の数が少ない。このアレイ基板５０を利用したデバイスの種類にもよるが、第１素子１１の数に対する第２素子１２の数の割合は、1ppm～30%であり、より現実には0.01%～15%である。 The number of second elements 12 is smaller than the number of first elements 11. Depending on the type of device using the array substrate 50, the ratio of the number of the second elements 12 to the number of the first elements 11 is 1 ppm to 30%, and more practically 0.01% to 15%. .
　アレイ基板５０上の所定の領域に、複数の第２素子１２が隣接して連続して配置されていてもよい。 The plurality of second elements 12 may be arranged adjacently and continuously in a predetermined region on the array substrate 50.
　２．アレイ基板の製造方法 2. Method for manufacturing array substrate
　図２Ａ～Ｅは、アレイ基板５０を製造する方法を示した図である。例えば、図２Ａでは、複数の第１素子１１が形成された半導体ウェハ等の転写元基板６０が用意される。図２Ｂに示すように、未実装の転写先基板である実装基板１０が用意される。 2A to 2E are diagrams showing a method of manufacturing the array substrate 50. FIG. For example, in FIG. 2A, a transfer source substrate 60 such as a semiconductor wafer on which a plurality of first elements 11 are formed is prepared. As shown in FIG. 2B, a mounting substrate 10 which is an unmounted transfer destination substrate is prepared.
　転写元基板６０には、実装基板１０上の実装ピッチと実質的に同一のピッチ、またはそれに適したピッチで、アレイ構造で第１素子１１が形成されている。第１素子１１が実装基板１０上ではんだ接合が可能なように、実装基板１０上には、第１素子１１の各実装領域（破線で示す）に電気的接続用のＵＢＭ（Under Bump Metallization）として構成されるランド（ここでは図示せず）がそれぞれ形成されている。第１素子１１には、それらランドには対応するはんだバンプ（ここでは図示せず）が形成されている。以下、はんだバンプを単に「バンプ」という。 On the transfer source substrate 60, the first elements 11 are formed in an array structure at a pitch substantially the same as the mounting pitch on the mounting substrate 10 or a suitable pitch. A UBM (UnderＵBump Metalization) for electrical connection is provided on each mounting region (indicated by a broken line) of the first element 11 on the mounting board 10 so that the first element 11 can be soldered on the mounting board 10. Lands (not shown here) configured as are formed respectively. Corresponding solder bumps (not shown here) are formed on the lands of the first element 11. Hereinafter, the solder bump is simply referred to as “bump”.
　図２Ｃに示すように、転写元基板６０から、実装基板１０へ第１素子１１が転写される。実装基板１０には、所定の実装領域の全面に、一括でそれら第１素子１１が転写される。この転写方法としては、例えば転写元基板６０と実装基板１０とを位置合わせし、重ね合わせ、そして、リフローなどの熱処理により、第１素子１１を実装基板１０上に実装する（第１素子１１のバンプがランドに接合する）。 As shown in FIG. 2C, the first element 11 is transferred from the transfer source substrate 60 to the mounting substrate 10. The first elements 11 are collectively transferred to the mounting substrate 10 over the entire surface of a predetermined mounting area. As this transfer method, for example, the transfer source substrate 60 and the mounting substrate 10 are aligned, superposed, and the first element 11 is mounted on the mounting substrate 10 by heat treatment such as reflow (of the first element 11). Bump joins to land).
　図２Ｄに示すように、実装基板１０上の所定の位置に配置された１以上の第１素子１１が実装基板１０から除去される。本実施形態では、複数の第１素子１１が除去される。その除去方法としては、例えば特開2001-007508号、2010-36232号、2004-260053号、2013-21325号等の公報に記載された公知の方法が挙げられる。 As shown in FIG. 2D, one or more first elements 11 arranged at predetermined positions on the mounting substrate 10 are removed from the mounting substrate 10. In the present embodiment, the plurality of first elements 11 are removed. Examples of the removal method include known methods described in JP 2001-007508, 2010-36232, 2004-260053, 2013-21325, and the like.
　そして、図２Ｅに示すように、実装基板１０上の、第１素子１１が除去された後の領域である除去領域１４に、１以上の第２素子１２が実装される。本実施形態では、複数の除去領域１４に複数の第２素子１２がそれぞれ実装される。これにより、アレイ基板５０が完成する。 Then, as shown in FIG. 2E, one or more second elements 12 are mounted on the removal region 14 on the mounting substrate 10 after the first element 11 is removed. In the present embodiment, the plurality of second elements 12 are mounted in the plurality of removal regions 14, respectively. Thereby, the array substrate 50 is completed.
　第２素子１２の実装方法として、例えばレーザーアブレーションによる転写を用いてもよいし、あるいは、部品実装機を用いてもよい。 As a mounting method of the second element 12, for example, transfer by laser ablation may be used, or a component mounting machine may be used.
　図３は、上記のように製造されたアレイ基板５０が、破線で示す位置でカットされて分割され、複数のアレイ基板５０'が形成される様子を示す。この図では、４分割とされているが、５分割以上であってもよい。これにより、１つのアレイ基板５０から複数のアレイ基板５０'が形成される。 FIG. 3 shows a state where the array substrate 50 manufactured as described above is cut and divided at a position indicated by a broken line to form a plurality of array substrates 50 ′. In this figure, it is divided into four, but it may be divided into five or more. Thereby, a plurality of array substrates 50 ′ are formed from one array substrate 50.
　以上のように、本実施形態に係る製造方法は、複数の第１素子１１を転写により一斉に実装基板１０に実装し、第１素子１１が除去された除去領域１４に第２素子１２を実装する工程を有する。これにより、本製造方法は、複雑な工程を含まず、第１素子１１および第２素子１２を含むアレイ基板５０を容易に製造することができる。また、本製造方法によれば、特許文献１の方法に比べ必要な材料も減らすことができるので、コストの削減を実現できる。また、完成したアレイ基板５０上に、離型部材等の余計な材料も残らない。 As described above, in the manufacturing method according to the present embodiment, the plurality of first elements 11 are mounted on the mounting substrate 10 simultaneously by transfer, and the second elements 12 are mounted in the removal region 14 where the first elements 11 are removed. The process of carrying out. Thereby, this manufacturing method does not include a complicated process, and can easily manufacture the array substrate 50 including the first element 11 and the second element 12. Moreover, according to this manufacturing method, since a required material can also be reduced compared with the method of patent document 1, cost reduction is realizable. Further, no extra material such as a release member is left on the completed array substrate 50.
　第２素子１２として、第１素子１１と同じ機能を有するリペア素子を使用してもよい。すなわち、複数の第１素子１１のうち、特定の第１素子１１に不具合があった場合、その不具合がある第１素子１１に代えて、リペア素子が第２素子１２として実装される。すなわち、第１素子１１の除去とリペア工程を兼ねることができ、リペア工程を含むアレイ基板５０の製造工程数を削減し、高い歩留りでアレイ基板５０の製造を実現することができる。 As the second element 12, a repair element having the same function as the first element 11 may be used. That is, when a specific first element 11 is defective among the plurality of first elements 11, a repair element is mounted as the second element 12 instead of the first element 11 having the defect. That is, the removal of the first element 11 and the repair process can be performed, the number of manufacturing processes of the array substrate 50 including the repair process can be reduced, and the manufacture of the array substrate 50 can be realized with a high yield.
　後述するように、例えばリペア素子のサイズ（本体の一辺の長さ）が第１素子１１のそれとは異なるように、リペア素子が構成されることが好ましい。 As described later, it is preferable that the repair element is configured so that the size of the repair element (the length of one side of the main body) is different from that of the first element 11, for example.
　図４は、このアレイ基板５０を利用したデバイスを示す図である。このデバイス１００において、アレイ基板５０の２辺には、フレキシブル配線板１３が接続されている。なお、この図で示した素子１５の数は、図３で示したアレイ基板５０上の素子１５の数とは異なる。図１～４では、説明を理解しやすくするため、素子数を少なく描いたが、実際の素子数は、数千～数万、あるいはさらに多い場合もある。 FIG. 4 is a diagram showing a device using the array substrate 50. As shown in FIG. In this device 100, the flexible wiring board 13 is connected to two sides of the array substrate 50. The number of elements 15 shown in this figure is different from the number of elements 15 on the array substrate 50 shown in FIG. In FIGS. 1 to 4, the number of elements is illustrated to be easy to understand, but the actual number of elements may be several thousand to several tens of thousands or even larger.
　アレイ基板５０を利用したデバイスとしては、本実施形態のような受発光デバイスの他、次のようなデバイスが挙げられる。例えば、ミラーアレイデバイス、ＭＥＭＳ（Micro Electro Mechanical Systems）デバイス、他のセンサアレイデバイス、または、これらのうち少なくとも２つの組み合わせでなるデバイスである。本製造方法を用いることにより、センサアレイデバイス等、多数、複数種類の素子を実装するデバイスの大幅な工程数を削減でき、特定の特徴を有するデバイスの製造が容易になる。 Examples of devices using the array substrate 50 include the following devices in addition to the light emitting and receiving devices as in the present embodiment. For example, a mirror array device, a MEMS (Micro Electro Mechanical Systems) device, another sensor array device, or a device composed of a combination of at least two of them. By using this manufacturing method, it is possible to significantly reduce the number of steps of a device on which a large number of types of elements such as sensor array devices are mounted, and it becomes easy to manufacture a device having specific characteristics.
　３．個々の素子の形態について 3. About the form of individual elements
　３．１）素子のサイズについて 3.1) Element size
　図５は、第１素子１１および第２素子１２のサイズを示すための図である。第１素子１１は、本体１１ａと、本体１１ａに設けられたバンプ１１ｂ（複数）とを有する。第２素子１２も同様に、本体１２ａと、バンプ１２ｂ（複数）とを有する。本体１１ａ、１２ａは、矩形状を有する。第２素子１２の本体１２ａの一辺の長さは、第１素子１１のそれより短い。この場合、第２素子１２の機能上、悪影響がない程度に、その一辺の長さが設定される。 FIG. 5 is a diagram for showing the sizes of the first element 11 and the second element 12. The first element 11 includes a main body 11a and bumps 11b (plural) provided on the main body 11a. Similarly, the second element 12 includes a main body 12a and bumps 12b (plural). The main bodies 11a and 12a have a rectangular shape. The length of one side of the main body 12 a of the second element 12 is shorter than that of the first element 11. In this case, the length of one side is set to the extent that there is no adverse effect on the function of the second element 12.
　素子１５の本体１１ａ、１２ａの一辺のサイズは、50μm以上2000μm以下、より狭い範囲として90μm以上400μm以下である。第１素子１１の本体１１ａの一辺の長さは、60μm以上2000μm以下であり、より狭い範囲として70μm以上1500μm以下、さらに狭い範囲として80μm以上1000μm以下である。一方、第２素子１２の本体１２ａの一辺の長さは、50μm以上1990μm以下であり、より狭い範囲として、50μm以上1490μm以下、さらに狭い範囲として60μm以上600μm以下である。 The size of one side of the main body 11a, 12a of the element 15 is not less than 50 μm and not more than 2000 μm, and a narrower range is not less than 90 μm and not more than 400 μm. The length of one side of the main body 11a of the first element 11 is 60 μm or more and 2000 μm or less, 70 μm or more and 1500 μm or less as a narrower range, and 80 μm or more and 1000 μm or less as a narrower range. On the other hand, the length of one side of the main body 12a of the second element 12 is 50 μm or more and 1990 μm or less, a narrower range is 50 μm or more and 1490 μm or less, and a narrower range is 60 μm or more and 600 μm or less.
　しかし、第２素子１２のバンプ１２ｂの配列ピッチは、第１素子１１のそれと同じである。これにより、実装基板１０の除去領域１４（図２Ｄ参照）上にあるランド（１つの除去領域１４にある複数のランド１６とその上の残留はんだ１１ｃ）に、第２素子１２の各バンプ１２ｂがそれぞれ接続されるように、第２素子１２を実装基板１０に実装することができる。 However, the arrangement pitch of the bumps 12b of the second element 12 is the same as that of the first element 11. Thereby, each bump 12b of the second element 12 is formed on the land (the plurality of lands 16 in one removal region 14 and the residual solder 11c thereon) on the removal region 14 (see FIG. 2D) of the mounting substrate 10. The second elements 12 can be mounted on the mounting substrate 10 so as to be connected to each other.
　１つの素子１５が持つバンプの数は、数個～数十個であり、素子サイズによる。バンプ１１ａ、１２ｂの径は、15μm以上40μm以下、より狭くは20μm以上30μm以下である。 The number of bumps that one element 15 has is several to several tens, depending on the element size. The diameters of the bumps 11a and 12b are 15 μm or more and 40 μm or less, and more narrowly 20 μm or more and 30 μm or less.
　以下、第２素子１２のサイズが第１素子１１より小さい場合のメリットを説明する。図６Ａ～Ｃは、図２Ｃ～Ｅで示したアレイ基板５０の製造工程を断面で示す。 Hereinafter, the merit when the size of the second element 12 is smaller than the first element 11 will be described. 6A to 6C are sectional views showing the manufacturing process of the array substrate 50 shown in FIGS. 2C to 2E.
　図６Ａに示すように、実装基板１０の各ランド１６に第１素子１１のバンプ１１ｂが接合されることにより、第１素子１１が実装基板１０に実装される。 As shown in FIG. 6A, the bumps 11b of the first element 11 are bonded to the lands 16 of the mounting board 10, whereby the first element 11 is mounted on the mounting board 10.
　図６Ｂに示すように、いくつかの第１素子１１が除去される。第１素子１１が除去されると、除去領域１４には、第１素子１１のバンプ１１ｂの残留はんだ１１ｃが形成される。 As shown in FIG. 6B, some first elements 11 are removed. When the first element 11 is removed, residual solder 11c of the bumps 11b of the first element 11 is formed in the removal region 14.
　図６Ｃに示すように、その除去領域１４に第２素子１２が実装される時、例えば第２素子１２のバンプ１２ｂがランド１６に接合はされるが、ずれて実装される場合がある。このように第２素子１２が所期の位置からずれて実装されても、その本体１２ａの一辺の長さが短いため、第２素子１２はその隣の第１素子１１に接触しないというメリットがある（実装が容易になる）。特に、素子１５が高密度で配置される場合にそのメリットは大きい。 As shown in FIG. 6C, when the second element 12 is mounted in the removal region 14, for example, the bump 12b of the second element 12 is bonded to the land 16, but may be mounted in a shifted manner. Thus, even when the second element 12 is mounted out of the intended position, the length of one side of the main body 12a is short, so that the second element 12 does not contact the adjacent first element 11. Yes (easy to implement) In particular, when the elements 15 are arranged at a high density, the merit is great.
　これに対し、図７に示すように、素子１１２の本体１１２ａ一辺の長さが第１素子１１のそれと同じである場合、本体１１ａ、１１２ａ同士が接触するおそれがある。 On the other hand, as shown in FIG. 7, when the length of one side of the main body 112a of the element 112 is the same as that of the first element 11, the main bodies 11a and 112a may come into contact with each other.
　図８は、第２素子１２のずれ量を説明するための図であり、図６Ｃにおいて一点鎖線で囲まれる部分を拡大して示す図である。除去領域１４には元々第１素子１１が実装されていたので、この除去領域１４における、両隣の第１素子１１間の距離（図６Ｂにおける距離ａ）は、第１素子１１の本体１１ａの一辺の長さよりわずかに大きく設定されている。第２素子１２が第１素子１１より小さいので、正確に所期の位置に第２素子が実装されれば、第２素子１２がこの除去領域１４内に第２素子１２が収められるということは、言うまでもない。 FIG. 8 is a diagram for explaining the shift amount of the second element 12, and is an enlarged view of a portion surrounded by a one-dot chain line in FIG. 6C. Since the first element 11 was originally mounted in the removal region 14, the distance between the adjacent first elements 11 (distance a in FIG. 6B) in this removal region 14 is one side of the main body 11 a of the first element 11. It is set slightly larger than the length. Since the second element 12 is smaller than the first element 11, if the second element is mounted at an exact position, the second element 12 can be accommodated in the removal region 14. Needless to say.
　隣り合う本体１１ａの間の間隔ｄは、例えば10μm以上30μm以下であり、より狭くは、10μm以上20μm以下、15μm以上25μm以下、または、15μm以上20μm以下である。 The distance d between the adjacent main bodies 11a is, for example, 10 μm or more and 30 μm or less, and more narrowly 10 μm or more and 20 μm or less, 15 μm or more and 25 μm or less, or 15 μm or more and 20 μm or less.
　第２素子１２の本体１２ａの一辺の長さと、第１素子１１のそれとの差は、ランド１６（残留はんだ１１ｃ）の半径とバンプ１２ｂの半径の和ｂの２倍以上に設定されることが望ましい。ランド１６とバンプ１２ｂの半径は実質同じである。このような条件によれば、ランド１６とバンプ１２ｂが接合される（電気的接続が可能な）状態で、第２素子１２がたとえ所期の位置からずれて配置されても、本体１１ａ、１２ａ同士の接触は起こらない。その条件のうち「２倍」というのは、ランド１６の位置を基準として、第２素子１２が、図８中、左右のどちらにずれてもよい、という趣旨である。 The difference between the length of one side of the main body 12a of the second element 12 and that of the first element 11 may be set to be twice or more the sum b of the radius of the land 16 (residual solder 11c) and the radius of the bump 12b. desirable. The radii of the land 16 and the bump 12b are substantially the same. According to such conditions, even if the second element 12 is arranged with a deviation from the intended position in a state where the land 16 and the bump 12b are joined (electrical connection is possible), the main bodies 11a and 12a There is no contact between them. Among the conditions, “double” means that the second element 12 may be shifted to the left or right in FIG. 8 with respect to the position of the land 16.
　以上のように、ランド１６とバンプ１２ｂとが接合された状態で、所期の位置から最大のずれが発生するように第２素子１２が実装されたとしても、第２素子１２とその隣の第１素子１１との接触を防止できる。 As described above, even if the second element 12 is mounted so that the maximum deviation from the intended position occurs in a state where the land 16 and the bump 12b are bonded, the second element 12 and the adjacent element Contact with the first element 11 can be prevented.
　以上では、第２素子１２のサイズが第１素子１１より小さい形態について示したが、第１素子のサイズが第２素子のサイズより小さくてもよい。 In the above description, the size of the second element 12 is smaller than that of the first element 11, but the size of the first element may be smaller than the size of the second element.
　３．２）素子のバンプの配列について 3.2) About the bump arrangement of the element
　図９Ａ～Ｄは、素子１５のバンプ（バンプ群）の配列の各種の形態をそれぞれ示した図である。最上段の図は、第１素子１１のバンプ（第１バンプ群１１０）の配列形態をそれぞれ示す。上からの２段目の図は、第２素子１２のバンプ（第２バンプ群１２０）の配列形態をそれぞれ示す。上から３段目の図は、第１素子１１が除去され、除去領域１４（図６Ｂ参照）に第１バンプ群１１０のはんだの一部がそれぞれ残留した状態で、第２素子１２が実装基板１０に実装された時の平面図である。最下段の図は、３段目の破線における断面を示す。なお、図９Ｄでは、第１素子１１のサイズが第２素子１２のサイズより小さい形態を示している。 FIGS. 9A to 9D are diagrams respectively showing various forms of the arrangement of bumps (bump groups) of the element 15. The uppermost drawing shows the arrangement form of the bumps (first bump group 110) of the first element 11 respectively. The second drawing from the top shows the arrangement of the bumps (second bump group 120) of the second element 12, respectively. In the third drawing from the top, the first element 11 is removed, and a part of the solder of the first bump group 110 remains in the removal region 14 (see FIG. 6B), and the second element 12 is mounted on the mounting board. FIG. The lowermost figure shows a cross section taken along the broken line in the third stage. FIG. 9D shows a form in which the size of the first element 11 is smaller than the size of the second element 12.
　図９Ａは、第１バンプ群１１０の配列が第２バンプ群１２０の配列と全部一致する形態を示す。この場合、実装基板１０の除去領域１４に第２素子１２が実装されると、除去領域１４に残留する第１バンプ群１１０の残留はんだ１１ｃ（図６Ｂ参照）と、第２素子１２のバンプ１２ｂとのすべてが接合される。 FIG. 9A shows a form in which the arrangement of the first bump group 110 is completely the same as the arrangement of the second bump group 120. In this case, when the second element 12 is mounted on the removal region 14 of the mounting substrate 10, the residual solder 11 c (see FIG. 6B) of the first bump group 110 remaining in the removal region 14 and the bump 12 b of the second element 12. And everything is joined.
　残留はんだ１１ｃとバンプ１２ｂとが融合した状態の電極として、図９Ａ、Ｂにおいて符号１７で示す。 An electrode in a state where the residual solder 11c and the bump 12b are fused is denoted by reference numeral 17 in FIGS. 9A and 9B.
　図９Ｂは、第２バンプ群１２０の配列が第１バンプ群１１０の配列の一部と一致し、第１バンプ群１１０の配列が、第２バンプ群１２０の配列を包含する形態を示す。この場合、第２バンプ群１２０のすべてが、除去領域１４に残留する第１バンプ群１１０の一部の残留はんだ１１ｃに接合される。 FIG. 9B shows a form in which the arrangement of the second bump group 120 matches a part of the arrangement of the first bump group 110, and the arrangement of the first bump group 110 includes the arrangement of the second bump group 120. In this case, all of the second bump group 120 is bonded to a part of the residual solder 11c of the first bump group 110 remaining in the removal region 14.
　図９Ｃは、第１バンプ群１１０の配列と、第２バンプ群１２０の配列が全部一致しない、すなわち全部異なる形態を示す。この場合も、第２バンプ群１２０のすべてが、第１バンプ群１１０の残留はんだ１１ｃには接合されず、実装基板１０のランド（ここでは図示しない）上に接合される。 FIG. 9C shows a form in which the arrangement of the first bump group 110 and the arrangement of the second bump group 120 do not all match, that is, all differ. Also in this case, all of the second bump group 120 is not bonded to the residual solder 11c of the first bump group 110, but is bonded to a land (not shown here) of the mounting substrate 10.
　図９Ｄは、図９Ｃと同様の趣旨の図である。 FIG. 9D is a diagram having the same purpose as FIG. 9C.
　以上のように、図９Ａ～Ｄで示す素子１５のバンプ配列によれば、除去領域１４の、ランド１６上または第１バンプ群１１０の残留はんだ１１ｃ上に、第２素子１２の全部のバンプ１２ｂが接合される。 As described above, according to the bump arrangement of the element 15 shown in FIGS. 9A to 9D, all the bumps 12b of the second element 12 are formed on the land 16 or the residual solder 11c of the first bump group 110 in the removal region 14. Are joined.
　図１０は、第１バンプ群１１０の配列内に第２バンプ群１２０の配列が包含されない形態を示す。すなわち、第２バンプ群１２０の一部は第１バンプ群１１０の一部と重複するが、他部は重複しない。このようなバンプの配列形態では、第２素子１２の実装はエラーとなる。この場合、第２バンプ群１２０の重複しないバンプ１２ｂが、実装基板１０上のランド（ここでは図示しない）と接合されない場合がある。これは、重複する第２バンプ群１２０は、第１バンプ群１１０の残留はんだの高さ分高い位置で、これら残留はんだに接合されるからである。 FIG. 10 shows a form in which the arrangement of the second bump group 120 is not included in the arrangement of the first bump group 110. That is, a part of the second bump group 120 overlaps with a part of the first bump group 110, but the other part does not overlap. In such a bump arrangement, mounting of the second element 12 results in an error. In this case, the non-overlapping bumps 12b of the second bump group 120 may not be joined to lands (not shown here) on the mounting substrate 10. This is because the overlapping second bump group 120 is joined to the residual solder at a position higher by the height of the residual solder of the first bump group 110.
　以上のように、第１バンプ群１１０の配列が第２バンプ群１２０の配列と全部一致する、または、第１バンプ群１１０の配列が第２バンプ群１２０の配列を包含することにより、第２素子１２が実装されるときの接続不具合の発生を防止できる。 As described above, the arrangement of the first bump group 110 completely matches the arrangement of the second bump group 120, or the arrangement of the first bump group 110 includes the arrangement of the second bump group 120. Occurrence of a connection failure when the element 12 is mounted can be prevented.
　３．３）素子のバンプの高さについて 3.3) About bump height of element
　３．３．１）例１ 3.3.1) Example 1
　図１１は、残留はんだ１１ｃを有する実装基板１０を示す断面図である。上述したように、第１素子１１の除去後、実装基板１０上のランド１６上には、バンプ１１ｂの一部のはんだが残る。 FIG. 11 is a cross-sectional view showing the mounting substrate 10 having the residual solder 11c. As described above, after removing the first element 11, a part of the solder of the bump 11 b remains on the land 16 on the mounting substrate 10.
　図１２Ａ、Ｂは、第１素子１１、第２素子１２をそれぞれ示す断面図である。第２バンプ群１２０のバンプ１２ｂの高さ（径、または体積でもよい）が、第１バンプ群１１０のバンプ１１ｂの高さより低くなるように設計される。なお、図１２Ａ、Ｂでは、第１素子１１のバンプ１１ｂの径がＸであり、第２素子１２のバンプ１２ｂの径がＸ-αとされている。 12A and 12B are cross-sectional views showing the first element 11 and the second element 12, respectively. The bumps 12b of the second bump group 120 are designed so that the height (which may be a diameter or volume) is lower than the height of the bumps 11b of the first bump group 110. 12A and 12B, the diameter of the bump 11b of the first element 11 is X, and the diameter of the bump 12b of the second element 12 is X-α.
　残留はんだ１１ｃの体積と、第２素子１２のバンプ１２ｂの体積との和が、実質的に第１素子１１のバンプ１１ｂの体積に等しくなるように、バンプ１２ｂの体積が設計される。具体的には、第２素子１２の製造工程において、バンプ１２ｂを形成するはんだ材料の径を、マスクを用いて制御することにより（この場合、高さ（厚さ）は一定）、形成されるいバンプ１２ｂの体積を制御できる。 The volume of the bump 12b is designed so that the sum of the volume of the residual solder 11c and the volume of the bump 12b of the second element 12 is substantially equal to the volume of the bump 11b of the first element 11. Specifically, in the manufacturing process of the second element 12, the diameter of the solder material forming the bump 12b is controlled using a mask (in this case, the height (thickness) is constant). The volume of the bump 12b can be controlled.
　図１３Ａ、Ｂは、第１素子１１のバンプ１１ｂの高さと、第２素子１２のそれとが同じである場合の実装工程（例えばリフロー工程）を示す。この場合、図１３Ｂに示すように、実装後の第２素子１２の本体１２ａの高さ（残留はんだ１１ｃを含む）と、他の第１素子１１の本体１１ａの高さに差が発生する。 13A and 13B show a mounting process (for example, a reflow process) when the height of the bump 11b of the first element 11 is the same as that of the second element 12. FIG. In this case, as shown in FIG. 13B, a difference occurs between the height of the main body 12a of the second element 12 after mounting (including the residual solder 11c) and the height of the main body 11a of the other first element 11.
　一方、図１４Ａに示すように、第２素子１２のバンプ１２ｂの高さが、第１素子１１のそれより予め低く設定されている場合、図１４Ｂに示すようになる。すなわち、第２素子１２の実装後のバンプ１２ｂの高さ（残留はんだ１１ｃを含む）が、他の第１素子１１のバンプ１１ｂの高さと同じになる。これにより、実装された第２素子１２の本体１２ａの高さを、第１素子１１の本体１１ａの高さと同じにすることができる。その結果、例えば、それら素子１５の全体の表面の高さを均一にすることができる。 On the other hand, as shown in FIG. 14A, when the height of the bump 12b of the second element 12 is set in advance lower than that of the first element 11, it becomes as shown in FIG. 14B. That is, the height of the bump 12b (including the residual solder 11c) after mounting the second element 12 is the same as the height of the bump 11b of the other first element 11. Thereby, the height of the main body 12a of the mounted second element 12 can be made the same as the height of the main body 11a of the first element 11. As a result, for example, the height of the entire surface of the elements 15 can be made uniform.
　ただし、残留はんだ１１ｃの量を考慮して、第１素子１１の本体１１ａの高さより、第２素子１２のそれを意図的に高くするような設計もあり得る。この場合、図１３Ａ、Ｂで示したようなバンプ１１ｂ、１２ｂの設計でよい。 However, in consideration of the amount of the residual solder 11c, there may be a design in which the height of the second element 12 is intentionally higher than the height of the main body 11a of the first element 11. In this case, the design of the bumps 11b and 12b as shown in FIGS. 13A and 13B may be used.
　その逆に、残留はんだ１１ｃの量を考慮して、第１素子１１の本体１１ａの高さより、第２素子１２のそれを低くするように、バンプ１１ｂ、１２ｂが設計されてもよい。 On the contrary, the bumps 11b and 12b may be designed so as to make the second element 12 lower than the height of the main body 11a of the first element 11 in consideration of the amount of the residual solder 11c.
　以上のように、本実施形態によれば、素子１５の高さを調整することができ、また、残留はんだ１１ｃを除去する工程を省くことができる。 As described above, according to this embodiment, the height of the element 15 can be adjusted, and the process of removing the residual solder 11c can be omitted.
　３．３．２）例２ 3.3.2) Example 2
　図１５は、１つの除去領域１４において、ランド１６上の残留はんだ１１ｃの量がそれぞれ異なる形態を示す。この場合、図１５の下に示すように、第２素子１２が傾いた状態で実装されてしまう。 FIG. 15 shows a form in which the amount of the residual solder 11c on the land 16 is different in one removal region. In this case, as shown in the lower part of FIG. 15, the second element 12 is mounted in an inclined state.
　そこで、図１６に示すように、少なくとも２つの異なる高さ（径、または体積でもよい）を持つバンプ１２ｂを有する第２素子１２が用いられる。図１６では、１つのバンプ１２ｂの径がＸ-αであり、他のバンプ１２ｂの径がＸ-βである。また、α<βである。大きい方の径Ｘ-αを有するバンプ１２ｂが、残留量の少ない残留はんだ１１ｃに接合され、小さい方の径Ｘ-βを有するバンプ１２ｂが、残留量の多い残留はんだ１１ｃに接合される。これにより、実装された第２素子１２の本体１２ａと、実装基板１０とを平行にすることができる。 Therefore, as shown in FIG. 16, a second element 12 having a bump 12b having at least two different heights (which may be a diameter or a volume) is used. In FIG. 16, the diameter of one bump 12b is X-α, and the diameter of the other bump 12b is X-β. Also, α <β. The bump 12b having the larger diameter X-α is joined to the residual solder 11c having a small residual amount, and the bump 12b having the smaller diameter X-β is joined to the residual solder 11c having a large residual amount. Thereby, the main body 12a of the mounted second element 12 and the mounting substrate 10 can be made parallel.
　図１７では、１つの除去領域１４において複数のランド１６上の残留はんだ１１ｃの量が実質的に同じである場合に、少なくとも２つの異なる高さのバンプ１２ｂを持つ第２素子１２が実装される。この場合、その本体１２ａが実装基板１０に対して傾斜するように配置される。 In FIG. 17, when the amount of residual solder 11c on the plurality of lands 16 is substantially the same in one removal region 14, the second element 12 having at least two bumps 12b having different heights is mounted. . In this case, the main body 12 a is disposed so as to be inclined with respect to the mounting substrate 10.
　このようにして、設計時において第２素子１２のバンプ１２ｂの径を制御することにより、実装後の第２素子１２の本体１２ａの傾斜角を制御することができる。すなわち、バンプ１２ｂの径のみの制御により、実装基板１０に対して任意の角度で傾斜する第２素子１２を実現することができる。 Thus, the inclination angle of the main body 12a of the second element 12 after mounting can be controlled by controlling the diameter of the bump 12b of the second element 12 at the time of design. That is, the second element 12 that is inclined at an arbitrary angle with respect to the mounting substrate 10 can be realized by controlling only the diameter of the bump 12b.
　４．変形例 4. Modified example
　上記実施形態は、第１素子１１、第２素子１２の２種類の素子について述べたが、３種類以上の素子についても同様の趣旨である。すなわち、第１素子１１の数より少ない第２素子の他、第１素子１１の数より少ない第３素子が、第１素子が除去された除去領域に実装されてもよい。 In the above embodiment, two types of elements, the first element 11 and the second element 12, have been described, but the same applies to three or more types of elements. That is, in addition to the second elements smaller than the number of the first elements 11, third elements smaller than the number of the first elements 11 may be mounted in the removed region where the first elements are removed.
　なお、本技術は以下のような構成もとることができる。
（１）
　実装基板と、
　２以上の第１素子と、前記第１素子とは異なる１以上の第２素子とを含み、前記実装基板上にアレイ構造で配列されるように実装された複数の素子と
　を具備するアレイ基板。
（２）
　前記（１）に記載のアレイ基板であって、
　前記複数の素子は、それぞれ、本体と、前記本体に設けられた１以上のバンプとを有する
　アレイ基板。
（３）
　前記（２）に記載のアレイ基板であって、
　前記第２素子の本体の一辺の長さが、前記第１素子のそれより短い
　アレイ基板。
（４）
　前記（２）または（３）に記載のアレイ基板であって、
　前記実装基板は、前記複数の素子のバンプが接続されるランドを有し、
　前記第２素子の本体の一辺の長さと、前記第１素子のそれとの差は、前記ランドの半径と前記第２素子のバンプの半径の和の２倍以上である
　アレイ基板。
（５）
　前記（２）から（４）のうちいずれか１項に記載のアレイ基板であって、
　前記第１素子の本体の一辺の長さは、60μm以上2000μm以下であり、
　前記第２素子の本体の一辺の長さは、50μm以上1990μm以下である
　アレイ基板。
（６）
　前記（２）から（５）のうちいずれか１項に記載のアレイ基板であって、
　前記第１素子は第１バンプ群を有し、
　前記第２素子は、前記第１バンプ群の配列と一致する配列を持つ第２バンプ群を有する
　アレイ基板。
（７）
　前記（２）から（５）のうちいずれか１項に記載のアレイ基板であって、
　前記第１素子は第１バンプ群を有し、
　前記第２素子は、前記第１バンプ群の配列の一部と一致する配列を持つ第２バンプ群を有し、
　前記第１バンプ群の配列が、前記第２バンプ群の配列を包含する
　アレイ基板。
（８）
　前記（２）から（５）のうちいずれか１項に記載のアレイ基板であって、
　前記第１素子は第１バンプ群を有し、
　前記第２素子は、前記第１バンプ群の配列の全部と異なる配列を持つ第２バンプ群を有する
　アレイ基板。
（９）
　前記（２）から（８）のうちいずれか１項に記載のアレイ基板であって、
　前記第２素子のバンプの高さは、前記第１素子のバンプの高さより低い
　アレイ基板。
（１０）
　前記（２）から（８）のうちいずれか１項に記載のアレイ基板であって、
　前記第２素子のバンプは、少なくとも２つの異なる高さを持つ
　アレイ基板。
（１１）
　２以上の第１素子および１以上の第２素子を含む複数の素子を備えるアレイ基板の実装基板に実装された前記第２素子であって、
　前記複数の素子が前記実装基板上にアレイ構造で配列され、
　一辺の長さが、前記第１素子の本体の一辺の長さより短くなるように構成された本体と、
　前記本体に設けられた１以上のバンプと
　を具備する実装素子。
（１２）
　前記（１１）に記載の実装素子であって、
　前記第２素子のバンプは、少なくとも２つの異なる高さを持つ
　実装素子。
（１３）
　実装基板と、
　２以上の第１素子と、前記第１素子とは異なる１以上の第２素子とを含み、前記実装基板上にアレイ構造で配列されるように実装された複数の素子と
　を有するアレイ基板を備えたデバイス。
（１４）
　アレイ構造で配列された複数の第１素子を実装基板上に転写して実装し、
　複数の第１素子のうち１以上の第１素子を、前記実装基板から除去し、
　前記実装基板上の、前記第１素子が除去された除去領域に、前記第１素子とは異なる１以上の第２素子を実装する
　アレイ基板の製造方法。
（１５）
　前記（１４）に記載のアレイ基板の製造方法であって、
　前記複数の素子は、それぞれ、本体と、前記本体に設けられた１以上のバンプとを有する
　前記実装基板は、前記複数の素子のバンプが接続されるランドを有する
　アレイ基板の製造方法。
（１６）
　前記（１５）に記載のアレイ基板の製造方法であって、
　前記実装基板からの前記第１素子の本体の高さと、前記第２素子のそれとが同じになるように、前記第２素子の実装前の当該第２素子のバンプの高さが、前記第１素子のバンプの高さより低く構成される
　アレイ基板の製造方法。
（１７）
　前記（１５）に記載のアレイ基板の製造方法であって、
　１つの前記除去領域に残るそれらランドが、少なくとも２つの異なる高さを持つ場合、前記第２素子の実装後の、前記実装基板と当該第２素子の本体とが平行になるように、前記第２素子の実装前の当該第２素子のそれらバンプが少なくとも異なる２つの高さを持つ
　アレイ基板の製造方法。
（１８）
　前記（１５）に記載のアレイ基板の製造方法であって、
　前記第２素子の実装後の、前記実装基板に対して前記第２素子の本体が傾斜するように前記第２素子が前記実装基板上に配置される
　アレイ基板の製造方法。
（１９）
　前記（１８）に記載のアレイ基板の製造方法であって、
　前記第２素子のそれらバンプは、少なくとも２つの異なる高さを持つ
　アレイ基板の製造方法。 In addition, this technique can also take the following structures.
(1)
A mounting board;
An array substrate comprising: two or more first elements; and a plurality of elements mounted to be arranged in an array structure on the mounting substrate, including one or more second elements different from the first elements .
(2)
The array substrate according to (1) above,
Each of the plurality of elements has a main body and one or more bumps provided on the main body.
(3)
The array substrate according to (2) above,
The length of one side of the main body of the second element is shorter than that of the first element.
(4)
The array substrate according to (2) or (3),
The mounting substrate has lands to which bumps of the plurality of elements are connected,
The difference between the length of one side of the main body of the second element and that of the first element is at least twice the sum of the radius of the land and the radius of the bump of the second element.
(5)
The array substrate according to any one of (2) to (4),
The length of one side of the main body of the first element is 60 μm or more and 2000 μm or less,
The length of one side of the main body of the second element is 50 μm or more and 1990 μm or less. Array substrate.
(6)
The array substrate according to any one of (2) to (5),
The first element has a first bump group,
The second element has an array substrate having a second bump group having an arrangement that matches the arrangement of the first bump group.
(7)
The array substrate according to any one of (2) to (5),
The first element has a first bump group,
The second element has a second bump group having an arrangement that matches a part of the arrangement of the first bump group,
An array substrate in which the arrangement of the first bump group includes the arrangement of the second bump group.
(8)
The array substrate according to any one of (2) to (5),
The first element has a first bump group,
The second element has a second bump group having an arrangement different from the whole arrangement of the first bump group.
(9)
The array substrate according to any one of (2) to (8),
The height of the bump of the second element is lower than the height of the bump of the first element.
(10)
The array substrate according to any one of (2) to (8),
The bump of the second element has at least two different heights.
(11)
The second element mounted on a mounting substrate of an array substrate comprising a plurality of elements including two or more first elements and one or more second elements,
The plurality of elements are arranged in an array structure on the mounting substrate,
A main body configured such that the length of one side is shorter than the length of one side of the main body of the first element;
A mounting element comprising one or more bumps provided on the main body.
(12)
The mounting element according to (11),
The bump of the second element has at least two different heights.
(13)
A mounting board;
An array substrate comprising: two or more first elements; and a plurality of elements mounted on the mounting substrate so as to be arranged in an array structure, including at least one second element different from the first element. Device provided.
(14)
A plurality of first elements arranged in an array structure are transferred and mounted on a mounting substrate,
Removing one or more first elements of the plurality of first elements from the mounting substrate;
A method for manufacturing an array substrate, wherein one or more second elements different from the first element are mounted in a removal region on the mounting substrate where the first element is removed.
(15)
The method of manufacturing an array substrate according to (14),
Each of the plurality of elements has a main body and one or more bumps provided on the main body. The mounting substrate has a land to which bumps of the plurality of elements are connected.
(16)
The method for manufacturing an array substrate according to (15),
The height of the bump of the second element before mounting the second element is set so that the height of the main body of the first element from the mounting substrate is the same as that of the second element. An array substrate manufacturing method configured to be lower than the bump height of the element.
(17)
The method for manufacturing an array substrate according to (15),
When the lands remaining in one removal region have at least two different heights, the mounting substrate and the main body of the second element after mounting the second element are parallel to each other. The method of manufacturing an array substrate, wherein the bumps of the second element before the two elements are mounted have at least two different heights.
(18)
The method for manufacturing an array substrate according to (15),
The method of manufacturing an array substrate, wherein the second element is disposed on the mounting substrate so that a main body of the second element is inclined with respect to the mounting substrate after mounting the second element.
(19)
The method of manufacturing an array substrate according to (18),
The bumps of the second element have at least two different heights.
　１０…実装基板
　１１…第１素子
　１１ａ、１２ａ…本体
　１１ｂ、１２ｂ…バンプ
　１２…第２素子
　１４…除去領域
　１５…素子
　１６…ランド
　５０…アレイ基板
　１１０…第１バンプ群
　１２０…第２バンプ群 DESCRIPTION OF SYMBOLS 10 ... Mounting board 11 ... 1st element 11a, 12a ... Main body 11b, 12b ... Bump 12 ... 2nd element 14 ... Removal area | region 15 ... Element 16 ... Land 50 ... Array substrate 110 ... 1st bump group 120 ... 2nd bump group

Claims (19)

  1. 　実装基板と、
    　２以上の第１素子と、前記第１素子とは異なる１以上の第２素子とを含み、前記実装基板上にアレイ構造で配列されるように実装された複数の素子と
    　を具備するアレイ基板。     A mounting board;
    An array substrate comprising: two or more first elements; and a plurality of elements mounted to be arranged in an array structure on the mounting substrate, including one or more second elements different from the first elements .
  2. 　請求項１に記載のアレイ基板であって、
    　前記複数の素子は、それぞれ、本体と、前記本体に設けられた１以上のバンプとを有する
    　アレイ基板。     The array substrate according to claim 1,
    Each of the plurality of elements has a main body and one or more bumps provided on the main body.
  3. 　請求項２に記載のアレイ基板であって、
    　前記第２素子の本体の一辺の長さが、前記第１素子のそれより短い
    　アレイ基板。     The array substrate according to claim 2, wherein
    The length of one side of the main body of the second element is shorter than that of the first element.
  4. 　請求項２に記載のアレイ基板であって、
    　前記実装基板は、前記複数の素子のバンプが接続されるランドを有し、
    　前記第２素子の本体の一辺の長さと、前記第１素子のそれとの差は、前記ランドの半径と前記第２素子のバンプの半径の和の２倍以上である
    　アレイ基板。     The array substrate according to claim 2, wherein
    The mounting substrate has lands to which bumps of the plurality of elements are connected,
    The difference between the length of one side of the main body of the second element and that of the first element is at least twice the sum of the radius of the land and the radius of the bump of the second element.
  5. 　請求項２に記載のアレイ基板であって、
    　前記第１素子の本体の一辺の長さは、60μm以上2000μm以下であり、
    　前記第２素子の本体の一辺の長さは、50μm以上1990μm以下である
    　アレイ基板。     The array substrate according to claim 2, wherein
    The length of one side of the main body of the first element is 60 μm or more and 2000 μm or less,
    The length of one side of the main body of the second element is 50 μm or more and 1990 μm or less. Array substrate.
  6. 　請求項２に記載のアレイ基板であって、
    　前記第１素子は第１バンプ群を有し、
    　前記第２素子は、前記第１バンプ群の配列と一致する配列を持つ第２バンプ群を有する
    　アレイ基板。     The array substrate according to claim 2, wherein
    The first element has a first bump group,
    The second element has an array substrate having a second bump group having an arrangement that matches the arrangement of the first bump group.
  7. 　請求項２に記載のアレイ基板であって、
    　前記第１素子は第１バンプ群を有し、
    　前記第２素子は、前記第１バンプ群の配列の一部と一致する配列を持つ第２バンプ群を有し、
    　前記第１バンプ群の配列が、前記第２バンプ群の配列を包含する
    　アレイ基板。     The array substrate according to claim 2, wherein
    The first element has a first bump group,
    The second element has a second bump group having an arrangement that matches a part of the arrangement of the first bump group,
    An array substrate in which the arrangement of the first bump group includes the arrangement of the second bump group.
  8. 　請求項２に記載のアレイ基板であって、
    　前記第１素子は第１バンプ群を有し、
    　前記第２素子は、前記第１バンプ群の配列の全部と異なる配列を持つ第２バンプ群を有する
    　アレイ基板。     The array substrate according to claim 2, wherein
    The first element has a first bump group,
    The second element has a second bump group having an arrangement different from the whole arrangement of the first bump group.
  9. 　請求項２に記載のアレイ基板であって、
    　前記第２素子のバンプの高さは、前記第１素子のバンプの高さより低い
    　アレイ基板。     The array substrate according to claim 2, wherein
    The height of the bump of the second element is lower than the height of the bump of the first element.
  10. 　請求項２に記載のアレイ基板であって、
    　前記第２素子のバンプは、少なくとも２つの異なる高さを持つ
    　アレイ基板。     The array substrate according to claim 2, wherein
    The bump of the second element has at least two different heights.
  11. 　２以上の第１素子および１以上の第２素子を含む複数の素子を備えるアレイ基板の実装基板に実装された前記第２素子であって、
    　前記複数の素子が前記実装基板上にアレイ構造で配列され、
    　一辺の長さが、前記第１素子の本体の一辺の長さより短くなるように構成された本体と、
    　前記本体に設けられた１以上のバンプと
    　を具備する実装素子。     The second element mounted on a mounting substrate of an array substrate comprising a plurality of elements including two or more first elements and one or more second elements,
    The plurality of elements are arranged in an array structure on the mounting substrate,
    A main body configured such that the length of one side is shorter than the length of one side of the main body of the first element;
    A mounting element comprising one or more bumps provided on the main body.
  12. 　請求項１１に記載の実装素子であって、
    　前記第２素子のバンプは、少なくとも２つの異なる高さを持つ
    　実装素子。     The mounting element according to claim 11,
    The bump of the second element has at least two different heights.
  13. 　実装基板と、
    　２以上の第１素子と、前記第１素子とは異なる１以上の第２素子とを含み、前記実装基板上にアレイ構造で配列されるように実装された複数の素子と
    　を有するアレイ基板を備えたデバイス。     A mounting board;
    An array substrate comprising: two or more first elements; and a plurality of elements mounted on the mounting substrate so as to be arranged in an array structure, including at least one second element different from the first element. Device provided.
  14. 　アレイ構造で配列された複数の第１素子を実装基板上に転写して実装し、
    　複数の第１素子のうち１以上の第１素子を、前記実装基板から除去し、
    　前記実装基板上の、前記第１素子が除去された除去領域に、前記第１素子とは異なる１以上の第２素子を実装する
    　アレイ基板の製造方法。     A plurality of first elements arranged in an array structure are transferred and mounted on a mounting substrate,
    Removing one or more first elements of the plurality of first elements from the mounting substrate;
    A method for manufacturing an array substrate, wherein one or more second elements different from the first element are mounted in a removal region on the mounting substrate where the first element is removed.
  15. 　請求項１４に記載のアレイ基板の製造方法であって、
    　前記複数の素子は、それぞれ、本体と、前記本体に設けられた１以上のバンプとを有する
    　前記実装基板は、前記複数の素子のバンプが接続されるランドを有する
    　アレイ基板の製造方法。     A method for manufacturing an array substrate according to claim 14,
    Each of the plurality of elements has a main body and one or more bumps provided on the main body. The mounting substrate has a land to which bumps of the plurality of elements are connected.
  16. 　請求項１５に記載のアレイ基板の製造方法であって、
    　前記実装基板からの前記第１素子の本体の高さと、前記第２素子のそれとが同じになるように、前記第２素子の実装前の当該第２素子のバンプの高さが、前記第１素子のバンプの高さより低く構成される
    　アレイ基板の製造方法。     A method for manufacturing an array substrate according to claim 15,
    The height of the bump of the second element before mounting the second element is set so that the height of the main body of the first element from the mounting substrate is the same as that of the second element. An array substrate manufacturing method configured to be lower than the bump height of the element.
  17. 　請求項１５に記載のアレイ基板の製造方法であって、
    　１つの前記除去領域に残るそれらランドが、少なくとも２つの異なる高さを持つ場合、前記第２素子の実装後の、前記実装基板と当該第２素子の本体とが平行になるように、前記第２素子の実装前の当該第２素子のそれらバンプが少なくとも異なる２つの高さを持つ
    　アレイ基板の製造方法。     A method for manufacturing an array substrate according to claim 15,
    When the lands remaining in one removal region have at least two different heights, the mounting substrate and the main body of the second element after mounting the second element are parallel to each other. The method of manufacturing an array substrate, wherein the bumps of the second element before the two elements are mounted have at least two different heights.
  18. 　請求項１５に記載のアレイ基板の製造方法であって、
    　前記第２素子の実装後の、前記実装基板に対して前記第２素子の本体が傾斜するように前記第２素子が前記実装基板上に配置される
    　アレイ基板の製造方法。     A method for manufacturing an array substrate according to claim 15,
    The method of manufacturing an array substrate, wherein the second element is disposed on the mounting substrate so that a main body of the second element is inclined with respect to the mounting substrate after mounting the second element.
  19. 　請求項１８に記載のアレイ基板の製造方法であって、
    　前記第２素子のそれらバンプは、少なくとも２つの異なる高さを持つ
    　アレイ基板の製造方法。     A method of manufacturing an array substrate according to claim 18,
    The bumps of the second element have at least two different heights.
PCT/JP2018/000747 2017-02-17 2018-01-15 Array substrate, mounted element, device comprising array substrate and method for producing array substrate WO2018150776A1 (en)

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JPH09162545A (en) * 1995-12-11 1997-06-20 Nec Corp Structure and method for packaging ball grid array
JP2005123381A (en) * 2003-10-16 2005-05-12 Seiko Epson Corp Method for mounting element chip, mounting substrate, electro-optical device and electronic equipment
WO2005067062A1 (en) * 2003-12-26 2005-07-21 Nec Corporation Substrate with light input, substrate with light output, substrate with light input/output, and semiconductor integrated circuit with optical element
WO2005067061A1 (en) * 2003-12-26 2005-07-21 Nec Corporation Semiconductor integrated circuit with optical element
US20060148281A1 (en) * 2004-12-30 2006-07-06 Horine Bryce D Connection of package, board, and flex cable

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162545A (en) * 1995-12-11 1997-06-20 Nec Corp Structure and method for packaging ball grid array
JP2005123381A (en) * 2003-10-16 2005-05-12 Seiko Epson Corp Method for mounting element chip, mounting substrate, electro-optical device and electronic equipment
WO2005067062A1 (en) * 2003-12-26 2005-07-21 Nec Corporation Substrate with light input, substrate with light output, substrate with light input/output, and semiconductor integrated circuit with optical element
WO2005067061A1 (en) * 2003-12-26 2005-07-21 Nec Corporation Semiconductor integrated circuit with optical element
US20060148281A1 (en) * 2004-12-30 2006-07-06 Horine Bryce D Connection of package, board, and flex cable

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