WO2018137560A1 - Power module and manufacturing method therefor - Google Patents

Power module and manufacturing method therefor Download PDF

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Publication number
WO2018137560A1
WO2018137560A1 PCT/CN2018/073368 CN2018073368W WO2018137560A1 WO 2018137560 A1 WO2018137560 A1 WO 2018137560A1 CN 2018073368 W CN2018073368 W CN 2018073368W WO 2018137560 A1 WO2018137560 A1 WO 2018137560A1
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Prior art keywords
conductive layer
chip
power module
terminal
electrically connected
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PCT/CN2018/073368
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French (fr)
Chinese (zh)
Inventor
李慧
杨胜松
廖雯祺
杨钦耀
李艳
张建利
曾秋莲
Original Assignee
比亚迪股份有限公司
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Publication of WO2018137560A1 publication Critical patent/WO2018137560A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors

Definitions

  • the present application relates to the field of hybrid integrated circuits, and in particular to a power module and a method of fabricating the same.
  • a power semiconductor module is a device that packages a plurality of semiconductor chips together in a certain circuit structure.
  • IGBT Insulated Gate Bipolar Transistor
  • the IGBT chip and the diode chip are integrated on a common substrate, and the power device of the power semiconductor module is insulated from the mounting surface thereof (ie, the heat sink) .
  • the power semiconductor module includes a supporting electrical adapter block, which makes the module larger in size and less integrated.
  • the object of the present invention is to provide a power module and a manufacturing method thereof, which are intended to solve the problem that a conventional power semiconductor module needs to be opened and includes a supporting electrical switch block, and the module has a large volume.
  • the invention provides a power module comprising:
  • An insulating dielectric substrate having a patterned first conductive layer on an upper surface thereof;
  • At least one switch tube chip and at least one diode chip, the switch tube chip and the diode chip are attached on an upper surface of the insulating dielectric substrate to form an electrical connection with the first conductive layer;
  • a patterned second conductive layer disposed on the insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer through the conductive material, and the switch chip is formed by the conductive material Connected to the diode chip circuit.
  • the invention also provides a method for manufacturing a power module, comprising the following steps:
  • An insulating layer is disposed on the first insulating dielectric substrate to encapsulate the switch chip and the diode chip;
  • the conductive material inside is electrically connected to the first conductive layer, and the switch transistor chip and the diode chip are electrically connected.
  • the present invention has at least the following advantages:
  • the above power module and its manufacturing method module package do not need to be opened and sealed, which saves production cost; in addition, the power semiconductor chip is electrically connected by opening a through hole in the insulating layer and filling the conductive material with the upper conductive layer, thereby reducing the module.
  • the volume is conducive to the miniaturization of the module.
  • FIG. 1 is a schematic structural view of a power module according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a power module according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an embodiment of a power module overall layout according to the present invention.
  • FIG. 4 is a schematic structural view of a heat dissipation flat plate according to an embodiment of the present invention.
  • FIG. 5 is a flow chart of a method of fabricating a power module in accordance with a preferred embodiment of the present invention.
  • the power module in the preferred embodiment of the present invention includes an insulating dielectric substrate 10 , at least one switch chip 20 , at least one diode chip 30 , an insulating layer 40 , and a second conductive layer 50 .
  • the insulating dielectric substrate 10 has oppositely disposed upper and lower surfaces, at least one of which is coated with a metal, and the intermediate layer is a ceramic layer 11.
  • the upper surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the lower surface may be covered with a metal to form another patterned conductive layer 13.
  • the heat dissipating fins 14 may be directly disposed (see figure 2).
  • the switch tube chip 20 in this embodiment is an IGBT, and the diode chip 30 is an FRD (Fast Recovery Diode).
  • the power module has one or more IGBTs and one or more FRDs to constitute a drive circuit.
  • the upper and lower surfaces of the switch tube chip 20 have polarity pins.
  • the upper surface of the switch tube chip 20 has two polarity pins, which are a gate and an emitter, respectively, and a lower surface has a collector.
  • the upper surface of the diode chip 30 has an anode, and the lower surface has a cathode, or vice versa.
  • the switch tube chip 20 and the diode chip 30 are attached to the upper surface of the insulating dielectric substrate 10 to form an electrical connection with the first conductive layer 12. Specifically, when a circuit pattern is formed on the first conductive layer 12, and the switch chip 20 and the diode chip 30 are attached to the circuit pattern by soldering or crimping, the polarity pins of the lower surface and the corresponding circuit patterns are formed. A circuit connection is formed to lead.
  • An insulating layer 40 covers the insulating dielectric substrate 10, and the switching transistor chip 20, the diode chip 30, and the first conductive layer 12 are covered, and the insulating layer 40 is covered on the insulating dielectric substrate by lamination. 10 on.
  • the lower surface of the insulating layer 40 is provided with a recess for accommodating the switch tube chip 20 and the diode chip 30.
  • the predetermined position of the insulating layer 40 defines a plurality of through holes 42 extending through the upper and lower surfaces thereof. As shown in FIG. 1 and FIG.
  • the plurality of through holes 42 extend through the insulating layer 40 to the switch tube chip 20 , the diode chip 30 , the first conductive layer 12 and the second conductive layer 50 , respectively, and the through holes 42 .
  • a conductive material electrically connected to the switch chip 20, the diode chip 30, the first conductive layer 12, and the second conductive layer 50 is filled therein.
  • the plurality of through holes 42 extend through the second conductive layer 50 and the insulating layer 40 to the switch chip chip 20, the diode chip 30, and the first conductive layer 12, respectively, and the through holes 42 are filled with A conductive material electrically connected to the switch chip 20, the diode chip 30, the first conductive layer 12, and the second conductive layer 50.
  • the through holes 42 of the same circuit connection path are disposed as much as possible to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
  • the insulating layer 40 is formed by pre-pregnant heating and curing, and at the same time, the conductive material in the through hole 42 is simultaneously metalized; wherein the prepreg is mainly composed of a resin and a reinforcing material.
  • the reinforcing material may be a fiberglass cloth, a paper base, a composite material or the like, and the coefficient of thermal expansion of the prepreg is matched with the thermal expansion coefficient of the switch tube chip 20 and the diode chip 30 to prevent the power device from being mismatched with the thermal expansion coefficient of the packaging material. The failure of the device is subject to excessive stress.
  • the second conductive layer 50 is disposed on the insulating layer 40, specifically, laminated on the insulating layer 40 by lamination.
  • the second conductive layer 50 is electrically connected to the switch chip 20, the diode chip 30, and the first conductive layer 12 through the conductive material, and the switch chip 20 and the diode chip 30 are electrically connected by the conductive material.
  • a circuit pattern is formed on the second conductive layer 50, and the polarity pins on the upper surface of the switch tube chip 20 are electrically connected to the corresponding circuit patterns for extraction.
  • the switch chip 20 is electrically connected to the second conductive layer 50 through the through hole 42 which is formed on the insulating layer 40, thereby replacing the electrical transfer block to achieve electrical connection, thereby reducing the volume of the module and facilitating the module. miniaturization.
  • the insulating dielectric substrate 10 in the listed embodiment is not limited to a DBC (Direct Bond Copper) substrate, and may be a DBA (Direct Bond Aluminum) substrate, or any other surface-covered metal insulating medium. Substrate, refer to Figure 1. In another embodiment, the insulating dielectric substrate 10 may be a copper-clad ceramic substrate having a surface coated with copper and the other surface provided with heat dissipating fins 14, as shown in FIG.
  • the second conductive layer 50 is a conductive metal sheet, and may be made of a copper sheet, an aluminum sheet or other conductive metal material.
  • the second conductive layer 50 may be made of a metal coated with a lower surface of another insulating dielectric substrate.
  • Another insulating dielectric substrate has opposite upper and lower surfaces, at least one of which is coated with a metal to form a second conductive layer 50, and the intermediate layer is a ceramic layer.
  • the upper surface may be coated with metal to form another conductive layer, and heat dissipating fins may also be provided.
  • the power module further includes a lead terminal 60 (ie, a power module pin), and one end of the lead terminal 60 is fixedly electrically connected to the first conductive layer 12 or the second conductive layer 50, and the through hole 42 is matched.
  • the conductive material inside is electrically connected to the corresponding polarity pins of the switch tube chip 20 and the diode chip 30, and the other end of the lead terminal 60 is outwardly extended.
  • the lead terminal 60 is for taking the switch tube chip 20 and the diode chip 30 out of the terminals of the circuit in a preset circuit for connection with an external circuit.
  • the lead terminal 60 may be fixed to the first conductive layer 12 or may be fixed to the second conductive layer 50.
  • the first terminal 12 is fixed to the first conductive layer 12 as an example.
  • the lead terminal 60 includes a control terminal 62 including an emitter power terminal 61A and a collector power terminal 61B, and a collector power terminal 61B, the first conductive layer 12 including a first circuit pattern 121 and a first portion on opposite sides of the power module
  • the two circuit patterns 122 include a emitter pad 121A and a collector pad 121B which are disposed side by side on the same side of the power module.
  • the switch pin chip 20 and the polarity pin on the lower surface of the diode chip 30 are electrically connected to the collector pad 121B of the first circuit pattern 121, and the collector power terminal 61B is electrically connected to the collector pad 121B;
  • the polarity pins of the upper surface of the chip 20 and the diode chip 30 are electrically connected to the emitter pads of the first circuit pattern 121 through the conductive materials in the corresponding through holes 42 and the second conductive layer 50, respectively.
  • 121A and the second circuit pattern 122, the control terminal 62 and the second circuit pattern 122 are soldered, and the emitter power terminal 61A and the emitter pad 121A of the first circuit pattern 121 are soldered.
  • the second circuit pattern 122 is also a pin pad.
  • the second conductive layer 50 includes a third circuit pattern 51 and a fourth circuit pattern 52.
  • the first circuit pattern 121 is connected to the switch chip through the conductive material in the corresponding through hole 42 and the third circuit pattern 51. 20 and a polarity pin on the upper surface of the diode chip 30.
  • the second circuit pattern 122 is connected to the polarity pin of the upper surface of the switch tube chip 20 through the conductive material in the corresponding through hole 42 and the fourth circuit pattern 52.
  • the switch tube chip 20 is electrically connected to the emitter pad 121A of the first circuit pattern 121, and is electrically connected to the second circuit pattern 122, and is connected to the collector of the first circuit pattern 12.
  • the pad 121B is electrically connected to a collector.
  • Figure 3 is a schematic diagram of the overall layout of the power module.
  • the filled area in the figure is substantially graphically patterned for the first conductive layer 12, and the blackened area of the wire frame is substantially graphically patterned for the second conductive layer 50.
  • the switch tube chip 20 and the diode chip 30 are soldered to the corresponding positions of the first conductive layer 12, and the control terminal 62 and the power terminal 61 are also soldered to the corresponding positions of the first conductive layer 12, and the chip polarity and the corresponding terminal are made via the metalized through holes 42.
  • the control terminal 62 and the power terminal 61 are respectively located on both sides of the module, and the low voltage control end is away from the high voltage power end, which reduces the electrical interference of the high voltage end to the low voltage end, and improves the reliability of the control end.
  • the power module further includes a heat sink 70 that is disposed on a lower surface of the insulating dielectric substrate 10 and/or an upper surface of the second conductive layer 50 .
  • the heat sink 70 may be directly formed of a metal-clad insulating dielectric substrate 10 (e.g., heat dissipating fins 14), or may be separately provided externally.
  • the heat sink 70 can be separately disposed on the lower surface of the power module, or can be disposed on the upper and lower surfaces of the power module to achieve double-sided heat dissipation.
  • the heat sink 70 is a heat dissipating fin or a flat heat pipe.
  • Figure 4 is a schematic view of a flat heat pipe. The heat generated by the switch tube chip 20 and the diode chip 30 is conducted to the heat pipe evaporation surface 71, and the working fluid 72 in the capillary absorbs heat and vaporizes and fills the steam chamber. The condensing surface 73 of the flat heat pipe 70 is cooled by circulating cooling liquid. The steam 90 is recondensed into a liquid on the condensation surface 73. Under the action of the capillary suction force of the capillary core 74, the liquid re-flows back to the evaporation surface 71, and the above steps are repeated to achieve circulating heat dissipation.
  • a manufacturing method capable of manufacturing the above power module including the following steps:
  • an insulating dielectric substrate 10 having a first conductive layer 12 on its upper surface is disposed.
  • the insulating dielectric substrate 10 is provided to have oppositely disposed upper and lower surfaces, at least one of which is metal-coated.
  • the upper surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the lower surface may be covered with a metal to form another conductive layer, and the heat dissipating fins 14 may be disposed (see FIG. 3); A corresponding circuit pattern should be preset on the first conductive layer 12.
  • At least one switch chip 20 and at least one diode chip 30 are disposed on the first conductive layer 12 to form an electrical connection with the first conductive layer 12.
  • the switch transistor chip 20 is an IGBT
  • the diode chip 30 is an FRD.
  • the upper and lower surfaces of the chip have polar pins, and the switch chip 20 is attached to the upper surface of the insulating dielectric substrate 10 to form an electrical connection with the first conductive layer 12.
  • the switch chip 20 and the diode chip 30 are attached to the circuit pattern of the first conductive layer 12 by soldering or crimping, the polarity pins of the lower surface are connected to the corresponding circuit pattern forming circuit to be led out. .
  • an insulating layer 40 is disposed on the first insulating dielectric substrate 10, and the switch tube chip 20 and the diode chip 30 are covered.
  • the insulating layer 40 is a prepreg, and the prepreg is insulated, and its thermal expansion coefficient needs to be matched with the thermal expansion coefficient of the switch chip 20 as much as possible.
  • a second conductive layer 50 is disposed on the insulating layer 40.
  • the second conductive layer 50 is preferably a conductive metal sheet.
  • the second conductive layer 50 (conductive metal sheet or second insulating dielectric substrate), the prepreg, and the insulating dielectric substrate 10 provided with the switch tube chip 20 and the diode chip 30 are sequentially laminated and pressed, and the prepreg is filled with glue.
  • the switch tube chip 20 and the diode chip 30 are covered.
  • the first conductive layer 12 is electrically connected, and the switch transistor chip 20 and the diode chip 30 are electrically connected.
  • a polarity pin reaching the switch transistor chip 20 and the diode chip 30 and a via hole 42 reaching the first conductive layer 12 are formed on the second conductive layer 50 and the insulating layer 40 by laser technology, and the through hole is formed in the through hole
  • the conductive material is filled in 42 to metalize the via hole 42.
  • the second conductive layer 50 needs to be formed with a circuit pattern before or after lamination, and the polarity pins of the switch tube chip 20 and the upper surface of the diode chip 30 are connected to the corresponding circuit pattern forming circuits through the metalized via holes 42.
  • the step S120 further includes: further providing a lead-out terminal 60, wherein the one end of the lead-out terminal 60 is fixedly electrically connected to the first conductive layer 12, and the other end is outwardly extended.
  • the lead-out terminal is provided, and one end of the lead-out terminal 60 is fixedly electrically connected to the second conductive layer 50, and the other end is outwardly extended.
  • the lead terminal includes a control terminal 62 and a power terminal 61, and the control terminal 62 and the power terminal 61 are respectively located on opposite sides of the power module.
  • the low voltage control terminal is away from the high voltage power terminal, which reduces the electrical interference of the high voltage terminal to the low voltage terminal and improves the reliability of the control terminal.
  • the method further includes the step of heating to cure the prepreg by heating to achieve insulation.
  • the method further includes the step of disposing a heat sink disposed on a lower surface of the insulating dielectric substrate and/or an upper surface of the second conductive layer.
  • the above manufacturing method is that the power module is manufactured without encapsulation, and the production cost is saved; the chip is electrically connected through the metalized through hole 42 to reduce the volume of the module and facilitate the miniaturization of the module.
  • the power module is manufactured by soldering the switch chip 20 and the diode chip 30, the control terminal 62, and the power terminal 61 to the first conductive layer 12 patterned on the insulating dielectric substrate 10 to form a prepreg of a corresponding thickness.
  • (Insulating layer) 40 the second conductive layer 50 is laminated with the chip-attached insulating dielectric substrate 10, and the flow of the prepreg 40 is filled and covers the chip.
  • the prepreg 40 is insulated, and the coefficient of thermal expansion needs to be as large as possible.
  • the thermal expansion coefficient of the power device is matched. Matching means that the values of the two coefficients of thermal expansion are as close as possible or equal.
  • the second conductive layer 50 of the laminated module is patterned, and the via hole 42 is formed by laser technology and metallized, so that the chip polarity pin and the corresponding lead terminal 60 are electrically connected.
  • the via hole 42 is disposed as much as possible in order to ensure the reliability of the bonding between the metallized via 42 and the chip, so as to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
  • the lower surface of the module (insulating dielectric substrate 10) is dissipated by the heat sink 70, and the upper surface of the module (second conductive layer 50) is coated with an insulating thermal conductive adhesive 80, and then connected to the other heat sink 70 to dissipate heat, thereby achieving double-sided heat dissipation and improving Cooling capacity.
  • the two heat sinks 70 do not necessarily need to be disposed at the same time, and in the case where the heat dissipation condition can be satisfied, the heat sink 70 on the lower surface alone may constitute a single-sided heat dissipation.

Abstract

A power module and a manufacturing method therefor, the power module comprising: an insulating dielectric substrate (10) having a first conductive layer (12) on an upper surface thereof; a switch tube chip (20) and a diode chip (30), wherein the chips (20, 30) are adhered onto the upper surface of the insulating dielectric substrate (10); an insulating layer (40) covering the insulating dielectric substrate (10) and cladding the chips (20, 30) inside, wherein the insulating layer (40) is provided with a through hole (42) located above the chips (20, 30), and the through hole (42) is filled with a conductive substance; and a second conductive layer (50) arranged on the insulating layer (40), wherein the second conductive layer (50) is electrically connected to the chips (20, 30) through the conductive substance. The package does not require opening a plastic packaging mould, thus saving on production costs. Additionally, a power semiconductor chip is electrically connected with an upper conductive layer by providing the through hole (42) on the insulating layer (40) and filling the conductive substance therein, thereby reducing the size of the module and being advantageous for miniaturizing the module.

Description

一种功率模块及其制造方法Power module and manufacturing method thereof
本申请要求于2017年01月24日提交中国专利局、申请号为201710063330.9、申请名称为“一种功率模块及其制造方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。The present application claims priority to Chinese Patent Application No. JP-A No. No. No. No. No. No. No. No. No. No. No. No. No. No. No. in.
技术领域Technical field
本申请涉及混合集成电路领域,特别是涉及一种功率模块及其制造方法。The present application relates to the field of hybrid integrated circuits, and in particular to a power module and a method of fabricating the same.
背景技术Background technique
功率半导体模块是将多只半导体芯片按一定的电路结构封装在一起的器件。在一个IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)模块中,IGBT芯片及二极管芯片被集成在一块共同的底板上,且功率半导体模块的功率器件与其安装表面(即散热板)相互绝缘。A power semiconductor module is a device that packages a plurality of semiconductor chips together in a certain circuit structure. In an IGBT (Insulated Gate Bipolar Transistor) module, the IGBT chip and the diode chip are integrated on a common substrate, and the power device of the power semiconductor module is insulated from the mounting surface thereof (ie, the heat sink) .
传统的功率半导体模块塑封成型需要开模,成本较高;另外,功率半导体模块包含起支撑作用的电气转接块,使得模块体积较大,集成度小。Conventional power semiconductor module molding requires mold opening and high cost. In addition, the power semiconductor module includes a supporting electrical adapter block, which makes the module larger in size and less integrated.
发明内容Summary of the invention
本发明目的在于提供一种功率模块及其制造方法,旨在解决传统的功率半导体模块需要开模,且包含起支撑作用的电气转接块,模块体积较大的问题。The object of the present invention is to provide a power module and a manufacturing method thereof, which are intended to solve the problem that a conventional power semiconductor module needs to be opened and includes a supporting electrical switch block, and the module has a large volume.
本发明提供了一种功率模块,包括:The invention provides a power module comprising:
绝缘介质基板,其上表面具有图形化的第一导电层;An insulating dielectric substrate having a patterned first conductive layer on an upper surface thereof;
至少一个开关管芯片和至少一个二极管芯片,所述开关管芯片和二极管芯片贴设于所述绝缘介质基板的上表面上,与所述第一导电层形成电气连接;At least one switch tube chip and at least one diode chip, the switch tube chip and the diode chip are attached on an upper surface of the insulating dielectric substrate to form an electrical connection with the first conductive layer;
绝缘层,覆盖于所述绝缘介质基板上,将所述开关管芯片和二极管芯片包覆在内,所述绝缘层开设有贯穿其上下表面的通孔,且所述通孔内填充有导电物质;An insulating layer covering the insulating dielectric substrate, the switching tube chip and the diode chip are covered, the insulating layer is provided with a through hole penetrating the upper and lower surfaces thereof, and the through hole is filled with a conductive substance ;
图形化的第二导电层,设置于所述绝缘层之上,所述第二导电层通过所述导电物质与所述第一导电层导电连接,并通过所述导电物质将所述开关管芯片 和二极管芯片电路连接。a patterned second conductive layer disposed on the insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer through the conductive material, and the switch chip is formed by the conductive material Connected to the diode chip circuit.
本发明还提供了一种功率模块的制造方法,包括以下步骤:The invention also provides a method for manufacturing a power module, comprising the following steps:
设置一上表面具有第一导电层的绝缘介质基板;Providing an insulating dielectric substrate having a first conductive layer on the upper surface;
将至少一个开关管芯片和至少一个二极管芯片设于所述第一导电层上,与所述第一导电层形成电气连接;Providing at least one switch chip and at least one diode chip on the first conductive layer to form an electrical connection with the first conductive layer;
在所述第一绝缘介质基板上设置一绝缘层,将所述开关管芯片和二极管芯片包覆在内;An insulating layer is disposed on the first insulating dielectric substrate to encapsulate the switch chip and the diode chip;
所述绝缘层上设置第二导电层,开设穿透所述绝缘层和第二导电层的通孔,并在所述通孔内填充导电物质,使所述第二导电层通过所述通孔内的导电物质与所述第一导电层电气连接,以及将开关管芯片和二极管芯片电路连接。Providing a second conductive layer on the insulating layer, opening a through hole penetrating the insulating layer and the second conductive layer, and filling a conductive material in the through hole, so that the second conductive layer passes through the through hole The conductive material inside is electrically connected to the first conductive layer, and the switch transistor chip and the diode chip are electrically connected.
与现有技术相比,本发明至少具有以下优点:Compared with the prior art, the present invention has at least the following advantages:
上述的功率模块及其制造方法模块封装无需开塑封模,节省了生产成本;另外,功率半导体芯片通过在绝缘层上开设通孔并填充导电物质与上层的导电层实现电气连接,减小了模块的体积,有利于模块小型化。The above power module and its manufacturing method module package do not need to be opened and sealed, which saves production cost; in addition, the power semiconductor chip is electrically connected by opening a through hole in the insulating layer and filling the conductive material with the upper conductive layer, thereby reducing the module. The volume is conducive to the miniaturization of the module.
附图说明DRAWINGS
图1为本发明第一实施例中功率模块的结构示意图;1 is a schematic structural view of a power module according to a first embodiment of the present invention;
图2为本发明第二实施例中功率模块的结构示意图;2 is a schematic structural diagram of a power module according to a second embodiment of the present invention;
图3为本发明功率模块整体布局一种实施例的结构示意图;3 is a schematic structural diagram of an embodiment of a power module overall layout according to the present invention;
图4为本发明实施例中散热平板的结构示意图;4 is a schematic structural view of a heat dissipation flat plate according to an embodiment of the present invention;
图5为本发明较佳实施例中功率模块的制造方法的流程图。5 is a flow chart of a method of fabricating a power module in accordance with a preferred embodiment of the present invention.
具体实施方式detailed description
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
请参阅图1至图4,本发明较佳实施例中的功率模块包括绝缘介质基板10、 至少一个开关管芯片20、至少一个二极管芯片30、绝缘层40及第二导电层50。Referring to FIG. 1 to FIG. 4 , the power module in the preferred embodiment of the present invention includes an insulating dielectric substrate 10 , at least one switch chip 20 , at least one diode chip 30 , an insulating layer 40 , and a second conductive layer 50 .
绝缘介质基板10具有相对设置的上下表面,其中至少一个表面覆金属,中间层为陶瓷层11。本实施例中,绝缘介质基板10的上表面覆金属形成图形化的第一导电层12,而下表面可以覆金属形成另一个图形化的导电层13,也可以直接设置散热翅片14(参阅图2)。The insulating dielectric substrate 10 has oppositely disposed upper and lower surfaces, at least one of which is coated with a metal, and the intermediate layer is a ceramic layer 11. In this embodiment, the upper surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the lower surface may be covered with a metal to form another patterned conductive layer 13. Alternatively, the heat dissipating fins 14 may be directly disposed (see figure 2).
本实施例中的开关管芯片20为IGBT,二极管芯片30为FRD(Fast Recovery Diode,快速恢复二极管),功率模块具有一个或多个IGBT和一个或多个FRD以构成驱动电路。开关管芯片20其上下表面均具有极性引脚,本实施例中,开关管芯片20上表面具有两个极性引脚,分别是门极和发射极,下表面具有集电极。二极管芯片30上表面具有阳极,下表面具有阴极,或反之。The switch tube chip 20 in this embodiment is an IGBT, and the diode chip 30 is an FRD (Fast Recovery Diode). The power module has one or more IGBTs and one or more FRDs to constitute a drive circuit. The upper and lower surfaces of the switch tube chip 20 have polarity pins. In this embodiment, the upper surface of the switch tube chip 20 has two polarity pins, which are a gate and an emitter, respectively, and a lower surface has a collector. The upper surface of the diode chip 30 has an anode, and the lower surface has a cathode, or vice versa.
开关管芯片20和二极管芯片30贴设于所述绝缘介质基板10的上表面上,与所述第一导电层12形成电气连接。具体地,在第一导电层12上形成电路图案,开关管芯片20和二极管芯片30通过焊接或压接的方式贴设于电路图案上时,其下表面的极性引脚与对应的电路图案形成电路连接以引出。The switch tube chip 20 and the diode chip 30 are attached to the upper surface of the insulating dielectric substrate 10 to form an electrical connection with the first conductive layer 12. Specifically, when a circuit pattern is formed on the first conductive layer 12, and the switch chip 20 and the diode chip 30 are attached to the circuit pattern by soldering or crimping, the polarity pins of the lower surface and the corresponding circuit patterns are formed. A circuit connection is formed to lead.
绝缘层40覆盖于所述绝缘介质基板10上,将所述开关管芯片20、二极管芯片30和所述第一导电层12包覆在内,绝缘层40通过层压的方式覆盖在绝缘介质基板10上。具体地,在产品中,绝缘层40的下表面开设有用于收容开关管芯片20和二极管芯片30的凹槽。所述绝缘层40的预设位置开设有多个贯穿其上下表面的通孔42。如图1和图2所示,该多个通孔42贯穿绝缘层40分别到达开关管芯片20、二极管芯片30、所述第一导电层12和第二导电层50,且所述通孔42内填充有与所述开关管芯片20、二极管芯片30、所述第一导电层12和第二导电层50电气连接的导电物质。如图3所示,该多个通孔42贯穿第二导电层50和绝缘层40分别到达开关管芯片20、二极管芯片30和所述第一导电层12,且所述通孔42内填充有与所述开关管芯片20、二极管芯片30、所述第一导电层12和第二导电层50电气连接的导电物质。优选地,在确保金属化通孔42与芯片之间结合的可靠性前提下,同一电路连接路径的通孔42尽可能地多设置,以便保证电路的过流能力及提高芯片上部散热能力。An insulating layer 40 covers the insulating dielectric substrate 10, and the switching transistor chip 20, the diode chip 30, and the first conductive layer 12 are covered, and the insulating layer 40 is covered on the insulating dielectric substrate by lamination. 10 on. Specifically, in the product, the lower surface of the insulating layer 40 is provided with a recess for accommodating the switch tube chip 20 and the diode chip 30. The predetermined position of the insulating layer 40 defines a plurality of through holes 42 extending through the upper and lower surfaces thereof. As shown in FIG. 1 and FIG. 2 , the plurality of through holes 42 extend through the insulating layer 40 to the switch tube chip 20 , the diode chip 30 , the first conductive layer 12 and the second conductive layer 50 , respectively, and the through holes 42 . A conductive material electrically connected to the switch chip 20, the diode chip 30, the first conductive layer 12, and the second conductive layer 50 is filled therein. As shown in FIG. 3, the plurality of through holes 42 extend through the second conductive layer 50 and the insulating layer 40 to the switch chip chip 20, the diode chip 30, and the first conductive layer 12, respectively, and the through holes 42 are filled with A conductive material electrically connected to the switch chip 20, the diode chip 30, the first conductive layer 12, and the second conductive layer 50. Preferably, under the premise of ensuring the reliability of the bonding between the metallized via 42 and the chip, the through holes 42 of the same circuit connection path are disposed as much as possible to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
在制作过程中,本实施例中,绝缘层40由半固化片(Pre-pregnant)加热 并固化形成,加热时同时将通孔42内的导电物质金属化;其中,半固化片主要由树脂和增强材料组成,增强材料可以为玻纤布、纸基和复合材料等,所述半固化片的热膨胀系数与所述开关管芯片20和二极管芯片30的热膨胀系数匹配,避免功率器件由于与封装材料热膨胀系数不匹配而导致的器件所受的应力过大出现的失效问题。In the manufacturing process, in the embodiment, the insulating layer 40 is formed by pre-pregnant heating and curing, and at the same time, the conductive material in the through hole 42 is simultaneously metalized; wherein the prepreg is mainly composed of a resin and a reinforcing material. The reinforcing material may be a fiberglass cloth, a paper base, a composite material or the like, and the coefficient of thermal expansion of the prepreg is matched with the thermal expansion coefficient of the switch tube chip 20 and the diode chip 30 to prevent the power device from being mismatched with the thermal expansion coefficient of the packaging material. The failure of the device is subject to excessive stress.
第二导电层50设置于所述绝缘层40之上,具体是通过层压的方式叠设在绝缘层40上。第二导电层50通过该导电物质分别与所述开关管芯片20、二极管芯片30以及第一导电层12电气连接,并通过所述导电物质将所述开关管芯片20和二极管芯片30电路连接。本实施例中,第二导电层50上形成电路图案,开关管芯片20上表面的极性引脚与对应的电路图案形成电气连接以引出。如此,开关管芯片20通过开设在绝缘层40上金属化的通孔42与第二导电层50实现电气连接,从而取代电气转接块以实现电气连接,减小了模块的体积,有利于模块小型化。The second conductive layer 50 is disposed on the insulating layer 40, specifically, laminated on the insulating layer 40 by lamination. The second conductive layer 50 is electrically connected to the switch chip 20, the diode chip 30, and the first conductive layer 12 through the conductive material, and the switch chip 20 and the diode chip 30 are electrically connected by the conductive material. In this embodiment, a circuit pattern is formed on the second conductive layer 50, and the polarity pins on the upper surface of the switch tube chip 20 are electrically connected to the corresponding circuit patterns for extraction. In this manner, the switch chip 20 is electrically connected to the second conductive layer 50 through the through hole 42 which is formed on the insulating layer 40, thereby replacing the electrical transfer block to achieve electrical connection, thereby reducing the volume of the module and facilitating the module. miniaturization.
所列实施例中的绝缘介质基板10不限于DBC(Direct Bond Copper,覆铜陶瓷基板)基板,也可为DBA(Direct Bond Aluminum,覆铝陶瓷基板)基板,或为其他任何表面覆金属绝缘介质基板,参考图1。另外实施例中,绝缘介质基板10也可以是一表面覆铜,另一表面设置散热翅片14的覆铜陶瓷基板,参考图2。The insulating dielectric substrate 10 in the listed embodiment is not limited to a DBC (Direct Bond Copper) substrate, and may be a DBA (Direct Bond Aluminum) substrate, or any other surface-covered metal insulating medium. Substrate, refer to Figure 1. In another embodiment, the insulating dielectric substrate 10 may be a copper-clad ceramic substrate having a surface coated with copper and the other surface provided with heat dissipating fins 14, as shown in FIG.
本实施例中,第二导电层50为导电金属片,具体可以是铜片、铝片或者其他导电金属材料制作而成。在其他实施方式中,第二导电层50可以由另一绝缘介质基板的下表面覆金属构成。另一绝缘介质基板具有相对设置的上下表面,其中至少一个表面覆金属构成第二导电层50,中间层为陶瓷层。而上表面可以覆金属形成另一个导电层,也可以设置散热翅片。In this embodiment, the second conductive layer 50 is a conductive metal sheet, and may be made of a copper sheet, an aluminum sheet or other conductive metal material. In other embodiments, the second conductive layer 50 may be made of a metal coated with a lower surface of another insulating dielectric substrate. Another insulating dielectric substrate has opposite upper and lower surfaces, at least one of which is coated with a metal to form a second conductive layer 50, and the intermediate layer is a ceramic layer. The upper surface may be coated with metal to form another conductive layer, and heat dissipating fins may also be provided.
具体的,功率模块还包括引出端子60(即功率模块引脚),引出端子60的一端与所述第一导电层12或所述第二导电层50固定电气连接,并配合所述通孔42内的导电物质电气连接到所述开关管芯片20和二极管芯片30相应的极性引脚上,所述引出端子60的另一端向外伸出。引出端子60用于将开关管芯片20和二极管芯片30以预设电路的形式将电路的端子引出以用作与外部电路连接。引出端子60可以固定在第一导电层12上,也可以固定在第二导电层 50上。Specifically, the power module further includes a lead terminal 60 (ie, a power module pin), and one end of the lead terminal 60 is fixedly electrically connected to the first conductive layer 12 or the second conductive layer 50, and the through hole 42 is matched. The conductive material inside is electrically connected to the corresponding polarity pins of the switch tube chip 20 and the diode chip 30, and the other end of the lead terminal 60 is outwardly extended. The lead terminal 60 is for taking the switch tube chip 20 and the diode chip 30 out of the terminals of the circuit in a preset circuit for connection with an external circuit. The lead terminal 60 may be fixed to the first conductive layer 12 or may be fixed to the second conductive layer 50.
本实施例中,以引出端子60固定在第一导电层12为例说明。In this embodiment, the first terminal 12 is fixed to the first conductive layer 12 as an example.
引出端子60包括控制端子62和功率端子61,功率端子61包括发射极功率端子61A和集电极功率端子61B,所述第一导电层12包括位于功率模块相对两侧的第一电路图案121和第二电路图案122,第一电路图案121包括并排设置在功率模块的提同一侧的发射极焊盘121A和集电极焊盘121B。所述开关管芯片20和二极管芯片30下表面的极性引脚与第一电路图案121的集电极焊盘121B电气连接,集电极功率端子61B与集电极焊盘121B电气连接;所述开关管芯片20和二极管芯片30上表面的极性引脚分别通过对应的所述通孔42内的导电物质以及所述第二导电层50分别电气连接到所述第一电路图案121的发射极焊盘121A和第二电路图案122,所述控制端子62和第二电路图案122焊接,发射极功率端子61A和所述第一电路图案121的发射极焊盘121A焊接。可以理解的是第二电路图案122也为引脚焊盘。The lead terminal 60 includes a control terminal 62 including an emitter power terminal 61A and a collector power terminal 61B, and a collector power terminal 61B, the first conductive layer 12 including a first circuit pattern 121 and a first portion on opposite sides of the power module The two circuit patterns 122 include a emitter pad 121A and a collector pad 121B which are disposed side by side on the same side of the power module. The switch pin chip 20 and the polarity pin on the lower surface of the diode chip 30 are electrically connected to the collector pad 121B of the first circuit pattern 121, and the collector power terminal 61B is electrically connected to the collector pad 121B; The polarity pins of the upper surface of the chip 20 and the diode chip 30 are electrically connected to the emitter pads of the first circuit pattern 121 through the conductive materials in the corresponding through holes 42 and the second conductive layer 50, respectively. 121A and the second circuit pattern 122, the control terminal 62 and the second circuit pattern 122 are soldered, and the emitter power terminal 61A and the emitter pad 121A of the first circuit pattern 121 are soldered. It can be understood that the second circuit pattern 122 is also a pin pad.
更具体地,第二导电层50包括第三电路图案51和第四电路图案52,第一电路图案121通过对应的所述通孔42内的导电物质及第三电路图案51连接到开关管芯片20和二极管芯片30上表面的极性引脚。第二电路图案122通过对应的所述通孔42内的导电物质和第四电路图案52连接到开关管芯片20上表面的极性引脚。本实施例中,开关管芯片20与第一电路图案121的发射极焊盘121A电气连接的是发射极,与第二电路图案122电气连接的是门极,与第一电路图案12的集电极焊盘121B电气连接的是集电极。More specifically, the second conductive layer 50 includes a third circuit pattern 51 and a fourth circuit pattern 52. The first circuit pattern 121 is connected to the switch chip through the conductive material in the corresponding through hole 42 and the third circuit pattern 51. 20 and a polarity pin on the upper surface of the diode chip 30. The second circuit pattern 122 is connected to the polarity pin of the upper surface of the switch tube chip 20 through the conductive material in the corresponding through hole 42 and the fourth circuit pattern 52. In this embodiment, the switch tube chip 20 is electrically connected to the emitter pad 121A of the first circuit pattern 121, and is electrically connected to the second circuit pattern 122, and is connected to the collector of the first circuit pattern 12. The pad 121B is electrically connected to a collector.
图3是功率模块整体布局图示意图。图中填充区域为第一导电层12大致所示图形化,线框加黑区域为第二导电层50大致所示图形化。开关管芯片20及二极管芯片30焊接在第一导电层12对应位置,控制端子62及功率端子61也焊接在第一导电层12对应位置,经由金属化的通孔42使得芯片极性与对应端子形成电气连接。控制端子62及功率端子61分别位于模块两侧,低压控制端远离高压功率端,减小了高压端对低压端的电气干扰,提高了控制端的可靠性。Figure 3 is a schematic diagram of the overall layout of the power module. The filled area in the figure is substantially graphically patterned for the first conductive layer 12, and the blackened area of the wire frame is substantially graphically patterned for the second conductive layer 50. The switch tube chip 20 and the diode chip 30 are soldered to the corresponding positions of the first conductive layer 12, and the control terminal 62 and the power terminal 61 are also soldered to the corresponding positions of the first conductive layer 12, and the chip polarity and the corresponding terminal are made via the metalized through holes 42. Form an electrical connection. The control terminal 62 and the power terminal 61 are respectively located on both sides of the module, and the low voltage control end is away from the high voltage power end, which reduces the electrical interference of the high voltage end to the low voltage end, and improves the reliability of the control end.
具体的,请参阅图1、2和3,功率模块还包括散热器70,所述散热器70设置所述绝缘介质基板10的下表面和/或所述第二导电层50的上表面。散热 器70可由覆金属绝缘介质基板10直接构成(如散热翅片14),也可外部另行设置。散热器70可单独设置在功率模块下表面,也可设置在功率模块上下表面实现双面散热。具体地,绝缘介质基板10的下表面和/或所述第二导电层50的上表面通过绝缘导热胶80后与散热器70连接。散热器70为散热翅片或平板热管。图4是平板热管示意图。开关管芯片20及二极管芯片30产生的热传导到热管蒸发面71,毛细管中工作液72吸收热量汽化并充满蒸汽腔。平板热管70的冷凝面73采用循环冷却液进行冷却。蒸汽90在冷凝面73重新凝结成液体,在毛细芯74的毛吸力作用下,液体重新流回蒸发面71,重复上述步骤实现循环散热。Specifically, referring to FIGS. 1 , 2 and 3 , the power module further includes a heat sink 70 that is disposed on a lower surface of the insulating dielectric substrate 10 and/or an upper surface of the second conductive layer 50 . The heat sink 70 may be directly formed of a metal-clad insulating dielectric substrate 10 (e.g., heat dissipating fins 14), or may be separately provided externally. The heat sink 70 can be separately disposed on the lower surface of the power module, or can be disposed on the upper and lower surfaces of the power module to achieve double-sided heat dissipation. Specifically, the lower surface of the insulating dielectric substrate 10 and/or the upper surface of the second conductive layer 50 are connected to the heat sink 70 through the insulating thermally conductive adhesive 80. The heat sink 70 is a heat dissipating fin or a flat heat pipe. Figure 4 is a schematic view of a flat heat pipe. The heat generated by the switch tube chip 20 and the diode chip 30 is conducted to the heat pipe evaporation surface 71, and the working fluid 72 in the capillary absorbs heat and vaporizes and fills the steam chamber. The condensing surface 73 of the flat heat pipe 70 is cooled by circulating cooling liquid. The steam 90 is recondensed into a liquid on the condensation surface 73. Under the action of the capillary suction force of the capillary core 74, the liquid re-flows back to the evaporation surface 71, and the above steps are repeated to achieve circulating heat dissipation.
此外,请结合图1至图5,还公开了一种可制造上述功率模块的制造方法,包括以下步骤:In addition, in conjunction with FIG. 1 to FIG. 5, a manufacturing method capable of manufacturing the above power module is further disclosed, including the following steps:
S110,设置一上表面具有第一导电层12的绝缘介质基板10。S110, an insulating dielectric substrate 10 having a first conductive layer 12 on its upper surface is disposed.
在该步骤中,所提供的绝缘介质基板10应具有相对设置的上下表面,其中至少一个表面覆金属。本实施例中,绝缘介质基板10的上表面覆金属形成图形化的第一导电层12,而下表面可以覆金属形成另一个导电层,也可以设置散热翅片14(参阅图3);并且,第一导电层12上应预设相应的电路图案。In this step, the insulating dielectric substrate 10 is provided to have oppositely disposed upper and lower surfaces, at least one of which is metal-coated. In this embodiment, the upper surface of the insulating dielectric substrate 10 is covered with a metal to form a patterned first conductive layer 12, and the lower surface may be covered with a metal to form another conductive layer, and the heat dissipating fins 14 may be disposed (see FIG. 3); A corresponding circuit pattern should be preset on the first conductive layer 12.
S120,将至少一个开关管芯片20和至少一个二极管芯片30设于所述第一导电层12上,与所述第一导电层12形成电气连接。S120, at least one switch chip 20 and at least one diode chip 30 are disposed on the first conductive layer 12 to form an electrical connection with the first conductive layer 12.
具体地,开关管芯片20为IGBT,二极管芯片30为FRD。芯片上下表面均具有极性引脚,开关管芯片20贴设于所述绝缘介质基板10的上表面上,与所述第一导电层12形成电气连接。具体地,开关管芯片20和二极管芯片30通过焊接或压接的方式贴设于第一导电层12的电路图案上时,其下表面的极性引脚与对应的电路图案形成电路连接以引出。Specifically, the switch transistor chip 20 is an IGBT, and the diode chip 30 is an FRD. The upper and lower surfaces of the chip have polar pins, and the switch chip 20 is attached to the upper surface of the insulating dielectric substrate 10 to form an electrical connection with the first conductive layer 12. Specifically, when the switch chip 20 and the diode chip 30 are attached to the circuit pattern of the first conductive layer 12 by soldering or crimping, the polarity pins of the lower surface are connected to the corresponding circuit pattern forming circuit to be led out. .
S130,在所述第一绝缘介质基板10上设置一绝缘层40,将所述开关管芯片20和二极管芯片30包覆在内。S130, an insulating layer 40 is disposed on the first insulating dielectric substrate 10, and the switch tube chip 20 and the diode chip 30 are covered.
本实施例中,所述绝缘层40为半固化片,半固化片是绝缘的,且其热膨胀系数需尽量与开关管芯片20的热膨胀系数匹配。In this embodiment, the insulating layer 40 is a prepreg, and the prepreg is insulated, and its thermal expansion coefficient needs to be matched with the thermal expansion coefficient of the switch chip 20 as much as possible.
S140,在所述绝缘层40上设置第二导电层50。第二导电层50优选为导电金属片。将所述第二导电层50(导电金属片或第二绝缘介质基板)、半固化 片和设有所述开关管芯片20和二极管芯片30的绝缘介质基板10依次层叠压合,使半固化片流胶填充并覆盖开关管芯片20和二极管芯片30。S140, a second conductive layer 50 is disposed on the insulating layer 40. The second conductive layer 50 is preferably a conductive metal sheet. The second conductive layer 50 (conductive metal sheet or second insulating dielectric substrate), the prepreg, and the insulating dielectric substrate 10 provided with the switch tube chip 20 and the diode chip 30 are sequentially laminated and pressed, and the prepreg is filled with glue. The switch tube chip 20 and the diode chip 30 are covered.
开设穿透所述绝缘层40和第二导电层50的通孔42,并在所述通孔42内填充导电物质,使所述第二导电层50通过所述通孔42内的导电物质与所述第一导电层12电气连接,以及将开关管芯片20和二极管芯片30电路连接。Opening a through hole 42 penetrating the insulating layer 40 and the second conductive layer 50, and filling the through hole 42 with a conductive material, so that the second conductive layer 50 passes through the conductive material in the through hole 42 and The first conductive layer 12 is electrically connected, and the switch transistor chip 20 and the diode chip 30 are electrically connected.
具体地,在第二导电层50和绝缘层40上采用激光技术制作到达开关管芯片20和二极管芯片30的极性引脚,以及到达第一导电层12的通孔42,在所述通孔42内填充导电物质使通孔42金属化。第二导电层50在层压之前或之后需制作电路图案,开关管芯片20和二极管芯片30上表面的极性引脚通过金属化的通孔42与对应的电路图案形成电路连接。Specifically, a polarity pin reaching the switch transistor chip 20 and the diode chip 30 and a via hole 42 reaching the first conductive layer 12 are formed on the second conductive layer 50 and the insulating layer 40 by laser technology, and the through hole is formed in the through hole The conductive material is filled in 42 to metalize the via hole 42. The second conductive layer 50 needs to be formed with a circuit pattern before or after lamination, and the polarity pins of the switch tube chip 20 and the upper surface of the diode chip 30 are connected to the corresponding circuit pattern forming circuits through the metalized via holes 42.
更具体的实施例中,在步骤S120中还包括:还设置引出端子60,使所述引出端子60的一端与所述第一导电层12固定电气连接,另一端向外伸出的步骤。在其他实施方式中,可以设置图形化的第二导电层50时,设置引出端子,将使所述引出端子60的一端与所述第二导电层50固定电气连接,另一端向外伸出。引出端子包括控制端子62和功率端子61,所述控制端子62和功率端子61分别位于功率模块相对两侧。低压控制端远离高压功率端,减小了高压端对低压端的电气干扰,提高了控制端的可靠性。In a more specific embodiment, the step S120 further includes: further providing a lead-out terminal 60, wherein the one end of the lead-out terminal 60 is fixedly electrically connected to the first conductive layer 12, and the other end is outwardly extended. In other embodiments, when the patterned second conductive layer 50 can be disposed, the lead-out terminal is provided, and one end of the lead-out terminal 60 is fixedly electrically connected to the second conductive layer 50, and the other end is outwardly extended. The lead terminal includes a control terminal 62 and a power terminal 61, and the control terminal 62 and the power terminal 61 are respectively located on opposite sides of the power module. The low voltage control terminal is away from the high voltage power terminal, which reduces the electrical interference of the high voltage terminal to the low voltage terminal and improves the reliability of the control terminal.
进一步地,所述方法还包括加热的步骤,通过加热使所述半固化片固化实现绝缘。Further, the method further includes the step of heating to cure the prepreg by heating to achieve insulation.
进一步地,所述方法还包括设置于所述绝缘介质基板的下表面和/或所述第二导电层的上表面的散热器的步骤。Further, the method further includes the step of disposing a heat sink disposed on a lower surface of the insulating dielectric substrate and/or an upper surface of the second conductive layer.
可见,上述的制作方法均在制作功率模块是封装无需开塑封模,节省了生产成本;芯片通过金属化的通孔42实现电气连接,减小了模块的体积,有利于模块小型化。It can be seen that the above manufacturing method is that the power module is manufactured without encapsulation, and the production cost is saved; the chip is electrically connected through the metalized through hole 42 to reduce the volume of the module and facilitate the miniaturization of the module.
更具体地,功率模块的制造方法为:将开关管芯片20和二极管芯片30、控制端子62及功率端子61均焊接在绝缘介质基板10图形化的第一导电层12上,将相应厚度的半固化片(绝缘层)40、第二导电层50与贴有芯片的绝缘介质基板10进行层压,使半固化片40的流胶填充并覆盖芯片,其中,半固化片40是绝缘的,且其热膨胀系数需尽量与功率器件热膨胀系数匹配。匹配是 指两个热膨胀系数的数值尽可能接近或相等。首先对层压后模块的第二导电层50图形化,再采用激光技术制作通孔42并金属化,使得芯片极性引脚与对应引出端子60形成电气连接。在确保金属化通孔42与芯片之间结合的可靠性前提下通孔42尽可能地多设置,以便保证电路的过流能力及提高芯片上部散热能力。模块(绝缘介质基板10)下表面由散热器70进行散热,模块(第二导电层50)上表面涂上绝缘导热胶80后与另一个散热器70连接散热,以此实现双面散热,提高散热能力。两个散热器70不一定需要同时设置,在能够满足散热条件情况下,也可仅由下表面的散热器70单独构成单面散热。More specifically, the power module is manufactured by soldering the switch chip 20 and the diode chip 30, the control terminal 62, and the power terminal 61 to the first conductive layer 12 patterned on the insulating dielectric substrate 10 to form a prepreg of a corresponding thickness. (Insulating layer) 40, the second conductive layer 50 is laminated with the chip-attached insulating dielectric substrate 10, and the flow of the prepreg 40 is filled and covers the chip. The prepreg 40 is insulated, and the coefficient of thermal expansion needs to be as large as possible. The thermal expansion coefficient of the power device is matched. Matching means that the values of the two coefficients of thermal expansion are as close as possible or equal. First, the second conductive layer 50 of the laminated module is patterned, and the via hole 42 is formed by laser technology and metallized, so that the chip polarity pin and the corresponding lead terminal 60 are electrically connected. The via hole 42 is disposed as much as possible in order to ensure the reliability of the bonding between the metallized via 42 and the chip, so as to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip. The lower surface of the module (insulating dielectric substrate 10) is dissipated by the heat sink 70, and the upper surface of the module (second conductive layer 50) is coated with an insulating thermal conductive adhesive 80, and then connected to the other heat sink 70 to dissipate heat, thereby achieving double-sided heat dissipation and improving Cooling capacity. The two heat sinks 70 do not necessarily need to be disposed at the same time, and in the case where the heat dissipation condition can be satisfied, the heat sink 70 on the lower surface alone may constitute a single-sided heat dissipation.
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制。虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。The above description is only a preferred embodiment of the invention and is not intended to limit the invention in any way. While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above, or modify the equivalents of equivalent changes without departing from the scope of the technical solutions of the present invention. Example. Therefore, any simple modifications, equivalent changes, and modifications of the above embodiments may be made without departing from the spirit and scope of the invention.

Claims (13)

  1. 一种功率模块,其特征在于,包括:A power module, comprising:
    绝缘介质基板,其上表面具有图形化的第一导电层;An insulating dielectric substrate having a patterned first conductive layer on an upper surface thereof;
    至少一个开关管芯片和至少一个二极管芯片,所述开关管芯片和二极管芯片贴设于所述绝缘介质基板的上表面上,与所述第一导电层形成电气连接;At least one switch tube chip and at least one diode chip, the switch tube chip and the diode chip are attached on an upper surface of the insulating dielectric substrate to form an electrical connection with the first conductive layer;
    绝缘层,覆盖于所述绝缘介质基板上,将所述开关管芯片和二极管芯片包覆在内,所述绝缘层开设有贯穿其上下表面的通孔,且所述通孔内填充有导电物质;An insulating layer covering the insulating dielectric substrate, the switching tube chip and the diode chip are covered, the insulating layer is provided with a through hole penetrating the upper and lower surfaces thereof, and the through hole is filled with a conductive substance ;
    图形化的第二导电层,设置于所述绝缘层之上,以使所述第二导电层通过所述导电物质与所述第一导电层导电连接,并通过所述导电物质将所述开关管芯片和二极管芯片电路连接。a patterned second conductive layer disposed on the insulating layer such that the second conductive layer is electrically connected to the first conductive layer through the conductive material, and the switch is turned by the conductive material The tube chip and the diode chip are electrically connected.
  2. 如权利要求1所述的功率模块,其特征在于,所述绝缘层为半固化片。The power module of claim 1 wherein said insulating layer is a prepreg.
  3. 如权利要求1或2所述的功率模块,其特征在于,还包括引出端子,所述引出端子的一端与所述第一导电层或所述第二导电层固定电气连接,并配合所述通孔内的导电物质电气连接到所述开关管芯片和二极管芯片相应的极性引脚上,所述引出端子的另一端向外伸出。The power module according to claim 1 or 2, further comprising a lead terminal, one end of the lead terminal being fixedly electrically connected to the first conductive layer or the second conductive layer, and matching the through The conductive material in the hole is electrically connected to the corresponding polarity pin of the switch tube chip and the diode chip, and the other end of the lead terminal protrudes outward.
  4. 如权利要求3所述的功率模块,其特征在于,所述引出端子包括控制端子和功率端子,所述第一导电层包括位于功率模块相对两侧的第一电路图案和第二电路图案;The power module according to claim 3, wherein the lead terminal comprises a control terminal and a power terminal, and the first conductive layer comprises a first circuit pattern and a second circuit pattern on opposite sides of the power module;
    所述开关管芯片和二极管芯片的极性引脚分别通过对应的所述通孔内的导电物质以及所述第二导电层分别电气连接到所述第一电路图案和第二电路图案,所述控制端子和功率端子分别和所述第一电路图案和第二电路图案固定电气连接。The polarity pins of the switch chip and the diode chip are respectively electrically connected to the first circuit pattern and the second circuit pattern through the conductive material in the corresponding through hole and the second conductive layer, respectively. The control terminal and the power terminal are fixedly electrically connected to the first circuit pattern and the second circuit pattern, respectively.
  5. 如权利要求4所述的功率模块,其特征在于,所述第一电路图案包括发射极焊盘和集电极焊盘,所述功率端子包括分别与发射极焊盘和集电极焊盘焊接的发射极功率端子和集电极功率端子。The power module of claim 4 wherein said first circuit pattern comprises an emitter pad and a collector pad, said power terminal comprising an emission soldered to the emitter pad and the collector pad, respectively Extreme power terminal and collector power terminal.
  6. 如权利要求1-5任意一项所述的功率模块,其特征在于,还包括散热器,所述散热器设置于所述绝缘介质基板的下表面和/或所述第二导电层的上表 面。The power module according to any one of claims 1 to 5, further comprising a heat sink disposed on a lower surface of the insulating dielectric substrate and/or an upper surface of the second conductive layer .
  7. 如权利要求6所述的功率模块,其特征在于,所述散热器为散热翅片或平板热管。The power module of claim 6 wherein said heat sink is a heat dissipating fin or a flat heat pipe.
  8. 如权利要求1-7任意一项所述的功率模块,其特征在于,所述通孔还贯穿所述第二导电层。The power module according to any one of claims 1 to 7, wherein the through hole further penetrates the second conductive layer.
  9. 一种功率模块的制造方法,其特征在于,包括以下步骤:A method of manufacturing a power module, comprising the steps of:
    设置一上表面具有第一导电层的绝缘介质基板;Providing an insulating dielectric substrate having a first conductive layer on the upper surface;
    将至少一个开关管芯片和至少一个二极管芯片设于所述第一导电层上,与所述第一导电层形成电气连接;Providing at least one switch chip and at least one diode chip on the first conductive layer to form an electrical connection with the first conductive layer;
    在所述第一绝缘介质基板上设置一绝缘层,将所述开关管芯片和二极管芯片包覆在内;An insulating layer is disposed on the first insulating dielectric substrate to encapsulate the switch chip and the diode chip;
    在所述绝缘层上设置第二导电层,开设穿透所述绝缘层和第二导电层的通孔,并在所述通孔内填充导电物质,使所述第二导电层通过所述通孔内的导电物质与所述第一导电层电气连接,以及将开关管芯片和二极管芯片电路连接。Providing a second conductive layer on the insulating layer, opening a through hole penetrating the insulating layer and the second conductive layer, and filling a conductive material in the through hole, so that the second conductive layer passes through the through hole A conductive substance in the hole is electrically connected to the first conductive layer, and the switch tube chip and the diode chip are electrically connected.
  10. 如权利要求9所述的功率模块的制造方法,其特征在于,在将至少一个开关管芯片和至少一个二极管芯片设于所述第一导电层上时,还设置引出端子,使所述引出端子的一端与所述第一导电层固定电气连接,另一端向外伸出;或,The method of manufacturing a power module according to claim 9, wherein when at least one of the switch tube chips and the at least one diode chip are disposed on the first conductive layer, a lead terminal is further provided to cause the lead terminal One end is fixedly electrically connected to the first conductive layer, and the other end is outwardly extended; or
    设置第二导电层时,设置引出端子,使所述引出端子的一端与所述第二导电层固定电气连接,另一端向外伸出。When the second conductive layer is disposed, the lead-out terminal is disposed such that one end of the lead-out terminal is fixedly electrically connected to the second conductive layer, and the other end is outwardly extended.
  11. 如权利要求10所述的半桥功率模块的制造方法,其特征在于,所述引出端子包括控制端子和功率端子,所述控制端子和功率端子分别位于所述功率模块相对两侧。The method of manufacturing a half-bridge power module according to claim 10, wherein the lead-out terminal comprises a control terminal and a power terminal, and the control terminal and the power terminal are respectively located on opposite sides of the power module.
  12. 如权利要求9-11任意一项所述的功率模块的制造方法,其特征在于,所述方法还包括加热的步骤;其中,所述绝缘层为半固化片,通过加热使所述半固化片固化实现绝缘。The method of manufacturing a power module according to any one of claims 9 to 11, characterized in that the method further comprises the step of heating; wherein the insulating layer is a prepreg, and the prepreg is cured by heating to achieve insulation.
  13. 如权利要求9-12任意一项所述的功率模块的制造方法,其特征在于,还包括设置于所述绝缘介质基板的下表面和/或所述第二导电层的上表面的散 热器。The method of manufacturing a power module according to any one of claims 9 to 12, further comprising a heat dissipator disposed on a lower surface of the insulating dielectric substrate and/or an upper surface of the second conductive layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110120354A (en) * 2019-05-06 2019-08-13 珠海格力电器股份有限公司 The packaging method and intelligent power module of intelligent power module

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113782498A (en) * 2021-07-27 2021-12-10 华为数字能源技术有限公司 Power module and power device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7829386B2 (en) * 2005-08-17 2010-11-09 General Electric Company Power semiconductor packaging method and structure
CN102460693A (en) * 2009-06-19 2012-05-16 株式会社安川电机 Power converter
CN104900609A (en) * 2014-03-05 2015-09-09 台达电子国际(新加坡)私人有限公司 Package structure
CN105006453A (en) * 2014-04-17 2015-10-28 台达电子国际(新加坡)私人有限公司 Package structure
CN106206483A (en) * 2015-05-29 2016-12-07 台达电子国际(新加坡)私人有限公司 Power module

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8455987B1 (en) * 2009-06-16 2013-06-04 Ixys Corporation Electrically isolated power semiconductor package with optimized layout
CN102800636B (en) * 2012-08-28 2015-02-18 中国科学院微电子研究所 Electronic component package and manufacturing method thereof
SG10201400396WA (en) * 2014-03-05 2015-10-29 Delta Electronics Int’L Singapore Pte Ltd Package structure and stacked package module with the same
KR20160049786A (en) * 2014-10-28 2016-05-10 현대모비스 주식회사 Power module and pakaking method thereof
CN105161467B (en) * 2015-08-14 2019-06-28 株洲南车时代电气股份有限公司 A kind of power module for electric car
CN205069617U (en) * 2015-09-29 2016-03-02 比亚迪股份有限公司 Power module and vehicle that has it

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7829386B2 (en) * 2005-08-17 2010-11-09 General Electric Company Power semiconductor packaging method and structure
CN102460693A (en) * 2009-06-19 2012-05-16 株式会社安川电机 Power converter
CN104900609A (en) * 2014-03-05 2015-09-09 台达电子国际(新加坡)私人有限公司 Package structure
CN105006453A (en) * 2014-04-17 2015-10-28 台达电子国际(新加坡)私人有限公司 Package structure
CN106206483A (en) * 2015-05-29 2016-12-07 台达电子国际(新加坡)私人有限公司 Power module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110120354A (en) * 2019-05-06 2019-08-13 珠海格力电器股份有限公司 The packaging method and intelligent power module of intelligent power module

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