WO2018130407A1 - Power module with optimized bond wire layout - Google Patents

Power module with optimized bond wire layout Download PDF

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Publication number
WO2018130407A1
WO2018130407A1 PCT/EP2017/084355 EP2017084355W WO2018130407A1 WO 2018130407 A1 WO2018130407 A1 WO 2018130407A1 EP 2017084355 W EP2017084355 W EP 2017084355W WO 2018130407 A1 WO2018130407 A1 WO 2018130407A1
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WO
WIPO (PCT)
Prior art keywords
power module
bond wires
substrates
semiconductor switches
bond
Prior art date
Application number
PCT/EP2017/084355
Other languages
French (fr)
Inventor
Ole MÜHLFELD
Guido Mannmeusel
Jörg BERGMANN
Original Assignee
Danfoss Silicon Power Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Danfoss Silicon Power Gmbh filed Critical Danfoss Silicon Power Gmbh
Publication of WO2018130407A1 publication Critical patent/WO2018130407A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters

Definitions

  • the present disclosure relates to a power module, and more particularly, to a power module with optimized bond wire layout.
  • a power module may be used for the controlled switching of high currents and can be used in power converters (such as inverters) to convert DC to AC or vice versa, or for converting between different voltages or frequencies of AC.
  • power converters such as inverters
  • inverters are used in motor controllers or interfaces between power generation or storage, or a power distribution grid.
  • a power module may be used in a "grid tie" inverter of a battery storage system. In such a battery storage system, current is supplied to a power supply grid either to stabilize the grid or to provide electrical power during times where the grid electric energy is expensive, i.e. in the morning and in the afternoon.
  • the batteries are recharged during night-time when grid energy cost is lower, or they can be recharged using solar power. Overall, the system helps the customer to reduce expenses for electrical energy.
  • the "grid tie” inverter connects the battery storage system to the grid and has the task to convert the DC voltage of the battery to AC voltage for the grid and vice versa.
  • semiconductor power module which can achieve optimized inductance/resistance ratios to allow for external load characteristics.
  • a power module comprising at least two substrates on which one or more semiconductor switches are mounted, wherein the at least two substrates are connected via a plurality of bond wires, and wherein the plurality of bond wires are optimized to minimize ohmic resistance thereof. That is to say, the plurality of bond wires are placed to have a smallest ohmic resistance that is allowed in design.
  • the plurality of bond wires are placed to have a small cross-sectional area thereof. That is to say, the plurality of bond wires are distributed so that the area of a surface normal to the path of the bond wires and which is bounded by the outermost bond wires has an area, which is smaller than that normally presented in a power module that is designed to minimize both stray inductance and ohmic resistance.
  • the plurality of bond wires are placed to be as close to each other as possible. That is to say, the plurality of bond wires are close to each other, with a gap therebetween far smaller than that normally presented in a power module that is designed to minimize both stray inductance and ohmic resistance.
  • the bond wires may be placed with an offset of a value which is less than 2 times thickness of the bond wires. Preferably, the value may be less than 1 .2 times the thickness of the bond wires.
  • the bond wires may typically be 300pm in diameter. In an example, the bond wires may be placed with an offset of 350pm which is .17 times the bond wire thickness. It means that there is a gap of 25pm between the bond wires. In a typical prior art power module layout that is designed to minimize both stray inductance and ohmic resistance the bond wire offset may be 600pm or more, which is twice the thickness of the bond wires.
  • the plurality of bond wires are placed to be as short as possible. That is to say, each of the plurality of bond wires is shorter than that normally presented in a power module that is designed a trade-off between stray
  • the number of the plurality of bond wires is larger than that needed for current carrying capability. That is to say, the number of bond wires is between 1 .2 and 15 times the number that would be required to ensure absolute temperature and/or temperature cycling are kept within limits required to ensure reliable bonds. In a preferred embodiment, the number may be between 1 .5 and 5 times the number that would be required to ensure absolute temperature and/or temperature cycling are kept within limits required to ensure reliable bonds. In an embodiment, the plurality of bond wires is placed in parallel.
  • the semiconductor switches comprise wide-bandgap
  • the semiconductor switches comprise SiC semiconductors.
  • the semiconductor switches comprise SiC-MOSFETs.
  • the at least two substrates comprise Direct Bonded Copper (DBC) substrates.
  • DBC Direct Bonded Copper
  • Such a substrate is formed by a copper/ceramic/copper sandwich, where a circuit structure may be created in the upper copper layer and which may be populated with semiconductor switches, capacitors and/or resistors as required to form a functioning circuit.
  • the power module is configured to provide power to an inductive load.
  • the plurality of bond wires are placed with an offset of a value which is less than 2 times thickness of the bond wires.
  • the value is less than 1 .2 times the thickness of the bond wires. In an embodiment, the number of the plurality of bond wires is 1 .5 times that needed for current carrying capability.
  • Fig. 1 shows a cross section view of a power module according to an embodiment of the present disclosure
  • Fig. 2 shows a perspective view of the power module according to the
  • FIG. 3 shows a view of a power module with lid placed according to an
  • Fig. 4 shows a diagram of a circuit structure of an exemplary power module according to an embodiment of the present disclosure.
  • Fig. 5 shows a top view of an exemplary power module according to an
  • Fig. 6 shows an example of an assembly where two substrates are connected with bond wires, where (a) shows that the bond wires are less dense and longer, while (b) shows that the bond wires are denser and shorter; and Fig. 7 shows the effect of the assembly shown in Fig. 6.
  • first and second etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of example embodiments.
  • the term “and/or” includes any and all combinations of one or more of the associated listed terms.
  • Fig. 1 shows a cross section view of a power module 100 according to an embodiment of the present disclosure
  • Fig. 2 shows a perspective view of the power module according to the embodiment of the present disclosure
  • the power module 100 according to an embodiment of the present disclosure comprises a copper baseplate 110 with two substrates 120 soldered on top of it.
  • Direct Bonded Copper (DBC) substrates are used in the power module 100.
  • the DBC substrates are formed by a sandwich of Cu 122 (for example, of 300pm), Ceramics 124 (for example, AIN of 320pm) and Cu 126 (for example, of 300pm) where in the upper Cu layer 122 a circuit structure can be found that holds semiconductor switches 130, capacitors 150 and gate resistors 140.
  • Aluminum bond wires 160 are used for the top-side connection of the die and for
  • the two DBC substrates are connected via bond wires 220.
  • the power module 100 is encapsulated with a molded plastic frame 170 (holding the press-fit contact pins). It is filled with Silicone-gel 180. The frame is fixed by metal bushings 230.
  • the power module 100 is closed by a plastic lid 300.
  • Fig. 3 shows a view of the power module 100 with lid 300 in place.
  • Fig. 4 shows a diagram of a circuit structure of an exemplary power module 400 according to an embodiment of the present disclosure. As shown, there are four semiconductors, T1-T4, and two substrates DBC1 and DBC2 inside the power module. DBC1 holds T1 and T4, and DBC2 holds T2 and T3.
  • the numerals 1-24 in the figure denote pin reference numbers of the power module.
  • the line ringed denotes the connection between the two DBC substrates.
  • Fig. 5 shows a top view of an exemplary power module 500 according to an embodiment of the present disclosure.
  • T1-T4 are doubled compared with those shown in Fig. 4.
  • DBC1 holds T1 and T4
  • DBC2 holds T2 and T3.
  • each transistor in Fig. 4 is realized by two transistors in parallel in Fig. 5.
  • the bond wires ringed denote the connection between the two DBC substrates.
  • the numerals 1- 26 in the figure denote pin reference numbers of the power module.
  • the semiconductor switches, resistors and capacitors are soldered to the DBC substrate. Afterwards the substrate is pre-tested. The tested DBC is then soldered to a 3mm thick copper baseplate covered with nickel plating. Afterwards the plastic frame is mounted; this is done by bonding the frame to the baseplate using silicone glue. In addition, the frame and the base plate are fixed by metal bushings. Afterwards the pins and the substrates are connected in a second bonding step with bond wires. In the final step the module is filled with silicone-gel, the lid is mounted and the module is tested in regards to secure the electrical function. The soldering steps may be combined into a single soldering step in order to save process complexity and hence cost.
  • the power module is designed to fulfill two major characteristics: High power conversion efficiency and high power density. Factors as lifetime, cost and quality are also taken into account.
  • high performance wide-bandgap semiconductors such as Silicon Carbide (SiC) semiconductor switches may be used, as they generally outperform standard silicon based components, i.e.
  • Insulated Gate Bipolar Transistors IGBT.
  • SiC devices put high demands on the design of the power module from thermal and electrical standpoint.
  • the wide-bandgap semiconductors e.g., SiC semiconductor switches
  • the wide-bandgap semiconductors have the characteristic that they switch very fast, meaning that the transition from
  • AIN aluminum-nitride
  • AIN helps to lower the thermal resistance (Rth), thus the semiconductor switch will be operated at reduced temperatures. Since losses in SiC semiconductor switches (for example, SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs)) reduce if the junction temperature is lower, this measure helps to further increase the power module efficiency.
  • SiC semiconductor switches for example, SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs)
  • MOSFETs SiC Metal-Oxide-Semiconductor Field Effect Transistors
  • SiC MOSFETs are used in applications where highest efficiency in small building volume is required by the application.
  • SiC MOSFETs show fast switching speeds and low on-state resistance (Rds.on) at the same time.
  • the die are typically very small (for example, 5-25mm 2 ). This keeps yield losses low, but restricts the total current that a component can pass.
  • several of these small components for example MOSFETs) need to be operated in parallel.
  • a power module may provide power to inductive loads, for example an electrical grid system, or an electrical motor. Such systems are known to be overwhelmingly inductive. Thus the stray inductance of the load is much higher than any stray inductances that are normally generated within the power module. While certain parts of the power module are much more effective with lower stray inductances, this is much less important in the load side of the power module. For such parts of the power module, the stray inductances of the load may often be 100 to 1000 times higher than those found within the power module.
  • the bond wire connection between DBC substrates is directly connected to the load output terminals (pins 11-14 shown in Figs. 4 and 5), and about a half of the total current supplied to the load passes through the connection. Therefore, the connection shall be carefully designed.
  • different bond wire designs can be used for the bond wire connection between DBCs of a power module. Generally, a trade-off between stray inductance and ohmic resistance shall be taken into account. However, if the output terminal of the power module is connected to inductive loads, the optimization of the power module internal phase inductance is not necessary. Instead, the ohmic resistance is in the focus of the optimization.
  • the bond wires are optimized to minimize ohmic resistance thereof.
  • the bond wires are placed to generate a smallest cross-sectional area thereof.
  • Fig. 6 shows an example of an assembly where two substrates 610, 610' are connected with bond wires 620, 620', which connect the Cu layer 630, 630' on respective substrates, where (a) shows that the bond wires 620 are less dense and longer, while (b) shows that the bond wires 620' are denser and shorter, i.e., the bond wires 620' are close to each other.
  • Fig. 7 shows the effect of the assembly shown in Fig. 6, where (a) corresponds to Fig. 6(a) while (b)
  • Fig. 6(b) corresponds to Fig. 6(b).
  • the bond wires 620 are some distance apart, and thus the magnetic fields have low coupling, resulting in low inductance, as shown in Fig. 7(a).
  • ohmic resistance is slightly increased as the bond wires are slightly longer.
  • the bond wires 520' are more densely packed, and thus the magnetic fields have strong coupling, resulting in higher stray inductance, as shown in Fig. 7(b).
  • ohmic resistance is reduced as the bond wires are shorter than those in Fig. 6(a).
  • the bond wires are placed with an offset of a value which is less than 2 times thickness of the bond wires. Preferably, the value is less than 1 .2 times the thickness of the bond wires.
  • the bond wires are typically 300pm in diameter. In an example, the bond wires are placed with an offset of 350pm which is 1 .17 times the bond wire thickness. It means that there is a gap of 25pm between the bond wires.
  • a connection that minimizes stray inductance would have a bond wire spacing of typically 600pm or more, which is 2 times the thickness of the bond wires.
  • the number of the bond wires is 1 .5 times that needed for current carrying capability. If only the current carrying capacity is taken into account in choosing the number of the bond wires, 7 aluminum bond wires would be needed to allow the transmission of normally expected currents. In an embodiment, around 10 aluminum bond wires will be used. The large number of paralleled bond wires reduces stray inductance, which in turns optimize the performance of the power module.
  • the performance of the power module is optimized in regards to ohmic resistance, which is dominant in the resulting performance.

Abstract

The present disclosure provides a power module comprising at least two substrates on which one or more semiconductors are mounted, wherein the at least two substrates are connected via a plurality of bond wires, and wherein the plurality of bond wires are optimized to minimize ohmic resistance thereof.

Description

POWER MODULE WITH OPTIMIZED BOND WIRE LAYOUT
TECHNICAL FIELD
The present disclosure relates to a power module, and more particularly, to a power module with optimized bond wire layout.
BACKGROUND
Semiconductor power modules are widely used in industry. For example, such a power module may be used for the controlled switching of high currents and can be used in power converters (such as inverters) to convert DC to AC or vice versa, or for converting between different voltages or frequencies of AC. Such inverters are used in motor controllers or interfaces between power generation or storage, or a power distribution grid. For example, a power module may be used in a "grid tie" inverter of a battery storage system. In such a battery storage system, current is supplied to a power supply grid either to stabilize the grid or to provide electrical power during times where the grid electric energy is expensive, i.e. in the morning and in the afternoon. The batteries are recharged during night-time when grid energy cost is lower, or they can be recharged using solar power. Overall, the system helps the customer to reduce expenses for electrical energy. The "grid tie" inverter connects the battery storage system to the grid and has the task to convert the DC voltage of the battery to AC voltage for the grid and vice versa.
SUMMARY
There is provided a power module with optimized bond wire layout of a
semiconductor power module, which can achieve optimized inductance/resistance ratios to allow for external load characteristics.
It is an object of the present disclosure to provide a power module with optimized performance, especially in terms of ohmic resistance.
In a first aspect, a power module is provided, comprising at least two substrates on which one or more semiconductor switches are mounted, wherein the at least two substrates are connected via a plurality of bond wires, and wherein the plurality of bond wires are optimized to minimize ohmic resistance thereof. That is to say, the plurality of bond wires are placed to have a smallest ohmic resistance that is allowed in design.
In an embodiment, the plurality of bond wires are placed to have a small cross-sectional area thereof. That is to say, the plurality of bond wires are distributed so that the area of a surface normal to the path of the bond wires and which is bounded by the outermost bond wires has an area, which is smaller than that normally presented in a power module that is designed to minimize both stray inductance and ohmic resistance.
In an embodiment, the plurality of bond wires are placed to be as close to each other as possible. That is to say, the plurality of bond wires are close to each other, with a gap therebetween far smaller than that normally presented in a power module that is designed to minimize both stray inductance and ohmic resistance.
For example, the bond wires may be placed with an offset of a value which is less than 2 times thickness of the bond wires. Preferably, the value may be less than 1 .2 times the thickness of the bond wires. The bond wires may typically be 300pm in diameter. In an example, the bond wires may be placed with an offset of 350pm which is .17 times the bond wire thickness. It means that there is a gap of 25pm between the bond wires. In a typical prior art power module layout that is designed to minimize both stray inductance and ohmic resistance the bond wire offset may be 600pm or more, which is twice the thickness of the bond wires. In an embodiment, the plurality of bond wires are placed to be as short as possible. That is to say, each of the plurality of bond wires is shorter than that normally presented in a power module that is designed a trade-off between stray
inductance and ohmic resistance. In an embodiment, the number of the plurality of bond wires is larger than that needed for current carrying capability. That is to say, the number of bond wires is between 1 .2 and 15 times the number that would be required to ensure absolute temperature and/or temperature cycling are kept within limits required to ensure reliable bonds. In a preferred embodiment, the number may be between 1 .5 and 5 times the number that would be required to ensure absolute temperature and/or temperature cycling are kept within limits required to ensure reliable bonds. In an embodiment, the plurality of bond wires is placed in parallel.
In an embodiment, the semiconductor switches comprise wide-bandgap
semiconductor switches.
In an embodiment, the semiconductor switches comprise SiC semiconductors.
In an embodiment, the semiconductor switches comprise SiC-MOSFETs.
In an embodiment, the at least two substrates comprise Direct Bonded Copper (DBC) substrates. Such a substrate is formed by a copper/ceramic/copper sandwich, where a circuit structure may be created in the upper copper layer and which may be populated with semiconductor switches, capacitors and/or resistors as required to form a functioning circuit.
In an embodiment, the power module is configured to provide power to an inductive load. In an embodiment, the plurality of bond wires are placed with an offset of a value which is less than 2 times thickness of the bond wires.
In an embodiment, the value is less than 1 .2 times the thickness of the bond wires. In an embodiment, the number of the plurality of bond wires is 1 .5 times that needed for current carrying capability.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages will be more apparent from the following description of embodiments with reference to the figures, in which:
Fig. 1 shows a cross section view of a power module according to an embodiment of the present disclosure; Fig. 2 shows a perspective view of the power module according to the
embodiment of the present disclosure; Fig. 3 shows a view of a power module with lid placed according to an
embodiment of the present disclosure; Fig. 4 shows a diagram of a circuit structure of an exemplary power module according to an embodiment of the present disclosure.
Fig. 5 shows a top view of an exemplary power module according to an
embodiment of the present disclosure;
Fig. 6 shows an example of an assembly where two substrates are connected with bond wires, where (a) shows that the bond wires are less dense and longer, while (b) shows that the bond wires are denser and shorter; and Fig. 7 shows the effect of the assembly shown in Fig. 6.
DETAILED DESCRIPTION
The embodiments of the disclosure will be detailed below with reference to the drawings. It should be noted that the following embodiments are illustrative only, rather than limiting the scope of the disclosure.
References in the specification to "one embodiment," "an embodiment," etc.
indicate that the embodiment described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
It shall be understood that although the terms "first" and "second" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed terms.
The terminology used herein is for the purpose of describing particular
embodiments only and is not intended to be liming of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "has", "having", "includes" and/or "including", when used herein, specify the presence of stated features, elements, and/or components etc., but do not preclude the presence or addition of one or more other features, elements, components and/ or combinations thereof.
In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.
Fig. 1 shows a cross section view of a power module 100 according to an embodiment of the present disclosure, and Fig. 2 shows a perspective view of the power module according to the embodiment of the present disclosure. As shown, the power module 100 according to an embodiment of the present disclosure comprises a copper baseplate 110 with two substrates 120 soldered on top of it. Direct Bonded Copper (DBC) substrates are used in the power module 100. The DBC substrates are formed by a sandwich of Cu 122 (for example, of 300pm), Ceramics 124 (for example, AIN of 320pm) and Cu 126 (for example, of 300pm) where in the upper Cu layer 122 a circuit structure can be found that holds semiconductor switches 130, capacitors 150 and gate resistors 140. Aluminum bond wires 160 are used for the top-side connection of the die and for
interconnection with pins 210, including signal pins and power pins of the power module 100. The two DBC substrates are connected via bond wires 220. The power module 100 is encapsulated with a molded plastic frame 170 (holding the press-fit contact pins). It is filled with Silicone-gel 180. The frame is fixed by metal bushings 230. The power module 100 is closed by a plastic lid 300. Fig. 3 shows a view of the power module 100 with lid 300 in place. Fig. 4 shows a diagram of a circuit structure of an exemplary power module 400 according to an embodiment of the present disclosure. As shown, there are four semiconductors, T1-T4, and two substrates DBC1 and DBC2 inside the power module. DBC1 holds T1 and T4, and DBC2 holds T2 and T3. The numerals 1-24 in the figure denote pin reference numbers of the power module. The line ringed denotes the connection between the two DBC substrates.
Fig. 5 shows a top view of an exemplary power module 500 according to an embodiment of the present disclosure. As shown, there are eight semiconductors, where T1-T4 are doubled compared with those shown in Fig. 4. DBC1 holds T1 and T4, and DBC2 holds T2 and T3. In other words, each transistor in Fig. 4 is realized by two transistors in parallel in Fig. 5. Similar as Fig. 4, the bond wires ringed denote the connection between the two DBC substrates. The numerals 1- 26 in the figure denote pin reference numbers of the power module.
During assembly of the power module, first the semiconductor switches, resistors and capacitors are soldered to the DBC substrate. Afterwards the substrate is pre-tested. The tested DBC is then soldered to a 3mm thick copper baseplate covered with nickel plating. Afterwards the plastic frame is mounted; this is done by bonding the frame to the baseplate using silicone glue. In addition, the frame and the base plate are fixed by metal bushings. Afterwards the pins and the substrates are connected in a second bonding step with bond wires. In the final step the module is filled with silicone-gel, the lid is mounted and the module is tested in regards to secure the electrical function. The soldering steps may be combined into a single soldering step in order to save process complexity and hence cost.
The power module is designed to fulfill two major characteristics: High power conversion efficiency and high power density. Factors as lifetime, cost and quality are also taken into account. In order to achieve high power density, high performance wide-bandgap semiconductors, such as Silicon Carbide (SiC) semiconductor switches may be used, as they generally outperform standard silicon based components, i.e.
Insulated Gate Bipolar Transistors (IGBT). SiC devices put high demands on the design of the power module from thermal and electrical standpoint. The wide-bandgap semiconductors (e.g., SiC semiconductor switches) have the characteristic that they switch very fast, meaning that the transition from
conduction to blocking mode takes only a few nanoseconds. As current gradients during switching are high, the parasitic inductance of the whole assembly needs to be as small as possible.
In order to allow for efficient cooling, substrates which comprise aluminum-nitride (AIN) are used. AIN helps to lower the thermal resistance (Rth), thus the semiconductor switch will be operated at reduced temperatures. Since losses in SiC semiconductor switches (for example, SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs)) reduce if the junction temperature is lower, this measure helps to further increase the power module efficiency.
SiC MOSFETs are used in applications where highest efficiency in small building volume is required by the application. SiC MOSFETs show fast switching speeds and low on-state resistance (Rds.on) at the same time. As SiC wafers are expensive to manufacture, and with current manufacturing processes it is hard to fabricate components with an acceptably low crystal failure amount, the die are typically very small (for example, 5-25mm2). This keeps yield losses low, but restricts the total current that a component can pass. In order to achieve high output powers, several of these small components (for example MOSFETs) need to be operated in parallel.
A power module may provide power to inductive loads, for example an electrical grid system, or an electrical motor. Such systems are known to be overwhelmingly inductive. Thus the stray inductance of the load is much higher than any stray inductances that are normally generated within the power module. While certain parts of the power module are much more effective with lower stray inductances, this is much less important in the load side of the power module. For such parts of the power module, the stray inductances of the load may often be 100 to 1000 times higher than those found within the power module.
As can be seen from Figs. 4 and 5, the bond wire connection between DBC substrates is directly connected to the load output terminals (pins 11-14 shown in Figs. 4 and 5), and about a half of the total current supplied to the load passes through the connection. Therefore, the connection shall be carefully designed. For the bond wire connection between DBCs of a power module, different bond wire designs can be used. Generally, a trade-off between stray inductance and ohmic resistance shall be taken into account. However, if the output terminal of the power module is connected to inductive loads, the optimization of the power module internal phase inductance is not necessary. Instead, the ohmic resistance is in the focus of the optimization. That is, it is beneficial to optimize the bond wires in regards to ohmic resistance rather than in regards to stray inductance. In an embodiment, the bond wires are optimized to minimize ohmic resistance thereof. In another embodiment, the bond wires are placed to generate a smallest cross-sectional area thereof. In still another embodiment, it is advantageous to place the bond wires between the DBCs to be as close to each other as possible in order to generate a smallest possible cross-sectional area, which leads to high inductance but low ohmic resistance. In yet another embodiment, it is
advantageous to place the bond wires between the DBCs to be as short as possible, which leads to low ohmic resistance.
It is also advantageous to bond the interconnection between two substrates with a higher amount of bond wires than that needed for the current carrying capability. In other words, they are "overbonded". The large number of paralleled bond wires reduces stray inductance and ohmic resistance, which is relevant for SiC based modules. Therefore, a large number of paralleled bond wires may be used to optimize electric performance of the power module. From pure cost perspective, it does not make sense for standard Si modules as it requires more wire material and longer process times. Therefore it is normally avoided by module
manufacturers for the standard Si modules.
Fig. 6 shows an example of an assembly where two substrates 610, 610' are connected with bond wires 620, 620', which connect the Cu layer 630, 630' on respective substrates, where (a) shows that the bond wires 620 are less dense and longer, while (b) shows that the bond wires 620' are denser and shorter, i.e., the bond wires 620' are close to each other. Fig. 7 shows the effect of the assembly shown in Fig. 6, where (a) corresponds to Fig. 6(a) while (b)
corresponds to Fig. 6(b). In Fig. 6(a) the bond wires 620 are some distance apart, and thus the magnetic fields have low coupling, resulting in low inductance, as shown in Fig. 7(a). At the same time, ohmic resistance is slightly increased as the bond wires are slightly longer. In Fig. 6(b) the bond wires 520' are more densely packed, and thus the magnetic fields have strong coupling, resulting in higher stray inductance, as shown in Fig. 7(b). At the same time, ohmic resistance is reduced as the bond wires are shorter than those in Fig. 6(a).
In an embodiment, the bond wires are placed with an offset of a value which is less than 2 times thickness of the bond wires. Preferably, the value is less than 1 .2 times the thickness of the bond wires. The bond wires are typically 300pm in diameter. In an example, the bond wires are placed with an offset of 350pm which is 1 .17 times the bond wire thickness. It means that there is a gap of 25pm between the bond wires. Compared with the embodiment where ohmic resistance is minimized instead of inductance, a connection that minimizes stray inductance would have a bond wire spacing of typically 600pm or more, which is 2 times the thickness of the bond wires.
In another embodiment, the number of the bond wires is 1 .5 times that needed for current carrying capability. If only the current carrying capacity is taken into account in choosing the number of the bond wires, 7 aluminum bond wires would be needed to allow the transmission of normally expected currents. In an embodiment, around 10 aluminum bond wires will be used. The large number of paralleled bond wires reduces stray inductance, which in turns optimize the performance of the power module.
In the present disclosure, by using a densely packed assembly of wire bonds to connect two substrates in a power module, the performance of the power module is optimized in regards to ohmic resistance, which is dominant in the resulting performance.
The disclosure has been described above with reference to embodiments thereof. It should be understood that various modifications, alternations and additions can be made by those skilled in the art without departing from the spirits and scope of the disclosure. Therefore, the scope of the disclosure is not limited to the above particular embodiments but only defined by the claims as attached.

Claims

1. A power module comprising at least two substrates on which one or more semiconductor switches are mounted, wherein the at least two substrates are connected via a plurality of bond wires, and wherein the plurality of bond wires are optimized to minimize ohmic resistance thereof.
2. The power module of claim 1 , wherein the plurality of bond wires are placed to have a small cross-sectional area thereof.
3. The power module of claim 1 , wherein the plurality of bond wires are placed to be as close to each other as possible.
4. The power module of claim 1 , wherein the plurality of bond wires are placed to be as short as possible.
5. The power module of claim 1 , wherein the number of the plurality of bond wires is larger than that needed for current carrying capability.
6. The power module of claim 1 , wherein the plurality of bond wires are placed in parallel.
7. The power module of claim 1 , wherein the semiconductor switches comprise wide-bandgap semiconductor switches.
8. The power module of claim 7, wherein the wide-bandgap
semiconductor switches comprise Silicon Carbide (SiC) semiconductor switches.
9. The power module of claim 7, wherein the wide-bandgap
semiconductor switches comprise SiC
Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs)
10. The power module of claim 1 , wherein the at least two substrates comprise Direct Bonded Copper (DBC) substrates.
11 . The power module of claim 1 , wherein the power module is configured to provide power to an inductive load.
12. The power module of claim 1 , wherein the plurality of bond wires are placed with an offset of a value which is less than 2 times thickness of the bond wires.
13. The power module of claim 12, wherein the value is less than 1 .2
times the thickness of the bond wires.
14. The power module of claim 1 , wherein the number of the plurality of bond wires is 1 .5 times that needed for current carrying capability.
PCT/EP2017/084355 2017-01-12 2017-12-22 Power module with optimized bond wire layout WO2018130407A1 (en)

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DE102019215724A1 (en) * 2019-10-14 2021-04-15 Zf Friedrichshafen Ag Power module for operating an electric vehicle drive with increased immunity to interference

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