WO2018126788A1 - 准循环低密度奇偶校验编码方法、装置和存储介质 - Google Patents

准循环低密度奇偶校验编码方法、装置和存储介质 Download PDF

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WO2018126788A1
WO2018126788A1 PCT/CN2017/110133 CN2017110133W WO2018126788A1 WO 2018126788 A1 WO2018126788 A1 WO 2018126788A1 CN 2017110133 W CN2017110133 W CN 2017110133W WO 2018126788 A1 WO2018126788 A1 WO 2018126788A1
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matrix
row
columns
rows
column
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PCT/CN2017/110133
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English (en)
French (fr)
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李立广
徐俊
许进
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a quasi-cyclic Low Density Parity Check (LDPC) encoding method, apparatus, and storage medium.
  • LDPC Low Density Parity Check
  • the digital communication system generally includes three parts: a transmitting end, a channel, and a receiving end.
  • the transmitting end may perform channel coding on the information sequence to obtain an encoded codeword, interleave the encoded codeword, and map the interleaved bits into modulation symbols, and then process and transmit the modulation symbols according to the communication channel information.
  • factors such as multipath, movement, etc., cause specific channel response and other factors will distort the data transmission, and the data transmission will be further deteriorated due to noise and interference.
  • the receiving end receives the modulation symbol data after passing through the channel, and the modulation symbol data at this time is already distorted, and specific processing is required to restore the original information sequence.
  • the receiving end can perform corresponding processing on the received data to reliably restore the original information sequence.
  • the encoding method must be that both ends of the transceiver are visible, that is, both are known.
  • the coding mode may be based on Forward Error Correction (FEC) coding, wherein forward error correction coding adds some redundant information to the information sequence.
  • FEC Forward Error Correction
  • the transport block to be transmitted is subjected to code block partitioning to obtain a plurality of small transport blocks, and then the FEC encoding is performed on the plurality of small transport blocks, and the transport block length to be transmitted is simply referred to as TBS is an abbreviation of Transport Block Size.
  • the FEC code rate is generally defined as the ratio of the number of bits entering the encoder to the actual transmitted bits.
  • LTE Long Term Evolution
  • MCS Modulation and Coding Scheme
  • the size is: the communication resources of 12 consecutive subcarriers on one time slot and the resources left by some control signals and reference signals are removed.
  • the channel type may include: a data channel and a control channel.
  • the data channel generally carries user data.
  • the control channel carries control information, including control information such as MCS index number and channel information.
  • the bandwidth size generally refers to the bandwidth allocated by the system to the data transmission.
  • the LTE system is divided into 20M, 10M, 5M and other bandwidths.
  • the data transmission direction includes an uplink direction and a downlink direction, and the uplink direction is a transmission direction of the uplink data.
  • the uplink data may be data transmitted by the user equipment to the base station, and the downlink direction is a transmission direction of the downlink data.
  • the downlink data may be data transmitted by the base station to the user equipment.
  • FEC codes include: convolutional codes, Turbo codes, and Low Density Parity Check (LDPC) codes.
  • the information sequence of the bit number k is FEC-encoded to obtain an n-bit FEC encoded codeword (redundant bits are n-k), and the FEC encoding code rate is k/n.
  • LDPC code is a linear block code that can be defined by a very sparse parity check matrix or bipartite graph. It is the sparseness of its check matrix that can realize low complexity codec, which makes LDPC practical. .
  • the LDPC code is the most excellent channel coding under the Additive White Gaussian Noise (AWGN) channel, and the performance is very close to the Shannon limit.
  • AWGN Additive White Gaussian Noise
  • LDPC codes are widely available. application.
  • each row is a parity code, and if the value of an element of an index position is equal to 1 in each row, the bit participates in the parity code, and if it is equal to 0, the The location bit does not participate in the parity code.
  • the parity check matrix H of the quasi-cyclic LDPC code is a matrix of mb ⁇ Z rows and nb ⁇ Z columns.
  • H is composed of mb ⁇ nb sub-matrices, each of which is a different power of the basic permutation matrix of Z ⁇ Z, and can also be regarded as a sub-value obtained by cyclically shifting several values of the Z ⁇ Z unit matrix. matrix.
  • a quasi-cyclic LDPC code can be determined, and all the shift values constitute a mb ⁇ nb matrix, which can be called a basic matrix or a basic check matrix or a prototype image. (base photograph).
  • the encoding flexibility value is the selectivity of the supported encoding rate and encoding length.
  • the coding performance includes the correctness of the coding and the like.
  • embodiments of the present invention are expected to provide a quasi-cyclic LDPC encoding method, apparatus, and storage medium to solve the above problems.
  • a first aspect of the embodiments of the present invention provides an LPDC coding method, including:
  • the quasi-cyclic LDPC encoding is performed on the coded information based on a basic matrix and a spreading factor value to obtain an LDPC coded output sequence.
  • the basic matrix includes: a first class element and a second class element; and the basic matrix includes At least one sub-matrix; the row weight of the i-th row of the sub-matrix is g0, and the value of the g0 is located within a preset range; the row weight of the j-th row of the sub-matrix is not less than a sum of g0 and ⁇ g, Wherein, the j is not equal to the i; the i and j are both row index numbers of the sub-matrix, the ⁇ g is a positive integer greater than a preset value, and the row weight is a corresponding row of the sub-matrix The number of the second type of elements;
  • a rate matching output sequence is selected from the LDPC coded output sequence.
  • a second aspect of the embodiments of the present invention provides a quasi-cyclic low-density parity check LPDC encoding apparatus, including:
  • a coding unit configured to perform quasi-cyclic LDPC coding on the coded information based on a base matrix and an extension factor value, to obtain an LDPC coded output sequence
  • the base matrix includes: a first class element and a second class element
  • the base matrix includes at least one sub-matrix; the row weight of the i-th row of the sub-matrix is g0, and the value of the g0 is located within a preset range; the row weight of the j-th row of the sub-matrix is not less than g0 And a sum of ⁇ g, wherein the j is not equal to the i; the i and j are both row index numbers of the sub-matrix, the ⁇ g is a positive integer greater than a preset value, and the row weight is
  • the sub-matrix corresponds to the number of the second type of elements in the row;
  • a rate matching unit is configured to select a rate matching output sequence from the LDPC coded output sequence.
  • the embodiment of the invention discloses a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used in the LPDC encoding method.
  • the basic matrix used for encoding is a specially set matrix, and the basic matrix includes at least one sub-matrix; the sub-matrix column row difference is less than or equal to The number of columns of the basic matrix is different, and the number of columns of the sub-matrix and the basic matrix is greater than the number of rows; the minimum row weight of the sub-matrix is g0, and the value of the g0 is within a preset range.
  • the other row weights of the submatrix are not less than the sum of g0 and ⁇ g; the row weight is the number of non-second class elements in the row element of the submatrix.
  • the minimum row weight is g0, it means that all the row weights of the submatrix are not less than the sum of g0 and ⁇ g, such a line redistribution will result in high decoding rate and low decoding.
  • the rate has good decoding performance, so as to ensure the translation performance while ensuring flexibility.
  • FIG. 1 is a block diagram showing the structure of a digital communication system according to the related art
  • FIG. 2 is a schematic flowchart of a quasi-cyclic LDPC encoding method according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a basic matrix and a sub-matrix according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a quasi-cyclic LDPC encoding apparatus according to an embodiment of the present invention.
  • FIG. 5 is a diagram showing an example of a basic matrix of a first quasi-cyclic LDPC encoding according to an embodiment of the present invention
  • FIG. 6 is a diagram showing an example of a second basic matrix provided by an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of performance of a quasi-cyclic LDPC encoding according to an embodiment of the present invention.
  • FIG. 8 is a diagram showing an example of a third basic matrix according to an embodiment of the present invention.
  • 9 is a basic matrix comparison example 2 according to an example of the present invention.
  • FIG. 10 is a schematic diagram of performance of another quasi-cyclic LDPC encoding according to an embodiment of the present invention.
  • FIG. 11 is a diagram showing an example of a third basic matrix provided by an embodiment of the present invention.
  • FIG. 12 is a diagram showing an example of interleaving of a basic matrix according to an embodiment of the present invention.
  • FIG. 13 is a diagram showing an example of a fourth basic matrix according to an embodiment of the present invention.
  • FIG. 14 is a diagram showing an example of a fifth basic matrix according to an embodiment of the present invention.
  • 15 is a schematic diagram of a sub-matrix provided by an embodiment of the present invention.
  • FIG. 16 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 17 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 18 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 19 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 20 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 21 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 22 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 23 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 24 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 25 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 26 is a schematic diagram of a reference matrix according to an embodiment of the present invention.
  • FIG. 27 is a schematic diagram of another sub-matrix provided by an embodiment of the present invention.
  • FIG. 28 is a schematic diagram of another reference matrix according to an embodiment of the present invention.
  • this embodiment provides a quasi-cyclic LPDC coding method, including:
  • Step S110 Perform quasi-cyclic LDPC encoding on the information to be encoded based on a basic matrix and a spreading factor value to obtain an LDPC encoded output sequence.
  • the basic matrix includes: a first type element and a second type element; the basic matrix includes at least one sub-matrix; the row weight of the i-th row of the sub-matrix is g0, and the value of the g0 a positive integer located within a preset range; a row weight of the jth row of the submatrix is not less than a sum of g0 and ⁇ g, wherein j is not equal to the i; the i and j are both the submatrix a row index number, the ⁇ g is a positive integer greater than a preset value, and the row weight is the number of the second type elements of the corresponding row of the submatrix;
  • Step S120 Select a rate matching output sequence from the LDPC coded output sequence
  • the LPDC encoding method in this embodiment is a method used at the transmitting end.
  • it may comprise obtaining a set of spreading factors, the set of spreading factors comprising one or more spreading factor values from which the spreading factor values for LDPC encoding are derived.
  • the set of spreading factors includes at least one spreading factor value, typically comprising two or more spreading factor values.
  • the value of the spreading factor value is equal to the dimension of the all-zero square matrix and the unit square matrix.
  • the all-zero square matrix and the unit square matrix are matrices whose number of rows is equal to the number of columns.
  • the spreading factor value may be a value indicating the number of rows or columns of the all-zero square matrix and the unit square matrix.
  • the basic matrix is a non-empty matrix
  • the non-empty matrix is a matrix including at least one element. That is, the number of rows and the number of columns of the basic matrix are not less than one.
  • the number of rows of the basic matrix may be mb, the number of columns of the basic matrix is nb; and the nb is greater than the mb, and both mb and nb are positive integers.
  • the base matrix is a matrix whose column dimension is larger than the row dimension.
  • the elements in the basic matrix can be divided into two categories, one is a first class element, and the other is a second class element other than the first class element.
  • the first type of element may be an element whose value is a predetermined value.
  • the first type element may be an element with a value of -1; Can be a non-1 element, 0 or a positive integer.
  • the first type of element is used to replace an element of the all-zero square matrix;
  • the second type element is an element replaced with a predetermined matrix, and is used to indicate a displacement of a unit square array cyclic displacement forming the preset matrix Step size; the set of spreading factors, including at least one spreading factor value.
  • the sub-matrix column row number difference is less than or equal to the column row number difference of the base matrix, and the number of columns of the sub-matrix and the base matrix is greater than the number of rows.
  • the value of g0 may be a positive integer not greater than 5, for example, 2, 3, 5, and the like.
  • the value of ⁇ g may be a value of 3, 2 or 4 or the like.
  • step S100 may be further included; the step S100 may include: acquiring the basic matrix and the set of expansion factors, optionally, including: querying the storage medium in the sending end A base matrix and the set of expansion factors.
  • the step S110 may further include: receiving, by the peripheral device, the base matrix or the set of extended factor values, for example, receiving the base matrix and the extended factor value from the communication peer, using the slave communication pair
  • the base matrix and the set of the extended factor values received by the terminal are encoded, so that the communication peer can decode the corresponding base matrix and the set of the extended factor values.
  • the base matrix and the extension factor values in the present embodiment can be used to form a parity check matrix.
  • An element in the basic matrix is replaced by a preset square matrix after the cyclic shift of the all-zero matrix or the unit square matrix.
  • the step size of the cyclic displacement is equal to the value of one of the second type of elements.
  • the value of the second type element may be 0 or a positive integer; when one of the second type elements is x, then The displacement step of the cyclic displacement is equal to x.
  • the specific row of the basic matrix and the elements of the specific column may constitute the sub-matrix, where the minimum row weight of the sub-matrix is less than the specified value, and the other row weights are not less than the preset value, for example, the row weights of other rows are not less than Specify the sum of the value and ⁇ g.
  • the preset value here may be any value.
  • the specified value takes a value of 4 or 5.
  • the basic matrix Hb is a matrix of 2 rows and 4 columns, as follows:
  • the spreading factor value is equal to 4
  • the all-zero matrix in which the number of rows and the number of columns are equal to 4 or the matrix replacement after the cyclic shift of the unit matrix in which the number of rows and the number of columns are equal to 4 is used.
  • the elements in the base matrix are used.
  • the parity check matrix H corresponding to the above basic matrix is:
  • the non-1 element is equal to 0, and the unit square matrix does not perform cyclic shift. If the non-1 element is 2, the preset matrix after the cyclic shift of the unit square matrix is:
  • the information to be encoded is mapped into the parity check matrix in step S110.
  • one bit block in the information to be encoded corresponds to a column element S in the basic matrix, that is, a sub-matrix corresponding to the parity check matrix and S.
  • the columns in the parity check matrix that are not corresponding to the information to be encoded are used as check codes of the information to be encoded, and are completed.
  • the LDPC coded output sequence is obtained; the dimension of the output LDPC code sequence is equal to the dimension of the parity code.
  • the basic matrix of quasi-cyclic LDPC coding generally includes two parts: a system column partial matrix and a check column partial matrix.
  • a basic matrix of mb ⁇ nb, generally the front (nb-mb) column is the system column partial matrix, and the latter mb column is the check column partial matrix.
  • the check column partial matrix includes two structures: a lower triangular structure and a double diagonal structure.
  • the lower triangular structure refers to an element determined by any row index number and any column index number in the matrix, and the element is equal to -1 when the column index number is greater than the row index number (for indicating replacement with an all-zero matrix)
  • the element is described as a first class element in the embodiment of the present invention; the double diagonal structure refers to: in the matrix, the element whose row index number is 0 and the column index number is 0 is a non-1 element (this implementation)
  • the example is described as the second type of element), and in the column index number i, the two elements determined by the downlink index number i and (i+1) are non-1 elements, and the column index number is i0 and the row index.
  • the value of the element indexed by the number i1 is equal to -1, where. I0 is greater than i1+1. All of the lower triangular structure descriptions and the double diagonal structures in the embodiments of the present invention are consistent with the above description. If the matrix is subjected to row permutation and/or column permutation, the lower triangular structure and the double diagonal structure are also considered to be the above basic proofs.
  • the partial sequence output in the LDPC coded output sequence is selected in step S120. When step S130 is performed, how many partial outputs in the LDPC coded output sequence are selected according to the encoding rate; thereby ensuring flexibility.
  • the basic matrix includes a sub-matrix that satisfies the above condition
  • the distribution of the non-all-zero matrix in the parity check matrix corresponding to the encoded information satisfies the row-re-distribution of the sub-matrix.
  • the coding performance degradation caused by the short 4-ring or short 6-ring phenomenon in the encoding process can be reduced, thereby ensuring coding performance.
  • the submatrix may be formed after the base matrix is determined by picking specific rows in the base matrix and elements of a particular column, in some embodiments, the base matrix is generated after the submatrix is determined of.
  • the method for generating the basic matrix includes: determining the sub-matrix, performing matrix expansion based on the sub-matrix, and obtaining the sub-matrix in the basic matrix The elements other than the matrix get the basic matrix.
  • the first type element and the second type element may be randomly added, and usually the first type element is added more.
  • the expansion of the basic matrix based on the sub-matrix may be performed by any existing method, which may not be limited in this embodiment.
  • the base matrix 302 includes a submatrix 301 of mb0 rows and nb0 columns, and elements indicated by reference numeral 303 are elements of the base matrix 302 other than the submatrix 301, which may be derived based on the submatrix 301.
  • the sub-matrix is a matrix of mb0 rows and nb0 columns. There are various ways to determine the sub-matrix. Two alternative methods are provided below:
  • the sub-matrix is a matrix of mb0 rows nb0 columns, the i is equal to 0, and the sub-matrices are:
  • A is a matrix of mb0 rows (nb0-mb0) columns
  • B is a matrix of 1 row and 1 column
  • C is a matrix of (mb0-1) rows 1 column
  • D is 1 row ( Mb0-1) a matrix of columns, said E being a matrix of (mb0-1) rows (mb0-1) columns
  • the row weight of the first row in A is the smallest and the row weight of the first row is equal to g0-1
  • B includes one of the second type of elements
  • the C includes (mb0-1) the first type of elements
  • the D includes: (mb0-1) the first type of elements
  • the sub-matrix is a matrix of mb1 rows nb1 columns, the i is equal to (mb1-1), and the sub-matrices are:
  • A0 is a matrix of (mb1-1) rows (nb1-mb1) columns
  • the A1 is a matrix of (mb1-1) rows (mb1-1) columns
  • the A2 is a (mb1-1) row A matrix of 1 column
  • the A3 being a matrix of 1 row nb1 column.
  • the A1 may be a lower triangular structure or a double diagonal structure, and when the A1 is a double diagonal structure, the mb1 is equal to one of the following integers: 3, 4, 5.
  • the last element of A3 is the second type of element.
  • the submatrix is: [B0 B1],
  • the B0 is a matrix of mb2 rows kb2 columns
  • the B1 is a matrix of mb2 rows mb2 columns
  • the row index number of the element of the row in the matrix B1 where the largest row weight is located in the base matrix is equal to the i.
  • the i is equal to 0, and the submatrix is:
  • C0 is a matrix of 1 row nb3 columns
  • C1 is a matrix of (mb3-1) rows (kb3+1) columns
  • C2 is a matrix of (mb3-1) rows (mb3-1) columns
  • the basic matrix After the sub-matrix of a basic matrix is determined, the basic matrix can be expanded on the basis of the sub-matrix, thereby expanding the sub-matrix. After determining the sub-matrix, the basic matrix may be obtained by randomly adding the required number of elements, for example, based on the sub-matrix, the random condition first-class element and/or the second class The element gets the base matrix.
  • the sub-matrix can be quickly constructed in the above manner, and the basic matrix can be quickly obtained through the expansion of the sub-matrix.
  • the basic matrix is a matrix of mb rows and nb columns, and the basic matrix is [D0 D1], wherein The D0 is a matrix of mb row kb columns, and the D1 is a matrix of mb rows mb columns; all the second class elements of the i-th row in the D1 form a column index number of the i-th row in the basic matrix Collection Cset.
  • the LDPC coded output sequence includes: nb bit blocks; the nb bit blocks include: kb system bit blocks with a bit block index number of 0 to (kb-1) and a bit block index number of kb to (nb-) 1) mb check bit blocks.
  • the step S120 may include:
  • the interleaved output sequence after the interleaving is selected to obtain the rate matching output sequence.
  • the preset interleaving sequence may be preset, and may be used to indicate row and column switching in the basic matrix, and the interleaved output sequence may be obtained by the row and column switching.
  • the interleaving may include: first performing row switching according to the preset interleaving sequence, and then performing column switching; or performing column switching according to the preset interleaving sequence, and performing row switching.
  • step S120 in the sub-matrix.
  • the embodiment further provides another implementation manner:
  • the base matrix is a matrix of mb rows and nb columns, and the base matrix is [D0 D1], wherein the D0 is a matrix of mb rows and kb columns, and the D1 is a matrix of mb rows and mb columns; All the second type elements of the i-th row form a set Cset in the column index number of the i-th row in the base matrix;
  • the step S120 may include: performing row and column shifting of the matrix on the basic matrix to obtain a modified basic matrix, wherein the corrected kb column to the (kb+t-1) column of the basic matrix, and the like All the elements in the set Cset indicate columns in the base matrix; the (kb+t)th column to the (kb+t1-1)th column of the modified base matrix is equal to all element indications in the set Cset' a column of the base matrix, wherein the set Cset' is a difference set between the set ⁇ kb, kb+1, ..., (kb+t1-1) ⁇ and the set Cset, and t1 is in the set Cset The maximum element value is subtracted from the value obtained by (nb-mb), the t is the number of elements of the set Cset; the corrected basic matrix is used to perform quasi-cyclic LDPC encoding on the encoded information sequence.
  • the sub-matrix performs the row and column displacement in the embodiment, including: performing row displacement first, and then performing column displacement; or, performing column displacement first, performing row displacement.
  • the purpose of the displacement is the corrected base matrix, and the positional exchange between the above-mentioned row and column elements with respect to the matrix before the correction.
  • the row and row displacement may include: row-to-row position exchange; the row and column displacement may include: row switching and column switching.
  • a row index number of an element in the base matrix in the submatrix forms a set Rset0, a column index number of an element in the base matrix in the submatrix forming a set Cset0; wherein the row index number and the row Column index numbers are continuously distributed.
  • selecting a corresponding element constitutes the sub-matrix.
  • the row index number of the Rset and the column index number in the Cset are continuously distributed. For example, from x1, x1+1...x1+y.
  • the index numbers of Rset and Cset are continuously distributed, and both take values from 0.
  • the submatrix is composed of a part of the elements in the upper left corner of the basic matrix. This can simplify LDPC coding, reduce coding delay, and improve the robustness of the communication system.
  • the set Rset0 is a set of 0 to (mb'-1), the set Cset0 being a set of 0 to (nb'-1), where mb' is the set The number of elements of Rset0, nb' is the number of elements of the set Cset0.
  • the step S120 may include:
  • the column number of the E-bit block corresponding to the base matrix constitutes a set T0; the column index number of the second class element in the i-th row of the sub-matrix constitutes a set T1; wherein the set T0 is A subset of the set T1 is described.
  • the E bit blocks correspond to the column index numbers of the base matrix to form a set T0; the row weight in the sub-matrix is equal to the column index number of the second class element in the row of the g0 in the basic matrix, A set T1 is formed; the set T0 is a subset of the set T1. For example, if the second type of elements in the row with the smallest row weight of the submatrix are in columns 3, 5, 7, and 8 of the base matrix, then T1 includes 3, 5, 7, and 8.
  • the T0 is composed of one or more elements of 3, 5, 7, and 8.
  • the value of E is 0 or a positive integer, which is smaller than the total number of bit blocks included in the information to be encoded.
  • the partially transmitted bit block is removed, and the remaining is the rate matched output sequence that satisfies the encoding rate that needs to be output.
  • the E bit blocks are a plurality of bit blocks that are continuously distributed among the information to be encoded.
  • the nb4 is equal to the nb0, and if the mb4 is equal to the mb1, the nb1 is equal to the nb1.
  • the position of the second type element in the base matrix has at least a predetermined proportion of element positions identical to the position of '1' in the reference matrix, the reference matrix being intercepted from the matrix; the reference matrix Intercepting the row index numbers of the following matrix to form a set Set0, and the reference matrix intercepts the column index numbers of the following matrix to form a set Set1;
  • the set Set0 includes the number of elements mb
  • the set Set1 includes the number of elements nb, and nb is greater than mb.
  • the preset ratio here may be 80%, 75% or 60% or 85%, and the like.
  • this embodiment provides a quasi-cyclic LPDC encoding apparatus, including:
  • the coding unit 110 is configured to perform quasi-cyclic LDPC coding on the coded information based on a base matrix and a spreading factor value to obtain an LDPC coded output sequence, where the basic matrix includes: a first class element and a second class element;
  • the base matrix includes at least one sub-matrix; the row weight of the i-th row of the sub-matrix is g0, and the value of the g0 is located within a preset range; the row weight of the j-th row of the sub-matrix is not less than a sum of g0 and ⁇ g, wherein the j is not equal to the i; the i and j are both row index numbers of the sub-matrix, the ⁇ g is a positive integer greater than a preset value, and the row weight is
  • the submatrix corresponds to the number of the second type of elements in the row;
  • the rate matching unit 120 is configured to select a rate matching output sequence from the LDPC coded output sequence.
  • the device in this embodiment may be a device for implementing the foregoing method, and may be used for a device at the transmitting end.
  • both the encoding unit 110 and the rate matching unit 120 may correspond to a processor or a processing circuit.
  • the processor may include a central processing unit (CPU), a digital signal processing (DSP), an application processor (AP), a microprocessor (MCU), or a programmable array (PLC) or the like.
  • the processing circuit can include an application specific integrated circuit (ASIC).
  • the encoding unit 110 may also correspond to a dedicated encoder or the like.
  • the processor or processing circuit can perform the above operations by execution of specific instructions.
  • the encoding unit 110 and the rate matching unit 120 may correspond to the same processor or processing circuit, and may also correspond to different processors or processing circuits.
  • these functional units correspond to different processors, these processors are connected to each other, and the above operations can be realized, thereby performing flexible coding while ensuring coding performance.
  • the sub-matrix is a matrix of mb0 rows and nb0 columns, and the processor or the processing circuit may calculate the sub-matrix according to a function relationship, and then obtain a basic matrix according to the sub-matrix.
  • the processing or processing circuit may also obtain the basic matrix first, and then determine whether the sub-matrix satisfying the above requirements can be selected in the basic matrix.
  • the sub-matrix is a matrix of mb0 rows nb0 columns, the i is equal to 0, and the sub-matrices are:
  • A is a matrix of mb0 rows (nb0-mb0) columns
  • B is a matrix of 1 row and 1 column
  • C is a matrix of (mb0-1) rows 1 column
  • D is 1 row ( Mb0-1) a matrix of columns
  • said E being a matrix of (mb0-1) rows (mb0-1) columns
  • the row weight of the first row in A is the smallest and the row weight of the first row is equal to g0-1
  • B includes one of the second type of elements
  • the C includes (mb0-1) the first type of elements
  • the D includes: (mb0-1) the first type of elements
  • It is a lower triangular structure or a double diagonal structure.
  • the sub-matrix is a matrix of mb1 rows of nb1 columns, the i is equal to (mb1-1), and the sub-matrices are:
  • A0 is a matrix of (mb1-1) rows (nb1-mb1) columns
  • the A1 is a matrix of (mb1-1) rows (mb1-1) columns
  • the A2 is a (mb1-1) row A matrix of 1 column
  • the A3 being a matrix of 1 row nb1 column.
  • the A1 is a lower triangular structure or a double diagonal structure.
  • the mb1 is equal to one of the following integers: 3, 4, 5.
  • the last element of the A3 is the second type of element.
  • the row index number of the element in the matrix in which the largest row weight in the matrix B1 is located is equal to the i.
  • the i is equal to 0 and the submatrix is:
  • the C0 is a matrix of 1 row nb3 columns
  • the C1 is a matrix of (mb3-1) rows (kb3+1) columns
  • the C2 is a matrix of (mb3-1) rows (mb3-1) columns
  • the base matrix is a matrix of mb rows nb columns, the base matrix is [D0D1], wherein the D0 is a matrix of mb rows kb columns, and the D1 is a matrix of mb rows mb columns
  • the column index numbers of the i-th row of the i-th row in the D1 form a set Cset;
  • the LDPC coded output sequence includes: nb bit blocks;
  • nb bit blocks include: kb system bit blocks with a bit block index number of 0 to (kb-1) and mb parity bit blocks with a bit block index number of kb to (nb-1);
  • the rate matching unit 120 is configured to perform interleaving on the LDPC coded output sequence according to a preset interleaving sequence, where the interleaved output sequence is obtained, where the kbth to the (kb+t-) of the preset interleaved sequence 1) an element equal to an element value in the set Cset; the preset interleaving sequence includes a number of elements less than or equal to the nb; the t is an element number of the set Cset; The interleaved output sequence is selected to obtain the rate matching output sequence.
  • the base matrix is a matrix of mb rows and nb columns, the base moment
  • the array is [D0 D1], wherein the D0 is a matrix of mb rows and kb columns, and the D1 is a matrix of mb rows and mb columns; all the second type elements of the i-th row in the D1 are in the basic matrix
  • the column index number of the i-th row forms a set Cset;
  • the encoding unit 120 is specifically configured to perform row-column shifting of the matrix on the basic matrix to obtain a modified basic matrix, wherein the modified basic matrix
  • the kbth column to the (kb+t-1)th column is equal to all the elements in the set Cset indicating the columns in the base matrix; the (kb+t)th column to the (kb+) of the modified base matrix T1-1) a column equal to all the elements in the set Cset' indicating the columns of the base matrix, wherein the set Cset' is a set ⁇ kb
  • a row index number of an element in the base matrix in the submatrix forms a set Rset0
  • a column index number of an element in the base matrix in the submatrix forms a set Cset0; wherein the row index number and The column index numbers are continuously distributed.
  • the set Rset0 is a set of 0 to (mb'-1), the set Cset0 being a set of 0 to (nb'-1), wherein mb' is the set Rset0
  • the number of elements, nb' is the number of elements of the set Cset0.
  • the rate matching unit 120 is specifically configured to remove E bit blocks of the to-be-coded information sequence, and determine the rate matching output sequence based on the remaining coded information sequence in the to-be-coded information sequence;
  • the column index numbers of the E-bit blocks corresponding to the basic matrix form a set T0;
  • the column index numbers of the second class elements in the i-th row of the sub-matrix constitute a set T1; wherein the set T0 is the set T1 a subset of.
  • nb4 is the number of columns of the sub-matrix
  • the column row number difference of the submatrix is equal to the column row number of the base matrix Poor, and the number of columns of the sub-matrix is greater than the number of rows of the sub-matrix, and the number of columns of the basic matrix is greater than the number of rows of the basic matrix.
  • the value of the g0 is located within a preset range, including: the g0 is a positive integer not greater than 5; and the preset value is equal to 3 or 4.
  • the position of the second type element in the base matrix has at least a predetermined proportion of element positions identical to the position of '1' in the reference matrix, the reference matrix being intercepted from the matrix; the reference matrix Intercepting the row index numbers of the following matrix to form a set Set0, and the reference matrix intercepts the column index numbers of the following matrix to form a set Set1;
  • the set Set0 includes the number of elements mb
  • the set Set1 includes the number of elements nb, and nb is greater than mb.
  • the preset ratio here may be 80%, 75% or 60% or 85%, and the like.
  • This example provides a method of quasi-cyclic LDPC encoding, including the following steps:
  • Step 1 Obtain a base matrix and a spreading factor value used for quasi-cyclic LDPC coding from the storage module; the basic matrix includes an element for indicating an all-zero square matrix and a shift for indicating a cyclic shift of the unit array An element of the step size, the spreading factor value is used to indicate the number of rows of the all-zero square matrix or the unit matrix, and the spreading factor value is an integer greater than zero.
  • Storage here
  • the modules correspond to the foregoing, and may specifically correspond to a storage medium.
  • the submatrix in the basic matrix includes an element whose index number in the base matrix is sufficient to be a set Rset; the element index of the element included in the sub-matrix constitutes a set Cset in the base matrix.
  • the minimum row weight of the submatrix is g0, where g0 is an integer greater than 1 and less than 5, and the other rows of the submatrix have a row weight equal to 5 or greater than 5.
  • the set Rset is a subset of a set of all row index numbers of the base matrix
  • the set Cset is a subset of a set of all column index numbers of the base matrix. a value obtained by subtracting the number of rows of the submatrix from the number of columns of the submatrix is less than or equal to the number of columns of the basic matrix minus the number of rows of the basic matrix;
  • Step 2 performing quasi-cyclic LDPC encoding on the sequence of the information to be encoded based on the one basic matrix and one spreading factor value, to obtain an LDPC encoded output sequence;
  • Step 3 Select a rate matching output sequence from the LDPC coded output sequence.
  • step 1 the basic matrix is as follows:
  • the sub-matrix is a matrix Hb0 mb0 ⁇ nb0 of a mb0 row nb0 column, including:
  • A is the matrix of the Amb0 row (nb0-mb0) column
  • B is the matrix of 1 row and 1 column
  • C is the matrix of (mb0-1) row 1 column
  • D is the matrix of 1 row (mb0-1) column
  • EE is a matrix of (mb0-1) rows (mb0-1) columns.
  • the row weight of the first row in A is the smallest and the row weight of the first row is equal to g0-1.
  • B includes one element for indicating the shift step size of the unit array cyclic shift
  • D includes (mb0-1).
  • E is a lower triangular structure or a double diagonal structure.
  • the value in the '-1' element refers to the first type of element indicating the all-zero square matrix, the sub-block of an all-zero square matrix of the parity check matrix of the corresponding quasi-cyclic LDPC code, and other elements Refers to the element used to indicate the shift step size of the unit array cyclic shift.
  • the row index is the set Rset
  • the element determined by any row index number and any column index number in the matrix is a matrix of the first class element when the column index number is greater than the row index number.
  • the beneficial effects of the line redistribution design of the basic matrix are: firstly, the quasi-cyclic LDPC coding and decoding performance is better, and the basic matrix used for the high-rate quasi-cyclic LDPC coding is substantially completely related to the sub-matrix.
  • the sub-matrix design can ensure better performance; an example of the basic matrix as shown in FIG.
  • the first row weight is added on the basis of the basic matrix example shown in FIG. 5 to form a basic matrix as shown in FIG. 6.
  • the row weight of the first row 501 of the sub-matrix 502 of the base matrix shown in FIG. 6 is increased relative to the row weight of the first row of the sub-matrix 401 in FIG.
  • FIG. 7 is a performance comparison diagram after encoding of the basic matrix shown in FIGS. 5 and 6.
  • the abscissa of Fig. 7 represents the signal-to-noise ratio (SNR); the ordinate represents the block error rate (BLER).
  • the solid line in Fig. 7 shows the performance variation curve using the basic matrix encoding shown in Fig. 5, and the broken line shows the performance variation curve encoded using the basic matrix shown in Fig. 6.
  • SNR signal-to-noise ratio
  • BLER block error rate
  • the length of the information to be encoded is 1024, and the corresponding expansion factor value is 128, and a set of expansion factor values stored in the storage module are ⁇ 4, 6, 8, 10, 12, 14 ,16,20,24,28,32,40,48,56,64,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024 ⁇ .
  • (h ij b ) uniform is the element value of the i-th row and the j-th column of the base matrix
  • (h ij b ) modified is the converted base matrix (ie, corresponding to the expansion factor value) Equation value of the i-th row and j-th column in the base matrix of 128)
  • the real number x is rounded down (ie, the largest integer less than or equal to x).
  • a rate matching output sequence is selected from the LDPC coded output sequence.
  • rate matching does not need to be aligned with the parity bits of the LDPC coded output sequence of the cyclic LDPC coded output, and the sequence is directly selected from the corresponding start bit position, thereby reducing the interleaving operation, the transmitting end and the receiving end.
  • the delay of the end is small, which is beneficial to increase the robustness of the communication system. Since in the rate matching process, the parity block corresponding to the first row (corresponding to 410 in FIG. 5, the eighth bit block of the LDPC coded output sequence) must be transmitted, performance can be guaranteed, as described at this time.
  • the 8th bit block is already in the front (the top of all parity bits), so there is no need to interleave to the most when making sequential selections.
  • the interleaving module can be reduced, thereby reducing the rate matching delay and improving the response speed of the system, thereby improving the robustness of the system.
  • the row weight is the number of elements in the specified row in the matrix for indicating the shift step size of the unit array cyclic shift, which is only a preferred scheme.
  • the row weight of the sub-matrix in the constraint basic matrix needs to increase the row weight of other rows except the lightest row weight. The beneficial effects are: the performance of the long code length can be increased, and the performance of the long code length is better.
  • the set Rset is a set of all integers greater than or equal to 0 and less than the number of elements of the set Rset, the set Cset being greater than or equal to 0 and less than the number of elements of the set Cset A collection of all integers.
  • the set Rset ⁇ 0,1,2,3,4 ⁇
  • the set Cset ⁇ 0,1,2,3,4,5,6,7,8,9,10 , 11, 12 ⁇ .
  • the sub-matrix directly corresponds to a part of consecutive element blocks of the basic matrix (the continuous row index number and the continuous column index number are jointly indexed), and the beneficial effect is that the quasi-cyclic LDPC coding can be implemented relatively simple, and no other operations are required.
  • the sub-matrix in the basic matrix which is indexed by the row index number as the set Rset and the column index number as the set Cset is only a preferred scheme.
  • the set Rset pilot index numbers are not necessarily continuous and set.
  • the column index number of Cset is not necessarily contiguous.
  • the sub-matrix may be regarded as a core matrix of the quasi-cyclic LDPC code, and may support any code rate greater than or equal to R0 and less than 1, but need to adopt the sub-matrix when decoding at the receiving end ( The core matrix is decoded.
  • the beneficial effect of the constraint on the sub-matrix (core matrix) is that the number of rows mb0 and the number of columns nb0 of the constrained sub-matrix can make the sub-matrix relatively small, and when performing high-rate quasi-cyclic LDPC decoding.
  • the number of rows to be updated is relatively small, that is, the computational complexity is relatively small, the decoding speed is fast, and the peak decoding throughput is high.
  • the elements other than the sub-matrices in the basic matrix are obtained based on the extension of the sub-matrices.
  • the sub-matrix with the code rate R0 is first designed, and then the basic matrix elements of the lower code rate are gradually extended by the sub-matrix.
  • the sub-matrix is better for high bit rate performance. Because of the uniform basic matrix design, the high-rate basic matrix is embedded in the low-rate basic matrix, as shown in Figure 3.
  • the base matrix is a matrix 302 of mb rows nb columns
  • the submatrix is a matrix 301 of upper left mb0 rows nb0 columns of the base matrix, and other elements 303 (basic matrix) in the base matrix other than the submatrix
  • the other blanks in the whole are extended on the basis of the sub-matrix to support the lower bit rate design.
  • the beneficial effect is that the high-rate quasi-cyclic LDPC code can be performed well, and the extended elements are supported.
  • the lower bit rate does not affect the performance of the sub-matrix. As long as the sub-matrix is designed well, it can guarantee high code rate performance. Since the matrix of low bit rate is relatively large, the sub-matrix has less influence on low bit rate performance. Therefore, the performance at a continuous code rate can be guaranteed to be good.
  • the double-diagonal structure means that in the matrix, the element whose row index number is 0 and the column index number is 0 is a non-1 element, and in the case where the column index number is i, the downlink index numbers are i and (i+1)
  • the two elements identified are all non-1 elements.
  • Reference numerals 704, 710, 704, and 702 are sub-matrices of the basic matrix; wherein the sub-matrices include only one element that is "0".
  • Figure 9 is another basic matrix different from that shown in Figure 8.
  • the row weight of the first row 801 of the sub-matrix 802 of the base matrix shown in FIG. 9 is increased.
  • FIG. 10 is a corresponding performance comparison, and it can be found that increasing the row weight performance corresponding to the first row is decreased (the solid line is an example of the basic matrix shown in FIG. 8 in the performance curve, and the dotted line is a comparison example of the basic matrix in FIG. 9), and it can be found.
  • the performance provided by this example is better.
  • the abscissa of Fig. 10 is also the signal-to-noise ratio (SNR), and the ordinate is the block error rate (BLER).
  • SNR signal-to-noise ratio
  • BLER block error rate
  • the dB in Figures 7 and 10 is in units of decibels.
  • the present example also provides an example of a basic matrix of a quasi-cyclic LDPC coding method, the basic matrix including a sub-matrix, and the condition of the sub-matrix can be seen in the example 1, which is not repeated here.
  • the submatrix is a matrix of mb1 rows and nb1 columns, which can be obtained by the following functional relationship:
  • A0 is a matrix of (mb1-1) rows (nb1-mb1) columns
  • A1 is a matrix of (mb1-1) rows mb1 columns
  • A2 is a matrix of 1 row nb1 columns.
  • A1 is the lower triangular structure
  • the row weight of A2 For g0, the last element in A2 is the element used to indicate the shift size of the unit array cyclic shift.
  • the submatrix of the basic matrix is partially constrained.
  • the matrix of the preferred part (corresponding to A1) is a lower triangular structure.
  • A1 is a lower triangular structure, and the lower triangular structure means that an element determined by an arbitrary row index number and an arbitrary column index number in the matrix is equal to -1 when the column index number is larger than the row index number.
  • the row weight distribution of A3 is ⁇ 10, 12, 11, 10 ⁇ .
  • the row weight of the sub-matrix that is, the row weight of other rows except the lightest row weight (that is, the row weight of A3 is heavier), the beneficial effect is that the performance of the long code length can be increased to ensure the long code length. Better performance.
  • the sub-matrix directly corresponds to a part of consecutive element blocks of the basic matrix (the continuous row index number and the continuous column index number are jointly indexed), and the beneficial effect is that the quasi-cyclic LDPC coding can be implemented relatively simple, and no other operations are required. Less latency can increase system communication robustness.
  • the sub-matrix can be regarded as the core matrix of the quasi-cyclic LDPC code, and can support any code rate greater than or equal to R0 and less than 1, but need to adopt the sub-matrix (core matrix) when decoding at the receiving end. Perform decoding.
  • the beneficial effect of the constraint on the sub-matrix is that the number of rows mb0 and the number of columns nb0 of the constrained sub-matrix can make the sub-matrix relatively small, and is updated when high-rate quasi-cyclic LDPC decoding is performed.
  • the number of rows is relatively small, that is, The computational complexity is relatively small, the decoding speed is fast, and the peak decoding throughput is high.
  • elements other than the sub-matrices in the basic matrix are obtained based on the extension of the sub-matrix.
  • the coded information sequence is subjected to quasi-cyclic LDPC coding to obtain an LDPC coded output sequence.
  • Z 128 bits in the same bit block.
  • the reliability is the same, so if interleaving is generally performed, the interleaving is performed in units of bit blocks, and the length of the bit block is equal to the spreading factor value.
  • the spreading factor value Z 128, so the bit block in this example The length is equal to 128.
  • the interleaving method includes:
  • the (mb2-1)th bit block is placed at the forefront of the parity bit.
  • the beneficial effect is that the sequence is started from a certain starting bit. Selected, so at any code rate, the first bit block is always selected first to ensure the performance of quasi-cyclic LDPC encoding.
  • the present example is based on the basic matrix example described in Example 2, in the encoding process, comprising: modifying the basic matrix to obtain a new basic matrix, the modifying method comprising: first performing matrix column shifting and then performing matrix row shifting;
  • the correction method may further include: first performing matrix row shifting The matrix column shift is then performed to obtain the new base matrix.
  • the mb3 is a row index number in the base matrix whose row weight is equal to the minimum row weight is g0, and mb3 is an element value in the set Rset, and it can be known that the mb3 is equal to 5; performing matrix column shift
  • the quasi-cyclic LDPC encoding is performed on the coded information sequence by using the new basic matrix.
  • the beneficial effect is that since the sequential selection is started from a certain starting bit, the first bit block is always preferentially selected at any code rate to ensure quasi-cyclic LDPC encoding. Since the new base matrix itself has been subjected to column and row permutation, there is no need to perform interleaving operations when performing rate matching, which can reduce the interleaving operation of the encoding end, and save transmission time and improve efficiency.
  • the matrix column shift and the matrix row shift performed as described above may also perform the matrix row shift and then the matrix column operation with the same effect, without affecting the scope of the patent protection; and, as described above, the matrix column shift And the matrix row shift operation only shifts one bit block for a certain row or a column of the matrix, and if multiple bit blocks need to be shifted, multiple matrix column shifts and matrix row shift operations can be performed.
  • This example is not limited to performing one matrix column shift and matrix row shift operation, and multiple operations can be performed.
  • Step 2 Perform quasi-cyclic LDPC coding on the coded information sequence based on the one basic matrix and one spreading factor value to obtain an LDPC coded output sequence, where: 1). correct the basic matrix to obtain an extension corresponding to the extension
  • the obtained coding base matrix is shown in Fig. 13.
  • the beneficial effect is that since in the rate matching process, the starting position of the bit selection is generally obtained according to the transmission version number, some bits (or bit blocks) in the information sequence to be encoded are not transmitted, even in the first data transmission. Therefore, in the design of the basic matrix of quasi-cyclic LDPC coding, the minimum row weight of the basic matrix corresponding to the bit block needs to be involved in the bit block check, and it has a certain protection effect to increase the quasi-cyclic LDPC. The performance of the code, which in turn increases the robustness of the communication system.
  • This example provides an example of a basic matrix of quasi-cyclic LDPC coding.
  • the sub-matrix is as shown in FIG.
  • the A1 is a lower triangular structure
  • the last element of the A3 is the The second type of element.
  • This example provides an example of a basic matrix of quasi-cyclic LDPC coding.
  • the A1 is a double diagonal structure
  • the last element of the A3 is the second type of element.
  • the sub-matrix may also be three rows, and details are not described herein again.
  • This example provides an example of a basic matrix of quasi-cyclic LDPC coding.
  • Line nb2 16 columns.
  • the row weight is 5.
  • the row index number of the largest row weight (equal to 3) in the matrix B1 (2304 shown in FIG. 23) is 2, that is, exactly equal to the i.
  • Reference numeral 2304 is another matrix B0 constituting the sub-matrix 2301.
  • Reference numeral 2303 is another sub-matrix in the base matrix.
  • This example provides an example of a basic matrix of quasi-cyclic LDPC coding.
  • the C2 is a lower triangular structure.
  • corresponding to the matrix C2 is a double diagonal structure, as shown in FIG.
  • the present example provides an example of a basic matrix of quasi-cyclic LDPC coding in which at least 80% of the positions of the elements of the second type of elements are the same as the positions of '1' in the reference matrix, and the reference matrix is from the matrix ( As shown in Fig. 26), the row index number is set Set0 and the column index number is set to be set Set1, as shown in Fig. 26, the matrix is a matrix of 26 rows and 38 columns.
  • the set Set0 ⁇ 0,1,2,...,25 ⁇
  • Figure 27 shows an example of a base matrix comprising a sub-matrix 2701 in which the position of the second type of element has 100% element position identical to the position of '1' in the reference matrix.
  • the position of the element of the second type of element having 80% (or between 80% and 100%) being the same as the position of '1' in the reference matrix.
  • the reference matrix is obtained from the matrix (as shown in FIG. 28) by the row index number being the set Set0 and the column index number being the set Set1, as shown in FIG. 28, the matrix is a 34 row.
  • the embodiment of the present invention discloses a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used in the LPDC encoding method provided by the foregoing one or more technical solutions, for example, performing, for example, The method shown in Figure 2.
  • the computer storage medium provided in this embodiment may be: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, and the program code may be stored.
  • the medium can be selected as a non-transitory storage medium or a non-volatile storage medium.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division, and may be implemented in actual implementation. Additional ways of dividing, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the above integration
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the specific base matrix is set, so that the row weight of the sub-matrix formed based on the basic matrix is not less than the sum of g0 and ⁇ g; such row redistribution will make the decoding performance after encoding good, and It maintains great flexibility and has a positive industrial effect.
  • the technical solution provided by the embodiment of the present invention can realize high-performance decoding by defining the basic matrix, so that it can be widely applied in industry and has strong industrial applicability.

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Abstract

本发明实施例公开了一种LPDC编码方法及装置，方法包括：基于一个基础矩阵和一个扩展因子值，对待编码信息进行准循环LDPC编码，得到LDPC编码输出序列；其中，所述基础矩阵中包括：第一类元素和第二类元素；所述基础矩阵中包括至少一个子矩阵；所述子矩阵的第i行的行重为g0，所述g0的取值位于预设范围内的正整数；所述子矩阵的第j行的行重不小于g0与Δg的和，其中，所述j不等于所述i；所述i和j均是所述子矩阵的行索引号，所述Δg是大于预设值的正整数，所述行重为所述子矩阵对应行所述第二类元素的个数；从所述LDPC编码输出序列中选出速率匹配输出序列。本发明实施例还公开了一种计算机存储介质。

Description

准循环低密度奇偶校验编码方法、装置和存储介质
本申请基于申请号为201710005652.8、申请日为2017年01月04日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及通信技术领域，尤其涉及一种准循环低密度奇偶校验(Low Density Parity Check，LDPC)编码方法、装置和存储介质。
背景技术
图1是根据相关技术的数字通信系统的结构框图。如图1所示，数字通信系统中一般包括三个部分：发送端、信道和接收端。发送端可对信息序列进行信道编码从而获取编码码字，对编码码字进行交织，并将交织后的比特映射成调制符号，然后可以根据通信信道信息来处理和发送调制符号。在信道中，由于多径、移动等因素导致特定的信道响应等因素都会使数据传输失真，同时由于噪声和干扰也会进一步恶化数据传输。接收端接收通过信道后的调制符号数据，此时的调制符号数据已经失真，需要进行特定处理才能恢复原始信息序列。
根据发送端对信息序列的编码方法，接收端可以对接收数据进行相应处理从而可靠地恢复原始信息序列。所述的编码方式必须是收发双端都是可见的，即都知晓的。一般地，所述编码方式可是基于前向纠错(Forward Error Correction，FEC)编码，其中，前向纠错编码在信息序列中添加一些冗余信息。接收端可以利用该冗余信息来可靠地恢复原始信息序列。
在发送端，需要对待传输的传输块进行码块分割获得多份小传输块，然后对多份小传输块分别进行FEC编码，所述待传输的传输块长度简称为 TBS是Transport Block Size的缩写。FEC编码码率一般定义为进入编码器的比特数目比上实际传输比特的比值。在长期演进(Long Term Evolution，LTE)系统中，非常灵活的传输块尺寸可以支持LTE系统的各种包长度需求，以及采用调制编码方案(Modulation and Coding Scheme，MCS)索引来指示不同调制阶数和编码码率R以及确定TBS索引，以及根据资源块(Resource Block，RB)数目(Number of Resource Block，NRB)和传输块尺寸(TBS)索引来确定在不同的传输块尺寸，所述资源块尺寸是：连续12子载波在1个时隙上的通信资源并去除一些控制信号和参考信号所剩下的资源。信道类型中可以包括：数据信道和控制信道。数据信道一般承载的是用户数据。控制信道承载控制信息，包括MCS索引号、信道信息等控制类信息。带宽尺寸一般是指系统分配给数据传输所占用的带宽宽度，LTE系统中分为20M、10M、5M等带宽。数据传输方向包括：上行方向和下行方向，所述上行方向为上行数据的传输方向。所述上行数据可为用户设备向基站传输的数据，所述下行方向为下行数据的传输方向。所述下行数据可基站向用户设备传输的数据。
一些常见的FEC编码包括：卷积码、Turbo码和低密度奇偶校验(Low Density Parity Check，LDPC)码。FEC编码过程中，对比特数目为k的信息序列进行FEC编码获得n比特的FEC编码码字(冗余比特为n-k)，FEC编码码率为k/n。LDPC码是一种可以用非常稀疏的奇偶校验矩阵或者二分图定义的线性分组码，正是利用它的校验矩阵的稀疏性，才能实现低复杂度的编译码，从而使得LDPC走向实用化。经过各种实践和理论证明，LDPC码是在加性高斯白噪声(Additive White Gaussian Noise，AWGN)信道下性能最为优良的信道编码，性能非常靠近香农极限。
在通信协议IEEE802.11ac、IEEE802.11ad、IEEE802.11aj、IEEE802.16e、IEEE802.11n、微波通信以及光纤通信等通信协议中，LDPC码都获得大量 应用。LDPC码的奇偶校验矩阵中，每一行都是一个奇偶校验码，每一行中如果某一索引位置元素值等于1则说明该比特参与到该奇偶校验码，如果等于0，则说明该位置比特不参与该奇偶校验码。而准循环LDPC码(quasi-cyclic LDPC)的奇偶校验矩阵H为mb×Z行和nb×Z列的矩阵。即H是由mb×nb个子矩阵构成，每个子矩阵都是为Z×Z的基本置换矩阵的不同幂次，也可以认为是大小为Z×Z单位阵的循环移位若干值所获得的子矩阵。此时，只要知道循环移位值以及子矩阵维度就可以确定一个准循环LDPC码，所述的所有移位值构成一个mb×nb矩阵，可以称为基础矩阵或者基础校验矩阵或者原模图(base photograph)。但是现有技术中的在进行LDPC编码时，总是很难在保证编码灵活性的情况下，确保编码性能，特别是在高码率下的性能。这里额编码灵活性值的是支持的编码码率和编码长度的可选择性。编码性能包括编码的正确性等。
发明内容
有鉴于此，本发明实施例期望提供一种准循环LDPC编码方法、装置和存储介质，以解决上述问题。
本发明实施例的技术方案是这样实现的：
本发明实施例第一方面提供一种LPDC编码方法，包括：
基于一个基础矩阵和一个扩展因子值，对待编码信息进行准循环LDPC编码，得到LDPC编码输出序列；其中，所述基础矩阵中包括：第一类元素和第二类元素；所述基础矩阵中包括至少一个子矩阵；所述子矩阵的第i行的行重为g0，所述g0的取值位于预设范围内；所述子矩阵的第j行的行重不小于g0与Δg的和，其中，所述j不等于所述i；所述i和j均是所述子矩阵的行索引号，所述Δg是大于预设值的正整数，所述行重为所述子矩阵对应行所述第二类元素的个数；
从所述LDPC编码输出序列中选出速率匹配输出序列。
本发明实施例第二方面提供一种准循环低密度奇偶校验LPDC编码装置，包括：
编码单元，配置为基于一个基础矩阵和一个扩展因子值，对待编码信息进行准循环LDPC编码，得到LDPC编码输出序列；其中，所述基础矩阵中包括：第一类元素和第二类元素；所述基础矩阵中包括至少一个子矩阵；所述子矩阵的第i行的行重为g0，所述g0的取值位于预设范围内；所述子矩阵的第j行的行重不小于g0与Δg之和，其中，所述j不等于所述i；所述i和j均是所述子矩阵的行索引号，所述Δg是大于预设值的正整数，所述行重为所述子矩阵对应行所述第二类元素的个数；
速率匹配单元，配置为从所述LDPC编码输出序列中选出速率匹配输出序列。
本发明实施例公开了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于上述LPDC编码方法。
本发明实施例提供的一种准循环LDPC编码方法及装置，用于进行编码的基础矩阵为特别设定的矩阵，该基础矩阵至少包括一个子矩阵；所述子矩阵列行数差小于或等于所述基础矩阵的列行数差，且所述子矩阵和所述基础矩阵的列数均大于行数；所述子矩阵的最小行重为g0，所述g0的取值位于预设范围内；子矩阵的其他行重都不小于g0与Δg的和；所述行重为所述子矩阵一行元素中替换非第二类元素的个数。利用这种基础矩阵进行编码的时候，因为最小行重为g0，则表示该子矩阵的所有行重都不小于g0与Δg的和，这样的行重分布会使得高译码率和低译码率都有较好的译码性能，从而在确保灵活性的前提下，确保译性能。
附图说明
图1是根据相关技术的数字通信系统的结构框图；
图2是本发明实施例提供的一种准循环LDPC编码方法的流程示意图；
图3是本发明实施例提供的一种基础矩阵及子矩阵的示意图；
图4是本发明实施例提供的一种准循环LDPC编码装置的结构示意图；
图5是本发明实施例提供第一种准循环LDPC编码的基础矩阵的示例图；
图6是本发明实施例提供的第二种基础矩阵的示例图
图7是本发明实施例的一种准循环LDPC编码的性能示意图；
图8是本发明实施例提供的第三种基础矩阵的示例图；
图9是根据本发明示例的一种基础矩阵对比示例2
图10是本发明实施例提供的另一种准循环LDPC编码的性能示意图
图11是本发明实施例提供的第三种基础矩阵的示例图；
图12是本发明实施例提供的一种基础矩阵的交织示例图；
图13是本发明实施例提供的第四种基础矩阵的示例图；
图14是本发明实施例提供的第五种基础矩阵的示例图；
图15是本发明实施例提供的一个子矩阵的示意图；
图16是本发明实施例提供的另一个子矩阵的示意图。
图17是本发明实施例提供的另一个子矩阵的示意图。
图18是本发明实施例提供的另一个子矩阵的示意图。
图19是本发明实施例提供的另一个子矩阵的示意图。
图20是本发明实施例提供的另一个子矩阵的示意图。
图21是本发明实施例提供的另一个子矩阵的示意图。
图22是本发明实施例提供的另一个子矩阵的示意图。
图23是本发明实施例提供的另一个子矩阵的示意图。
图24是本发明实施例提供的另一个子矩阵的示意图。
图25是本发明实施例提供的另一个子矩阵的示意图。
图26是本发明实施例提供的参考矩阵的示意图。
图27是本发明实施例提供的另一个子矩阵的示意图。
图28是本发明实施例提供的另一个参考矩阵的示意图。
具体实施方式
以下结合说明书附图及具体实施例对本发明的技术方案做进一步的详细阐述，应当理解，以下所说明的优选实施例仅用于说明和解释本发明，并不用于限定本发明。
如图2所示，本实施例提供一种准循环LPDC编码方法，包括：
步骤S110：基于一个基础矩阵和一个扩展因子值，对待编码信息进行准循环LDPC编码，得到LDPC编码输出序列；
其中，所述基础矩阵中包括：第一类元素和第二类元素；所述基础矩阵中包括至少一个子矩阵；所述子矩阵的第i行的行重为g0，所述g0的取值位于预设范围内的正整数；所述子矩阵的第j行的行重不小于g0与Δg的和，其中，所述j不等于所述i；所述i和j均是所述子矩阵的行索引号，所述Δg是大于预设值的正整数，所述行重为所述子矩阵对应行所述第二类元素的个数；
步骤S120：从所述LDPC编码输出序列中选出速率匹配输出序列
本实施例所述LPDC编码方法为利用于发送端的方法。
在本实施例中将可包括获取一个扩展因子集合，所述扩展因子集合包括一个或多个扩展因子值，进行LDPC编码的扩展因子值来自于所述扩展因子集合。所述扩展因子集合包括至少一个扩展因子值，通常情况下为包括2个或2个以上的扩展因子值。所述扩展因子值的取值等于所述全零方阵和所述单位方阵的维度。在本实施例中所述全零方阵和所述单位方阵均为行数等于列数的矩阵。所述扩展因子值可为指示述全零方阵和所述单位方阵的行数或列数的值。
所述基础矩阵为非空矩阵，所述非空矩阵为包括至少一个元素的矩阵， 即所述基础矩阵的行数和列数都不小于1。在本实施例中所述基础矩阵的行数可为mb，所述基础矩阵的列数为nb；且所述nb大于所述mb，且mb和nb都为正整数。这样的话，所述基础矩阵为列维度大于行维度的矩阵。
所述基础矩阵中的元素可分为两大类，一类是第一类元素，另一类为所述第一类元素以外的第二类元素。例如，在本实施例中所述第一类元素可为取值为预定值的元素，在本实施例中所述第一类元素可为取值为-1的元素；所述第二类元素可为非-1的元素，为0或正整数。所述第一类元素，用于为替换全零方阵的元素；所述第二类元素为替换为预定矩阵的元素，且用于指示形成所述预设矩阵的单位方阵循环位移的位移步长；所述扩展因子集合，包括至少一个扩展因子值。在一些实施例中，所述子矩阵列行数差小于或等于所述基础矩阵的列行数差，且所述子矩阵和所述基础矩阵的列数均大于行数。
所述g0的取值可为不大于5的正整数，例如，2，3，5等。所述Δg的取值可为3、2或4等取值。
在一些实施例中，在步骤S110之前，还可包括步骤S100；所述步骤S100可包括：获取所述基础矩阵和所述扩展因子集合，可选可包括：在发送端的存储介质中查询所述基础矩阵和所述扩展因子集合。当然，在一些实施例中，所述步骤S110还可包括：从外设接收所述基础矩阵或拓展因子值集合，例如，从通信对端接收所述基础矩阵和拓展因子值，利用从通信对端接收的基础矩阵和拓展因子值集合进行编码，方便通信对端利用对应的基础矩阵和拓展因子值集合进行解码。
在本实施例中所述基础矩阵和所述拓展因子值可用于形成奇偶校验矩阵。所述基础矩阵中一个元素替换为一个所述全零矩阵或单位方阵循环移位后的预设方阵。这里循环位移的步长等于一个所述第二类元素的取值。所述第二类元素的取值可为0或正整数；当一个所述第二类元素为x，则所 述循环位移的位移步长就等于x。
所述基础矩阵的特定行及特定列的元素可以构成上述子矩阵，这里的子矩阵的最小行重小于指定值，其他行重都不小于预设值，例如，其他行的行重均不小于指定值与Δg的和。这里的预设值可为任意取值，在本实施例中所述指定值取值为4或5等各种取值。
例如，基础矩阵Hb为2行4列的矩阵，具体如下：
Figure PCTCN2017110133-appb-000001
假设扩展因子值等于4，则在编码过程中形成奇偶校验矩阵时，利用行数和列数均等于4的全零矩阵，或行数和列数均等于4的单位矩阵循环位移后矩阵替换基础矩阵中的元素。
上述基础矩阵对应的奇偶校验矩阵H为：
Figure PCTCN2017110133-appb-000002
在上述基础矩阵Hb中非-1元素等于0，则单位方阵不进行循环位移，若非-1元素为2，则单位方阵循环位移之后的预设矩阵为：
Figure PCTCN2017110133-appb-000003
在步骤S110中将待编码信息对应到所述奇偶校验矩阵中。通常所述待编码信息中一个比特块对应于基础矩阵中的一列元素S，即对应于该奇偶校验矩阵与S对应的子矩阵。在完成待编码信息的对应之后，所述奇偶校验矩阵中未与待编码信息进行对应的列均作为该待编码信息的校验码，完成 对应之后进行编码，变么得到LDPC编码输出序列；输出的LDPC编码序列的维度等于所述奇偶校验码的维度。
准循环LDPC编码的基础矩阵一般包括2部分：系统列部分矩阵和校验列部分矩阵。一个mb×nb的基础矩阵，一般来说前(nb-mb)列是系统列部分矩阵，后mb列是校验列部分矩阵。校验列部分矩阵包括两种结构：下三角结构和双对角结构。其中，所述下三角结构是指矩阵中任意行索引号和任意列索引号所确定的元素在所述列索引号大于所述行索引号时都等于-1(用于指示替换为全零矩阵的元素，本发明实施例中描述为第一类元素)；所述双对角结构是指：矩阵中，行索引号为0且列索引号为0所确定的元素是非-1元素(本实施例中描述为第二类元素)，并且在列索引号为i情况下行索引号为i和(i+1)所确定的2个元素都是非-1元素，以及列索引号为i0和行索引号i1所所索引的元素值等于-1，其中。i0大于i1+1。本发明实施例中的所有下三角结构描述和双对角结构都与以上描述是一致的。若矩阵经过行置换和/或列置换之后，得到下三角结构和双对角结构也可认为是上述基础举证。在步骤S120中会选择LDPC编码输出序列中的部分序列输出。在执行步骤S130时，将会根据根据编码速率，选择出LDPC编码输出序列中有多少个部分输出；从而确保灵活性。
而在本实施例中由于所述基础矩阵包括一个满足上述条件的子矩阵，这样的话，编码信息对应的奇偶校验矩阵中非全零矩阵的分布满足子矩阵的行重分布，在进行编码时可以减少编码过程中的短4环或短6环现象导致的编码性能的降低，从而可以确保编码性能。
在一些实施例中所述子矩阵可为基础矩阵确定之后，通过挑选基础矩阵中的特定行和特定列的元素来构成，在有一些实施例中，所述基础矩阵是在子矩阵确定之后生成的。例如，生成所述基础矩阵的方法包括：确定所述子矩阵，基于所述子矩阵进行矩阵拓展，得到所述基础矩阵中所述子 矩阵以外的元素，得到所述基础矩阵。在进行所述基础矩阵拓展时，可以随机添加第一类元素和第二类元素，通常添加的第一类元素较多。在本实施例中所述基础矩阵基于子矩阵的拓展可以采用现有的任意方法，在本实施例中可以不做限定。
如图3所示，基础矩阵302包括：mb0行nb0列的子矩阵301，标号303指示的元素为基础矩阵302中除所述子矩阵301的元素，均可是基于子矩阵301拓展而来的。
所述子矩阵为mb0行nb0列的矩阵，确定所述子矩阵的方式有多种，以下提供两种可选方式：
可选方式一：
所述子矩阵为mb0行nb0列的矩阵，所述i等于0，且所述子矩阵为：
Figure PCTCN2017110133-appb-000004
其中，所述A为mb0行(nb0-mb0)列的矩阵，所述B是1行1列的矩阵，所述C是(mb0-1)行1列的矩阵，所述D是1行(mb0-1)列的矩阵，所述E是(mb0-1)行(mb0-1)列的矩阵；所述A中首行的行重最小且首行的行重等于g0-1；所述B中包括1个所述第二类元素；所述C包括(mb0-1)个所述第一类元素；所述D包括：(mb0-1)个所述第一类元素；所述E是下三角结构或者双对角结构子矩阵。子矩阵可选方式二：
所述子矩阵为mb1行nb1列的矩阵，所述i等于(mb1-1)，且所述子矩阵为：
Figure PCTCN2017110133-appb-000005
其中，所述A0是(mb1-1)行(nb1-mb1)列的矩阵，所述A1是(mb1-1)行(mb1-1)列的矩阵，所述A2是(mb1-1)行1列的矩阵，所述A3是1行nb1列的矩阵。
在某些实施例中，所述A1可是下三角结构或双对角结构，当所述A1为双对角结构时，所述mb1等于以下整数之一：3、4、5。
在另一些实施例中，所述A3的最后一个元素为所述第二类元素。
可选方式三：
所述子矩阵为：[B0 B1]，
所述B0为mb2行kb2列的矩阵，所述B1是mb2行mb2列的矩阵，所述B1是双对角结构；其中，mb2是所述子矩阵的行数，nb2是所述子矩阵的列数，kb2＝nb2–mb2。
在一些实施例中，所述矩阵B1中最大行重所在行的元素在所述基础矩阵中的行索引号等于所述i。
可选方式三：
所述i等于0，且所述子矩阵为：
Figure PCTCN2017110133-appb-000006
其中，所述C0为1行nb3列的矩阵，所述C1是(mb3-1)行(kb3+1)列的矩阵，所述C2是(mb3-1)行(mb3-1)列的矩阵；所述C2是下三角结构或者双对角结构；其中，所述mb3是所述子矩阵的行数，所述nb3是所述子矩阵的列数，kb3＝nb3–mb3。
所述i＝0，表明所述子矩阵的首行的行重最小。
以上方式都提供简便获得子矩阵的方法，当一个基础矩阵的子矩阵确定了之后，所述基础矩阵可以在所述子矩阵的基础上进行拓展，从而拓展得到所述子矩阵。当确定了所述子矩阵之后，可以通过随机添加所需个数的元素，从而得到所述基础矩阵，例如，在所述子矩阵的基础上，随机条件第一类元素和/或第二类元素得到所述基础矩阵。
子矩阵总之采用上述方式都可以快速的构建所述子矩阵，进而通过子矩阵的拓展快速得到所述基础矩阵。
所述基础矩阵为mb行nb列的矩阵，所述基础矩阵为[D0 D1]，其中， 所述D0是mb行kb列的矩阵，所述D1是mb行mb列的矩阵；所述D1中第i行的所有第二类元素在所述基础矩阵中第i行的的列索引号形成集合Cset。
所述LDPC编码输出序列包括：nb个比特块；所述nb个比特块包括：比特块索引号为0至(kb-1)的kb个系统比特块和比特块索引号为kb至(nb-1)的mb个校验比特块。
所述步骤S120可包括：
对所述LDPC编码输出序列按预设交织序列进行交织，获得交织后输出序列，其中，所述预设交织序序列的第kb至第(kb+t-1)个元素等于所述集合Cset中的元素值；所述预设交织序列包括的元素数目小于或等于所述nb；所述t是所述集合Cset的元素数目；
对完成交织后的所述交织后输出序列进行选择，获得所述速率匹配输出序列。
所述预设交织序列可为预先设定的，可用于指示基础矩阵中的行列交换，通过所述行列交换可以得到所述交织后的输出序列。这里的交织可包括：可以根据所述预设交织序列先进行行交换，然后进行列交换；也可以根据所述预设交织序列先进行列交换，再进行行交换。
子矩阵所述步骤S120的可实现方式有多种，除了上述方式，本实施例还提供另一种可实现方式：
所述基础矩阵为mb行nb列的矩阵，所述基础矩阵为[D0 D1]，其中，所述D0是mb行kb列的矩阵，所述D1是mb行mb列的矩阵；所述D1中第i行的所有第二类元素在所述基础矩阵中第i行的的列索引号形成集合Cset；
所述步骤S120可包括：对所述基础矩阵进行矩阵的行列移位，获得修正后的基础矩阵，其中，所述修正后的基础矩阵的第kb列至第(kb+t-1)列等 于所述集合Cset中所有元素指示所述基础矩阵中的列；所述修正后的基础矩阵的第(kb+t)列至第(kb+t1-1)列等于集合Cset’中所有元素指示所述基础矩阵的列，其中，所述集合Cset’是集合{kb,kb+1,…,(kb+t1-1)}与所述集合Cset的差集，t1是所述集合Cset中的最大元素值减去(nb-mb)获得的数值，所述t是所述集合Cset的元素数目；采用所述修正后的基础矩阵对待编码信息序列进行准循环LDPC编码。
子矩阵在本实施例中进行所述行列位移，包括：先进行行位移，然后进行列位移；或者，先进行列位移，在进行行位移。但是位移的目的是是的修正后的基础矩阵，相对于修正前的矩阵，上述行列元素之间的位置交换。所述行行位移可包括：行与行之间的位置交换；所述行列位移可包括：行交换和列交换。
所述子矩阵中元素在所述基础矩阵中的行索引号形成集合Rset0，所述子矩阵中元素在所述基础矩阵中的列索引号形成集合Cset0；其中，所述行索引号和所述列索引号连续分布。
例如，根据所述Rset的行索引号和所述Cset的列索引号，选择出对应的元素构成了所述子矩阵。在本实施例中所述Rset的行索引号和Cset中的列索引号都连续分布。例如，从x1，x1+1…x1+y。在本实施例中进一步优选为Rset和Cset的索引号都连续分布，且都从0开始取值。这样的话，子矩阵就为基础矩阵中左上角的一部分元素构成。这样可以简化LDPC编码，降低编码延时，提升通信系统的鲁棒性。
在还有一些实施例中，所述集合Rset0为0到(mb’-1)构成的集合，所述集合Cset0为0到(nb’-1)构成的集合，其中，mb’是所述集合Rset0的元素数目，nb’是所述集合Cset0的元素数目。
在还有一些实施例中，所述步骤S120可包括：
去除所述待编码信息序列的E个比特块，基于所述待编码信息序列中 的剩余编码信息序列确定出所述速率匹配输出序列；
其中，所述E个比特块对应于所述基础矩阵的列索引号构成集合T0；所述子矩阵中第i行中第二类元素的列索引号构成集合T1；其中所述集合T0是所述集合T1的子集。
所述E个比特块对应于所述基础矩阵的列索引号构成集合T0；所述子矩阵中的行重等于所述g0的行中第二类元素在所述基础矩阵中所在列索引号，构成集合T1；所述集合T0是所述集合T1的子集。例如，子矩阵最小行重的行中第二类元素在所述基础矩阵中的第3，5，7，8列，则所述T1包括3，5，7，8。所述T0为3，5，7，8中的一个或多个元素构成。
这里的E取值为0或正整数，小于所述待编码信息包括的总比特块数。去除了部分传输的比特块，则剩余的为需要输出的满足编码速率的速率匹配输出序列。当E大于2时，所述E个比特块为所述待编码信息中连续分布的多个比特块。
在一些实施例中，mb4为所述子矩阵的行数；nb4为所述子矩阵的列数；所述mb4和所述nb4满足：(nb4-mb4)/nb4＝＝R0，其中，所述R0是大于0.5且小于1的实数，R0的取值为大于0.5且小于1的实数，这样的限定可以确保高码率编码的编码性能。
若所述mb4等于所述mb0，则所述nb4等于所述nb0，若所述mb4等于所述mb1，则所述nb1等于所述nb1。
在一些实施例中，所述基础矩阵中第二类元素的位置至少有预设比例的元素位置与参考矩阵中‘1’的位置相同，所述参考矩阵从以下矩阵中截取；所述参考矩阵截取以下矩阵的行索引号构成集合Set0，且所述参考矩阵截取以下矩阵的列索引号构成集合Set1；
Figure PCTCN2017110133-appb-000007
所述集合Set0包括的元素数目为mb，所述集合Set1包括的元素数目为nb，nb大于mb。
这里的预设比例的取之可为80％、75％或60％或85％等。
如图4所示，本实施例提供一种准循环LPDC编码装置，包括：
编码单元110，配置为基于一个基础矩阵和一个扩展因子值，对待编码信息进行准循环LDPC编码，得到LDPC编码输出序列；其中，所述基础矩阵中包括：第一类元素和第二类元素；所述基础矩阵中包括至少一个子矩阵；所述子矩阵的第i行的行重为g0，所述g0的取值位于预设范围内；所述子矩阵的第j行的行重不小于g0与Δg之和，其中，所述j不等于所述i；所述i和j均是所述子矩阵的行索引号，所述Δg是大于预设值的正整数，所述行重为所述子矩阵对应行所述第二类元素的个数；
速率匹配单元120，配置为从所述LDPC编码输出序列中选出速率匹配输出序列。
本实施例所述装置可为实现前述方法的装置，可用于发送端的装置。在本实施例中所述编码单元110和速率匹配单元120都可对应于处理器或处理电路。所述处理器可包括中央处理器(CPU)、数字信号处理(DSP)、应用处理器(AP)、微处理器(MCU)或可编程阵列(PLC)等。所述处理电路可包括专用集成电路(ASIC)。所述编码单元110还可对应于专用的编码器等。所述处理器或处理电路，可通过特定指令的执行，实现上述操作。
在本实施例中、编码单元110和速率匹配单元120可对应于同一个处理器或处理电路，也可以对应于不同的处理器或处理电路。当这些功能单元对应于不同的处理器时，这些处理器之间相互连接，可以实现上述操作，从而进行灵活编码的同时，确保编码性能。
所述子矩阵为mb0行nb0列的矩阵，所述处理器或处理电路可以根据函数关系，计算得到所述子矩阵，再根据子矩阵拓展得到基础矩阵。当然，所述处理或处理电路，也可以先获得到基础矩阵，再确定出所述基础矩阵中是否可以选择出满足上述要求的子矩阵。
所述子矩阵为mb0行nb0列的矩阵，所述i等于0，且所述子矩阵为：
Figure PCTCN2017110133-appb-000008
其中，所述A为mb0行(nb0-mb0)列的矩阵，所述B是1行1列的矩阵，所述C是(mb0-1)行1列的矩阵，所述D是1行(mb0-1)列的矩阵，所述E是(mb0-1)行(mb0-1)列的矩阵；所述A中首行的行重最小且首行的行重等于g0-1；所述B中包括1个所述第二类元素；所述C包括(mb0-1)个所述第一类元素；所述D包括：(mb0-1)个所述第一类元素；所述E是下三角结构或者双对角结构。
在一些实施例中，所述子矩阵为mb1行nb1列的矩阵，所述i等于(mb1-1)，且所述子矩阵为：
Figure PCTCN2017110133-appb-000009
其中，所述A0是(mb1-1)行(nb1-mb1)列的矩阵，所述A1是(mb1-1)行(mb1-1)列的矩阵，所述A2是(mb1-1)行1列的矩阵，所述A3是1行nb1列的矩阵。
可选地，所述A1是下三角结构或双对角结构，当所述A1为双对角结构是，则所述mb1等于以下整数之一：3、4、5。
可选地，所述A3的最后一个元素为所述第二类元素。
在另一个实施例中，所述子矩阵为：[B0 B1]，其中，所述B0为mb2行kb2列的矩阵，所述B1是mb2行mb2列的矩阵，所述B1是双对角结构；其中，mb2是所述子矩阵的行数，nb2是所述子矩阵的列数，kb2＝nb2–mb2。
可选地，所述矩阵B1中最大行重所在行的元素在所述基础矩阵中的行索引号等于所述i。
在另一个实施例中中，所述i等于0，且所述子矩阵为：
Figure PCTCN2017110133-appb-000010
所述C0为1行nb3列的矩阵，所述C1是(mb3-1)行(kb3+1)列的矩阵，所述C2是(mb3-1)行(mb3-1)列的矩阵；所述C2是下三角结构或者双对角结构；其中，所述mb3是所述子矩阵的行数，所述nb3是所述子矩阵的列数，kb3＝nb3–mb3。
在一些实施例中，所述基础矩阵为mb行nb列的矩阵，所述基础矩阵为[D0D1]，其中，所述D0是mb行kb列的矩阵，所述D1是mb行mb列的矩阵；所述D1中第i行的所有第二类元素在所述基础矩阵中第i行的的列索引号形成集合Cset；
所述LDPC编码输出序列包括：nb个比特块；
所述nb个比特块包括：比特块索引号为0至(kb-1)的kb个系统比特块和比特块索引号为kb至(nb-1)的mb个校验比特块；
所述速率匹配单元120，具体用于对所述LDPC编码输出序列按预设交织序列进行交织，获得交织后输出序列，其中，所述预设交织序序列的第kb至第(kb+t-1)个元素等于所述集合Cset中的元素值；所述预设交织序列包括的元素数目小于或等于所述nb；所述t是所述集合Cset的元素数目；对完成交织后的所述交织后输出序列进行选择，获得所述速率匹配输出序列。
在另一些实施例中，所述基础矩阵为mb行nb列的矩阵，所述基础矩 阵为[D0 D1]，其中，所述D0是mb行kb列的矩阵，所述D1是mb行mb列的矩阵；所述D1中第i行的所有第二类元素在所述基础矩阵中第i行的的列索引号形成集合Cset；所述编码单元120，具体用于对所述基础矩阵进行矩阵的行列移位，获得修正后的基础矩阵，其中，所述修正后的基础矩阵的第kb列至第(kb+t-1)列等于所述集合Cset中所有元素指示所述基础矩阵中的列；所述修正后的基础矩阵的第(kb+t)列至第(kb+t1-1)列等于集合Cset’中所有元素指示所述基础矩阵的列，其中，所述集合Cset’是集合{kb,kb+1,…,(kb+t1-1)}与所述集合Cset的差集，t1是所述集合Cset中的最大元素值减去(nb-mb)获得的数值，所述t是所述集合Cset的元素数目；采用所述修正后的基础矩阵对待编码信息序列进行准循环LDPC编码。
此外，所述子矩阵中元素在所述基础矩阵中的行索引号形成集合Rset0，所述子矩阵中元素在所述基础矩阵中的列索引号形成集合Cset0；其中，所述行索引号和所述列索引号连续分布。
在一些实施例中，所述集合Rset0为0到(mb’-1)构成的集合，所述集合Cset0为0到(nb’-1)构成的集合，其中，mb’是所述集合Rset0的元素数目，nb’是所述集合Cset0的元素数目。
此外，所述速率匹配单元120，具体用于去除所述待编码信息序列的E个比特块，基于所述待编码信息序列中的剩余编码信息序列确定出所述速率匹配输出序列；其中，所述E个比特块对应于所述基础矩阵的列索引号构成集合T0；所述子矩阵中第i行中第二类元素的列索引号构成集合T1；其中所述集合T0是所述集合T1的子集。
当mb4为所述子矩阵的行数，nb4为所述子矩阵的列数；所述mb4和所述nb4满足：(nb4-mb4)/nb4＝＝R0，其中，所述R0是大于0.5且小于1的实数。这样可以确保编码的鲁棒性。
在一些实施例中，所述子矩阵的列行数差等于所述基础矩阵的列行数 差，且所述子矩阵的列数大于所述子矩阵的行数，所述基础矩阵的列数大于所述基础矩阵的行数。
此外，所述g0的取值位于预设范围内，包括：所述g0是不大于5的正整数；所述预设值等于3或4。
在一些实施例中，所述基础矩阵中第二类元素的位置至少有预设比例的元素位置与参考矩阵中‘1’的位置相同，所述参考矩阵从以下矩阵中截取；所述参考矩阵截取以下矩阵的行索引号构成集合Set0，且所述参考矩阵截取以下矩阵的列索引号构成集合Set1；
Figure PCTCN2017110133-appb-000011
所述集合Set0包括的元素数目为mb，所述集合Set1包括的元素数目为nb，nb大于mb。
这里的预设比例的取之可为80％、75％或60％或85％等。
以下结合上述任意实施例提供几个具体示例：
示例1：
本示例提供一种准循环LDPC编码的方法，包括以下步骤：
步骤1、从存储模块中获取准循环LDPC编码所用的一个基础矩阵和一个扩展因子值；所述基础矩阵中包含用于指示全零方阵的元素和用于指示单位阵循环移位的移位步长的元素，所述扩展因子值用于指示所述全零方阵或所述单位阵的行数，所述扩展因子值是大于0的整数。这里的的存储 模块对应于前述的，具体可对应于存储介质。
所述基础矩阵中子矩阵。该子矩阵包括的元素在基础矩阵中的行索引号够为集合Rset；该子矩阵包括的元素在基础矩阵中的列索引号构成集合Cset。子矩阵的最小行重为g0，其中，g0是大于1且小于5的整数，子矩阵的其他行的行重等于5或大于5。所述集合Rset是所述基础矩阵的所有行索引号所构成集合的一个子集，所述集合Cset是所述基础矩阵的所有列索引号所构成集合的一个子集。所述子矩阵的列数减去所述子矩阵的行数所获得的数值小于或等于所述基础矩阵的列数减去所述基础矩阵的行数所获得的数值；
步骤2、基于所述一个基础矩阵和一个扩展因子值，对待编码信息序列进行准循环LDPC编码，得到LDPC编码输出序列；
步骤3、从所述LDPC编码输出序列中，选择出速率匹配输出序列。
步骤1中，所述基础矩阵为如下：
可选地，所述子矩阵是一个mb0行nb0列的矩阵Hb0mb0×nb0，包括：
Figure PCTCN2017110133-appb-000012
其中，A为A mb0行(nb0-mb0)列的矩阵，B是1行1列的矩阵，C是(mb0-1)行1列的矩阵，D是1行(mb0-1)列的矩阵，EE是(mb0-1)行(mb0-1)列的矩阵。A中首行的行重最小且首行的行重等于g0-1，B中包括1个用于指示单位阵循环移位的移位步长的元素，D中包括(mb0-1)个用于指示全零方阵的元素，E是下三角结构或者双对角结构。
在图5中所述的一个基础矩阵的示例，所处存储模块中存储所述基础矩阵，所述基础矩阵是mb＝18行nb＝26列的矩阵，对应的最大扩展因子值为1024，矩阵中的取值为‘-1’元素是指用于指示全零方阵的第一类元素，对应的准循环LDPC码的奇偶校验矩阵的一个全零方阵的子块，而其他元素都是指用于指示单位阵循环移位的移位步长的元素。
行索引号为集合Rset＝{0，1，2，3，4}且列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12}，所述行索引号为集合Rset且列索引号为集合Cset所索引的子矩阵为mb0＝5行nb0＝13列的子矩阵。如图5所示的子矩阵401，其中所述子矩阵中包括：最小行重为g0，其中g0都小于所述子矩阵中的其他行。而所述子矩阵中，包括mb0＝5行(nb0-mb0)＝8列的Amb0×(nb0-mb0)404，1行1列的B 402，(mb0-1)＝4行1列的C 406，1行(mb0-1)＝4列的D 403，(mb0-1)＝4行(mb0-1)＝4列的E 405，E是下三角结构，所述下三角结构是：指矩阵中任意行索引号和任意列索引号所确定的元素在所述列索引号大于所述行索引号时都为第一类元素的矩阵。
所述基础矩阵的行重分布设计的有益效果在于：首先有利于准循环LDPC编码译码性能较好，由于高码率的准循环LDPC编码用到的基础矩阵基本完全和所述的子矩阵有关，所述子矩阵设计可以保证性能较好；如图5所示的基础矩阵一个示例。在图5所示的基础矩阵示例的基础上增加首行行重，形成如图6所示的基础矩阵。图6所示的基础矩阵的子矩阵502的首行501的行重相对于图5中的子矩阵401的首行的行重增加了。
图7为图5和图6所示的基础矩阵的进行编码后的性能比对图。图7的横坐标表示的为信噪比(SNR)；纵坐标为块误码率(BLER)。图7中实线表示的利用图5所示基础矩阵编码的性能变化曲线，虚线表示的为利用图6所示的基础矩阵编码的性能变化曲线。产生如图7所示的性能为，待编码信息的长度为1024，对应扩展因子值为128，所述存储模块中保存的一组扩展因子值为{4，6，8，10，12，14，16，20，24，28，32，40，48，56，64，80，96，112，128，160，192，224，256，320，384，448，512，640，768，896，1024}。所述准循环LDPC编码过程中，基于所述一个基础矩阵和一个扩展因子值Z＝128，对待编码信息序列进行准循环LDPC编 码，得到LDPC编码输出序列。由于所述基础矩阵是对应最大扩展因子为Zmax＝1024，需要转换成扩展因子值为Z＝128的基础矩阵，才能进行准循环LDPC编码，所述转换方法为如下公式：
Figure PCTCN2017110133-appb-000013
其中，所述式子中，(hij b)uniform是所述基础矩阵的第i行第j列元素值，(hij b)modified是所述转换后的基础矩阵(即对应于扩展因子值为128的基础矩阵)中第i行第j列元素值，计算公式
Figure PCTCN2017110133-appb-000014
表示对实数x进行向下取整(即取小于或等于x的最大整数)。从而可以获得用于当前准循环LDPC编码所使用的基础矩阵，基于所述修正后的基础矩阵进行准循环LDPC编码，获得长度为nb×Z＝26×128＝3328比特的LDPC编码输出序列，总共有26个比特块，所述比特块的长度为128(与扩展因子值相等)比特，如图5所示的400，第0个连续和基础矩阵的第0列相关，第1个连续和基础矩阵的第1列相关，第2个连续和基础矩阵的第2列相关，后面依次类推。所述速率匹配过程中，从所述LDPC编码输出序列中，选择出速率匹配输出序列。所述图7性能示例中的码率为8/9，所以可以知道速率匹配输出的速率匹配输出序列的长度为1024/8×9＝1152比特。所述速率匹配过程中，是从第Z×2＝256比特(首比特为第0比特)开始进行顺序选择。
准循环LDPC编码后，进行速率匹配不需要对准循环LDPC编码输出的LDPC编码输出序列的校验比特进行交织，直接从对应起始比特位置开始进行顺序选择，从而减少交织操作，发送端和接收端的时延较少，有益于增加通信系统的鲁棒性。由于在速率匹配过程中，对应于首行的校验比特块(对应图5中的410，LDPC编码输出序列的第8个比特块)必须得传输，可以保证性能比较好，由于此时所述第8个比特块已经位于比较靠前(所有校验比特中的最前面)，所以在进行顺序选择时无需再进行交织到最 前面，可以减少交织模块，从而降低速率匹配时延，提高系统的反应速度，进而提高系统的鲁棒性。
可选地，所述C中包括(mb0-1)＝4个用于指示全零方阵的元素，如图5所示，基础矩阵示例的第8列中的406，其中所有元素值都等于-1(即用于指示全零方阵的元素)。所述的C中也不限于所述都等于-1，所述C包含w个非-1元素(用于指示单位阵循环移位的移位步长的元素)，其中，w是大于0小于4的整数，如下所述基础矩阵示例中，所述子矩阵中的C为2个非-1元素，即w＝2。
所述A中除了首行以外其他任意行的行重都大于nb0-mb0-3，所述nb0-mb0-3＝5，及所述A中非首行的行重大于5。所述行重是所述矩阵中指定行中的用于指示单位阵循环移位的移位步长的元素的数目，所述子矩阵只是一种优选方案。所述约束基础矩阵中的子矩阵的行重，即需要增加除了最轻行重以外的其他行的行重，有益效果在于：可以增加长码长的性能，保证长码长的性能较优。
可选地，所述集合Rset是由大于或等于0且小于所述集合Rset的元素数目的所有整数构成的集合，所述集合Cset是由大于或等于0且小于所述集合Cset的元素数目的所有整数构成的集合。从上述基础矩阵示例中可以看出，集合Rset＝{0，1，2，3，4}，集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12}。所述子矩阵直接对应所述基础矩阵的一部分连续元素块(连续行索引号和连续列索引号共同索引获得)，有益效果在于：可以使得所述准循环LDPC编码实现比较简单，无需其他操作，延时较少，可以增加系统通信鲁棒性。所述基础矩阵中由行索引号为集合Rset和列索引号为集合Cset共同索引的子矩阵只是一种优选方案，当然在其他基础矩阵设计中，集合Rset中航索引号不一定是连续的和集合Cset的列索引号也不一定是连续的。
可选地，以上所述的mb0和nb0满足：(nb0-mb0)/nb0＝＝R0，其中R0是大于0.5且小于1的实数。以上所述基础矩阵示例中的R0等于(nb0-mb0)/nb0＝8/13＝0.6154，所述R0的确定也是一个优选方案，所述R0不限于所述基础矩阵示例的值，一般来说R0越小，说明在实际编码码率越低情况下就可以实现最高吞吐量的要求。所述的子矩阵可以认为是所述准循环LDPC码的核心(core)矩阵，它可以支持任意大于或等于R0且小于1的码率，但是在接收端译码时需要采用所述子矩阵(核心矩阵)进行译码。对所述子矩阵(核心矩阵)的约束的有益效果在于：即约束子矩阵的行数mb0和列数nb0，可以使得所述子矩阵相对比较小，在进行高码率准循环LDPC译码时，进行更新的行数比较少，即计算复杂度比较少，译码速度快，峰值译码吞吐量较高。
所述基础矩阵中除了所述子矩阵以外的元素是基于所述子矩阵的基础上进行扩展获得。如上所述基础矩阵的设计过程中，其实是先设计码率为R0的子矩阵，然后再由所述子矩阵逐步扩展出更低码率的基础矩阵元素。在准循环LDPC编码的基础矩阵设计时，子矩阵是为了高码率性能比较好，由于在统一基础矩阵设计时，高码率的基础矩阵是嵌在低码率的基础矩阵中，如图3所示，基础矩阵为mb行nb列的矩阵302，而子矩阵为所述基础矩阵的左上mb0行nb0列所构成的矩阵301，基础矩阵中除了所述子矩阵外的其他元素303(基础矩阵中的其他空白部分)都是在子矩阵的基础上扩展而来，以支持更低码率设计，有益效果在于：可以使得高码率的准循环LDPC码性能良好，而扩展出来的元素是支持更低码率的，并不影响子矩阵的性能，只要子矩阵设计好了，就可以保证高码率性能优异，由于低码率的矩阵比较大，所以子矩阵对低码率性能影响较小，从而可以保证在连续码率下的性能良好。
可选地，还有一个基础矩阵示例如图8所示，所述基础矩阵示例和以 上所述的基础矩阵示例维数是一样的，本示例基础矩阵也是mb＝18行nb＝26列的矩阵，对应的最大扩展因子值为1024。其中，行索引号为集合Rset＝{0，1，2，3，4}且列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12}，所述行索引号为集合Rset且列索引号为集合Cset所索引的子矩阵为mb0＝5行nb0＝13列的子矩阵，如图8所示的子矩阵701。图8中标号700表示的矩阵的列号。所述子矩阵中，包括(mb0-1)＝4行1列的C 706，(mb0-1)＝4行(mb0-1)＝4列的E 705，E是双对角结构，所述双对角结构是指：矩阵中，行索引号为0且列索引号为0所确定的元素是非-1元素，并且在列索引号为i情况下行索引号为i和(i+1)所确定的2个元素都是非-1元素。标号704、710、704及702均为基础矩阵的子矩阵；其中，子矩阵仅包括一个为“0”的元素。
如图9是不同于图8所示的另一个基础矩阵。图9所示的基础矩阵的子矩阵802的首行801的行重增加了。图10是相应的性能对比，可以发现增加对应所述的首行的行重性能下降(性能曲线中，实线为图8所示基础矩阵示例，虚线为图9基础矩阵对比示例)，可以发现本示例提供的方案的性能较好。图10的横坐标也为信噪比(SNR)，纵坐标为块误码率(BLER)。图7和图10中的dB均为单位分贝。
示例2：
本示例还提供一种准循环LDPC编码方法的基础矩阵示例，所述基础矩阵包括一个子矩阵，该子矩阵的满足的条件可以参见示例1，在此就不重复了。在本示例中，所述子矩阵是一个mb1行nb1列的矩阵，可通过如下函数关系得到：
Figure PCTCN2017110133-appb-000015
其中，A0是(mb1-1)行(nb1-mb1)列的矩阵，A1是(mb1-1)行mb1列的矩阵，A2是1行nb1列的矩阵。A1是下三角结构，A2的行重 为g0，A2中的最后一个元素是用于指示单位阵循环移位的移位大小的元素。所述对基础矩阵的子矩阵进行部分约束，例如较优部分的矩阵(对应于A1)是下三角结构，有益效果在于：使得LDPC编码实现非常简单，直接计算出对应校验比特，无需联合其他未知校验比特进行计算，所以编码简单以及速度较快，可以提高准循环LDPC编码速度，提高编码效率。
图11是本示例中的一个基础矩阵示例，所述基础矩阵示例是一个mb＝23行nb＝35列的基础矩阵，对应的最大扩展因子值为Zmax＝512，其中，行索引号为集合Rset＝{0，1，2，3，4}且列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12，13，14，15，16}，根据行索引号为集合Rset且列索引号为集合Cset所索引的mb1＝5行nb1＝17列的子矩阵。如图11所示子矩阵1001，包括：(mb1-1)＝4行(nb1-mb1)＝12列的A0 1002。如图11中的A1 1003为(mb1-1)＝4行mb1＝5列的矩阵。如图11中A2 1004为1行nb1＝17列的矩阵。A1是下三角结构，所述下三角结构是指矩阵中任意行索引号和任意列索引号所确定的元素在所述列索引号大于所述行索引号时都等于-1。所述A2的行重为g0，g0＝3，也是整个所述子矩阵中的最小行重。
在一些实施例中，所述A0和A1构成的(mb1-1)＝4行nb1＝17列A3，A3＝[A0 A1]。如图11中的A1 1002和A2 1003合并一起构成的矩阵，所述A3中任一行的行重都大于或等于nb1-mb1-2＝10。如图11所示的基础矩阵示例中，A3的行重分布为{10，12，11，10}。所述子矩阵的行重，即需要增加除了最轻行重以外的其他行的行重(即A3的行重较重)，有益效果在于：可以增加长码长的性能，保证长码长的性能较优。
所述基础矩阵中的第(mb2-1)行元素中列索引号为(nb-mb)至nb-1的所有元素中只有列索引号为(nb-mb+mb2-1)的元素是用于指示单位阵循环移位的移位大小的元素，所述mb2是所述基础矩阵中行重等于所述最小 行重为g0的行索引号，且mb2是集合Rset中的一个元素值。从图11所示的基础矩阵示例中可以看出，所述的mb2等于5，即所述基础矩阵中的第(mb2-1)＝4行元素中列索引号为(nb-mb)＝12至nb-1＝34的所有元素中只有列索引号为(nb-mb+mb2-1)＝16的元素是用于指示单位阵循环移位的移位大小的元素。所述列索引号为(nb-mb)至nb-1其实是对应准循环LDPC码的校验比特部分，最轻行重的行中，参与本行校验方程的校验比特部分中只有第(mb2-1)＝4个元素(基础矩阵中是第(nb-mb+mb2-1)＝16元素)是用于指示单位阵循环移位的移位大小的元素，目的是让本行校验比特更容易实现，以及经过以上所述的矩阵行移位和矩阵列移位后不影响矩阵的编码特性。
所述集合Rset是由大于或等于0且小于所述集合Rset的元素数目的所有整数构成的集合，即以上所述的集合Rset的数目为5，集合Rset＝{0，1，2，3，4}；所述集合Cset是由大于或等于0且小于所述集合Cset的元素数目的所有整数构成的集合，即以上所述的集合Rset的数目为17，列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12，13，14，15，16}。所述子矩阵直接对应所述基础矩阵的一部分连续元素块(连续行索引号和连续列索引号共同索引获得)，有益效果在于：可以使得所述准循环LDPC编码实现比较简单，无需其他操作，延时较少，可以增加系统通信鲁棒性。
可选地，以上所述的mb0和nb0满足：(nb0-mb0)/nb0＝＝R0，R0＝12/17＝0.7059。所述的子矩阵可以认为是所述准循环LDPC码的核心矩阵，它可以支持任意大于或等于R0且小于1的码率，但是在接收端译码时需要采用所述子矩阵(核心矩阵)进行译码。对所述子矩阵的约束的有益效果在于：即约束子矩阵的行数mb0和列数nb0，可以使得所述子矩阵相对比较小，在进行高码率准循环LDPC译码时，进行更新的行数比较少，即计 算复杂度比较少，译码速度快，峰值译码吞吐量较高。
本示例中，所述基础矩阵中除了所述子矩阵以外的元素是基于所述子矩阵的基础上进行扩展获得。
示例3：
对于示例2中的基础矩阵示例，基于所述一个基础矩阵和一组扩展因子值Zset＝{8，16，32，64，128，256，512}，若待编码信息序列长度为K＝1536比特，那么需要采用的编码扩展因子值为Z＝128(一般是从Zset中获取大于或等于K/(nb-mb)的最小值作为编码使用的扩展因子值，所述K是待编码信息序列的比特数目，nb是所述基础矩阵的列数，mb是所述基础矩阵的行数)，获取编码使用的扩展因子值为128。由于所述基础矩阵示例是针对与扩展因子Zmax为512的，需要将基础矩阵修正为对应扩展因子值为Z＝128的新基础矩阵，所述基础矩阵修正方法如下：
Figure PCTCN2017110133-appb-000016
式中的mod(x，y)是指x对y求余操作，例如mod(133，128)＝5或mod(100，128)＝100等。基于所述新基础矩阵和扩展因子值Z＝128，，对待编码信息序列进行准循环LDPC编码，得到LDPC编码输出序列。所述准循环LDPC编码的基础矩阵中，每个元素相当于一个子方阵，每个子方阵的维数等于扩展因子值Z＝128，所述基础矩阵总共有35列，所以对应准循环LDPC码的基础矩阵中每行有35个子方阵块；对应的，所述LDPC编码输出序列也包括35个比特块(包括12个系统比特块对应基础矩阵的前12列，和23个校验比特块对应于基础矩阵的后23列)，每个比特块的长度为Z＝128比特，一般来说，由于准循环LDPC码的结构化特性，对于处于同一个比特块中的Z＝128比特的可靠性是相同的，所以一般进行交织的话，是按比特块为单位进行交织的，比特块的长度等于扩展因子值，在本示例中扩展因子值Z＝128，所以本示例中的比特块的长度都等于128。
在速率匹配过程中，一般需要对LDPC编码输出序列进行交织，所述交织方法包括：
1、对LDPC编码输出序列的校验比特块单独进行交织；
2、对对LDPC编码输出序列的系统比特块单独进行交织；
3、对LDPC编码输出序列进行交织。所述对所述LDPC编码输出序列中的校验比特序列进行交织获得交织后校验比特序列，所述交织后校验比特序列中，所述LDPC编码输出序列的校验比特序列中的第(mb2-1)＝4个比特块位于所述交织后校验比特序列中的首位；然后进行比特选择获得所述速率匹配输出序列，所述比特选择从第2×Z＝256比特开始进行选择，即从第3个比特块进行选择；其中，所述比特块的比特数目等于所述扩展因子值，所述mb2是所述基础矩阵中行重等于所述最小行重为g0的行索引号，且mb2是集合Rset中的一个元素值，即所述的mb2＝5。
或者，在速率匹配过程中，对整个LDPC编码输出序列进行交织，所述交织后输出序列中，所述LDPC编码输出序列中校验比特的第(mb2-1)＝4个比特块在所有其他校验比特块的前面，这样可以使得速率匹配时，顺序比特选择优先选择所述的LDPC编码输出序列中校验比特的第(mb2-1)＝4个比特块。
所述的速率匹配过程中，将第(mb2-1)个比特块，置于校验比特的最前面，在进行速率匹配过程中，有益效果在于：由于是采用从某一起始比特开始进行顺序选择的，所以在不管在任何码率下，所述为最前面比特块永远是优先被选择中的，以保证准循环LDPC编码的性能。
示例4：
本示例基于示例2所述的基础矩阵示例，在编码过程中，包括：对所述基础矩阵进行修正获得新基础矩阵，所述修正方法包括：先进行矩阵列移位然后进行矩阵行移位；所述修正方法还可包括：先进行矩阵行移位然 后进行矩阵列移位，获得所述新基础矩阵。
所述矩阵列移位是将基础矩阵的第(nb-mb+mb3-1)＝16列移至第(nb-mb)＝12列，如图12所示的1101，然后将基础矩阵的第(nb-mb)＝12列至第(nb-mb+mb3-2)＝15列顺序后移1列到第{13，14，15，16}列，如图12所示1104；所述矩阵行移位是将基础矩阵的第(mb3-1)＝4行移至第0行，如图12所示1102，然后将基础矩阵的第0行至第(mb3-2)＝3行顺序下移1行到第{1，2，3，4}行，如图12所示1103。其中，所述mb3是所述基础矩阵中行重等于所述最小行重为g0的行索引号，且mb3是集合Rset中的一个元素值，可以知道所述的mb3等于5；进行矩阵列移位和矩阵行移位后获得的新基础矩阵如图11所示的1105。从图12所示的新基础矩阵1105来看，可以发现其结构和示例1的基础矩阵示例是一样的，如图5所示的基础矩阵示例，只是本示例的新基础矩阵的系统列数为kb＝12(nb-mb＝12)。采用所述新基础矩阵对待编码信息序列进行准循环LDPC编码。所述将修正基础矩阵方法，所实现的效果和以上所述的交织方法是一致的，即将第(mb3-1)＝4个比特块，置于校验比特的最前面，在进行速率匹配过程中，有益效果在于：由于是采用从某一起始比特开始进行顺序选择的，所以在不管在任何码率下，所述为最前面比特块永远是优先被选择中的，以保证准循环LDPC编码的性能；由于新基础矩阵本身已经进行列和行置换，所以在进行速率匹配时就无需再进行交织操作，可以使得编码端减少交织操作，节省发送时间提高效率。如上所述的进行的矩阵列移位和矩阵行移位，也可以先进行矩阵行移位然后进行矩阵列操作，效果相同，不影响本专利保护范围；以及，如上所述的矩阵列移位和矩阵行移位操作只是针对矩阵的某一行或者某一列来移位1个比特块，如果需要移位多个比特块的话，可以进行多次矩阵列移位和矩阵行移位操作来实现，本示例不限于实行一次矩阵列移位和矩阵行移位操作，可以进行多次操作。
示例5：
本示例基于示例2所述的基础矩阵示例，编码步骤如下：
步骤1、从存储模块中获取准循环LDPC编码所用的一个基础矩阵和一个扩展因子值；所述存储模块存储的一个基础矩阵如示例2所述，存储的一组扩展因子值为Zset＝{4，6，8，10，12，14，16，20，24，28，32，40，48，56，64，80，96，112，128，160，92，224，256，320，384，448，512，640，768，896，1024}，获取的一个扩展因子值为Z＝40。
步骤2、基于所述一个基础矩阵和一个扩展因子值，对待编码信息序列进行准循环LDPC编码，得到LDPC编码输出序列；其中，包括：1).对所述基础矩阵进行修正，获得对应于扩展因子值为Z＝40的编码基础矩阵，所述修正方法如下：
Figure PCTCN2017110133-appb-000017
获得编码基础矩阵如图13所示。
2).基于所述编码基础矩阵和一个扩展因子值Z＝40，对长度为Z×12＝480比特的待编码信息序列进行准循环LDPC编码，获得长度为Z×35＝40×35＝1400比特的LDPC编码输出序列，所述LDPC编码输出序列包括35个比特块，所述比特块的比特数目等于扩展因子值Z＝40。
步骤3、先对所述LDPC编码输出序列包括35个比特块进行按比特块为单位进行交织，35个比特块的顺序索引序号{0，1，2，…，34}(索引编号为0至11是待编码信息序列中的12个比特块，索引编号为12至34是所述LDPC编码输出序列中校验比特块的23个比特块)变为交织索引号为{0，1，2，3，4，5，6，7，8，9，10，11，16，14，15，12，13，17，18，19，20，21，22，23，24，25，26，27，28，29，30，31，32，33，34}，从所述交织后的LDPC编码输出序列中，从第2个比特块开始进行选择，选择出速率匹配输出序列，即速率匹配输出序列小于或等于40×33＝1320比 特时，所述速率匹配输出序列是不会包括所述待编码的前2个比特块。其中，所述速率匹配过程中，所述速率匹配输出序列不包括所述待编码信息序列的E＝2个比特块，所述E＝2个比特块对应于基础矩阵的列索引号构成集合T0＝{0，1}；所述基础矩阵中子矩阵中行重等于所述最小行重为g0的行中所有用于指示单位阵循环移位的移位大小的元素的列索引号构成集合T1＝{0，1，16}；可以发现，所述集合T0是所述集合T1的子集。有益效果在于：由于在速率匹配过程中，一般是按传输版本号获得比特选择的起始位置，待编码信息序列中有些比特(或比特块)是不传输的，即使在首次数据传输中也不传，所以在准循环LDPC编码的基础矩阵设计时需要将所述比特块对应的基础矩阵最小行重参与到所述比特块校验中，并且让其有一定的保护作用，以增加准循环LDPC码的性能，进而提高通信系统的鲁棒性。
示例6：
本示例提供一种准循环LDPC编码的基础矩阵示例，所述基础矩阵示例是一个mb＝23行nb＝35列的基础矩阵，对应的最大扩展因子值为Zmax＝512，其中，行索引号为集合Rset＝{0，1，2，3，4，5}且列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12，13，14，15，16，17}，根据行索引号为集合Rset且列索引号为集合Cset所索引的mb1＝6行nb1＝18列的子矩阵，所述基础矩阵示例如图14所示。所述子矩阵为如图15所示。
若行索引号集合Rset重新排序为{1，0，3，2，4，5}，则所述子矩阵变为如图16所示。可发现所述子矩阵中包括最小行重为g0＝3。
示例7：
本示例提供一种准循环LDPC编码的基础矩阵示例，所述基础矩阵示例是一个mb＝25行nb＝37列的基础矩阵，对应的最大扩展因子值为 Zmax＝512，其中，行索引号为集合Rset＝{0，1，2，3，4}且列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12，13，14，15，16}，根据行索引号为集合Rset且列索引号为集合Cset所索引的mb1＝5行nb1＝17列的子矩阵，所述基础矩阵示例如图17所示，其中所述mb1＝5行nb1＝17列的子矩阵为如图17所示的1701；所述子矩阵为如图17所示，且所述子矩阵为：
Figure PCTCN2017110133-appb-000018
其中，所述A0是(mb1-1)＝4行(nb1-mb1)＝12列的矩阵1702，所述A1是(mb1-1)＝4行(mb1-1)＝4列的矩阵1703，所述A2是(mb1-1)＝4行1列的矩阵1704，所述A3是1行nb1＝17列的矩阵1705，所述A1是下三角结构，所述A3的最后一个元素为所述第二类元素。所述子矩阵示例中，i＝4，即所述子矩阵中第i＝4行最轻，行重为所述第i＝4行中第二类元素(矩阵为非-1元素)的个数，如本示例第i＝4行的行重为3。
示例8：
本示例提供一种准循环LDPC编码的基础矩阵示例，所述基础矩阵示例是一个mb＝25行nb＝37列的基础矩阵，对应的最大扩展因子值为Zmax＝512，其中，行索引号为集合Rset＝{0，1，2，3，4}且列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12，13，14，15，16}，根据行索引号为集合Rset且列索引号为集合Cset所索引的mb1＝5行nb1＝17列的子矩阵，所述基础矩阵示例如图18所示，其中所述mb1＝5行nb1＝17列的子矩阵为如图18所示的1801；所述子矩阵为如图19所示，且所述子矩阵为：
Figure PCTCN2017110133-appb-000019
其中，所述A0是(mb1-1)＝4行(nb1-mb1)＝12列的矩阵1901，所 述A1是(mb1-1)＝4行(mb1-1)＝4列的矩阵1902，所述A2是(mb1-1)＝4行1列的矩阵1903，所述A3是1行nb1＝17列的矩阵1904，所述A1是双对角结构，所述A3的最后一个元素为所述第二类元素。所述子矩阵示例中，i＝4，即所述子矩阵中第i＝4行最轻，行重为所述第i＝4行中第二类元素(矩阵为非-1元素)的个数，如本示例第i＝4行的行重为3。
以及还提供一种基础矩阵示例，如图20所示，子矩阵2001为基础矩阵中的第0行到第3行以及第0列到第15列构成，即所述子矩阵示例为mb1＝4行nb1＝16列。当然所述子矩阵也可以为3行的，在此不再赘述。
示例9：
本示例提供一种准循环LDPC编码的基础矩阵示例，所述基础矩阵示例是一个mb＝25行nb＝37列的基础矩阵，对应的最大扩展因子值为Zmax＝512，其中，行索引号为集合Rset＝{0，1，2，3}且列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12，13，14，15}，根据行索引号为集合Rset且列索引号为集合Cset所索引的mb2＝4行nb2＝16列的子矩阵。所述基础矩阵局部示例如图21所示的2102，其中所述mb2＝4行nb2＝16列的子矩阵为如图21所示的2101；所述子矩阵为如图21所示的2101，且所述子矩阵为：
[B0 B1]，
其中，所述B0 2103为mb2＝4行kb2＝12列的矩阵，所述B1 2104是mb2＝4行mb2＝4列的矩阵，所述B1是双对角结构；其中，kb2＝nb2–mb2＝16-4＝12。所述子矩阵中，i＝3，即所述子矩阵中第i＝3行最轻，行重为所述第i＝3行中第二类元素(矩阵为非-1元素)的个数，如本示例第i＝3行的行重为4。
以及还提供一种基础矩阵示例，如图22所示，子矩阵2201为基础矩阵中的第0行到第3行以及第0列到第15列构成，即所述子矩阵示例为 mb2＝4行nb2＝16列。所述子矩阵中，i＝0，即所述子矩阵中第i＝0行最轻，行重为所述第i＝0行中第二类元素(矩阵为非-1元素)的个数，如本示例第i＝0行的行重为4。
以及还提供一种基础矩阵示例，如图23所示，子矩阵2301为基础矩阵中的第0行到第3行以及第0列到第15列构成，即所述子矩阵示例为mb2＝4行nb2＝16列。所述子矩阵中，i＝2，即所述子矩阵中第i＝2行最轻，行重为所述第i＝2行中第二类元素(矩阵为非-1元素)的个数，如本示例第i＝2行的行重为5。以及，所述矩阵B1(图23所示的2304)中最大行重(等于3)的行索引号为2，即正好等于所述i。标号2304为组成子矩阵2301的另一个矩阵B0。标号2303为基础矩阵中的另一个子矩阵。
示例10：
本示例提供一种准循环LDPC编码的基础矩阵示例，所述基础矩阵示例是一个mb＝25行nb＝37列的基础矩阵，对应的最大扩展因子值为Zmax＝512，其中，行索引号为集合Rset＝{0，1，2，3}且列索引号为集合Cset＝{0，1，2，3，4，5，6，7，8，9，10，11，12，13，14，15}，根据行索引号为集合Rset且列索引号为集合Cset所索引的mb3＝4行nb3＝16列的子矩阵，所述基础矩阵示例如图24所示的2402，其中所述mb3＝4行nb3＝16列的子矩阵为如图24所示的2401；所述子矩阵为如图24所示的2401，且所述子矩阵为：
Figure PCTCN2017110133-appb-000020
其中，所述C0为1行nb3＝16列的矩阵2403，所述C1是(mb3-1)＝3行(kb3+1)＝13列的矩阵2404，所述C2是(mb3-1)＝3行(mb3-1)＝3列的矩阵2405；所述C2是下三角结构。以及提供一种基础矩阵示例，对应所述的矩阵C2是双对角结构，如图25所示，子矩阵2501中，i＝0，即所述子矩阵中第i＝0行最轻，行重为所述第i＝0行中第二类元素(矩阵为非-1元素)的 个数，如本示例第i＝0行的行重为3。
示例11：
本示例提供一种准循环LDPC编码的基础矩阵示例，所述基础矩阵中第二类元素的位置至少有80％的元素位置与参考矩阵中‘1’的位置相同，所述参考矩阵从矩阵(如图26)中按行索引号为集合Set0且列索引号为集合Set1截取获得，如图26矩阵是一个26行38列的矩阵。其中一个例子，集合Set0＝{0,1,2,…,25}，集合Set1＝{0,1,2,…,37}，即所述参考矩阵示例与如图26中的矩阵相等，如图27给出一个基础矩阵示例，包括子矩阵2701，所述基础矩阵示例中第二类元素的位置有100％的元素位置与所述参考矩阵中‘1’的位置相同。当然也可以获得其他基础矩阵示例，其第二类元素的位置有80％(或者％80到％100之间)的元素位置与所述参考矩阵中‘1’的位置相同。以及还提供一种矩阵示例(如图28)，所述参考矩阵从矩阵(如图28)中按行索引号为集合Set0且列索引号为集合Set1截取获得，如图28矩阵是一个34行50列的矩阵。其中一个例子，集合Set0＝{0,1,2,…,33}，集合Set1＝{0,1,2,…,49}，即所述参考矩阵示例与如图28中的矩阵相等。
本发明实施例公开了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于前述一个或多个技术方案提供的LPDC编码方法，例如，执行如图2所示的方法。
本实施例提供的计算机存储介质可为：移动存储设备、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质，可选为非瞬间存储介质或非易失性存储介质。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有 另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个处理模块中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，凡按照本发明原理所作的修改，都应当理解为落入本发明的保护范围。
工业实用性
本发明实施例中通过设定特定的基础矩阵，从而使得基于基础矩阵形成的子矩阵的行重都不小于g0与Δg的和；这样的行重分布会使得编码之后的译码性能好，且保持了很好的灵活性，从而具有积极的工业效果。与 此同时，在本发明实施例提供的技术方案可以通过限定基础矩阵，就可以实现高性能译码，从而可以在工业上广泛应用，具有很强的工业实用性。

Claims (21)

  1. 一种准循环低密度奇偶校验LPDC编码方法，包括：
    基于一个基础矩阵和一个扩展因子值，对待编码信息进行准循环LDPC编码，得到LDPC编码输出序列；其中，所述基础矩阵中包括：第一类元素和第二类元素；所述基础矩阵中包括至少一个子矩阵；所述子矩阵的第i行的行重为g0，所述g0的取值位于预设范围内的正整数；所述子矩阵的第j行的行重不小于g0与Δg的和，其中，所述j不等于所述i；所述i和j均是所述子矩阵的行索引号，所述Δg是大于预设值的正整数，所述行重为所述子矩阵对应行所述第二类元素的个数；
    从所述LDPC编码输出序列中选出速率匹配输出序列。
  2. 如权利要求1所述的方法，其中，所述子矩阵为mb0行nb0列的矩阵，所述i等于0，且所述子矩阵为：
    Figure PCTCN2017110133-appb-100001
    其中，所述A为mb0行(nb0-mb0)列的矩阵，所述B是1行1列的矩阵，所述C是(mb0-1)行1列的矩阵，所述D是1行(mb0-1)列的矩阵，所述E是(mb0-1)行(mb0-1)列的矩阵；所述A中首行的行重最小且首行的行重等于g0-1；所述B中包括1个所述第二类元素；所述C包括(mb0-1)个所述第一类元素；所述D包括：(mb0-1)个所述第一类元素；所述E是下三角结构或者双对角结构。
  3. 如权利要求1所述的方法，其中，所述子矩阵为mb1行nb1列的矩阵，所述i等于(mb1-1)，且所述子矩阵为：
    Figure PCTCN2017110133-appb-100002
    其中，所述A0是(mb1-1)行(nb1-mb1)列的矩阵，所述A1是(mb1-1) 行(mb1-1)列的矩阵，所述A2是(mb1-1)行1列的矩阵，所述A3是1行nb1列的矩阵。
  4. 如权利要求3所述的方法，其中，
    所述A1是下三角结构；
    或者，
    所述A1是双对角结构且所述mb1等于以下整数之一：3、4、5；
    或者，
    所述A3的最后一个元素为所述第二类元素。
  5. 如权利要求1所述的方法，其中，所述子矩阵为：[B0 B1]，
    其中，所述B0为mb2行kb2列的矩阵，所述B1是mb2行mb2列的矩阵，所述B1是双对角结构；其中，mb2是所述子矩阵的行数，nb2是所述子矩阵的列数，kb2＝nb2–mb2。
  6. 如权利要求5所述的方法，其中，所述矩阵B1中最大行重所在行的元素在所述基础矩阵中的行索引号等于所述i。
  7. 如权利要求1所述的方法，其中，所述i等于0，且所述子矩阵为：
    Figure PCTCN2017110133-appb-100003
    其中，所述C0为1行nb3列的矩阵，所述C1是(mb3-1)行(kb3+1)列的矩阵，所述C2是(mb3-1)行(mb3-1)列的矩阵；所述C2是下三角结构或者双对角结构；其中，所述mb3是所述子矩阵的行数，所述nb3是所述子矩阵的列数，kb3＝nb3–mb3。
  8. 如权利要求1所述的方法，其中，
    所述基础矩阵为mb行nb列的矩阵，所述基础矩阵为[D0 D1]，其中，所述D0是mb行kb列的矩阵，所述D1是mb行mb列的矩阵；所述D1中第i行的所有第二类元素在所述基础矩阵中第i行的的列索引号形成集合Cset；
    所述LDPC编码输出序列包括：nb个比特块；
    所述nb个比特块包括：比特块索引号为0至(kb-1)的kb个系统比特块和比特块索引号为kb至(nb-1)的mb个校验比特块；
    所述从所述LDPC编码输出序列中，选出速率匹配输出序列，包括：
    对所述LDPC编码输出序列按预设交织序列进行交织，获得交织后输出序列，其中，所述预设交织序序列的第kb至第(kb+t-1)个元素等于所述集合Cset中的元素值；所述预设交织序列包括的元素数目小于或等于所述nb；所述t是所述集合Cset的元素数目；
    对完成交织后的所述交织后输出序列进行选择，获得所述速率匹配输出序列。
  9. 如权利要求1所述的方法，其中，
    所述基础矩阵为mb行nb列的矩阵，所述基础矩阵为[D0 D1]，其中，所述D0是mb行kb列的矩阵，所述D1是mb行mb列的矩阵；所述D1中第i行的所有第二类元素在所述基础矩阵中第i行的的列索引号形成集合Cset；
    所述基于一个基础矩阵和一个扩展因子值，对待编码信息进行准循环LDPC编码，得到LDPC编码输出序列，包括：
    对所述基础矩阵进行矩阵的行列移位，获得修正后的基础矩阵，其中，所述修正后的基础矩阵的第kb列至第(kb+t-1)列等于所述集合Cset中所有元素指示所述基础矩阵中的列；所述修正后的基础矩阵的第(kb+t)列至第(kb+t1-1)列等于集合Cset’中所有元素指示所述基础矩阵的列，其中，所述集合Cset’是集合{kb,kb+1,…,(kb+t1-1)}与所述集合Cset的差集，t1是所述集合Cset中的最大元素值减去(nb-mb)获得的数值，所述t是所述集合Cset的元素数目；
    采用所述修正后的基础矩阵对待编码信息序列进行准循环LDPC编码。
  10. 如权利要求1至9任一项所述的方法，其中，
    所述子矩阵中元素在所述基础矩阵中的行索引号形成集合Rset0，所述子矩阵中元素在所述基础矩阵中的列索引号形成集合Cset0；其中，所述行索引号和所述列索引号连续分布；
    或者，
    所述集合Rset0为0到(mb’-1)构成的集合，所述集合Cset0为0到(nb’-1)构成的集合，其中，mb’是所述集合Rset0的元素数目，nb’是所述集合Cset0的元素数目。
  11. 如权利要求10所述的方法，其中，
    所述从所述LDPC编码输出序列中选出速率匹配输出序列，包括：
    去除所述待编码信息序列的E个比特块，基于所述待编码信息序列中的剩余编码信息序列确定出所述速率匹配输出序列；
    其中，所述E个比特块对应于所述基础矩阵的列索引号构成集合T0；所述子矩阵中第i行中第二类元素的列索引号构成集合T1；其中所述集合T0是所述集合T1的子集。
  12. 如权利要求9所述的方法，其中，mb4为所述子矩阵的行数；nb4为所述子矩阵的列数；所述mb4和所述nb4满足：(nb4-mb4)/nb4＝＝R0，其中，所述R0是大于0.5且小于1的实数；
    或者，
    所述子矩阵的列行数差等于所述基础矩阵的列行数差，且所述子矩阵的列数大于所述子矩阵的行数，所述基础矩阵的列数大于所述基础矩阵的行数。
  13. 如权利要求1至9任一项所述的方法，其中，
    所述g0的取值位于预设范围内，包括：所述g0是不大于5的正整数；
    所述预设值等于3或4。
  14. 如权利要求1所述的方法，其中，所述基础矩阵中第二类元素的位置至少有预设比例的元素位置与参考矩阵中‘1’的位置相同，所述参考矩阵从以下矩阵中截取；所述参考矩阵截取以下矩阵的行索引号构成集合Set0，且所述参考矩阵截取以下矩阵的列索引号构成集合Set1；
    Figure PCTCN2017110133-appb-100004
    所述集合Set0包括的元素数目为mb，所述集合Set1包括的元素数目为nb，nb大于mb。
  15. 一种准循环低密度奇偶校验LPDC编码装置，其中，包括：
    编码单元，配置为基于一个基础矩阵和一个扩展因子值，对待编码信息进行准循环LDPC编码，得到LDPC编码输出序列；其中，所述基础矩阵中包括：第一类元素和第二类元素；所述基础矩阵中包括至少一个子矩阵；所述子矩阵的第i行的行重为g0，所述g0的取值位于预设范围内；所述子矩阵的第j行的行重不小于g0与Δg之和，其中，所述j不等于所述i；所述i和j均是所述子矩阵的行索引号，所述Δg是大于预设值的正整数，所述行重为所述子矩阵对应行所述第二类元素的个数；
    速率匹配单元，配置为从所述LDPC编码输出序列中选出速率匹配输出序列。
  16. 如权利要求15所述的装置，其中，所述子矩阵为mb0行nb0列的矩阵，所述i等于0，且所述子矩阵为：
    Figure PCTCN2017110133-appb-100005
    其中，所述A为mb0行(nb0-mb0)列的矩阵，所述B是1行1列的矩阵，所述C是(mb0-1)行1列的矩阵，所述D是1行(mb0-1)列的矩阵，所述E是(mb0-1)行(mb0-1)列的矩阵；所述A中首行的行重最小且首行的行重等于g0-1；所述B中包括1个所述第二类元素；所述C包括(mb0-1)个所述第一类元素；所述D包括：(mb0-1)个所述第一类元素；所述E是下三角结构或者双对角结构。
  17. 如权利要求15所述的装置，其中，所述子矩阵为mb1行nb1列的矩阵，所述i等于(mb1-1)，且所述子矩阵为：
    Figure PCTCN2017110133-appb-100006
    其中，所述A0是(mb1-1)行(nb1-mb1)列的矩阵，所述A1是(mb1-1)行(mb1-1)列的矩阵，所述A2是(mb1-1)行1列的矩阵，所述A3是1行nb1列的矩阵。
  18. 如权利要求15所述的装置，其中，所述i等于0，且所述子矩阵为：
    Figure PCTCN2017110133-appb-100007
    其中，所述C0为1行nb3列的矩阵，所述C1是(mb3-1)行(kb3+1)列的矩阵，所述C2是(mb3-1)行(mb3-1)列的矩阵；所述C2是下三角结构或者双对角结构；其中，所述mb3是所述子矩阵的行数，所述nb3是所述子矩阵的列数，kb3＝nb3–mb3。
  19. 如权利要求15所述的装置，其中，
    所述基础矩阵为mb行nb列的矩阵，所述基础矩阵为[D0 D1]，其中，所述D0是mb行kb列的矩阵，所述D1是mb行mb列的矩阵；所述D1中第i行的所有第二类元素在所述基础矩阵中第i行的的列索引号形成集合Cset；
    所述LDPC编码输出序列包括：nb个比特块；
    所述nb个比特块包括：比特块索引号为0至(kb-1)的kb个系统比特块和比特块索引号为kb至(nb-1)的mb个校验比特块；
    所述速率匹配单元，具体用于对所述LDPC编码输出序列按预设交织序列进行交织，获得交织后输出序列，其中，所述预设交织序序列的第kb至第(kb+t-1)个元素等于所述集合Cset中的元素值；所述预设交织序列包括的元素数目小于或等于所述nb；所述t是所述集合Cset的元素数目；对完成交织后的所述交织后输出序列进行选择，获得所述速率匹配输出序列。
  20. 如权利要求15所述的装置，其中，
    所述基础矩阵为mb行nb列的矩阵，所述基础矩阵为[D0 D1]，其中，所述D0是mb行kb列的矩阵，所述D1是mb行mb列的矩阵；所述D1中第i行的所有第二类元素在所述基础矩阵中第i行的的列索引号形成集合Cset；
    所述编码单元，配置为对所述基础矩阵进行矩阵的行列移位，获得修正后的基础矩阵，其中，所述修正后的基础矩阵的第kb列至第(kb+t-1)列等于所述集合Cset中所有元素指示所述基础矩阵中的列；所述修正后的基础矩阵的第(kb+t)列至第(kb+t1-1)列等于集合Cset’中所有元素指示所述基础矩阵的列，其中，所述集合Cset’是集合{kb,kb+1,…,(kb+t1-1)}与所述集合Cset的差集，t1是所述集合Cset中的最大元素值减去(nb-mb)获得的数值，所述t是所述集合Cset的元素数目；采用所述修正后的基础矩阵对待编码信息序列进行准循环LDPC编码。
  21. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至14任一项提供的准循环低密度奇偶校验LPDC编码方法。
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