WO2018126604A1 - 一种像素结构、液晶面板和液晶显示器 - Google Patents

一种像素结构、液晶面板和液晶显示器 Download PDF

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Publication number
WO2018126604A1
WO2018126604A1 PCT/CN2017/086114 CN2017086114W WO2018126604A1 WO 2018126604 A1 WO2018126604 A1 WO 2018126604A1 CN 2017086114 W CN2017086114 W CN 2017086114W WO 2018126604 A1 WO2018126604 A1 WO 2018126604A1
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Prior art keywords
active switch
pixel
voltage
pixel electrode
liquid crystal
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PCT/CN2017/086114
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English (en)
French (fr)
Inventor
陈猷仁
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US15/557,807 priority Critical patent/US10386685B2/en
Publication of WO2018126604A1 publication Critical patent/WO2018126604A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present application relates to the field of liquid crystal display technologies, and in particular, to a pixel structure, a liquid crystal panel, and a liquid crystal display.
  • TFT-LCD Thin Film Transistor-Liquid Crystal
  • LCD Thin Film Transistor-Liquid Crystal
  • refresh frequency are getting higher and higher, resulting in less and less charging time of pixels.
  • 120Hz UD (3840P ⁇ 2160P) products as an example, the charging time of pixels is 1/120/ 2160 ⁇ 3.85 microseconds.
  • the charging time of the pixel is less and less, resulting in lower and lower charging rate of the pixel, which seriously affects the display effect of the TFT-LCD screen.
  • the present application provides a pixel structure, a liquid crystal panel, and a liquid crystal display capable of increasing the pixel charging rate.
  • an embodiment of the present application provides a pixel structure, where the pixel structure includes:
  • Each of the pixel regions includes:
  • the first active switch includes a gate, a source and a drain, a gate of the first active switch is connected to a corresponding one of the scan lines, and a drain connection of the first active switch is corresponding to a data line, the source of the first active switch is connected to a corresponding pixel electrode;
  • the second active switch includes a gate, a source and a drain, and a gate of the second active switch is connected to a same scan line as a gate of the first active switch, and the second active switch
  • the drain is connected to the reference voltage
  • the source of the second active switch is connected to the pixel electrode of the next row of the corresponding pixel electrode and located in the same column as the corresponding pixel electrode.
  • an embodiment of the present application provides a liquid crystal panel including a pixel structure
  • the pixel structure includes:
  • Each of the pixel regions includes:
  • the first active switch includes a gate, a source and a drain, a gate of the first active switch is connected to a corresponding one of the scan lines, and a drain connection of the first active switch is corresponding to a data line, the source of the first active switch is connected to a corresponding pixel electrode;
  • the second active switch includes a gate, a source and a drain, and a gate of the second active switch is connected to a same scan line as a gate of the first active switch, and the second active switch
  • the drain is connected to the reference voltage
  • the source of the second active switch is connected to the pixel electrode of the next row of the corresponding pixel electrode and located in the same column as the corresponding pixel electrode.
  • an embodiment of the present application provides a liquid crystal display, including: a liquid crystal panel, and a housing that fixes the liquid crystal panel;
  • the liquid crystal panel includes a pixel structure, and the pixel structure includes:
  • Each of the pixel regions includes:
  • the first active switch includes a gate, a source and a drain, a gate of the first active switch is connected to a corresponding one of the scan lines, and a drain connection of the first active switch is corresponding to a data line, the source of the first active switch is connected to a corresponding pixel electrode;
  • the second active switch includes a gate, a source and a drain, and a gate of the second active switch is connected to a same scan line as a gate of the first active switch, and the second active switch
  • the drain is connected to the reference voltage
  • the source of the second active switch is connected to the pixel electrode of the next row of the corresponding pixel electrode and located in the same column as the corresponding pixel electrode.
  • Embodiments of the present application connect the same scan line by the first active switch and the second active switch in the same pixel area, charge the corresponding pixel through the first active switch, and simultaneously pass the second active switch to the next row of pixels. Discharge, when the next row of pixels is charged, the scan time completely becomes the charging time, which prolongs the charging time of the pixel and improves the charging rate of the pixel.
  • FIG. 1 is a schematic partial structural diagram of a pixel structure according to an embodiment of the present application.
  • 2a is a partial pattern of a first reticle of an array substrate according to an embodiment of the present application
  • 2b is a partial pattern of a second mask of the array substrate in an embodiment of the present application.
  • 2c is a partial pattern of a third mask of the array substrate in an embodiment of the present application.
  • 2d is a partial pattern of a fourth mask of the array substrate in an embodiment of the present application.
  • 2e is a partial pattern of a fifth mask of the array substrate in an embodiment of the present application.
  • Figure 2f is an enlarged view of A in Figure 2e;
  • Figure 2g is an enlarged view of B in Figure 2e;
  • 3a is another partial reticle partial pattern of the array substrate in an embodiment of the present application.
  • FIG. 3b is a second partial mask pattern of the array substrate in an embodiment of the present application.
  • 3c is a third partial mask pattern of the array substrate in an embodiment of the present application.
  • FIG. 3d is another fourth reticle partial pattern of the array substrate in an embodiment of the present application.
  • 3e is a partial pattern of another fifth reticle of the array substrate in an embodiment of the present application.
  • Figure 3f is an enlarged view of A' in Figure 3e;
  • Figure 3g is an enlarged view of B' in Figure 3e;
  • FIG. 4 is a partial schematic structural view of a liquid crystal panel according to an embodiment of the present application.
  • FIG. 5 is a driving circuit diagram of a liquid crystal panel according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a liquid crystal display according to an embodiment of the present application.
  • FIG. 1 is a partial structural diagram of a pixel structure according to an embodiment of the present application.
  • the pixel structure includes: a plurality of scan lines 11; and a plurality of data lines 12 intersecting perpendicularly with the plurality of scan lines 11 to divide pixel regions 13 arranged in a matrix form.
  • Each of the pixel regions 13 includes: a pixel electrode 14, a first active switch 15 and a second active switch 16; the first active switch 15 and the second active switch 16 each include a gate, a source and a drain.
  • the gate of the first active switch 15 and the gate of the second active switch 16 are connected to a corresponding one of the scan lines 11, and the drain of the first active switch 15 is connected to a corresponding one of the data lines 12, the first The source of the active switch 15 is connected to the corresponding pixel electrode 14; the drain of the second active switch 16 is connected to the reference voltage, and the source of the second active switch 16 is connected to the next row of the corresponding pixel electrode 14
  • the pixel electrode 14 is located in the same column as the corresponding pixel electrode 14.
  • the plurality of scan lines 11 are arranged in parallel in the horizontal direction, the intervals of each of the scan lines 11 are uniform, and the plurality of data lines 12 are arranged in parallel in the vertical direction, and the intervals of each of the data lines 12 are uniform, and the two adjacent left and right
  • the data line 12 and the upper and lower adjacent scan lines 11 define a pixel area 13, and a liquid crystal is placed in the pixel area 13 to form one pixel.
  • the gate of the first active switch 15 of the pixel region 13 and the gate of the first second active switch 16 are connected to the upper scan line 11, and the drain of the first active switch 15 is connected to the left data line 12, the first active switch
  • the source of 15 is connected to the pixel electrode 14 of the pixel region 13, and the source of the second active switch 16 is connected to the corresponding pixel electrode 14 of the next row, and the drain of the second active switch 16 is connected to the reference voltage.
  • the drain of the second active switch 16 is connected to a common electrode that is connected to a reference voltage.
  • the common electrode provides a reference voltage for the liquid crystal, and the drain of the second active switch 16 is connected to the common electrode, which can reduce the layout of the voltage source, and can also save wiring trouble.
  • the first active switch 15 and the second active switch 16 are thin film transistors; for example, a top gate thin film transistor or a bottom gate thin film transistor.
  • the pixel region 13 further includes pixels.
  • the charging rate of the pixel is greatly affected by the charging time. In order to prevent the polarization of the liquid crystal molecules, the voltages of the adjacent two frames applied at the two ends of the liquid crystal are opposite, and the charging process of the pixel actually takes two stages:
  • the pixel voltage is charged from the reference voltage to the target voltage.
  • the ratio of the discharge time to the scan time will seriously affect the charging rate of the pixel, so reducing the ratio of the discharge time in the scan time can increase the charging rate of the pixel.
  • the driving voltage that causes the first active switch 15 and the second active switch 16 to be simultaneously turned on is input to the scan line 11
  • the data signal input by the data line 12 passes through the first active switch 15
  • the corresponding pixel is charged, and at the same time, since the drain of the second active switch 16 is connected to the reference voltage, the pixel voltage of the previous frame held by the pixel electrode 14 connected to the second active switch 16 is charged in the next frame data signal.
  • the front becomes the reference voltage, so that when the next row of pixels is charged after the pixel charging is completed, the scanning time of the next row of pixels completely becomes the charging time, which prolongs the charging time of the pixel and improves the charging rate of the pixel.
  • the turn-on voltage of the first active switch 15 and the turn-on voltage of the second active switch 15 are the same; when a row of scan lines 11 inputs a driving voltage, the first active connected to the scan line 11 The switch 15 and the second active switch 16 are turned on, the pixels of the row are charged by the first active switch 15, and the pixel voltage of the pixel electrode 14 connected to the second active switch 16 is pulled to a reference voltage, A row of pixels is discharged; the driving voltage is greater than or equal to the turn-on voltage.
  • the turn-on voltage of the first active switch 15 and the turn-on voltage of the second active switch 16 are different; when a row of scan lines 11 inputs a driving voltage, the first active connected to the scan line 11 The switch 15 and the second active switch 16 are turned on, the pixels of the row are charged by the first active switch 15, and the pixel voltage of the pixel electrode 14 connected to the second active switch 16 is pulled to a reference voltage, The pixel of one row is discharged; the driving voltage is greater than or equal to one of the turn-on voltage of the first active switch 15 and the turn-on voltage of the second active switch 16.
  • the source of the second active switch 16 of each pixel region 13 is connected to the next row of the corresponding pixel electrode 14 through a via and the pixel in the same column as the corresponding pixel electrode 14 Electrode 14.
  • the source of the second active switch 16 is connected to the pixel electrode 14 corresponding to the next row through the via hole, and no wiring is required to avoid wiring trouble.
  • the process of forming an array substrate having the pixel structure of the embodiment of the present application includes the following five processes:
  • the first process coating on a glass substrate (material is generally Al), upper photoresist, reticle and illumination, development, etching, and photoresist removal, resulting in a partial mask partial pattern as shown in Figure 2a or Figure 3a.
  • the second process after the first process is completed, a transparent insulating layer is deposited on the glass substrate, generally GiNx, and then a layer of AS is deposited thereon, the material is a-si, and then the photoresist, the mask and Illumination, development, etching, and photoresist removal yield a second mask partial pattern as shown in Figure 2a or Figure 3b.
  • the third process after the second process is completed, the film is further coated on the glass substrate, and the material is also Al, the upper photoresist, the photomask and the illumination, the development, the etching, and the photoresist are removed, and the third is obtained as shown in Fig. 2c or Fig. 3c. A partial pattern of the reticle.
  • the fourth process after the third process is completed, a transparent insulating layer is deposited on the glass substrate, generally GiNx, upper photoresist, photomask and illumination, development, etching, and photoresist removal, as shown in Figure 2d or A partial pattern of the fourth reticle via of Figure 3d.
  • the middle circle in the figure indicates a via.
  • the fifth process after the fourth process is completed, the film is coated on the glass substrate, generally ITO; the upper photoresist, the photomask and the illumination, the development, the etching, the photoresist, and finally the fifth as shown in Fig. 2e or Fig. 3e A partial pattern of the reticle.
  • the Nth row and the N+1th row in FIG. 2e are the wirings of the scanning lines 11, respectively, and the Mth column and the M+1th column are the wirings of the Mth column and the M+1th column data line 12, respectively.
  • C is the contact point of the common electrode;
  • FIG. 2f is an enlarged view of A of FIG. 2e, and
  • FIG. 2g is an enlarged view of B of FIG. 2e. If the active switch is added to A and B, then S, D, G denotes the source, drain and gate of the active switch, respectively. Both N and M are natural numbers.
  • the Nth row and the N+1th row in FIG. 3e are respectively the wiring of the scanning line 11, and the Mth column and the M+1th column are the wiring of the Mth column and the M+1th column data line 12, respectively.
  • C' is the contact point of the common electrode;
  • FIG. 3f is an enlarged view of A' of FIG. 3e, and
  • FIG. 3g is an enlarged view of B' of FIG. 3e, and S, D, and G respectively represent the source of the corresponding active switch Contact of the pole, drain and gate.
  • FIG. 4 is a schematic structural diagram of a liquid crystal panel 100 according to an embodiment of the present application.
  • the liquid crystal panel 100 can be used in a device such as a mobile phone, a computer, a tablet computer, or a television.
  • the liquid crystal panel 100 includes a pixel structure and a driving circuit for driving the pixel structure.
  • the pixel structure adopts the above pixel structure, and details are not described herein again.
  • the driving circuit includes a scan driving circuit 101, a data driving circuit 102, and a timing controller 103.
  • the scan driving circuit 101 is connected to the scan line 11
  • the data driving circuit 102 is connected to the data line 12
  • the timing controller 103 is connected to the scan driving circuit 101 and the data, respectively.
  • the drive circuit 102 controls the scan drive circuit 101 and the data drive circuit 102 to input signals to the scan line 11 and the data line 12, respectively.
  • the scan driving circuit 101 inputs a scan driving signal to the scan line 11 row by row, and the data driving circuit 102 inputs a data signal to the data line 12, and after the scan line 11 is turned on, charges a corresponding row of pixels through the data signal, and simultaneously discharges the pixels of the next row.
  • the driving voltage input by the scan driving circuit 101 to the scan line 11 causes the first active switch 15 and the second active switch 16 to be simultaneously turned on, and the data signal input by the data driving circuit 102 passes through the first active switch 15 to the corresponding pixel. Charging is performed.
  • the pixel voltage of the pixel electrode 14 connected to the second active switch 16 is pulled to the reference voltage, and the pixel of the next row is discharged, so that the pixel is in one row.
  • the scanning time of the next row of pixels completely becomes the charging time, the charging time of the pixels is prolonged, the charging rate of the pixels is high, and the display effect of the liquid crystal panel 100 is good.
  • FIG. 6 is a schematic structural diagram of a liquid crystal display according to an embodiment of the present disclosure.
  • the liquid crystal display includes a liquid crystal panel 100 and a housing 200 for fixing the liquid crystal panel.
  • the description of the liquid crystal panel 100 refers to the above embodiment.
  • the liquid crystal display further includes a base 300 that allows the display to be smoothly placed on a plane, such as a table top.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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Abstract

一种像素结构、液晶面板(100)和液晶显示器，该像素结构包括多条扫描线(11)以及与扫描线(11)垂直相交的多条数据线(12)，多条数据线(11)和多条扫描线(12)划分出以矩阵形式排列的像素区域(13)，每个像素区域(13)包括像素电极(14)、第一主动开关(15)和第二主动开关(16)，第一主动开关(15)的栅极和第二主动开关(16)的栅极连接相对应的一条扫描线(11)，第一主动开关(15)的漏极连接相对应的一条数据线(12)，第一主动开关(15)的源极连接相对应的像素电极(14)；第二主动开关(16)的漏极连接基准电压，第二主动开关(16)的源极连接相对应的像素电极(14)的下一行且与相对应的像素电极(14)位于同一列的像素电极(14)。

Description

一种像素结构、液晶面板和液晶显示器
技术领域
本申请涉及液晶显示技术领域，尤其涉及一种像素结构、液晶面板和液晶显示器。
背景技术
为了满足市场的需求，TFT-LCD（Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器）的解析度和刷新频率越来越高，导致像素的充电时间越来越少，以120Hz的UD（3840P×2160P）产品为例，像素的充电时间为1/120/2160≈3.85微秒。像素的充电时间越来越少，导致像素的充电率越来越低，这严重影响着TFT-LCD屏的显示效果。
申请内容
本申请提供了一种能够提高像素充电率的像素结构、液晶面板和液晶显示器。
第一方面，本申请的实施例提供了一种像素结构，该像素结构包括：
多条扫描线；
多条数据线，与所述多条扫描线垂直相交划分出以矩阵形式排列的像素区域；
每个所述像素区域包括：
像素电极；
第一主动开关，所述第一主动开关包括栅极、源极和漏极，所述第一主动开关的栅极连接相对应的一条扫描线，所述第一主动开关的漏极连接相对应的一条数据线，所述第一主动开关的源极连接相对应的像素电极；
第二主动开关，所述第二主动开关包括栅极、源极和漏极，所述第二主动开关的栅极与第一主动开关的栅极连接相同的扫描线，所述第二主动开关的漏极连接基准电压，所述第二主动开关的源极连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
第二方面，本申请的实施例提供了一种液晶面板，所述液晶面板包括一种像素结构；
所述像素结构包括：
多条扫描线；
多条数据线，与所述多条扫描线垂直相交划分出以矩阵形式排列的像素区域；
每个所述像素区域包括：
像素电极；
第一主动开关，所述第一主动开关包括栅极、源极和漏极，所述第一主动开关的栅极连接相对应的一条扫描线，所述第一主动开关的漏极连接相对应的一条数据线，所述第一主动开关的源极连接相对应的像素电极；
第二主动开关，所述第二主动开关包括栅极、源极和漏极，所述第二主动开关的栅极与第一主动开关的栅极连接相同的扫描线，所述第二主动开关的漏极连接基准电压，所述第二主动开关的源极连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
第三方面，本申请的实施例提供了一种液晶显示器，该液晶显示器包括：液晶面板、以及固定所述液晶面板的壳体；
所述液晶面板包括一种像素结构，所述像素结构包括：
多条扫描线；
多条数据线，与所述多条扫描线垂直相交划分出以矩阵形式排列的像素区域；
每个所述像素区域包括：
像素电极；
第一主动开关，所述第一主动开关包括栅极、源极和漏极，所述第一主动开关的栅极连接相对应的一条扫描线，所述第一主动开关的漏极连接相对应的一条数据线，所述第一主动开关的源极连接相对应的像素电极；
第二主动开关，所述第二主动开关包括栅极、源极和漏极，所述第二主动开关的栅极与第一主动开关的栅极连接相同的扫描线，所述第二主动开关的漏极连接基准电压，所述第二主动开关的源极连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
本申请的实施例通过在同一个像素区域内的第一主动开关和第二主动开关连接相同的扫描线，通过第一主动开关对相对应的像素充电，同时通过第二主动开关对下一行像素放电，待下一行像素充电时扫描时间完全变为了充电时间，延长了像素的充电时间，提高了像素的充电率。
附图说明
为了更清楚地说明本申请的实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例中一种像素结构的局部结构示意图；
图2a为本申请一实施例中的阵列基板的第一道光罩局部图案；
图2b为本申请一实施例中的阵列基板的第二道光罩局部图案；
图2c为本申请一实施例中的阵列基板的第三道光罩局部图案；
图2d为本申请一实施例中的阵列基板的第四道光罩局部图案；
图2e为本申请一实施例中的阵列基板的第五道光罩局部图案；
图2f为图2e中A处放大图；
图2g为图2e中B处放大图；
图3a为本申请一实施例中的阵列基板的另一第一道光罩局部图案；
图3b为本申请一实施例中的阵列基板的另一第二道光罩局部图案；
图3c为本申请一实施例中的阵列基板的另一第三道光罩局部图案；
图3d为本申请一实施例中的阵列基板的另一第四道光罩局部图案；
图3e为本申请一实施例中的阵列基板的另一第五道光罩局部图案；
图3f为图3e中A’处放大图；
图3g为图3e中B’处放大图；
图4为本申请一实施例中一种液晶面板的局部结构示意图；
图5为本申请一实施例中一种液晶面板的驱动电路图；
图6为本申请一实施例中一种液晶显示器的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解，当在本说明书和所附权利要求书中使用时，术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
请参照图1，其为本申请一实施例提供的一种像素结构的局部结构示意图。如图1所示，该像素结构包括：多条扫描线11；多条数据线12，与所述多条扫描线11垂直相交划分出以矩阵形式排列的像素区域13。
每个所述像素区域13包括：像素电极14、第一主动开关15和第二主动开关16；所述第一主动开关15和第二主动开关16均包括栅极、源极和漏极，所述第一主动开关15的栅极和第二主动开关16的栅极连接相对应的一条扫描线11，所述第一主动开关15的漏极连接相对应的一条数据线12，所述第一主动开关15的源极连接相对应的像素电极14；所述第二主动开关16的漏极连接基准电压，所述第二主动开关16的源极连接所述相对应的像素电极14的下一行且与所述相对应的像素电极14位于同一列的像素电极14。
具体地，多条扫描线11沿水平方向平行排列，每条扫描线11的间隔一致，多条数据线12沿竖直方向平行排列，每条数据线12的间隔一致，左右相邻的两条数据线12和上下相邻的扫描线11划分出一个像素区域13，在该像素区域13放入液晶便形成一个像素。该像素区域13的第一主动开关15的栅极和第一第二主动开关16的栅极连接上面的扫描线11，第一主动开关15的漏极连接左边的数据线12，第一主动开关15的源极连接该像素区域13的像素电极14，而第二主动开关16的源极连接下一行对应的像素电极14，第二主动开关16的漏极连接基准电压。
在一些实施例中，所述第二主动开关16的漏极连接公共电极，所述公共电极连接基准电压。
公共电极为液晶提供基准电压，第二主动开关16的漏极连接公共电极，可以减少电压源的布局，也可以省掉布线麻烦。
在一些实施例中，所述第一主动开关15和所述第二主动开关16为薄膜晶体管；例如为顶部栅极型薄膜晶体管或底部栅极型薄膜晶体管。
在一些实施例中，所述像素区域13还包括像素。像素的充电率受充电时间的影响很大，为了防止液晶分子的极化，加在液晶两端的相邻两帧的电压是相反的，像素的充电过程实际分两个阶段：
1.放电阶段，抵消上一帧，像素保留的电荷；
2.充电阶段，把像素电压从基准电压充到目标电压。
放电时间占据扫描时间的比例会严重影响到像素的充电率，因此降低放电时间在扫描时间中的比例可以提高像素的充电率。
通过本申请实施例的像素结构，当向扫描线11输入使第一主动开关15和第二主动开关16同时导通的驱动电压时，数据线12输入的数据信号通过第一主动开关15对相对应的像素进行充电，同时，由于第二主动开关16的漏极连接基准电压，使得与第二主动开关16连接的像素电极14保持的上一帧的像素电压在下一帧数据信号对其像素充电前变成基准电压，这样在该行像素充电结束后对下一行像素充电时，下一行像素的扫描时间完全变成了充电时间，延长了像素的充电时间，提高了像素的充电率。
在一些实施例中，所述第一主动开关15的导通电压和所述第二主动开关15的导通电压相同；当一行扫描线11输入驱动电压，连接所述扫描线11的第一主动开关15和第二主动开关16导通，通过所述第一主动开关15对所述行的像素充电，将所述第二主动开关16连接的像素电极14的像素电压拉至基准电压，对下一行的像素放电；所述驱动电压的大于或等于所述导通电压。
在一些实施例中，所述第一主动开关15的导通电压和所述第二主动开关16的导通电压不同；当一行扫描线11输入驱动电压，连接所述扫描线11的第一主动开关15和第二主动开关16导通，通过所述第一主动开关15对所述行的像素充电，将所述第二主动开关16连接的像素电极14的像素电压拉至基准电压，对下一行的像素放电；所述驱动电压大于或等于第一主动开关15的导通电压和第二主动开关16的导通电压中大的一个。
在一些实施例中，每个像素区域13的第二主动开关16的源极通过过孔连接所述相对应的像素电极14的下一行且与所述相对应的像素电极14位于同一列的像素电极14。第二主动开关16的源极通过过孔与下一行对应的像素电极14连接，不需要绕线，避免布线麻烦。
如图2a-3g或3a-3g，形成具有本申请实施例的像素结构的阵列基板的加工过程包括一下五道工艺：
第一道工艺：在玻璃基板上镀膜（材质一般是Al），上光阻、光罩和照光、显影、蚀刻、去光阻，得到如图2a或图3a的第一道光罩局部图案。
第二道工艺：第一道工艺完成之后，在玻璃基板上沉积一层透明的绝缘层，一般是GiNx，接着在上面沉积一层AS，材质是a-si，而后上光阻、光罩和照光、显影、蚀刻、去光阻，得到如图2a或图3b的第二道光罩局部图案。
第三道工艺：第二道工艺完成之后，在玻璃基板上再镀膜，材质也是Al，上光阻、光罩和照光、显影、蚀刻、去光阻，得到如图2c或图3c的第三道光罩局部图案。
第四道工艺：第三道工艺完成之后，在玻璃基板上沉积一层透明的绝缘层，一般是GiNx，上光阻、光罩和照光、显影、蚀刻、去光阻，得到如图2d或图3d的第四道光罩过孔的局部图案。其中，图中中间的圆圈表示过孔。
第五道工艺：第四道工艺完成之后，在玻璃基板上镀膜，一般是ITO；上光阻、光罩和照光、显影、蚀刻、去光阻，最后得到如图2e或图3e的第五道光罩局部图案。
图2e中的第N行和第N+1行分别为扫描线11的布线之处，第M列和第M+1列分别为第M列和第M+1列数据线12的布线之处，C处为公共电极的接触点；图2f为图2e的A处的放大图，图2g为图2e的B处的放大图，如将主动开关增加至A和B处，则S、D、G分别表示主动开关的源极、漏极和栅极。N和M均为自然数。
图3e中的第N行和第N+1行分别为扫描线11的布线之处，第M列和第M+1列分别为第M列和第M+1列数据线12的布线之处，C’处为公共电极的接触处；图3f为图3e的A’处的放大图，图3g为图3e的B’处的放大图，S、D、G分别表示对应的主动开关的源极、漏极和栅极的接触处。
参考图4，图4为本申请实施例提供的一种液晶面板100的结构示意图。该液晶面板100可用于手机、电脑、平板电脑、电视等装置中。
请结合图5，该液晶面板100包括像素结构以及驱动所述像素结构的驱动电路。该像素结构采用上述像素结构，在此不再赘述。
所述驱动电路包括扫描驱动电路101、数据驱动电路102和时序控制器103，扫描驱动电路101连接扫描线11，数据驱动电路102连接数据线12，时序控制器103分别连接扫描驱动电路101和数据驱动电路102，控制扫描驱动电路101和数据驱动电路102分别向扫描线11和数据线12输入信号。
扫描驱动电路101逐行向扫描线11输入扫描驱动信号，数据驱动电路102向数据线12输入数据信号，在扫描线11打开后通过数据信号对对应的一行像素充电，同时对下一行的像素放电 。具体地，扫描驱动电路101向扫描线11输入的驱动电压使第一主动开关15和第二主动开关16同时导通，数据驱动电路102输入的数据信号通过第一主动开关15对相对应的像素进行充电，同时，由于第二主动开关16的漏极连接基准电压，将所述第二主动开关16连接的像素电极14的像素电压拉至基准电压，对下一行的像素放电，这样在一行像素充电结束后对下一行像素充电时，下一行像素的扫描时间完全变成了充电时间，延长了像素的充电时间，像素的充电率高，液晶面板100的显示效果好。
如图6所示，图6为本申请实施例提供的一种液晶显示器的结构示意图，该液晶显示器包括液晶面板100以及固定所述液晶面板的壳体200。所述液晶面板100的描述参考上述实施例。
进一步地，所述液晶显示器还包括底座300，底座300使该显示器平稳地放置于平面上，例如桌面。
需要说明的是，在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详细描述的部分，可以参见其他实施例的相关描述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种像素结构，包括：
    多条扫描线；
    多条数据线，与所述多条扫描线垂直相交划分出以矩阵形式排列的像素区域；
    每个所述像素区域包括：
    像素电极；
    第一主动开关，所述第一主动开关包括栅极、源极和漏极，所述第一主动开关的栅极连接相对应的一条扫描线，所述第一主动开关的漏极连接相对应的一条数据线，所述第一主动开关的源极连接相对应的像素电极；
    第二主动开关，所述第二主动开关包括栅极、源极和漏极，所述第二主动开关的栅极与第一主动开关的栅极连接相同的扫描线，所述第二主动开关的漏极连接基准电压，所述第二主动开关的源极连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
  2. 如权利要求1所述的像素结构，其中，所述第二主动开关的漏极连接公共电极，所述公共电极连接基准电压。
  3. 如权利要求1所述的像素结构，其中，每个像素区域的第二主动开关的源极通过过孔连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
  4. 如权利要求1所述的像素结构，其中，所述像素区域还包括像素，所述第一主动开关的导通电压和所述第二主动开关的导通电压相同；
    当一行扫描线输入驱动电压，连接所述扫描线的第一主动开关和第二主动开关导通，通过所述第一主动开关对所述行的像素充电，将所述第二主动开关连接的像素电极的像素电压拉至基准电压，对下一行的像素放电；所述驱动电压的大于或等于所述导通电压。
  5. 如权利要求1所述的像素结构，其中，所述像素区域还包括像素，所述第一主动开关的导通电压和所述第二主动开关的导通电压不同；
    当一行扫描线输入驱动电压，连接所述扫描线的第一主动开关和第二主动开关导通，通过所述第一主动开关对所述行的像素充电，将所述第二主动开关连接的像素电极的像素电压拉至基准电压，对下一行的像素放电；所述驱动电压大于或等于第一主动开关的导通电压和第二主动开关的导通电压中大的一个。
  6. 如权利要求1所述的像素结构，其中，所述第一主动开关为顶部栅极型薄膜晶体管或底部栅极型薄膜晶体管。
  7. 如权利要求1所述的像素结构，其中，所述第二主动开关为顶部栅极型薄膜晶体管或底部栅极型薄膜晶体管。
  8. 一种液晶面板，包括一种像素结构，其中，所述像素结构包括：
    多条扫描线；
    多条数据线，与所述多条扫描线垂直相交划分出以矩阵形式排列的像素区域；
    每个所述像素区域包括：
    像素电极；
    第一主动开关，所述第一主动开关包括栅极、源极和漏极，所述第一主动开关的栅极连接相对应的一条扫描线，所述第一主动开关的漏极连接相对应的一条数据线，所述第一主动开关的源极连接相对应的像素电极；
    第二主动开关，所述第二主动开关包括栅极、源极和漏极，所述第二主动开关的栅极与第一主动开关的栅极连接相同的扫描线，所述第二主动开关的漏极连接基准电压，所述第二主动开关的源极连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
  9. 如权利要求8所述的液晶面板，其中，所述第二主动开关的漏极连接公共电极，所述公共电极连接基准电压。
  10. 如权利要求8所述的液晶面板，其中，每个像素区域的第二主动开关的源极通过过孔连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
  11. 如权利要求8所述的液晶面板，其中，所述像素区域还包括像素，所述第一主动开关的导通电压和所述第二主动开关的导通电压相同；
    当一行扫描线输入驱动电压，连接所述扫描线的第一主动开关和第二主动开关导通，通过所述第一主动开关对所述行的像素充电，将所述第二主动开关连接的像素电极的像素电压拉至基准电压，对下一行的像素放电；所述驱动电压的大于或等于所述导通电压。
  12. 如权利要求8所述的液晶面板，其中，所述像素区域还包括像素，所述第一主动开关的导通电压和所述第二主动开关的导通电压不同；
    当一行扫描线输入驱动电压，连接所述扫描线的第一主动开关和第二主动开关导通，通过所述第一主动开关对所述行的像素充电，将所述第二主动开关连接的像素电极的像素电压拉至基准电压，对下一行的像素放电；所述驱动电压大于或等于第一主动开关的导通电压和第二主动开关的导通电压中大的一个。
  13. 如权利要求8所述的液晶面板，其中，所述第一主动开关为顶部栅极型薄膜晶体管或底部栅极型薄膜晶体管。
  14. 如权利要求8所述的液晶面板，其中，所述第二主动开关为顶部栅极型薄膜晶体管或底部栅极型薄膜晶体管。
  15. 一种液晶显示器，包括液晶面板以及固定所述液晶面板的壳体，所述液晶面板包括一种像素结构，其中，所述像素结构包括：
    多条扫描线；
    多条数据线，与所述多条扫描线垂直相交划分出以矩阵形式排列的像素区域；
    每个所述像素区域包括：
    像素电极；
    第一主动开关，所述第一主动开关包括栅极、源极和漏极，所述第一主动开关的栅极连接相对应的一条扫描线，所述第一主动开关的漏极连接相对应的一条数据线，所述第一主动开关的源极连接相对应的像素电极；
    第二主动开关，所述第二主动开关包括栅极、源极和漏极，所述第二主动开关的栅极与第一主动开关的栅极连接相同的扫描线，所述第二主动开关的漏极连接基准电压，所述第二主动开关的源极连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
  16. 如权利要求15所述的液晶显示器，其中，所述第二主动开关的漏极连接公共电极，所述公共电极连接基准电压。
  17. 如权利要求15所述的液晶显示器，其中，每个像素区域的第二主动开关的源极通过过孔连接所述相对应的像素电极的下一行且与所述相对应的像素电极位于同一列的像素电极。
  18. 如权利要求15所述的液晶显示器，其中，所述像素区域还包括像素，所述第一主动开关的导通电压和所述第二主动开关的导通电压相同；
    当一行扫描线输入驱动电压，连接所述扫描线的第一主动开关和第二主动开关导通，通过所述第一主动开关对所述行的像素充电，将所述第二主动开关连接的像素电极的像素电压拉至基准电压，对下一行的像素放电；所述驱动电压的大于或等于所述导通电压。
  19. 如权利要求15所述的液晶显示器，其中，所述像素区域还包括像素，所述第一主动开关的导通电压和所述第二主动开关的导通电压不同；
    当一行扫描线输入驱动电压，连接所述扫描线的第一主动开关和第二主动开关导通，通过所述第一主动开关对所述行的像素充电，将所述第二主动开关连接的像素电极的像素电压拉至基准电压，对下一行的像素放电；所述驱动电压大于或等于第一主动开关的导通电压和第二主动开关的导通电压中大的一个。
  20. 如权利要求15所述的液晶显示器，其中，所述第一主动开关为顶部栅极型薄膜晶体管或底部栅极型薄膜晶体管，所述第二主动开关为顶部栅极型薄膜晶体管或底部栅极型薄膜晶体管。
PCT/CN2017/086114 2017-01-04 2017-05-26 一种像素结构、液晶面板和液晶显示器 Ceased WO2018126604A1 (zh)

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