WO2018125082A1 - Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si - Google Patents

Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si Download PDF

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Publication number
WO2018125082A1
WO2018125082A1 PCT/US2016/068886 US2016068886W WO2018125082A1 WO 2018125082 A1 WO2018125082 A1 WO 2018125082A1 US 2016068886 W US2016068886 W US 2016068886W WO 2018125082 A1 WO2018125082 A1 WO 2018125082A1
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Prior art keywords
regions
contact
rich
layer
transistor
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PCT/US2016/068886
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English (en)
Inventor
Glenn A. Glass
Anand S. Murthy
Karthik JAMBUNATHAN
Scott J. MADDOX
Tahir Ghani
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Intel Corporation
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Priority to PCT/US2016/068886 priority Critical patent/WO2018125082A1/fr
Publication of WO2018125082A1 publication Critical patent/WO2018125082A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor

Definitions

  • the Si-rich cladding layer can improve S/D contact resistance by at least two times (or, in other words, the Si-rich cladding layer can lower the contact resistance at that location by at least half).
  • the Si-rich layer may be formed either before or after S/D contact trench etch processing.
  • the Si-rich layer may be formed on at least one ⁇ 111 ⁇ faceted surface of a Ge-rich S/D region after the region has been formed.
  • the thickness and C concentration may be inversely related, such that if a relatively thicker carbon-based etch stop layer is employed (e.g., with a thickness of at least 8, 10, 12, or 15 nm, such as having a thickness in the range of 8-20 nm), then relatively lower C concentration may be used to ensure the etch stop layer is adequately robust/resilient enough to effectively function (e.g., C concentration in the range of 1-5%).
  • such devices may employ semiconductor materials that are three dimensional crystals as well as two dimensional crystals or nanotubes, for example.
  • the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).
  • Substrate 200 may include: a bulk substrate including group IV semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC), and/or group III-V material and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or dielectric material or some other electrically insulating material; or some other suitable multilayer structure where the top layer includes one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material).
  • group IV semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC), and/or group III-V material and/or any other suitable material(s) as will be apparent in light of this disclosure
  • XOI X on
  • Methods 100A-B of Figures 1A-B continue with etching 108 fins 202 to form fin-shaped trenches 225 between the STI material 220 as shown in the resulting example structure of Figure 2D, in accordance with some embodiments.
  • etching 108 may be performed using any suitable techniques, such as one or more wet and/or dry etch processes that selectively remove the material of fins 202 relative to the STI material 220 to form fin-shaped trenches 225, and/or any other suitable processing as will be apparent in light of this disclosure.
  • a sub-fin portion 203 from fins 202 remains below fin-shaped trenches 225, where the height (dimension in the Y-axis direction) of the sub- fin portion 203 may be based on the etch processing 108 used form fin-shaped trenches 225.
  • the etch processing 108 may be performed with characteristics (e.g., a longer etch duration) that removes relatively more of fins 202, such that a shorter (by height) sub-fin portion 203 may remain or the fins 202 may be completely removed, such that the fin-shaped trenches 225 extend to the bottom of STI material 220 and possibly beyond.
  • the end structure will include the final gate stack, as will be apparent in light of this disclosure.
  • a hardmask (not shown) may be formed over the dummy gate stack (which may also be formed over spacers 250) to protect the dummy gate stack during subsequent processing, for example.
  • the transistor type (e.g., MOSFET, TFET, HEMT, or other suitable type) may be described based on the doping and/or operating scheme of the source, channel, and drain regions, and thus those respective regions may be used to determine the type or classification of a given transistor, for example.
  • MOSFET versus TFET transistors may structurally be very similar (or the same), but include different doping schemes (e.g., source-drain doping schemes for MOSFET of p-p or n-n versus p-n or n-p for TFET).
  • Method 100B of Figure IB includes similar processing as method 100A of Figure 1A, with a few variations related to the S/D regions and contact processing, as previously described. More specifically, method 100 A includes forming the Si-rich layer 264 on ⁇ 111 ⁇ faceting of S/D regions 261/262 prior to the initiation of the S/D contact loop processing (e.g., prior to performing S/D contact processing 124), while method 100B includes forming the Si-rich layer 264' on ⁇ 111 ⁇ faceting of S/D regions 261/262 after the initiation of the S/D contact loop processing (e.g., during the S/D contact processing 124, through the contact trenches).
  • Method 100B of Figure IB continues from box 116 and structure 2H by forming 117 etch stop layer 265 on the S/D regions 261/262, thereby forming the example resulting structure of Figure 3A, in accordance with some embodiments.
  • the previous relevant description with respect to forming 120 the etch stop layer is equally applicable to formation process 117, except that for process 117, the etch stop layer 265 is formed directly on the S/D regions 261/262 as the Si-rich layer has not yet been formed (as compared to formation process 120, for example). Further, the previous relevant description with respect to etch stop layer 265 is equally applicable to the structure of Figure 3A.
  • Method 100B of Figure IB continues with performing 122 final gate stack processing to form the example resulting structure of Figure 3B, in accordance with some embodiments. The previous relevant description with respect to final gate stack processing 122 is equally applicable here.
  • Example 19 includes the subject matter of Example 18, wherein the first semiconductor material is Ge that is p-type doped.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne des techniques de formation de transistors permettant de former des transistors riches en Ge utilisant une couche de réduction de résistance de contact source/drain (S/D) riche en Si. Comme il est possible de le comprendre sur la base de cette invention, la couche riche en Si peut être utilisée à une interface de contact S/D donnée pour améliorer la résistance de contact, étant donné qu'un matériau riche en Si (par exemple, du Si ou du SiGe ayant moins de 50 % de concentration en Ge par pourcentage atomique) peut être plus fortement dopé qu'un matériau riche en Ge (par exemple, du Ge ou du SiGe ayant une concentration en Ge supérieure à 50 % en pourcentage atomique). Les techniques peuvent consister à former la couche riche en Si sur le facettage {111} d'une région de S/D riche en Ge donnée, sachant qu'un tel facettage fournit une densité améliorée d'états (DOS) se chevauchant entre les matériaux. Les techniques peuvent consister à utiliser une couche d'arrêt de gravure pour préserver la couche riche en Si pendant le traitement de gravure de tranchée de contact ou pour préserver le facettage {111} de S/D afin de permettre la formation de la couche riche en Si sur ce dernier à travers la tranchée de contact.
PCT/US2016/068886 2016-12-28 2016-12-28 Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si WO2018125082A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113206043A (zh) * 2020-01-31 2021-08-03 台湾积体电路制造股份有限公司 半导体器件及方法
EP4109553A1 (fr) * 2021-06-25 2022-12-28 INTEL Corporation Couche de recouvrement riche en silicium à faible teneur en germanium et à haute teneur en bore pour la stabilité thermique de résistance de contact pmos
US11887993B2 (en) 2019-05-13 2024-01-30 Hewlett-Packard Development Company, L.P. Thin-film transistors

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions
US20140175543A1 (en) * 2012-12-20 2014-06-26 Glenn A. Glass Conversion of thin transistor elements from silicon to silicon germanium
US20160049476A1 (en) * 2012-12-17 2016-02-18 Intel Corporation Semiconductor devices with germanium-rich active layers & doped transition layers
US20160071933A1 (en) * 2014-09-10 2016-03-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives Finfet transistor comprising portions of sige with a crystal orientation [111]
US20160111537A1 (en) * 2014-10-15 2016-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions
US20160049476A1 (en) * 2012-12-17 2016-02-18 Intel Corporation Semiconductor devices with germanium-rich active layers & doped transition layers
US20140175543A1 (en) * 2012-12-20 2014-06-26 Glenn A. Glass Conversion of thin transistor elements from silicon to silicon germanium
US20160071933A1 (en) * 2014-09-10 2016-03-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives Finfet transistor comprising portions of sige with a crystal orientation [111]
US20160111537A1 (en) * 2014-10-15 2016-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11887993B2 (en) 2019-05-13 2024-01-30 Hewlett-Packard Development Company, L.P. Thin-film transistors
CN113206043A (zh) * 2020-01-31 2021-08-03 台湾积体电路制造股份有限公司 半导体器件及方法
EP4109553A1 (fr) * 2021-06-25 2022-12-28 INTEL Corporation Couche de recouvrement riche en silicium à faible teneur en germanium et à haute teneur en bore pour la stabilité thermique de résistance de contact pmos

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