WO2018125081A1 - Transistors utilisant une couche tampon métamorphique à croissance de couverture - Google Patents

Transistors utilisant une couche tampon métamorphique à croissance de couverture Download PDF

Info

Publication number
WO2018125081A1
WO2018125081A1 PCT/US2016/068885 US2016068885W WO2018125081A1 WO 2018125081 A1 WO2018125081 A1 WO 2018125081A1 US 2016068885 W US2016068885 W US 2016068885W WO 2018125081 A1 WO2018125081 A1 WO 2018125081A1
Authority
WO
WIPO (PCT)
Prior art keywords
buffer layer
semiconductor material
transistor
substrate
gate
Prior art date
Application number
PCT/US2016/068885
Other languages
English (en)
Inventor
Willy Rachmady
Anand S. Murthy
Matthew V. Metz
Nicholas G. MINUTILLO
Sean T. MA
Gilbert Dewey
Jack T. Kavalieros
Tahir Ghani
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2016/068885 priority Critical patent/WO2018125081A1/fr
Publication of WO2018125081A1 publication Critical patent/WO2018125081A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • a field-effect transistor is a semiconductor device that includes three terminals: a gate, a source, and a drain.
  • a FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain.
  • charge carriers e.g., electrons or holes
  • the FET is referred to as an n-channel device
  • the FET is referred to as a p-channel device.
  • Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor.
  • MOSFETs metal-oxide-semiconductor FETs
  • MOSFETs include a gate dielectric layer between the gate and the channel.
  • MOSFETs may also be known as metal- insulator-semiconductor FETs (MISFETSs) or insulated-gate FETs (IGFETs).
  • MISFETSs metal- insulator-semiconductor FETs
  • IGFETs insulated-gate FETs
  • Complementary MOS (CMOS) structures use a combination of p-channel MOSFET (p-MOS) and n-channel MOSFET (n-MOS) to implement logic gates and other digital circuits.
  • a FinFET is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin).
  • the conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor.
  • a nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used for the channel region and the gate material generally surrounds each nanowire.
  • GAA gate-all-around
  • InGaAs indium gallium arsenide
  • Si silicon
  • lattice mismatch occurs because the Si substrate is relatively thicker and remains unstrained by the growth of the epitaxial InGaAs layer, resulting in that InGaAs layer (which has a relatively higher lattice constant) adopting the in- plane lattice constant of the substrate.
  • the metamorphic buffer layer (also more generally referred to as a buffer layer herein) may be formed between the epitaxial semiconductor material used for the channel region of the transistor and the substrate above which the transistor is formed.
  • the epitaxial semiconductor material is lattice mismatched relative to the material of the substrate (e.g., where the lattice delta or misfit absolute value between the epitaxial semiconductor material and the substrate material is at least 2-4%)
  • the metamorphic buffer layer can be utilized to enable the epitaxial semiconductor material to be formed with sufficient device quality.
  • the metamorphic buffer layer can enable epitaxial semiconductor material to be effectively used for a transistor channel region, even where the epitaxial semiconductor material would have otherwise been formed with relatively low-quality if grown directly on the substrate material (and thereby resulting in, e.g., relatively low performance or complete ineffectiveness/unsuitability).
  • This is due to the buffer layer reaching a metamorphic state, and thus, a strain relaxed state (as a result of it reaching a strain relaxation critical thickness), thereby allowing for a lattice transition to be made within the buffer layer to enable high-quality growth of the channel region material.
  • the metamorphic buffer layer described herein can enable the integration of group III-V semiconductor layers on group IV semiconductor substrates for use in forming group III-V transistors.
  • group III-V semiconductor layers on group IV semiconductor substrates for use in forming group III-V transistors.
  • suitable material combinations will be apparent in light of this disclosure.
  • InGaAs material being lattice mismatched to the Si substrate (e.g., approximately 7.5% lattice delta or misfit absolute value between Si and Ino.53Gao.47As), thereby causing the lattice-mismatched InGaAs to be unsuitable for use as the transistor channel region material.
  • a blanket-grown layer of InAlAs may be used as a buffer layer to mitigate the large lattice mismatch between the InGaAs material and the Si substrate, as InGaAs can be grown in a lattice-matched manner to InAlAs (e.g., as the lattice delta between Ino.53Gao.47As and Ino.47Alo.53As is approximately 0.3%).
  • the InAlAs buffer layer can be grown past its strain relaxation critical thickness (he), such that it is a metamorphic layer (as opposed to growing it below its strain relaxation critical thickness, making it a pseudomorphic layer).
  • the InAlAs buffer layer may be formed with a thickness of at least 0.5 microns to exceed its critical thickness and thereby address any defects that may occur at the InAlAs/Si interface (e.g., due to the lattice mismatch between those materials).
  • the critical thickness for the InAlAs buffer layer may be relatively lower than 0.5 microns, depending on, for example, the In concentration in the InAlAs material, and thus, the present disclosure is not intended to be limited to a threshold of 0.5 microns for achieving the strain relaxation critical thickness of an InAlAs buffer layer.
  • the critical thickness may be as low as 0.1 microns (or even lower), in some embodiments, depending on the material configuration.
  • two materials may be considered lattice matched if the absolute value of the lattice delta or misfit is less than or equal to 2-4% (e.g., less than/equal to 2, 2.5, 3, 3.5, or 4%, or less than/equal to the subrange of 2-3% or 3-4%>), or some other suitable threshold value or range as will be apparent in light of this disclosure.
  • the lattice delta or misfit absolute value (as a percentage) can be calculated by
  • the lattice delta or misfit absolute value (as a percentage) can be calculated as
  • two materials may be considered lattice matched if their lattice constant difference absolute value is less than or equal to 0.1-0.3 A at 300 K (e.g., less than/equal to 0.1, 0.15, 0.2, 0.25, or 0.3 A at 300 K, or less than/equal to the subrange of 0.1-0.2 or 0.2-0.3 A at 300 K).
  • their lattice constant difference absolute value can be calculated as
  • a buffer layer material should be selected such that the desired transistor channel material is lattice matched to the buffer layer material (e.g., using an InAlAs buffer layer, as InGaAs is lattice matched to InAlAs).
  • metamorphic buffer layer is referred to herein as blanket grown, the layer need not be formed over the entirety of the substrate, in some embodiments, but may instead be selectively blanket grown in one or more areas of the substrate, where such areas may be at least the size of a single transistor. In other words, the metamorphic buffer layer may be selectively blanket grown in areas where one or more transistors as described herein are to be formed above the metamorphic buffer layer.
  • the metamorphic buffer layer may have an IC footprint (e.g., occupying an area looking down at the top surface of substrate) that is at least 1.5 to billions of times the size of that of the overlying transistor (or some other relative amount).
  • the metamorphic buffer layer may be blanket-grown over the entirety of the substrate, in some embodiments, it may not be present over the entirety of the substrate in the final IC product. For instance, in some such embodiments, one or more portions of the blanket-grown metamorphic buffer layer may be removed after the buffer layer has been formed over the entirety of the substrate.
  • Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SFMS); time-of-flight SFMS (ToF-SFMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools.
  • tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or
  • whether two materials are lattice matched/mismatched can be determined based on determining what the materials are (e.g., using chemical analysis), determining the lattice constant values for those materials (e.g., by looking them up), and then calculating the lattice delta or lattice constant difference absolute values as described herein.
  • the techniques and structures may be detected based on the buffer layer having a thickness that exceeds its strain relaxation critical thickness, which can be determined based on determining the material included in the buffer layer (e.g., using chemical analysis) and determining the strain relaxation critical thickness of that material (e.g., by looking it up) to determine if it has been exceeded (such that the buffer layer is a metamorphic buffer layer, for example).
  • the relative conduction band offset (CBO) may be particularly beneficial for n-channel transistor devices while the relative valence band offset (VBO) may be particularly beneficial for p- channel transistor devices, as can be understood based on this disclosure. Numerous configurations and variations will be apparent in light of this disclosure.
  • Figures 1A-B illustrate methods 100A-B of forming an integrated circuit including one or more transistors employing a metamorphic buffer layer, in accordance with some embodiments of the present disclosure.
  • Figures 2A-K illustrate example integrated circuit structures that are formed when carrying out methods 100A-B of Figures 1A-B, in accordance with some embodiments.
  • method 100 A of Figure 1A relates to a process flow employing an aspect ratio trapping (ART) scheme to grow the channel region material and that method 100B of Figure IB relates to a blanket growth of the channel region material.
  • ART aspect ratio trapping
  • transistors that can benefit from the techniques described herein include, but are not limited to, field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), tunnel-FETs (TFETs), high-electron mobility transistors (HEMT), planar configuration transistors, finned or FinFET configuration transistors (e.g., dual-gate or tri-gate), and nanowire (or nanoribbon or gate-all-around (GAA)) configuration transistors.
  • FETs field-effect transistors
  • MOSFETs metal-oxide-semiconductor FETs
  • TFETs tunnel-FETs
  • HEMT high-electron mobility transistors
  • planar configuration transistors finned or FinFET configuration transistors (e.g., dual-gate or tri-gate)
  • nanowire or nanoribbon or gate-all-around (GAA)) configuration transistors.
  • the techniques can be used to benefit p-type devices (e.g.,
  • the techniques may be used to form complementary transistor circuits (such as CMOS circuits), where the techniques employing a metamorphic buffer layer may be used to benefit one or more of the included n-type and/or p-type transistors making up the CMOS circuit.
  • Other example transistor devices include few to single electron quantum transistor devices, for example.
  • such devices may employ semiconductor materials that are three dimensional crystals as well as two dimensional crystals or nanotubes, for example.
  • the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).
  • Methods 100A-B of Figures 1A-B include providing 102 a substrate, such as substrate 200 shown in Figure 2A, in accordance with some embodiments.
  • Substrate 200 may include: a bulk substrate including group IV semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC), and/or at least one group III-V material and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or dielectric material or some other electrically insulating material; or some other suitable multilayer structure where the top layer includes one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material).
  • group IV semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon
  • group III-V semiconductor material includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and so forth.
  • group III element e.g., aluminum, gallium, indium
  • group V element e.g., nitrogen, phosphorus, arsenic, antimony, bismuth
  • substrate 200 may include a surface crystalline orientation described by a Miller Index of ⁇ 100>, ⁇ 110>, or ⁇ 111>, or its equivalents, as will be apparent in light of this disclosure.
  • substrate 200 in this example embodiment, is shown as having a thickness (dimension in the Y-axis direction) similar to other layers shown in subsequent structures for ease of illustration, in some instances, substrate 200 may be much thicker than the other layers, such as having a thickness in the range of 50 to 950 microns, for example, or any other suitable thickness as will be apparent in light of this disclosure.
  • substrate 200 may be used for one or more other IC devices, such as various diodes (e.g., light- emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC devices, depending on the end use or target application.
  • various diodes e.g., light- emitting diodes (LEDs) or laser diodes
  • transistors e.g., MOSFETs or TFETs
  • various capacitors e.g., MOSCAPs
  • MEMS microelectromechanical systems
  • NEMS nanoelectromechanical systems
  • RF radio frequency
  • the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this disclosure.
  • Methods 100A-B of Figures 1A-B continue with blanket growing (or otherwise blanket forming) 104 metamorphic buffer layer 210 on and/or above substrate 200 to form the example structure of Figure 2B, in accordance with some embodiments.
  • the blanket growth or deposition process may be performed using any suitable technique, such as one or more of chemical vapor deposition (CVD), metalorganic CVD (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and/or any other suitable process as can be understood based on this disclosure.
  • CVD chemical vapor deposition
  • MOCVD metalorganic CVD
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • MBE molecular beam epitaxy
  • buffer layer 210 may be undoped/intrinsic or relatively minimally doped, such as including a dopant concentration of less than 1E16 atoms per cubic centimeter (cm).
  • buffer layer 210 is illustrated as a single layer in Figure 2B, the present disclosure is not intended to be so limited.
  • buffer layer 210 may include a multilayer structure, such that the buffer layer 210 includes at least two layers.
  • buffer layer 210 may be formed using a layer-by-layer epitaxial growth approach (e.g., using an MBE process), such that layer 210 may or may not appear to have distinct interfaces within the layer 210, depending on the particular configuration and observation level.
  • the concentration of one or more materials may be graded (e.g., increased and/or decreased) throughout buffer layer 210 (e.g., as buffer layer 210 is grown in the Y-axis direction).
  • the material of layer 210 will be described in more detail herein.
  • buffer layer 210 is referred to herein as blanket grown, the layer need not be formed over the entirety of the substrate 200, in some embodiments, but may instead be selectively blanket grown in one or more areas of the substrate 200, where such areas may be at least the size of a single transistor. In other words, the buffer layer 210 may be selectively blanket grown in areas where one or more transistors as described herein are to be formed above the metamorphic buffer layer.
  • the metamorphic buffer layer is not grown in a fin trench using an ART scheme, so it would not substantially match the fin-like shape of the channel region of the transistor (e.g., as compared to growth of a buffer layer in a fin trench using an ART scheme, where such a buffer layer would substantially match the fin-like shape of the channel region). Note that this is true regardless of whether the channel region is converted to a nanowire (or nanoribbon or gate-all-around (GAA) configuration).
  • GAA gate-all-around
  • buffer layer 210 may include a thickness of at least its strain relaxation critical thickness (he), such that it is considered a metamorphic layer (as opposed to growing it below its strain relaxation critical thickness, making it a pseudomorphic layer).
  • buffer layer 210 may be formed with at least its critical thickness to thereby address any defects that may occur at the buffer layer/substrate interface (e.g., due to the lattice mismatch between the materials of those two features). Accordingly, in some embodiments, buffer layer 210 may be referred to as a metamorphic buffer layer.
  • buffer layer can allow a semiconductor material to be epitaxially grown above substrate 200 that it would otherwise have a lattice mismatch with, due to the presence of the intervening buffer layer 210, the epitaxial semiconductor material being lattice matched to the 210 buffer layer, and the buffer layer 210 being formed with a sufficient thickness such that it addresses any defects caused by the lattice mismatch between that layer 210 and the substrate 200.
  • Method 100A of Figure 1A will continue to be described below with respect to Figures 2C-G, in accordance with some embodiments.
  • the variations with respect to method 100B of Figure IB will then be described with respect to Figure 2F'-G.
  • method 100A of Figure 1A includes forming the fins to be utilized for the final transistor device(s) using an aspect ratio trapping (ART) scheme, whereby one or more dummy fins are formed, sacrificial material is formed around the dummy fins, the dummy fins are removed to form fin-shaped trenches (e.g., via selective etch processing), the final fins are formed in the fin-shaped trenches (e.g., via an epitaxial growth of semiconductor material in the fin-shaped trenches), and then the sacrificial material is either removed or recessed (e.g., if it is to be used as shallow trench isolation (STI) material).
  • ART aspect ratio trapping
  • the dummy material layer may be deposited/grown using any suitable techniques as will be apparent in light of this disclosure, such as using any of the techniques described herein (e.g., CVD, PVD, ALD).
  • the patterning of the dummy material layer into dummy fins 220 may include any suitable technique, such as one or more masking processes and/or etch processes, for example. Dummy fins 220 are referred to as such because they can be used as a template to form fin- shaped trenches for subsequent growth of epitaxial semiconductor material, via the removal of the dummy fins 220, for example, as will be apparent in light of this disclosure.
  • the dummy fin widths DFw may be in the range of 4-400 nm, for example, or any other suitable value, as will be apparent in light of this disclosure.
  • the dummy fin heights DFh may be in the range of 4-800 nm, for example, or any other suitable value, as will be apparent in light of this disclosure.
  • the dummy fins 220 may be formed to have particular height to width ratios such that when they are later recessed and/or removed, the resulting fin trenches formed allow for defects in the replacement epitaxial semiconductor material deposited to terminate on a side surface as the material grows vertically, such as non-crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects.
  • ART aspect ratio trapping
  • the height to width ratio of the dummy fins may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or any other suitable threshold ratio, as will be apparent in light of this disclosure.
  • the dummy fins 210 (four shown) and trenches 225 therebetween are shown as having the same widths and depths/heights in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited.
  • the dummy fins 220 may be formed to have varying heights DFh and/or varying widths DFw that may correspond with the final desired fin heights (Fh) and widths (Fw) described in more detail herein.
  • DFh final desired fin heights
  • Fw widths
  • any number of dummy fins may be formed, such as one, two, ten, hundreds, thousands, millions, and so forth, as can be understood based on this disclosure.
  • Method 100 A of Figure 1A continues with forming 108 sacrificial material around the dummy fins 220, such as the sacrificial material 230 shown in the example structure of Figure 2D, in accordance with some embodiments.
  • the sacrificial material 230 may be deposited/grown using any suitable techniques as will be apparent in light of this disclosure, such as using any of the techniques described herein (e.g., CVD, PVD, ALD).
  • an optional planarization process may be formed after depositing/forming the sacrificial material 230, such as a chemical mechanical polish/planarization (CMP) process, for example.
  • CMP chemical mechanical polish/planarization
  • sacrificial material 230 may include any suitable material, such as a nitride, oxide, or other suitable dielectric material, for example.
  • Specific oxide and nitride materials may include silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, silicon nitride, or titanium nitride, just to name a few.
  • the sacrificial material 230 may be selected based on the material of dummy fins 220, for example, such that the two materials are different and enable selectively etching the dummy fins 220 to remove them (or at least recess them), thereby forming fin-shaped trenches, as will be described in more detail below.
  • Method 100A of Figure 1A continues with removing 110 the dummy fins 220 to form fin- shaped trenches 235 shown in the example structure of Figure 2E, in accordance with some embodiments.
  • the removal 110 process may be performed using any suitable techniques, such as using selective etch processing that removes the material of dummy fins 220 relative to the sacrificial material 230, such as at a relatively faster rate (e.g., at least 1.5- 100 times faster), thereby allowing for the complete (or near complete) removal of dummy fins 220 while leaving at least a portion of sacrificial material 230 remaining.
  • sacrificial material 230 may only be minimally affected by the selective etch processing (or practically not affected at all), such that the majority or all of sacrificial material structures 230 remain, such as is shown in Figure 2E.
  • the selective etch processing may also be selective to the material of buffer layer 210, such that if the entirety of dummy fins 220 are consumed by the selective etch processing, the buffer layer 210 can act as an etch stop, preventing the etch process from removing material in the trenches 235 (or minimally removing the material at a relatively slower rate).
  • dummy fins 220 may be completely removed, such as is shown in Figure 2E.
  • the present disclosure is not intended to be so limited, such that in other embodiments, the dummy fins 220 may only be recessed, such that a portion remains in trenches 235, for example.
  • one or more of the dummy fins 220 may be masked off to allow for subsequent processing of a first set of dummy fins 220 (e.g., to form replacement fins to be used for one of n-channel and p-channel devices), followed by masking off the first set of replacement fins to allow for subsequent processing of a second set of dummy fins 220 (e.g., to form replacement fins to be used for the other of n-channel and p-channel devices).
  • any number of mask and replace processes may be used to form any number of sets of replacement fins, as will be apparent in light of this disclosure.
  • removal process 110 completely removed all four dummy fins 220 as shown, thereby forming four fin-shaped trenches 235.
  • the narrow or fin-shaped trenches 235 may include the same or similar dimensions as the original dummy fins (e.g., having the same or similar widths as DFw and having the same or similar heights as DFh, as described herein).
  • Method 100A of Figure 1A continues with growing 112 epitaxial semiconductor material in the fin-shaped trenches 235 to form fins 240 as shown in the example structure of Figure 2F, in accordance with some embodiments.
  • the epitaxial semiconductor material may be grown/deposited (or otherwise formed) using any suitable technique, such as one or more of the deposition processes described herein (e.g., CVD, MOCVD, PVD, ALD, MBE).
  • an optional planarization (or re-planarization) process may be performed after growing (or otherwise forming) the epitaxial semiconductor material, such as via a CMP process, for example.
  • Method 100 A of Figure 1 A continues with removing 114 sacrificial material 230 to expose semiconductor fins 240 as shown in the example structure of Figure 2G, in accordance with some embodiments.
  • sacrificial material 230 may be completely removed, such as is shown in Figure 2G, while in other embodiments, a portion of the sacrificial material 230 may remain to be used as shallow trench isolation (STI) material (such as STI material 215 as shown in Figure 2H and described herein), for example.
  • STI shallow trench isolation
  • fins 240 are replacement fins, as method 100A of Figure 1A includes an ART scheme, as previously described.
  • the ART scheme for growing the epitaxial semiconductor material fins 240 avoids patterning and etching that may be used in other approaches (such as the blanket and pattern approach described herein with reference to method 100B of Figure IB), where that patterning/etching may be difficult to perform and/or include processes that are detrimental to the epitaxial semiconductor material, such as plasma etching processes, for example. Therefore, it may be desired, in some embodiments, to form epitaxial semiconductor fins using an ART scheme, such as was done in method 100 A, for example.
  • Method 100B of Figure IB continues from the structure of Figure 2B (after buffer layer 210 was blanket grown 104 on substrate 200) and includes blanket growing 105 epitaxial semiconductor material layer 240' on buffer layer 210 to form the example structure of Figure 2F', in accordance with some embodiments.
  • the epitaxial semiconductor material 240' may be grown/deposited (or otherwise formed) using any suitable technique, such as one or more of the deposition processes described herein (e.g., CVD, MOCVD, PVD, ALD, MBE).
  • the previous relevant description with respect to the blanket growth of buffer layer 210 is equally applicable to the blanket growth of semiconductor material layer 240', such as the blanket growth not needing to be performed above the entirety of substrate 200 or on the entirety of buffer layer 210, in accordance with some embodiments.
  • the epitaxial semiconductor material layer 240' may include any suitable semiconductor material, such as one or more group IV and/or group III-V materials, as will be described in more detail herein with reference to semiconductor material fins 240.
  • the semiconductor material fins 240 of Figure 2G may be formed via this blanket growth and pattern approach.
  • method 100B of Figure IB continues from the structure of Figure 2F' (after semiconductor material layer 240' was formed on buffer layer 210) and includes forming 107 fins from the semiconductor material layer 240', thereby providing an alternative approach to forming fins 240 shown in the example structure of Figure 2G, in accordance with some embodiments.
  • forming 107 fins 240 using this approach may be achieved using any suitable techniques, such as patterning and etching (e.g., using plasma etch processing) to form the fins 240, for example.
  • semiconductor fins 240 are shown, with the width (Fw) and height (Fh) of the right-most fin indicated, in this example embodiment.
  • fins 240 are referred to as semiconductor fins herein because they include semiconductor material.
  • semiconductor fins 240 may include the same or similar sizes shapes as dummy fins 220, as they may have been formed using an ART scheme (e.g., using method 100A of Figure 1A).
  • the fin heights Fh may be in the range of 4-800 nm (e.g., in the subrange of 4-10, 4-20, 4- 50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-100, 10-200, 10-400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400, 100-800, or 400-800 nm), for example, or any other suitable value or range, as will be apparent in light of this disclosure.
  • semiconductor fins 240 may be formed to have particular height to width ratios such that when they are formed, they allow for any potential defects in the epitaxial semiconductor material to terminate on a side surface as the material grows vertically, such as non- crystalline/dielectric sidewalls (e.g., of sacrificial material 230), where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects.
  • the height to width ratio of the fins (Fh:Fw) may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or any other suitable threshold ratio, as will be apparent in light of this disclosure.
  • the fins 240 (four shown) and trenches 245 therebetween are shown in Figure 2G as having the same relative sizes and shapes in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited.
  • the fins 240 may be formed to have varying heights Fh and/or varying widths Fw, depending on the desired configuration.
  • any number of fins may be formed, such as one, two, ten, hundreds, thousands, millions, and so forth, as can be understood based on this disclosure.
  • the epitaxial semiconductor material used for semiconductor fins 240 may include any suitable semiconductor material as will be apparent in light of this disclosure.
  • semiconductor fins 240 may include group IV and/or group III-V semiconductor material.
  • semiconductor fins 240 may include any suitable n-type or p-type dopants at any suitable dopant concentration, such as a concentration in the range of 1E16 to 1E22 atoms per cubic cm (e.g., in the range of 5E19 to 5E21 atoms per cubic cm), or any other suitable concentration as will be apparent in light of this disclosure.
  • the semiconductor fins 240 may be formed using a layer-by-layer epitaxial growth approach (e.g., using an MBE process), such that the fins 240 may or may not appear to have distinct interfaces within the feature, depending on the particular configuration and observation level.
  • a multilayer structure including sacrificial material may be utilized, such that the sacrificial material can be removed (e.g., via a selective etch process) to release the nanowires (or nanoribbons) in the channel region of the transistor, as can be understood based on this disclosure.
  • buffer layer 210 may be formed between the semiconductor fins
  • the buffer layer 210 may be considered a sub-fin (or sub-channel) layer, as it is located between the semiconductor fins 240 and the substrate 200.
  • it may be desired to integrate InGaAs transistors on a Si substrate (e.g., a bulk Si wafer), in some embodiments.
  • semiconductor fins 240 would include InGaAs and substrate 200 would include Si.
  • an InAlAs buffer layer may be employed, such that the InGaAs fins can be formed in a lattice-matched manner on the InAlAs buffer layer (e.g., as the lattice delta between Ino.53Gao.47As and Ino.47Alo.53As is approximately 0.3%).
  • the InAlAs buffer layer can be grown past its strain relaxation critical thickness (he), such that it is a metamorphic layer (as opposed to growing it below its strain relaxation critical thickness, making it a pseudomorphic layer), as previously described.
  • the InAlAs buffer layer may be formed with a thickness (between semiconductor fins 240 and substrate 200) of at least 0.5 microns to exceed its critical thickness and thereby address any defects that may occur at the InAlAs/Si interface (e.g., due to the lattice mismatch between those materials).
  • the critical thickness for the InAlAs buffer layer may be relatively lower than 0.5 microns, depending on, for example, the In concentration in the InAlAs material, and thus, the present disclosure is not intended to be limited to a threshold of 0.5 microns for achieving the strain relaxation critical thickness of an InAlAs buffer layer. Also note that the critical thickness may be as low as 0.1 microns (or even lower), in some embodiments, depending on the material configuration.
  • the InGaAs material may be represented as In x Gai -x As, where x is at least 0.3-1 (e.g., at least 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, or 0.95), or any other suitable threshold value as will be apparent in light of this disclosure.
  • semiconductor fins 240 may include Ino.53Gao.47As, for instance.
  • the InAlAs material may be represented as In y Ali -y As, where y is in the range of 0.35-0.75 (e.g., in the range of 0.35-0.5, 0.35-0.65, 0.4-0.7, 0.45-0.65, 0.45-0.75, 0.65-0.75), or any other suitable range or value as will be apparent in light of this disclosure.
  • buffer layer 210 may include Ino.47Alo.53 As, for instance.
  • the buffer layer 210 and/or the semiconductor fins 240 may include indium gallium aluminum arsenide (InGaAlAs), for example.
  • material combinations may include: a group IV substrate, a group III-V buffer layer, and a group III-V fin; a group IV substrate, a group III-V buffer layer, and a group IV fin; a group IV substrate, a group IV buffer layer, and a group IV fin; and a group III-V substrate, a group IV buffer layer, and a group IV fin.
  • buffer layer 210 may be employed to enable the growth of relatively high quality (or otherwise suitably desired quality) epitaxial semiconductor material (to be used for semiconductor fins 240) above substrate 200, where the epitaxial semiconductor material is lattice mismatched to the substrate 200 material.
  • two materials may be considered lattice mismatched if the absolute value of the lattice delta (or lattice misfit) between the materials is greater than 2-4% (e.g., greater than 2, 2.5, 3, 3.5, or 4%, or greater than the subrange of 2-3% or 3-4%), or some other suitable threshold value or range as will be apparent in light of this disclosure.
  • two materials may be considered lattice matched if the absolute value of the lattice delta or misfit is less than or equal to 2-4% (e.g., less than/equal to 2, 2.5, 3, 3.5, or 4%, or less than/equal to the subrange of 2-3% or 3-4%), or some other suitable threshold value or range as will be apparent in light of this disclosure.
  • 2-4% e.g., less than/equal to 2, 2.5, 3, 3.5, or 4%, or less than/equal to the subrange of 2-3% or 3-4%
  • the lattice delta or misfit absolute value (as a percentage) can be calculated as
  • the lattice mismatching/matching described above may be expressed based on the difference between the lattice constants of the materials involved, due to the value of the lattice constants of group IV and group III-V materials, for example.
  • two materials may be considered lattice mismatched if the absolute value of the difference between the lattice constant of the two materials (which may be represented by
  • two materials may be considered lattice matched if their lattice constant difference absolute value is less than or equal to 0.1-0.3 A at 300 K (e.g., less than/equal to 0.1, 0.15, 0.2, 0.25, or 0.3 A at 300 K, or less than/equal to the subrange of 0.1-0.2 or 0.2-0.3 A at 300 K).
  • their lattice constant difference absolute value can be calculated as
  • That 0.44 A value is relatively high (e.g., greater than 0.1 A at 300K), thereby indicating that Ino.53Gao.47As and Si can be considered lattice mismatched, in some embodiments, and thereby further indicating (as can be understood based on this disclosure) that Ino.53Gao.47As can benefit from an intervening buffer layer as described herein when integrating the epitaxial semiconductor material on a Si substrate.
  • a buffer layer material should be selected such that the desired transistor channel material is lattice matched to the buffer layer material (e.g., using an InAlAs buffer layer, as InGaAs is lattice matched to InAlAs).
  • the lattice constant different absolute value is approximately 0.02 A at 300K, which is relatively low (e.g., less than or equal to 0.1 A at 300K), thereby indicating that Ino.53Gao.47As and Ino.47Alo.53As can be considered lattice matched, in some embodiments.
  • the relative conduction band offset (CBO) between the material of buffer layer 210 and the material of semiconductor fins 240 may be particularly beneficial for n-channel transistor devices (e.g., where the semiconductor fins 240 are to be used to form n-channel transistor devices), while the relative valence band offset (VBO) between the material of buffer layer 210 and the material of semiconductor fins 240 may be particularly beneficial for p-channel transistor devices (e.g., where the semiconductor fins 240 are to be used to form p-channel transistor devices), as can be understood based on this disclosure.
  • CBO conduction band offset
  • VBO relative valence band offset
  • CMOS circuit complementary circuit
  • a buffer layer e.g., buffer layer 210
  • CMOS circuit may be formed above a Si substrate, where the CMOS circuit includes an InGaAs n-channel transistor (e.g., n-MOS) formed on an InAlAs buffer layer and a Ge p-channel transistor (e.g., p-MOS) formed on a GaAs buffer layer.
  • InGaAs n-channel transistor e.g., n-MOS
  • Ge p-channel transistor e.g., p-MOS
  • the buffer layer 210 may include grading (e.g., increasing and/or decreasing) the content of one or more materials throughout the layer.
  • Figure 2F" illustrates a blown-out portion of Figure 2F', showing buffer layer 210' including a specific grading scheme, whereby the content of a material is increased and then decreased, such that the graded material has the relatively highest concentration near the center of that buffer layer 210', in accordance with some embodiments.
  • buffer layer 210' may include InAlAs, where the group III semiconductor material component atomic percentage for the included indium (In) in the InAlAs is initially grown with a first In %, increasing the In % (and thus, decreasing the Al %) as the layer is grown, reaching a maximum In %, and then decreasing the In % (and thus, increasing the Al %) as growth of the layer is completed.
  • the buffer layer may provide beneficial stress to the overlying semiconductor fin, such that it increases mobility in the channel region of a transistor formed in that semiconductor fin, to provide an example.
  • the processing is described herein in the context of a gate last transistor fabrication flow, where the processing includes forming a dummy gate stack, performing the S/D processing, and then forming the final gate stack after the S/D regions have been processed.
  • the techniques may be performed using a gate first process flow.
  • a dummy gate stack need not be formed, as the final gate stack can be formed in the first instance.
  • the description of the continued processing 116 will be described using a gate last process flow, to allow for such a gat last flow (which may include additional processes) to be adequately described.
  • the end structure will include the end gate stack, as will be apparent in light of this disclosure.
  • dummy gate stack including dummy gate dielectric 252 and dummy gate (or dummy gate electrode) 254, in accordance with some embodiments.
  • the formation of the dummy gate stack is optional, because it need not be performed in all embodiments (such as those employing a gate first process flow).
  • dummy gate dielectric 252 e.g., dummy oxide material
  • dummy gate (or dummy gate electrode) 254 e.g., dummy poly-silicon material
  • side-wall spacers 250 referred to generally as gate spacers (or simply, spacers), on either side of the dummy gate stack were also formed, and such spacers 250 can help determine the channel length and can help with replacement gate processing, for example.
  • the dummy gate stack (and spacers 250) help define the channel region and source/drain (S/D) regions of each fin 240, where the channel region is below the dummy gate stack (as it will be located below the final gate stack), and the S/D regions are on either side of the channel region (e.g., not below the dummy gate stack).
  • Formation of the dummy gate stack may include depositing the dummy gate dielectric material 252 and dummy gate (or dummy gate electrode) material 254, patterning the dummy gate stack, depositing gate spacer material 250, and performing a spacer etch to form the structure shown in Figure 2H, for example.
  • Spacers 250 may include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure.
  • a hardmask (not shown) may be formed over the dummy gate stack (which may also be formed over spacers 250) to protect the dummy gate stack during subsequent processing, for example.
  • completing 116 the transistor processing includes performing source/drain (S/D) processing to form the example resulting structure of Figure 21, in accordance with some embodiments.
  • the S/D regions 260 may be formed using any suitable techniques, such as masking regions outside of the S/D regions to be processed, etching at least a portion of the fins 240 from the structure of Figure 2H, and forming/depositing/growing the S/D regions 260 (e.g., using any suitable techniques, such as CVD, MOCVD, ALD, PVD, MBE), for example.
  • the semiconductor fins 240 need not be completely removed, but they may remain and be doped and/or cladded and/or have some other suitable processing performed to convert them into suitable S/D regions, for example.
  • the material of the S/D regions 260 is replacement material, there is a distinct interface between the remainder 241 of semiconductor fins 240 and S/D regions 260, as shown in Figure 21.
  • one or more of the S/D regions 260 may have a multilayer structure including multiple material layers, for example.
  • one or more of the S/D regions 260 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in some or all of the region(s).
  • the S/D regions may be formed one polarity at a time, such as performing processing for one of n-type and p-type S/D regions, and then performing processing for the other of the n-type and p-type S/D regions.
  • the S/D regions may include any suitable material, such as group IV semiconductor material (e.g., Si, SiGe, Ge), group III-V semiconductor material (e.g., InGaAs, GaAs, InAlGaAs), and/or any other suitable material, as will be apparent in light of this disclosure.
  • the S/D regions may include any suitable doping scheme, such as including suitable n-type and/or p-type dopant in a corresponding set of S/D regions.
  • the S/D regions may include the same type of dopants (e.g., where both are p-type doped or both are n-type doped).
  • the four sets of S/D regions 260 may include doping configurations that are all the same, some the same, or none the same, as can be understood based on this disclosure (note that in Figure 21, only one S/D region set is indicated as 260 for ease of illustration, which is the left-most set). Numerous transistor S/D configurations and variations will be apparent in light of this disclosure.
  • completing 116 the transistor processing includes performing gate stack processing to form the example resulting structure of Figure 2J, in accordance with some embodiments.
  • the processing in this example embodiment included depositing interlayer dielectric (ILD) layer 270 on the structure of Figure 21, followed by optional planarization and/or polishing to reveal the dummy gate stack.
  • ILD layer 270 is shown as transparent in the example structure of Figure 2J to allow for the underlying features to be seen (and the ILD layer 270 may actually be transparent or translucent at such a small scale); however, the present disclosure is not intended to be so limited.
  • the ILD layer 270 may include any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure.
  • the gate stack processing in this example embodiment, continued with removing the dummy gate stack (including dummy gate 254 and dummy gate dielectric 252) to allow for the final gate stack to be formed.
  • the formation of the final gate stack which includes gate dielectric layer 282 and gate (or gate electrode) 284, may be performed using a gate first flow (e.g., an up-front hi-k gate process).
  • the final gate processing may have been performed prior to the S/D processing, for example.
  • the gate stack is formed using a gate last flow (also called a replacement gate or replacement metal gate (RMG) process).
  • the process may include dummy gate oxide deposition, dummy gate electrode (e.g., poly-Si) deposition, and, optionally, patterning hardmask deposition, as previously described.
  • the final gate stack can include gate dielectric layer 282 and gate 284 as shown in Figure 2G, in accordance with some embodiments.
  • the channel region of fins 240 (that were covered by the dummy gate) are exposed to allow for any desired processing of the channel regions of the fins.
  • processing of the channel regions may include various different techniques, such as removing and replacing the channel region with replacement material, doping the channel region of the fin as desired, forming the fin into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, cleaning/polishing the channel region, and/or any other suitable processing as will be apparent in light of this disclosure.
  • GAA gate-all-around
  • finned channel region 242 is illustrated (which is the channel region of the right-most finned structure), which may have been from the original semiconductor fin 240 or may have been formed by doping the original semiconductor fin 240 with a desired suitable n- type or p-type dopant, for example.
  • nanowire channel region 244 (which is the channel region of the left most finned structure) may have been formed after the dummy gate was removed and the channel regions of the fins were exposed, by converting the multilayer finned structure into the two nanowires (or nanoribbons) shown, using any suitable techniques, for example.
  • nanowire channel region 244 includes two nanowires (or nanoribbons)
  • a nanowire (or nanoribbon or GAA) transistor formed using the techniques disclosed herein may include any number of nanowires (or nanoribbons) such as 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or more, depending on the desired configuration.
  • the channel region is at least below the gate stack, in some embodiments.
  • the channel region may be below and between the gate stack, as the gate stack may be formed on three sides of the finned structure, as is known in the art.
  • the gate stack may substantially (or completely) surround each nanowire/nanoribbon in the channel region.
  • the gate stack may simply be above the channel region.
  • the channel region may include group IV and/or group III-V semiconductor material, for example, such as the material described with reference to semiconductor fins 240.
  • the channel region of a given transistor may be doped (e.g., with any suitable n-type and/or p-type dopants) or intrinsic/undoped, depending on the particular configuration.
  • the S/D regions are adjacent to either side of the channel region, as can be seen in Figure 2J. In other words, the channel region is between corresponding S/D regions.
  • the configuration/geometry of a transistor formed using the techniques described herein may primarily be described based on the shape/configuration of the respective channel region of that transistor, for example. For instance, a nanowire (or nanoribbon or GAA) transistor may be referred to as such because it includes one or more nanowires (or nanoribbons) in the channel region of that transistor.
  • a given transistor's type (e.g., MOSFET or TFET or other suitable type) may be described based on the doping and/or operating scheme of the source, drain, and channel, and thus those respective regions may be used to determine the type or classification of a given transistor, for example. This is especially true for MOSFET versus TFET transistors, as they may structurally be similar (or the same), but include different doping schemes (e.g., p-n-p/p-i-p or n-p-n/n-i-n versus p-i-n or n-i-p, respectively).
  • the final gate stack can be formed, in accordance with some embodiments.
  • the final gate stack includes gate dielectric layer 282 and gate (or gate electrode) 284, as shown in Figure 2G.
  • the gate dielectric layer 282 may include, for example, any suitable oxide (such as silicon dioxide), high-k gate dielectric material, and/or any other suitable material as will be apparent in light of this disclosure.
  • high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples.
  • an annealing process may be carried out on the gate dielectric layer 282 to improve its quality when high-k material is used.
  • the gate 284 may include a wide range of materials, such as polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), or tantalum nitride (TaN), for example.
  • gate dielectric layer 282 and/or gate 284 may include a multilayer structure of two or more material layers, for example.
  • gate dielectric layer 282 and/or gate 284 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the feature(s).
  • One or more additional layers may also be present in the final gate stack, in some embodiments, such as one or more work function layers or other suitable layers, for example.
  • gate dielectric layer 282 is only shown below gate 284 in the example embodiment of Figure 2J, in other embodiments, the gate dielectric layer 282 may also be present on one or both sides of gate 284, such that the gate dielectric layer 282 may also be between gate 284 and one or both spacers 250, for example. Numerous different gate stack configurations will be apparent in light of this disclosure.
  • the length of gate 284 (e.g., the dimension between spacers 250 in the Z-axis direction), which may be the same as or approximate the channel length (e.g., the gate length may be approximately longer than the channel length due to potential diffusion of dopant from the S/D regions into the channel region), may be any suitable length as will be apparent in light of this disclosure.
  • completing 116 the transistor processing can include performing S/D contact processing to form the example resulting structure of Figure 2K, in accordance with some embodiments.
  • S/D contacts 290 were formed to make contact to each of the S/D regions 260, in this example embodiment.
  • S/D contacts 290 may be formed using any suitable techniques, such as forming contact trenches in ILD layer 270 over the respective S/D regions 260 and depositing metal or metal alloy (or other suitable electrically conductive material) in the trenches.
  • S/D contact 290 formation may include silicidation, germinidation, and/or annealing processes, for example.
  • S/D contacts 290 may include aluminum or tungsten, although any suitable conductive metal or alloy can be used, such as silver, nickel-platinum, or nickel-aluminum, for example.
  • one or more of the S/D contacts 290 may include a resistance reducing metal and a contact plug metal, or just a contact plug, for instance.
  • Example contact resistance reducing metals include, for instance, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys.
  • Example contact plug metals include, for instance, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used.
  • additional layers may be present in the S/D contact 290 regions, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired.
  • a contact resistance reducing layer may be present between a given S/D region 260 and its corresponding S/D contact 290, such as a relatively highly doped (e.g., degenerately doped with dopant concentrations greater than 1E18, 1E19, 1E20, 1E21, or 1E22 atoms per cubic cm) intervening semiconductor material layer, for example.
  • the contact resistance reducing layer may include semiconductor material and/or impurity dopants based on the material and/or dopant concentration of the corresponding S/D region, for example.
  • IC processing 118 may occur as desired, in accordance with some embodiments.
  • Such additional processing to complete an IC may include back-end or back-end-of-line (BEOL) processing to form one or more metallization layers and/or to interconnect the transistor devices formed, for example. Any other suitable processing may be performed, as will be apparent in light of this disclosure.
  • BEOL back-end or back-end-of-line
  • Any other suitable processing may be performed, as will be apparent in light of this disclosure.
  • the processes 102-118 of methods 100A-B in Figures 1A-B are shown in a particular order for ease of description. However, one or more of the processes may be performed in a different order or may not be performed at all (and thus be optional), in accordance with some embodiments.
  • the devices formed may include p-channel transistor devices (e.g., p-MOS or p-TFET) and/or n-channel transistor devices (e.g., n-MOS or n-TFET).
  • CMOS complementary MOS
  • CTFET complementary TFET
  • quantum devices e.g., few to single electron
  • FIG. 3 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.
  • the computing system 1000 houses a motherboard 1002.
  • the motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein.
  • the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.
  • computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002.
  • these other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • graphics processor e.g., a digital signal processor
  • crypto processor e.g., a graphics processor
  • any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.
  • multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).
  • the communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing system 1000 may include a plurality of communication chips 1006.
  • a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004.
  • the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • the term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006.
  • the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein.
  • multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips).
  • processor 1004 may be a chip set having such wireless capability.
  • any number of processor 1004 and/or communication chips 1006 can be used.
  • any one chip or chip set can have multiple functions integrated therein.
  • the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • PDA personal digital assistant
  • an ultra-mobile PC a mobile phone
  • desktop computer a server
  • printer a printer
  • a scanner a monitor
  • a set-top box a set-top box
  • an entertainment control unit a digital camera
  • portable music player a digital video recorder
  • Example 1 is an integrated circuit (IC) including: a substrate including a first semiconductor material having a first lattice constant; a transistor above the substrate, the transistor including a gate, a channel region below the gate and including a second semiconductor material having a second lattice constant, wherein the absolute value of the difference between the first and second lattice constants is greater than 0.1 angstroms (A) at 300 Kelvin (K), and source and drain (S/D) regions adjacent the channel region; and a buffer layer between the substrate and the transistor, the buffer layer including a third semiconductor material having a third lattice constant, wherein the absolute value of the difference between the second and third lattice constants is less than or equal to 0.3 A at 300 K.
  • IC integrated circuit
  • Example 2 includes the subject matter of Example 1, wherein the first semiconductor material includes silicon (Si).
  • Example 3 includes the subject matter of Example 1 or 2, wherein there is at least a 0.3 electronvolt (eV) offset between at least one of conduction bands and valence bands of the second and third semiconductor materials.
  • Example 4 includes the subject matter of any of Examples 1-3, wherein the second semiconductor material includes at least one of indium gallium arsenide (InGaAs) and germanium (Ge).
  • Example 5 includes the subject matter of Example 4, wherein the second semiconductor material includes InGaAs having a group III semiconductor material component atomic percentage for the included indium (In) of at least 40%.
  • Example 6 includes the subject matter of any of Examples 1-5, wherein the third semiconductor material includes at least one of indium aluminum arsenide (InAlAs) and gallium arsenide (GaAs).
  • the third semiconductor material includes at least one of indium aluminum arsenide (InAlAs) and gallium arsenide (GaAs).
  • Example 7 includes the subject matter of Example 6, wherein the third semiconductor material includes InAlAs having a group III semiconductor material component atomic percentage for the included indium (In) between 40% and 70%.
  • Example 8 includes the subject matter of Example 7, wherein In content included in the buffer layer is graded, such that the In content increases and then decreases along a thickness of the buffer layer.
  • Example 9 includes the subject matter of any of Examples 1-8, wherein the buffer layer includes a thickness between the substrate and the transistor of at least the third semiconductor material strain relaxation critical thickness.
  • Example 10 includes the subject matter of any of Examples 1-9, wherein the buffer layer includes a thickness between the substrate and the transistor of at least 0.1-0.5 micrometers (microns).
  • Example 11 includes the subject matter of any of Examples 1-10, wherein the absolute value of the difference between the first and second lattice constants is greater than 0.2 A at 300 K.
  • Example 12 includes the subject matter of any of Examples 1-11, wherein the absolute value of the difference between the second and third lattice constants is less than or equal to 0.2 A at 300 K.
  • Example 13 includes the subject matter of any of Examples 1-12, wherein one of the S/D regions includes p-type dopant and the other of the S/D regions includes n-type dopant.
  • Example 14 includes the subject matter of any of Examples 1-13, wherein the S/D regions both include one of p-type and n-type dopant.
  • Example 15 includes the subject matter of any of Examples 1-14, wherein the transistor has at least one of a finned, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA) configuration.
  • FinFET finned field-effect transistor
  • GAA gate-all-around
  • Example 16 includes the subject matter of any of Examples 1-15, wherein the transistor is at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET), tunnel field-effect transistor (TFET), and high-electron-mobility transistor (HEMT).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • TFET tunnel field-effect transistor
  • HEMT high-electron-mobility transistor
  • Example 17 is a computing system including the subject matter of any of Examples 1-16.
  • Example 18 is an integrated circuit (IC) including: a substrate including silicon (Si); a transistor above the substrate, the transistor including a gate, a channel region below the gate and including indium gallium arsenide (InGaAs), and source and drain (S/D) regions adjacent the channel region; and a buffer layer between the substrate and the transistor, the buffer layer including indium aluminum arsenide (InAlAs).
  • IC integrated circuit
  • Example 19 includes the subject matter of Example 18, wherein the InGaAs included in the channel region has a group III semiconductor material component atomic percentage for the included indium (In) of at least 40%.
  • Example 20 includes the subject matter of Example 18 or 19, wherein the InAlAs included in the buffer layer has a group III semiconductor material component atomic percentage for the included indium (In) between 40% and 70%.
  • Example 21 includes the subject matter of any of Examples 18-20, wherein In content included in the buffer layer is graded, such that the In content increases and then decreases along a thickness of the buffer layer.
  • Example 22 includes the subject matter of any of Examples 18-21, wherein the buffer layer includes a thickness between the substrate and the transistor of at least 0.5 micrometers (microns).
  • Example 23 includes the subject matter of any of Examples 18-22, wherein the Si included in the substrate is p-type doped.
  • Example 24 includes the subject matter of any of Examples 18-23, wherein one of the S/D regions includes p-type dopant and the other of the S/D regions includes n-type dopant.
  • Example 25 includes the subject matter of any of Examples 18-24, wherein the S/D regions both include one of p-type and n-type dopant.
  • Example 26 includes the subject matter of any of Examples 18-25, wherein the transistor has at least one of a finned, tri-gate, and finned field-effect transistor (FinFET) configuration.
  • Example 27 includes the subject matter of any of Examples 18-25, wherein the transistor has at least one of a nanowire, nanoribbon, and gate-all-around (GAA) configuration.
  • GAA gate-all-around
  • Example 28 includes the subject matter of any of Examples 18-27, wherein the transistor is at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET), tunnel field-effect transistor (TFET), and high-electron-mobility transistor (HEMT).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • TFET tunnel field-effect transistor
  • HEMT high-electron-mobility transistor
  • Example 29 is a computing system including the subject matter of any of Examples 18-28.
  • Example 30 is a method of forming an integrated circuit (IC), the method including: form a buffer layer on a substrate, wherein the substrate includes a first semiconductor material having a first lattice constant and the buffer layer includes a second semiconductor material having a second lattice constant; form a fin on the buffer layer, wherein the substrate includes a first semiconductor material having a first lattice constant, the fin includes a second semiconductor material having a second lattice constant, and the buffer layer includes a third semiconductor material having a third lattice constant; and form a transistor, wherein the transistor channel region is included in the second semiconductor material native to the fin; wherein the absolute value of the difference between the first and second lattice constants is greater than 0.1 angstroms (A) at 300 Kelvin (K); and wherein the absolute value of the difference between the second and third lattice constants is less than or equal to 0.3 A at 300 K.
  • IC integrated circuit
  • Example 31 includes the subject matter of Example 30, wherein the fin is formed on the buffer layer in a fin-shaped trench using an aspect ratio trapping (ART) scheme.
  • ART aspect ratio trapping
  • Example 32 includes the subject matter of Example 30, wherein the fin is formed on the buffer layer by blanket-growing the second semiconductor material on the buffer layer and patterning the second semiconductor material to form the fin.
  • Example 33 includes the subject matter of any of Examples 30-32, wherein the first semiconductor material includes silicon (Si).
  • Example 34 includes the subject matter of any of Examples 30-33, wherein there is at least a 0.3 electronvolt (eV) offset between at least one of conduction bands and valence bands of the second and third semiconductor materials.
  • eV electronvolt
  • Example 35 includes the subject matter of any of Examples 30-34, wherein the second semiconductor material includes at least one of indium gallium arsenide (InGaAs) and germanium (Ge).
  • Example 36 includes the subject matter of Example 35, wherein the second semiconductor material includes InGaAs having a group III semiconductor material component atomic percentage for the included indium (In) of at least 40%.
  • Example 37 includes the subject matter of any of Examples 30-36, wherein the third semiconductor material includes at least one of indium aluminum arsenide (InAlAs) and gallium arsenide (GaAs).
  • the third semiconductor material includes at least one of indium aluminum arsenide (InAlAs) and gallium arsenide (GaAs).
  • Example 38 includes the subject matter of Example 37, wherein the third semiconductor material includes InAlAs having a group III semiconductor material component atomic percentage for the included indium (In) between 40% and 70%.
  • Example 39 includes the subject matter of Example 38, wherein In content included in the buffer layer is graded, such that the In content increases and then decreases along a thickness of the buffer layer.
  • Example 40 includes the subject matter of any of Examples 30-39, wherein the buffer layer includes a thickness between the substrate and the transistor of at least the third semiconductor material strain relaxation critical thickness.
  • Example 41 includes the subject matter of any of Examples 30-40, wherein the buffer layer includes a thickness between the substrate and the transistor of at least 0.1-0.5 micrometers (microns).
  • Example 42 includes the subject matter of any of Examples 30-41, wherein the absolute value of the difference between the first and second lattice constants is greater than 0.2 A at 300 K.
  • Example 43 includes the subject matter of any of Examples 30-42, wherein the absolute value of the difference between the second and third lattice constants is less than or equal to 0.2 A at 300 K.
  • Example 44 includes the subject matter of any of Examples 30-43, wherein the transistor has at least one of a finned, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA) configuration.
  • FinFET finned field-effect transistor
  • GAA gate-all-around
  • Example 45 includes the subject matter of any of Examples 30-44, wherein the transistor is at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET), tunnel field-effect transistor (TFET), and high-electron-mobility transistor (HEMT).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • TFET tunnel field-effect transistor
  • HEMT high-electron-mobility transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne des techniques de formation de transistors utilisant une couche tampon métamorphique à croissance de couverture. Comme on peut le comprendre sur la base de la présente invention, l'utilisation de la couche tampon permet l'intégration d'un matériau semi-conducteur épitaxial de qualité relativement élevée (ou de qualité dispositif) à un substrat, que l'on ne pourrait autrement pas intégrer du fait d'un désaccord de réseau. À titre d'exemple, les techniques peuvent permettre la formation monolithique d'InGaAs de qualité relativement élevée pour des transistors à InGaAs à grande échelle au-dessus d'un substrat en Si par l'utilisation d'une couche tampon d'InAlAs métamorphique d'intervention. À noter que le terme métamorphique indique que la couche a crû au-delà de son épaisseur critique de relaxation de contrainte. L'obtention d'une épaisseur métamorphique de la couche tampon permet d'atténuer le désaccord de réseau qui serait autrement présent entre le matériau semi-conducteur épitaxial et le matériau de substrat. Dans certains cas, la couche tampon fournit également une isolation électrique du matériau semi-conducteur épitaxial sus-jacent.
PCT/US2016/068885 2016-12-28 2016-12-28 Transistors utilisant une couche tampon métamorphique à croissance de couverture WO2018125081A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2016/068885 WO2018125081A1 (fr) 2016-12-28 2016-12-28 Transistors utilisant une couche tampon métamorphique à croissance de couverture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2016/068885 WO2018125081A1 (fr) 2016-12-28 2016-12-28 Transistors utilisant une couche tampon métamorphique à croissance de couverture

Publications (1)

Publication Number Publication Date
WO2018125081A1 true WO2018125081A1 (fr) 2018-07-05

Family

ID=62710111

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2016/068885 WO2018125081A1 (fr) 2016-12-28 2016-12-28 Transistors utilisant une couche tampon métamorphique à croissance de couverture

Country Status (1)

Country Link
WO (1) WO2018125081A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021242346A1 (fr) * 2020-05-29 2021-12-02 Microsoft Technology Licensing, Llc Croissance localisée de nanofils et procédé de planarisation
US11488822B2 (en) 2020-05-29 2022-11-01 Microsoft Technology Licensing, Llc SAG nanowire growth with ion implantation
US11798988B2 (en) 2020-01-08 2023-10-24 Microsoft Technology Licensing, Llc Graded planar buffer for nanowires
TWI853848B (zh) 2019-11-07 2024-09-01 聯華電子股份有限公司 半導體結構的製作方法及半導體結構

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060194387A1 (en) * 2005-02-25 2006-08-31 Chih-Hao Wang High performance transistors with SiGe strain
US20090042344A1 (en) * 2007-06-15 2009-02-12 Amberwave Systems Corporation InP-Based Transistor Fabrication
US20140361378A1 (en) * 2013-06-07 2014-12-11 Dong-Kyu Lee Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
US20150228730A1 (en) * 2014-02-13 2015-08-13 Jung-Gil YANG Metal-oxide semiconductor field effect transistor, method of fabricating the same, and semiconductor apparatus including the same
WO2016043775A1 (fr) * 2014-09-19 2016-03-24 Intel Corporation Appareil et procédés pour créer une sous-structure dopée afin de réduire une fuite dans des transistors micro-électroniques

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060194387A1 (en) * 2005-02-25 2006-08-31 Chih-Hao Wang High performance transistors with SiGe strain
US20090042344A1 (en) * 2007-06-15 2009-02-12 Amberwave Systems Corporation InP-Based Transistor Fabrication
US20140361378A1 (en) * 2013-06-07 2014-12-11 Dong-Kyu Lee Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
US20150228730A1 (en) * 2014-02-13 2015-08-13 Jung-Gil YANG Metal-oxide semiconductor field effect transistor, method of fabricating the same, and semiconductor apparatus including the same
WO2016043775A1 (fr) * 2014-09-19 2016-03-24 Intel Corporation Appareil et procédés pour créer une sous-structure dopée afin de réduire une fuite dans des transistors micro-électroniques

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI853848B (zh) 2019-11-07 2024-09-01 聯華電子股份有限公司 半導體結構的製作方法及半導體結構
US11798988B2 (en) 2020-01-08 2023-10-24 Microsoft Technology Licensing, Llc Graded planar buffer for nanowires
WO2021242346A1 (fr) * 2020-05-29 2021-12-02 Microsoft Technology Licensing, Llc Croissance localisée de nanofils et procédé de planarisation
US11488822B2 (en) 2020-05-29 2022-11-01 Microsoft Technology Licensing, Llc SAG nanowire growth with ion implantation
US11929253B2 (en) 2020-05-29 2024-03-12 Microsoft Technology Licensing, Llc SAG nanowire growth with a planarization process
US20240170286A1 (en) * 2020-05-29 2024-05-23 Microsoft Technology Licensing, Llc Sag nanowire growth with a planarization process
US12119224B2 (en) 2020-05-29 2024-10-15 Microsoft Technology Licensing, Llc SAG nanowire growth with ion implantation

Similar Documents

Publication Publication Date Title
US11588052B2 (en) Sub-Fin isolation schemes for gate-all-around transistor devices
US11495672B2 (en) Increased transistor source/drain contact area using sacrificial source/drain layer
US11101350B2 (en) Integrated circuit with germanium-rich channel transistors including one or more dopant diffusion barrier elements
US11164974B2 (en) Channel layer formed in an art trench
US10886272B2 (en) Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices
US20190348415A1 (en) Transistors employing cap layer for ge-rich source/drain regions
US11276694B2 (en) Transistor structure with indium phosphide channel
US11398479B2 (en) Heterogeneous Ge/III-V CMOS transistor structures
US20190348501A1 (en) Germanium-rich channel transistors including carbon-based dopant diffusion barrier
US11121030B2 (en) Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch
US11404575B2 (en) Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer
US11757004B2 (en) Transistors including source/drain employing double-charge dopants
US11056592B2 (en) Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer
US11011620B2 (en) Techniques for increasing channel region tensile strain in n-MOS devices
US11482457B2 (en) Substrate defect blocking layers for strained channel semiconductor devices
WO2018125081A1 (fr) Transistors utilisant une couche tampon métamorphique à croissance de couverture
WO2018182619A1 (fr) Co-intégration de matériaux semi-conducteurs de compositions différentes à l'aide d'une couche de germe mince commune
WO2018125082A1 (fr) Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si
TWI784035B (zh) 用於應變電晶體的磊晶氧化物插塞及形成積體電路結構的方法
WO2018063333A1 (fr) Transistors à effet tunnel comprenant des régions de source/drain traitées par l'intermédiaire de tranchées de contact
WO2018125035A1 (fr) Transistors comprenant un matériau de source/drain final traité après traitement de grille de remplacement
WO2018182627A1 (fr) Transistors comprenant des entretoises de grille asymétriques
WO2018063335A1 (fr) Transistors à effet tunnel comprenant des régions de source/drain utilisant une couche d'arrêt de gravure à base de carbone
WO2018063310A1 (fr) Transistors à effet tunnel comprenant des régions de source/drain utilisant différents matériaux semi-conducteurs

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16925331

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16925331

Country of ref document: EP

Kind code of ref document: A1