WO2018120122A1 - 内嵌式触控面板及其阵列基板 - Google Patents

内嵌式触控面板及其阵列基板 Download PDF

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Publication number
WO2018120122A1
WO2018120122A1 PCT/CN2016/113740 CN2016113740W WO2018120122A1 WO 2018120122 A1 WO2018120122 A1 WO 2018120122A1 CN 2016113740 W CN2016113740 W CN 2016113740W WO 2018120122 A1 WO2018120122 A1 WO 2018120122A1
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Prior art keywords
touch
touch panel
metal connection
array substrate
thin film
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PCT/CN2016/113740
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English (en)
French (fr)
Inventor
张启沛
张春倩
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武汉华星光电技术有限公司
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Priority to US15/502,789 priority Critical patent/US10310649B2/en
Publication of WO2018120122A1 publication Critical patent/WO2018120122A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the present invention relates to a touch panel, and more particularly to an in-cell touch panel and an array substrate thereof.
  • Liquid crystal display is one of the most widely used flat panel displays, and has gradually become a variety of such as mobile phones, personal digital assistants (PDAs), digital cameras, desktop computers or laptop computers.
  • PDAs personal digital assistants
  • the touch sensor can be divided into a liquid crystal cell (On Cell), and the touch sensor is embedded in the liquid crystal cell (In Cell) and touch sensor are external to the display panel (Out Cell).
  • the In-Cell type touch panel refers to a method of embedding a touch function into a liquid crystal pixel, which not only further reduces the thickness of the whole machine, but also can be produced together with the LCD, without additional manufacturing processes, and does not affect its outdoor appearance. Visibility in bright environments. Therefore, research on In-Cell type touch panels is becoming more and more popular.
  • a design structure of the existing in-cell touch panel utilizes a metal connection layer to transmit a touch signal, and the metal connection layer includes a plurality of metal connection lines parallel to each other for electrically connecting different touch sensors. Pad electrode.
  • the metal connection line is generally disposed above the data line of the touch panel.
  • resistive capacitive load RC Loading
  • An object of the present invention is to provide an array substrate of an in-cell touch panel capable of reducing a resistive capacitive load of a trace in an effective area of a touch panel and improving touch precision of the touch panel.
  • the present invention provides an array substrate of an in-cell touch panel, the array substrate includes: a touch electrode disposed in an array in an effective area of the touch panel; and a touch sensing chip disposed on the touch panel
  • the metal connection line is disposed on the outer layer of the touch electrode and connected to the touch electrode through the via hole, and is insulated from the data line of the touch panel, wherein the touch electrode passes through the metal connection line.
  • a switching circuit is disposed between the metal connecting line and the data line, and the switch circuit connects the metal connecting line and the data line in the touch phase, and disconnects the metal connecting line and the data line in the display phase. open.
  • the switching circuit can include a thin film transistor and a common conductive line.
  • the gate of the thin film transistor may be connected to a common conductive line, one of the source and the drain of the thin film transistor may be connected to the metal connection line, and the other of the source and the drain of the thin film transistor may be connected to the data line.
  • the common conductive line can be taken out by the touch sensing chip.
  • the thin film transistor may be an NMOS, a PMOS, a CMOS, a transmission gate, or the like.
  • the switch circuit can be disposed on an upper side or a lower side of the active area of the touch panel.
  • the array substrate of the in-cell touch panel provides a signal to the common conductive line through the touch sensing chip during the touch phase of the touch panel to electrically connect the thin film transistor, thereby electrically connecting the data line and the metal connection line. Therefore, the resistance value and the capacitance value of the trace of the touch panel in the active area are greatly reduced, and the resistance and capacitive load are reduced, thereby increasing the working accuracy of the touch panel.
  • FIG. 1 is a schematic cross-sectional view showing an In-Cell touch array substrate according to the related art.
  • FIG. 2 is a schematic diagram showing the architecture of a self-capacitance In-Cell touch array substrate according to the prior art.
  • FIG. 3 is a block diagram showing an In-Cell touch array substrate according to an exemplary embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view showing an In-Cell touch array substrate according to the related art.
  • the touch array substrate 100 may include a substrate 110, a light shielding layer 115, a buffer layer 120, a semiconductor element SE, a planarization layer 140, a common electrode layer 145, a second interlayer insulating layer 150, a metal connection layer M3, and a blunt Layer 155 and pixel electrode layer 160.
  • Substrate 110 can include a transparent substrate, preferably a glass substrate.
  • the light shielding layer 115 may be disposed on the substrate 110 and under the semiconductor element SE for preventing light from entering a channel region of the thin film transistor that the semiconductor element SE may include, thereby functioning to reduce leakage current and improve electrical performance of the thin film transistor device.
  • the light shielding layer 115 may be a stacked combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • the buffer layer 120 may be disposed on the substrate 110 and cover the light shielding layer 115 on the substrate 110.
  • the buffer layer 120 may reduce or effectively prevent diffusion of metal atoms and/or impurities from the substrate 110 to other layers of the touch array substrate on the substrate 110 and may improve the flatness of the irregular surface of the substrate 110.
  • the buffer layer 120 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the semiconductor element SE may be disposed on the buffer layer 120.
  • the semiconductor element SE may include a thin film transistor.
  • the thin film transistor may include a polysilicon layer 125, a source S, a drain D, a gate G, and a gate insulating layer 130 and a first interlayer insulating layer 135 disposed therebetween.
  • the polysilicon layer 125 may be disposed on the buffer layer 120 and includes an N-type heavily doped region N+ at both ends, a channel region CH located in the middle, and an N-type between the N-type heavily doped region N+ and the channel region CH Lightly doped zone N-.
  • the gate insulating layer 130 may be disposed on the buffer layer 120 and cover the polysilicon layer 125 on the buffer layer 120.
  • the gate insulating layer 130 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the gate G may be disposed on the gate insulating layer 130.
  • the gate G may overlap the channel region CH of the polysilicon layer 125.
  • the gate G may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.
  • the first interlayer insulating layer 135 may be disposed on the gate insulating layer 130 and cover the gate G on the gate insulating layer 130.
  • the first interlayer insulating layer 135 may be formed using an inorganic material or an organic material.
  • the source S and the drain D may be disposed on the first interlayer insulating layer 135.
  • the source S and the drain D may be in contact with the N-type heavily doped region N+ through the first via H1, respectively.
  • the first via hole H1 is formed on the N-type heavily doped region N+ at both ends and passes through the first interlayer insulating layer 135 and the gate insulating layer 130.
  • Each of the source S and the drain D may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and/or a transparent conductive film.
  • the planarization layer 140 may be disposed on the first interlayer insulating layer 135.
  • the planarization layer 140 may completely cover the source S and the drain D, and may have a substantially horizontal surface without a step surrounding the source S and the drain D.
  • the planarization layer 140 may include an organic material or an inorganic material.
  • the common electrode layer 145 may be disposed on the planarization layer 140.
  • the material of the common electrode layer 145 may be a transparent metal oxide, and the transparent metal oxide may be one of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide. Or a variety.
  • the second interlayer insulating layer 150 may be disposed on the planarization layer 140 and cover the common electrode layer 145 on the planarization layer 140.
  • the second interlayer insulating layer 150 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the metal connection layer M3 may be disposed on the second interlayer insulating layer 150 and overlap the source S of the semiconductor element SE.
  • the metal connection layer M3 is in contact with the common electrode layer 145 located thereunder through the second via hole H2, and the second via hole H2 is formed on the common electrode 145 and passes through the second interlayer insulating layer 150.
  • Metal connection layer M3 can be constructed of any suitable electrically conductive material.
  • the passivation layer 155 may be disposed on the second interlayer insulating layer 150 and may cover the metal connection layer M3 on the second interlayer insulating layer 150.
  • the material of the passivation layer 155 may be silicon nitride or silicon oxide.
  • the pixel electrode layer 160 may be disposed on the passivation layer 155.
  • the pixel electrode layer 160 may be in contact with the drain D of the semiconductor element SE through the third via hole H3.
  • the third via hole H3 is on the drain D of the semiconductor element SE and passes through the planarization layer 140, the second interlayer insulating layer 150, and the passivation layer 155.
  • the material of the pixel electrode layer 160 may be a transparent metal oxide, and the transparent metal oxide may be one of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide. Or a variety.
  • the source S of the semiconductor element SE is connected to the data line, and the gate G of the semiconductor element SE is connected to the gate line.
  • the display panel is driven by the gate signal provided by the gate line and the data voltage supplied from the data line.
  • the metal connection layer M3 of the touch panel is overlapped with the data line, there is a resistive capacitive load (RC Loading) between the metal connection layer M3 and the data line, and the load affects the touch signal transmitted by the metal connection layer.
  • RC Loading resistive capacitive load
  • the in-cell touch array substrate is implemented by the arrangement of the common electrode layer 145 and the metal connection layer M3.
  • the touch technology is self-capacitive.
  • the common electrode layer 145 is used as the touch panel. Capacitor electrode.
  • FIG. 2 is a schematic diagram showing the architecture of a self-capacitance In-Cell touch array substrate according to the prior art.
  • the self-capacitance In-Cell touch array substrate includes a touch sensing chip IC, a plurality of parallel metal connecting lines ML connected to the touch sensing chip IC, and a plurality of self-capacitance electrodes 200 .
  • the touch sensing chip IC is disposed outside the active area of the touch panel.
  • a plurality of self-capacitance electrodes 200 are formed in an array in an effective area of the touch panel, each of the plurality of metal connection lines ML It is used for electrically connecting a touch sensing chip IC and a corresponding one of the plurality of self-capacitance electrodes 200.
  • the self-capacitance electrode 200 may correspond to the common electrode layer 145 shown in FIG. 1, and the metal connection line ML may correspond to the metal connection layer M3 as shown in FIG.
  • the self-capacitance electrode 200 and the metal connection line ML are disposed in different layers, and the self-capacitance electrode 200 is electrically connected to the corresponding metal connection line ML through the via hole H, wherein the via hole H can correspond to the one shown in FIG.
  • the metal via layer M3 and the second via hole H2 of the common electrode layer 145 are electrically connected.
  • a hollowed out design may be adopted for the common electrode layer 145 serving as a self-capacitance electrode under the metal connection layer M3 as shown in FIG. 1 such that the plurality of self-capacitance electrodes 200 are spaced apart from each other as shown in FIG. Thereby, crosstalk between the plurality of self-capacitance electrodes 200 is improved.
  • the capacitance of each self-capacitance electrode is a fixed value.
  • the capacitance of the corresponding self-capacitance electrode is a fixed value superimposed on the human body capacitance, and the touch sensing chip can determine the touch position by detecting the change of the capacitance value of each capacitor electrode during the touch phase.
  • the touch panel In order to reduce the mutual interference between the display signal and the touch signal, and improve the picture quality and the touch accuracy, it is generally required to drive the touch and display phases in a time-sharing manner.
  • the touch panel During the touch phase, the touch panel generates a driving signal and receives a sensing signal to determine a touch position.
  • the touch panel In the display phase, the touch panel generates a common voltage and connects the common electrode layer located under the via hole to realize the normal display of the liquid crystal display.
  • FIG. 3 is a block diagram showing an In-Cell touch array substrate according to an exemplary embodiment of the present invention.
  • a switching circuit including a group of thin film transistors TFT and a common conductive line TP-SW may be added around the active area AA of the touch panel, and the switch circuit is used to connect the metal connection lines ML and the data lines. With disconnected.
  • the number of thin film transistors TFT may be the same as the number of metal connection lines ML.
  • FIG. 3 a case where the switching circuit includes three thin film transistors TFT is exemplarily shown.
  • one of the source and the drain of each thin film transistor TFT is connected to the corresponding metal connection line ML, and the other of the source and the drain of each thin film transistor is connected to a corresponding one of the data lines.
  • one of the source and the drain of the first thin film transistor TFT1 is electrically connected to the first metal connection line ML(n+1), and the other of the source and the drain of the first thin film transistor TFT1 is electrically connected to First data line DL (n+1).
  • One of the source and the drain of the second thin film transistor TFT2 is electrically connected to the second metal connection line ML(n+2), and the other of the source and the drain of the second thin film transistor TFT2 is electrically connected to the second data Line DL(n+2).
  • One of the source and the drain of the third thin film transistor TFT3 is electrically connected to the third metal connection line ML(n+3).
  • the other of the source and the drain of the third thin film transistor TFT3 is electrically connected to the third data line DL(n+3).
  • the gates of the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may be electrically connected to the common conductive line TP-SW.
  • the switching circuit can be disposed on the upper side or the lower side of the active area AA.
  • the thin film transistor TFT may be an NMOS, a PMOS, a CMOS, a transfer gate, or the like.
  • the common conductive line TP-SW can be taken out by the touch sensing chip IC.
  • the touch sensing chip IC can provide a signal to turn off the thin film transistor TFT, whereby the data line is disconnected from the metal connection line ML.
  • the touch sensing chip IC can provide a signal to turn on the thin film transistor TFT, and thus the data line is connected to the metal connecting line ML, so that the resistance value and the capacitance value of the touch panel in the active area AA are both Significantly reduced, the resistance and capacitive load are reduced, and the working accuracy of the touch panel is improved.
  • a switching circuit including a group of thin film transistors and a common conductive line (for example, a switching circuit composed of a group of thin film transistors and a common conductive line) is added around the effective area of the touch panel.
  • the touch sensing chip provides a signal to the common conductive line to turn on the thin film transistor, thereby electrically connecting the data line and the metal connection line, thereby the touch panel is routed in the effective area.
  • Both the resistance value and the capacitance value are greatly reduced, and the resistance capacitive load is reduced, thereby increasing the operational accuracy of the touch panel.

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Abstract

一种内嵌式触控面板的阵列基板，阵列基板包括：触控电极（200），以阵列的形式设置在触控面板的有效区中；触控感测芯片（IC），设置在触控面板的有效区外；金属连接线（ML），与触控电极（200）异层设置且通过过孔（H）连接到触控电极（200），并且与触控面板的数据线（DL）相互绝缘地叠置，其中，触控电极（200）通过金属连接线（ML）连接到触控感测芯片（IC），在金属连接线（ML）与数据线（DL）之间设置有开关电路，开关电路在触控阶段使金属连接线（ML）与数据线（DL）接通，而在显示阶段使金属连接线（ML）与数据线（DL）断开。触控面板在有效区内走线的电阻电容性负载减小，使得触控面板的工作精度提高。

Description

内嵌式触控面板及其阵列基板 技术领域
本发明涉及一种触控面板，尤其涉及一种内嵌式触控面板及其阵列基板。
背景技术
液晶显示器(Liquid Crystal Display，LCD)是目前使用最广泛的一种平板显示器，已经逐渐成为诸如移动电话、个人数字助理(PDA)、数码相机、桌上型计算机或膝上型计算机等的各种电子设备所使用的具有高分辨率彩色屏幕的显示器。
随着液晶显示技术的发展进步，人们对LCD的显示品质、外观设计、人机界面等提出了更高的要求，触控技术(Touch Technology)因具有操作方便、高度集成等特点而成为技术发展的热点。
触控技术近些年发展迅猛，目前已有多种触控面板投入量产。对于现有的触控面板，根据触控传感器(Touch Sensor)设置位置的不同，可分为触控传感器覆盖于液晶盒上式(On Cell)、触控传感器内嵌在液晶盒内式(In Cell)、以及触控传感器外挂于显示面板式(Out Cell)。其中，In-Cell型触控面板是指将触控功能嵌入到液晶像素中的方法，不仅进一步降低了整机厚度，而且可以和LCD一同制作，没有额外的制作工序，也不影响其在室外等明亮的环境下的可视性。因此，对In-Cell型触控面板的研究日渐盛行。
现有的内嵌式触控面板的一种设计结构是利用一金属连接层来传递触控信号，该金属连接层包括多条彼此平行的金属连接线，用以电连接不同的触控传感器的焊盘电极。为了不影响像素开口率，所述金属连接线一般设置在触控面板的数据线的上方，如此，在金属连接线与数据线之间会存在电阻电容性负载(RC Loading)，该负载会影响金属连接线所传递的触控信号的准确性，导致触控精度下降。
发明内容
本发明的目的在于提供一种能够降低在触控面板的有效区内走线的电阻电容性负载，提高触控面板的触控精度的内嵌式触控面板的阵列基板。
本发明提供了一种内嵌式触控面板的阵列基板，所述阵列基板包括：触控电极，以阵列的形式设置在触控面板的有效区中；触控感测芯片，设置在触控面板的有效区外；金属连接线，与触控电极异层设置且通过过孔连接到触控电极，并且与触控面板的数据线相互绝缘地叠置，其中，触控电极通过金属连接线连接到触控感测芯片，在金属连接线与数据线之间设置有开关电路，开关电路在触控阶段使金属连接线与数据线接通，而在显示阶段使金属连接线与数据线断开。
开关电路可包括薄膜晶体管和公共导电线。
薄膜晶体管的栅极可连接到公共导电线，薄膜晶体管的源极和漏极中的一个可连接到金属连接线，薄膜晶体管的源极和漏极中的另一个可连接到数据线。
公共导电线可由触控感测芯片接出。
薄膜晶体管可以是NMOS、PMOS、CMOS或传输门等。
开关电路可设置在触控面板的有效区的上侧或下侧。
根据本发明的内嵌式触控面板的阵列基板在触控面板的触控阶段通过触控感测芯片提供信号至公共导电线以使薄膜晶体管导通，从而使数据线与金属连接线电连接，由此触控面板在有效区内走线的电阻值和电容值都大幅下降，电阻电容性负载减小，从而可增加触控面板的工作准确度。
附图说明
通过以下结合附图对示例性实施例的描述，本发明的各方面将变得更加容易理解，在附图中：
图1是示出根据现有技术的In-Cell触控阵列基板的示意性剖视图。
图2是示出根据现有技术的自电容In-Cell触控阵列基板的架构示意图。
图3是示出根据本发明的示例性实施例的In-Cell触控阵列基板的架构示意图。
具体实施方式
在下文中，将通过参考附图对示例性实施例进行解释来详细描述本发明构思。然而，本发明构思可以按照多种不同形式具体实施，而不应当解释为限制为本文所阐述的各实施例；相反，提供这些实施例是为了使得本公开是清楚且完整的，并且将向本领域普通技术人员充分地传达本发明构思。在附图中，相同的附图标记表示相同的元件。此外，各个元件和区域是示意性示出的。因而，本发明构思不限于图中所示出的相对尺寸或距离。将要理解的是，尽管在这里会使用术语第一、第二等来描述各个元件和/或部件，但这些元件和/或部件不应当被这些术语限制。这些术语仅仅用于将一个元件和/或部件与另一个元件和/或部件区分开。因此，下面讨论的第一元件或第一部件可以被称为第二元件或第二部件，而没有背离本发明构思的教导。
图1是示出根据现有技术的In-Cell触控阵列基板的示意性剖视图。
参照图1，触控阵列基板100可包括基底110、遮光层115、缓冲层120、半导体元件SE、平坦化层140、公共电极层145、第二层间绝缘层150、金属连接层M3、钝化层155和像素电极层160。
基底110可包括透明基板，优选为玻璃基板。
遮光层115可设置在基底110上以及半导体元件SE下方，用于防止光线进入半导体元件SE可包括的薄膜晶体管的沟道区，从而可以起到降低漏电流、提高薄膜晶体管器件电学性能的作用。遮光层115可为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
缓冲层120可设置在基底110上并且覆盖基底110上的遮光层115。缓冲层120可减少或有效地防止金属原子和/或杂质从基底110向触控阵列基板的在基底110上的其他层的扩散并且可改善基底110的不规则表面的平整度。缓冲层120可为氧化硅(SiOx)层、氮化硅(SiNx)层或者由氧化硅层与氮化硅层 叠加构成的复合层。
半导体元件SE可设置在缓冲层120上。半导体元件SE可包括薄膜晶体管。薄膜晶体管可包括多晶硅层125、源极S、漏极D、栅极G以及设置在它们之间的栅极绝缘层130和第一层间绝缘层135。
多晶硅层125可设置在缓冲层120上，并且包括位于两端的N型重掺杂区N+、位于中间的沟道区CH以及位于N型重掺杂区N+与沟道区CH之间的N型轻掺杂区N-。
栅极绝缘层130可设置在缓冲层120上并且覆盖在缓冲层120上的多晶硅层125。栅极绝缘层130可为氧化硅(SiOx)层、氮化硅(SiNx)层或者由氧化硅层与氮化硅层叠加构成的复合层。
栅极G可设置在栅极绝缘层130上。栅极G可与多晶硅层125的沟道区CH叠置。栅极G可包括金属、合金、导电金属氧化物、透明导电材料等。
第一层间绝缘层135可设置在栅极绝缘层130上并且覆盖在栅极绝缘层130上的栅极G。第一层间绝缘层135可使用无机材料或有机材料来形成。
源极S和漏极D可设置在第一层间绝缘层135上。源极S和漏极D可分别通过第一过孔H1与N型重掺杂区N+相接触。第一过孔H1形成在两端的N型重掺杂区N+上并且穿过第一层间绝缘层135和栅极绝缘层130。源极S和漏极D中的每个可包括金属膜、合金膜、金属氮化物膜、导电金属氧化物膜和/或透明导电膜。
平坦化层140可设置在第一层间绝缘层135上。平坦化层140可完全覆盖源极S和漏极D，并且可具有基本上水平的表面而没有围绕源极S和漏极D的台阶。平坦化层140可包括有机材料或无机材料。
公共电极层145可设置在平坦化层140上。公共电极层145的材料可为透明金属氧化物，所述透明金属氧化物可为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
第二层间绝缘层150可设置在平坦化层140上并且覆盖在平坦化层140上 的公共电极层145。第二层间绝缘层150可为氧化硅(SiOx)层、氮化硅(SiNx)层或者由氧化硅层与氮化硅层叠加构成的复合层。
金属连接层M3可设置在第二层间绝缘层150上并且与半导体元件SE的源极S叠置。金属连接层M3通过第二过孔H2与位于其下方的公共电极层145相接触，第二过孔H2形成在公共电极145上并且穿过第二层间绝缘层150。金属连接层M3可由任何合适的导电材料构成。
钝化层155可设置在第二层间绝缘层150上并且可覆盖在第二层间绝缘层150上的金属连接层M3。钝化层155的材料可为氮化硅或氧化硅。
像素电极层160可设置在钝化层155上。像素电极层160可通过第三过孔H3与半导体元件SE的漏极D相接触。第三过孔H3在半导体元件SE的漏极D上并且穿过平坦化层140、第二层间绝缘层150和钝化层155。像素电极层160的材料可为透明金属氧化物，所述透明金属氧化物可为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
半导体元件SE的源极S连接到数据线，半导体元件SE的栅极G连接到栅极线。显示面板通过栅极线提供的栅极信号和数据线提供的数据电压来驱动。
由于触控面板的金属连接层M3与数据线叠置，因此在金属连接层M3与数据线之间会存在电阻电容性负载(RC Loading)，该负载会影响金属连接层所传递的触控信号的准确性，导致面板的触控精度下降。
上述的内嵌式触控阵列基板是以公共电极层145与金属连接层M3的排布来实现触控功能，触控技术属于自电容式，其中，公共电极层145用作触控面板的自电容电极。
图2是示出根据现有技术的自电容In-Cell触控阵列基板的架构示意图。
如图2所示，自电容In-Cell触控阵列基板包括触控感测芯片IC、连接到触控感测芯片IC的多条平行的金属连接线ML以及多个自电容电极200。其中，触控感测芯片IC设置在触控面板的有效区(Active Area)外。多个自电容电极200以阵列的形式形成在触控面板的有效区中，多条金属连接线ML中的每条 用于电连接触控感测芯片IC和多个自电容电极200中的相应的一个。
自电容电极200可对应于图1中所示的公共电极层145，金属连接线ML可对应于如图1中所示的金属连接层M3。自电容电极200和金属连接线ML为异层设置，且自电容电极200与相应的金属连接线ML通过过孔H电性连接，其中，过孔H可对应于图1中所示的用于电连接金属连接层M3和公共电极层145的第二过孔H2。
可对如图1中所示的位于金属连接层M3下方的用作自电容电极的公共电极层145采取挖空设计，以使得多个自电容电极200如图2所示地被彼此间隔开，从而改善多个自电容电极200之间的串扰。
当人体未触碰屏幕时，各个自电容电极所承受的电容为一固定值。当人体触碰屏幕时，对应的自电容电极所承受的电容为固定值叠加人体电容，触控感测芯片在触控阶段通过检测各自电容电极的电容值变化可以判断出触控位置。
为了降低显示信号和触控信号之间的相互干扰，提高画面品质和触控准确性，一般需要将触控和显示阶段进行分时驱动。在触控阶段，触控面板产生驱动信号并接收感测信号，以确定触控位置。而在显示阶段，触控面板产生公共电压，并通过过孔连接位于下方的公共电极层，以实现液晶显示器的正常显示。
图3是示出根据本发明的示例性实施例的In-Cell触控阵列基板的架构示意图。
为了克服上述缺点，可在触控面板的有效区AA周边增加包括一组薄膜晶体管TFT和一条公共导电线TP-SW的开关电路，该开关电路用于实现金属连接线ML与数据线的接通与断开。
薄膜晶体管TFT的数量可与金属连接线ML的数量相同。作为示例，参照图3，示例性地示出了开关电路包括三个薄膜晶体管TFT的情况。其中，每个薄膜晶体管TFT的源极和漏极中的一个连接到相应的金属连接线ML，每个薄膜晶体管的源极和漏极中的另一个连接到相应的一条数据线。具体地，第一薄膜晶体管TFT1的源极和漏极中的一个电连接到第一金属连接线ML(n+1)，第一薄膜晶体管TFT1的源极和漏极中的另一个电连接到第一数据线DL (n+1)。第二薄膜晶体管TFT2的源极和漏极中的一个电连接到第二金属连接线ML(n+2)，第二薄膜晶体管TFT2的源极和漏极中的另一个电连接到第二数据线DL(n+2)。第三薄膜晶体管TFT3的源极和漏极中的一个电连接到第三金属连接线ML(n+3)。第三薄膜晶体管TFT3的源极和漏极中的另一个电连接到第三数据线DL(n+3)。另外，第一薄膜晶体管TFT1、第二薄膜晶体管TFT2和第三薄膜晶体管TFT3的栅极可电连接到公共导电线TP-SW。
开关电路可设置在有效区AA的上侧或下侧。
薄膜晶体管TFT可以是NMOS、PMOS、CMOS或传输门等。
公共导电线TP-SW可由触控感测芯片IC接出。
在显示阶段，触控感测芯片IC可提供信号使薄膜晶体管TFT截止，由此数据线与金属连接线ML断开。在触控阶段，触控感测芯片IC可提供信号使薄膜晶体管TFT导通，由此数据线与金属连接线ML连接，从而触控面板在有效区AA内走线的电阻值和电容值都大幅降低，电阻电容性负载减小，触控面板的工作精度提高。
根据本发明的示例性实施例，在触控面板的有效区周边增加包括一组薄膜晶体管和一条公共导电线的开关电路(例如，由一组薄膜晶体管和一条公共导电线构成的开关电路)。在触控面板的触控阶段，触控感测芯片提供信号至公共导电线以使薄膜晶体管导通，从而使数据线与金属连接线电连接，由此触控面板在有效区内走线的电阻值和电容值都大幅下降，电阻电容性负载减小，从而可增加触控面板的工作准确度。
虽然参照本发明的示例性实施例具体示出并描述了本发明，但是本领域技术人员应该理解，在不脱离本发明的精神和范围的情况下，可做出形式上和细节上的各种改变。结合一个实施例描述的特征或方面可以适用于其他实施例。

Claims (10)

  1. 一种内嵌式触控面板的阵列基板，其中，所述阵列基板包括：
    触控电极，以阵列的形式设置在触控面板的有效区中；
    触控感测芯片，设置在触控面板的有效区外；
    金属连接线，与触控电极异层设置且通过过孔连接到触控电极，并且与触控面板的数据线相互绝缘地叠置，
    其中，触控电极通过金属连接线连接到触控感测芯片，
    其中，在金属连接线与数据线之间设置有开关电路，开关电路在触控阶段使金属连接线与数据线接通，而在显示阶段使金属连接线与数据线断开。
  2. 如权利要求1所述的内嵌式触控面板的阵列基板，其中，开关电路包括薄膜晶体管和公共导电线。
  3. 如权利要求2所述的内嵌式触控面板的阵列基板，其中，薄膜晶体管的栅极连接到公共导电线，薄膜晶体管的源极和漏极中的一个连接到金属连接线，薄膜晶体管的源极和漏极中的另一个连接到数据线。
  4. 如权利要求3所述的内嵌式触控面板的阵列基板，其中，公共导电线由触控感测芯片接出。
  5. 如权利要求2所述的内嵌式触控面板的阵列基板，其中，薄膜晶体管是NMOS、PMOS、CMOS或传输门。
  6. 如权利要求1所述的内嵌式触控面板的阵列基板，其中，开关电路设置在触控面板的有效区的上侧或下侧。
  7. 一种内嵌式触控面板，包括阵列基板，其中，所述阵列基板包括：
    触控电极，以阵列的形式设置在触控面板的有效区中；
    触控感测芯片，设置在触控面板的有效区外；
    金属连接线，与触控电极异层设置且通过过孔连接到触控电极，并且与触控面板的数据线相互绝缘地叠置，
    其中，触控电极通过金属连接线连接到触控感测芯片，
    其中，在金属连接线与数据线之间设置有开关电路，开关电路在触控阶段使金属连接线与数据线接通，而在显示阶段使金属连接线与数据线断开。
  8. 如权利要求7所述的内嵌式触控面板，其中，开关电路包括薄膜晶体管和公共导电线，薄膜晶体管的栅极连接到公共导电线，薄膜晶体管的源极和漏极中的一个连接到金属连接线，薄膜晶体管的源极和漏极中的另一个连接到数据线。
  9. 如权利要求8所述的内嵌式触控面板，其中，公共导电线由触控感测芯片接出。
  10. 如权利要求7所述的内嵌式触控面板，其中，开关电路设置在触控面板的有效区的上侧或下侧。
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