WO2018119773A1 - 非易失内存访问方法、装置和系统 - Google Patents

非易失内存访问方法、装置和系统 Download PDF

Info

Publication number
WO2018119773A1
WO2018119773A1 PCT/CN2016/112699 CN2016112699W WO2018119773A1 WO 2018119773 A1 WO2018119773 A1 WO 2018119773A1 CN 2016112699 W CN2016112699 W CN 2016112699W WO 2018119773 A1 WO2018119773 A1 WO 2018119773A1
Authority
WO
WIPO (PCT)
Prior art keywords
address information
page table
ait
address
nvm
Prior art date
Application number
PCT/CN2016/112699
Other languages
English (en)
French (fr)
Inventor
肖世海
方磊
朗诺斯弗洛里安
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP16925965.2A priority Critical patent/EP3553665B1/en
Priority to PCT/CN2016/112699 priority patent/WO2018119773A1/zh
Priority to CN201680084386.6A priority patent/CN109219804B/zh
Publication of WO2018119773A1 publication Critical patent/WO2018119773A1/zh
Priority to US16/455,466 priority patent/US10997078B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/651—Multi-level translation tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Definitions

  • Embodiments of the present invention relate to the field of computers, and in particular, to a nonvolatile memory access method, apparatus, and system.
  • DRAM Dynamic Random Access Memory
  • NVM Non-Volatile Memory
  • PCM Phase Change Memory
  • MRAM Magneto-Resistive Random-Access Memory
  • Fe_RAM Ferroelectric Memory
  • flash memory for example, Phase Change Memory (PCM), Magneto-Resistive Random-Access Memory (MRAM), and Ferroelectric Memory ( Ferro electronic RAM, Fe_RAM) and flash memory.
  • PCM Phase Change Memory
  • MRAM Magneto-Resistive Random-Access Memory
  • Fe_RAM Ferroelectric Memory
  • flash memory for example, Phase Change Memory (PCM), Magneto-Resistive Random-Access Memory (MRAM), and Ferroelectric Memory ( Ferro electronic RAM, Fe_RAM) and flash memory.
  • PCM Phase Change Memory
  • MRAM Magneto-Resistive Random-Access Memory
  • Fe_RAM Ferroelectric Memory
  • the present invention discloses a method, device and system for accessing a non-volatile memory (NVM) by pre-preserving an Indirect Address Table (AIT) entry to be accessed.
  • the AIT cache is taken, which reduces the latency of memory access.
  • the present application discloses a method for accessing a non-volatile memory, the method comprising: receiving, by an NVM controller, a first access request from a processor, and determining, according to the first address information carried in the first access request, Whether the first access request is used to access the page table, and if the first access request is used to access the page table, the NVM controller reads the page table entry indicated by the first address information, and records according to the page table entry The recorded second address information is obtained from the AIT, and the AIT entry corresponding to the second address information is cached, and the AIT entry is cached in the AIT cache.
  • the second address information may be a physical page number indicating the physical page that the processor is about to access.
  • the AIT is used to record the mapping relationship between the physical address and the NVM device address. More specifically, the AIT is used to record the mapping relationship between the physical block number and the NVM internal block number.
  • the NVM controller monitors access to the page table. If the AIT entry corresponding to the physical page number of the accessed page table entry does not exist in the AIT cache, the NMV controller prefetches one or more corresponding to the physical page number. AIT entries are cached into the AIT cache. The subsequent NVM can directly obtain the NVM internal block number corresponding to the physical block number to be accessed from the AIT cache.
  • the method further includes: the NVM controller sends the second address information to the processor, and receives a second access request from the processor, where The second access information carries the second address information, and the NVM controller obtains the NVM device address corresponding to the second address information according to the second address information and the AIT entry in the AIT cache, and uses the NVM device address corresponding to the second address information to the NVM. Make an access.
  • the second access request carries the third address information
  • the partial field of the third address information is the second address information
  • the third address information is a physical address to be accessed by the processor
  • the second address information is a physical page number.
  • the NVM device address corresponding to the second address information is an NVM internal block number
  • the NVM controller obtains the NVM internal block number corresponding to the physical page number according to the physical page number and the AIT entry in the AIT cache, and according to the NVM internal block number.
  • a partial field of the third address information accesses the NVM.
  • the method further includes: determining, by the NVM controller, whether the second access request is used to access the page table according to the second address information After the second access request is used to access the page table, the NVM controller obtains the NVM device address corresponding to the second address information, and deletes the AIT entry corresponding to the second address information from the AIT cache.
  • the page table is a multi-level page table, and the access to the page table, after the page table access, will be the final virtual page number and the physical page number.
  • the corresponding relationship is cached in the TLB.
  • the reusability of the previously cached AIT entries is not high.
  • the AIT entries corresponding to the second address information can be deleted from the AIT cache. It should be understood that the deletion here may be to invalidate the page table entry or replace it in the next cache replacement.
  • the method further includes: before the NVM controller determines whether the access request is used to access the page table entry, the method further includes : The NVM controller receives page table address information from the processor. NVM controller based The first address information and the page table address information determine whether the first access request is used to access the page table.
  • the page table address information includes a page table base address and a page table size
  • the NVM controller can determine the address range of the page table according to the page table base address and the page table size, and the NVM controller can determine whether the first address information falls.
  • the address range of the incoming page table is used to determine whether the first access request is used to access the page table.
  • the method further includes: receiving, by the NVM controller, page table invalidation information from the processor, according to the first aspect or the first aspect, The page table invalidation information invalidates the page table address information.
  • the processor After destroying a process, the processor sends a page table invalid message to the NVM controller. After receiving the page table invalid message from the processor, the NVM controller invalidates the page table address information related to the process. Thereby saving storage space on the NVM controller side.
  • the present application provides a readable medium, including execution instructions, when the processor of the memory controller executes an execution instruction, the memory controller performs the first aspect or any possible implementation of the first aspect The method in .
  • the present application provides an NVM storage controller, including: a processor, a memory, and a bus; a memory for storing execution instructions, a processor and a memory connected by a bus, and when the NVM storage controller is running, the processor The execution instructions of the memory storage are executed to cause the NVM storage controller to perform the method of any of the first aspect or the first aspect of the first aspect.
  • the present application provides a non-volatile memory access device, the device includes: a receiving unit, configured to receive a first access request from a processor, where the first access request carries the first address information, determining a unit, configured to determine, according to the first address information, whether the first access request is used to access the page table, and the processing unit, if the first access request is used to access the page table, the processing unit is configured to read the first address information indication a page table entry, and obtaining, according to the second address information recorded in the page table entry, the AIT entry corresponding to the second address information from the indirect address table AIT, and buffering the AIT entry to the AIT A cache, wherein the AIT is used to record a mapping relationship between a physical address and an NVM device address.
  • the device further includes: a sending unit, configured to send the second address information to the processor, where the receiving unit is further configured to receive the second access from the processor a request, wherein the second access request carries the second address information, and the processing unit is further configured to obtain, according to the second address information and the AIT entry in the AIT cache, the NVM device address corresponding to the second address information, and according to the second address information The corresponding NVM device address is accessed to the NVM.
  • a sending unit configured to send the second address information to the processor
  • the receiving unit is further configured to receive the second access from the processor a request, wherein the second access request carries the second address information
  • the processing unit is further configured to obtain, according to the second address information and the AIT entry in the AIT cache, the NVM device address corresponding to the second address information, and according to the second address information The corresponding NVM device address is accessed to the NVM.
  • the determining unit is further configured to determine, according to the second address information, whether the second access request is used to access the page.
  • the table if the second access request is used to access the page table, the processing unit obtains the NVM device address corresponding to the second address information, and is further used to delete the AIT entry from the AIT cache.
  • the receiving unit is further configured to receive page table address information from the processor, where the determining unit is configured to The first address information and the page table address information determine whether the first access request is used to access the page table.
  • the receiving unit is further configured to receive the page table invalid information from the processor, where the processing unit is further configured to: Invalidate page table address information.
  • the fourth aspect is the device implementation manner corresponding to the method of the first aspect, so the description in the first aspect or any possible implementation manner of the first aspect corresponds to the fourth aspect or any possible implementation manner of the fourth aspect, I will not repeat them here.
  • the present application provides a nonvolatile memory access system, including a processor, a nonvolatile memory NVM, and a nonvolatile memory in any of the possible implementations of the fourth or fourth aspect Access the device.
  • the NVM controller monitors the access of the processor to the page table, and after obtaining the access request of the processor to the page table, parses the content of the page table to obtain a physical page number that may be accessed subsequently. And before the processor actually accesses the physical page number, pre-fetch the AIT entry corresponding to the physical page number from the AIT, and cache the prefetched AIT entry to the AIT cache, thereby reducing the subsequent AIT cache. Missing, increasing the speed of NVM data access.
  • FIG. 1 is a schematic diagram showing the logical structure of a system according to an embodiment of the invention.
  • FIG. 2 is an exemplary flow chart of address translation in accordance with an embodiment of the present invention.
  • FIG. 3 is an exemplary flowchart of a nonvolatile memory access method in accordance with an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing the logical structure of a nonvolatile memory access device according to an embodiment of the invention.
  • FIG. 6 is a schematic diagram showing the hardware structure of a nonvolatile memory access device according to an embodiment of the invention.
  • the system application uses the virtual address of the memory.
  • the virtual address needs to be mapped to a physical address. More specifically, the processor needs to convert the virtual page number in the virtual address to a physical page number.
  • the page table stores the physical page number corresponding to the virtual page number, and the processor can index the physical page number corresponding to the virtual page number in the page table according to the virtual address (or a partial field of the virtual address).
  • the page table is generally stored in memory, and a memory access is required for one access to the page table.
  • the processor uses a translation look aside buffer (TLB) to cache the mapping between the virtual page number that is frequently used and the physical page number.
  • TLB translation look aside buffer
  • an access request sent by the processor to the NVM controller carries a physical address to be accessed, and after receiving the access request sent by the processor, the NVM controller receives the access request sent by the processor. It is also necessary to translate the physical address to be accessed into the actual NVM device address and perform memory access based on the NVM device address. More specifically, the NVM controller manages and corresponds to the physical address space and the NVM device address space in units of blocks. The NVM controller needs to convert the physical block number in the physical address into the NVM internal block number.
  • the Indirect Address Table (AIT) stores the correspondence between the physical block number and the NVM internal block number.
  • the NVM controller can index the physical block number in the AIT according to the physical address (or part of the physical address).
  • the internal block number of the NVM For the convenience of description, in the embodiment of the present invention, the mapping relationship between the physical address and the NVM device address may be specifically a mapping relationship between the physical block number and the NVM internal block number.
  • the NVM controller uses an AIT cache to cache mappings of physical addresses that are frequently used to NVM device addresses.
  • the AIT cache hit occurs when the mapping between the physical address required by the NVM controller and the NVM device address exists in the AIT cache; the mapping between the physical address required by the NVM controller and the NVM device address does not exist in the AIT cache.
  • the NVM controller needs to go to the AIT to query the physical address. NVM device address.
  • the NVM controller accesses the AIT to bring a large delay to the memory access.
  • the NVM controller listens to the access event of the processor to the page table. When the processor is to access the page table, the NVM controller determines the physical page number to be accessed according to the page table entry accessed by the processor. If there is no NVM internal block number corresponding to the physical page to be accessed in the AIT cache, the NVM The controller determines an AIT entry corresponding to the physical page number to be accessed, and caches the AIT entry to the AIT cache.
  • the NVM controller determines an AIT entry corresponding to the physical block where the physical page to be accessed is located, and caches the AIT entry to the AIT cache, where the AIT entry records the physical block number and the NVM internal block number. Inter-map relationship. This reduces or avoids subsequent AIT cache misses, which reduces the latency of NVM memory access.
  • a virtual address, a physical address, and an NVM device address are used to describe multiple schemes, but it should be understood that the virtual address may be a partial field of an actual virtual address, and the physical address may be a part of an actual physical address.
  • the NVM device address can also be a partial field of the actual NVM device address.
  • the virtual page number is a partial field of the virtual address
  • the physical page number is a partial field of the physical address
  • the physical block number is also a partial field of the physical address
  • the NVM internal The block number is a partial field of the NVM device address.
  • FIG. 1 is a schematic diagram showing the logical structure of a system 100 according to an embodiment of the present invention.
  • the system 100 includes a processor 102, a cache 104, a page table cache 106, an indirect address table cache 108, and a nonvolatile memory control.
  • the device 110 non-volatile memory 112, indirect address table 114, page table 116 and bus 118.
  • the page table 116 stores the physical page number corresponding to the system virtual page number.
  • the page table cache 106 stores a mapping relationship between the virtual page number frequently used by the system and the physical page number.
  • the page table cache 106 may be configured inside the processor 102 or external to the processor 102 and interconnected with the processor 102 via the bus 118.
  • the indirect address table 114 stores a mapping relationship between the system physical address and the NVM device address.
  • the AIT 114 can be stored in a storage space independent of the non-volatile memory 112, and is opaque to the processor 102.
  • the AIT 114 can be stored in a dynamic random access memory (Dynamic Random Access Memory) mounted on the NVM controller 110. DRAM), but it should be understood that the embodiment of the present invention does not limit the saved form of the AIT 114.
  • the AIT 114 is also directly stored in a separate storage space in the NVM 112.
  • the indirect address table cache 108 stores physical addresses and NVM device addresses frequently used by the system.
  • the mapping between the indirect address table cache 108 is a subset of the data stored in the indirect address table 114.
  • mapping relationship between the physical address stored in the AIT 114 or the AIT cache 108 and the NVM device address is a mapping relationship between the physical block number and the NVM internal block number.
  • Processor 102 may include one or more processor cores for executing computer program instructions of system 100.
  • the processor 102 can be implemented by using a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • a component for performing a specific function for example, the processor 102, may be implemented by configuring a general-purpose component to perform a corresponding function, or may be through a dedicated component that specifically performs a specific function. To achieve this, this application does not limit this.
  • Cache 104 may contain one or more levels of cache, for example, cache 104 may include a level one (L0) cache and a level two (L1) cache.
  • L0 level one
  • L1 level two
  • the non-volatile memory controller 110 is configured to handle access operations to the NVM 112.
  • the memory controller may be implemented by a general-purpose processor, a microprocessor, an application specific integrated circuit, or one or more integrated circuits.
  • the non-volatile memory 112 can be directly interconnected with the non-volatile memory controller 110, as shown in FIG. 1, or directly connected to the bus 110, and interconnected with the non-volatile memory controller 110 via the bus 110. This embodiment of the present invention does not limit this.
  • Non-volatile memory controller 110 such as memory reads, memory writes, and prefetches.
  • the processor 102 runs the memory access instruction, it first queries whether the virtual address to be accessed by the TLB 106 to the memory access instruction corresponds to the physical address. If the mapping between the virtual address and the physical address to be accessed by the memory access instruction is found in the TLB 106, that is, a TLB hit occurs, a memory access request is transmitted, which includes the physical address to be accessed. If a TLB miss occurs, the processor needs to go to the page table 116 to find the physical page number corresponding to the virtual page number to be accessed.
  • the AIT cache 108 maintains a mapping relationship between a portion of the physical address and the NVM device address. After the NVM controller 110 receives the access request from the processor 102, it first searches the AIT cache 108 for the mapping relationship between the physical address to be accessed and the NVM device address. If an AIT cache hit occurs, the NVM controller 110 obtains the The NVM device address accesses the NVM memory 112. If an AIT miss occurs, the NVM controller 110 needs to query the AIT 114 to obtain the physical address to be accessed and the NVM device address. Mapping relationship.
  • the NVM controller 110 after receiving the access request sent by the processor 102, the NVM controller 110 first searches the AIT cache 108 for the NVM internal block number corresponding to the physical block number. If an AIT cache hit occurs, the NVM is based on the NVM. After the internal block number and the partial field of the address information carried by the access request determine the NVM device address, the access request is added to the access queue to the NVM. If the AIT cache miss occurs, the NMV controller 110 needs to go to the AIT table 114 to find the NVM internal block number corresponding to the physical block number, and then determine the NVM device address according to the NVM internal block number and the partial field of the address information carried by the access request. , join the access request to the access queue to the NVM.
  • the NVM controller 110 needs one more access to the AIT table 114, and access to the AIT table 114 is time consuming and affects memory access relative to access to the AIT cache 108. speed.
  • system 100 includes an input/output interface and a communication interface (not shown in FIG. 1).
  • the input/output interface is used to receive input data and information, and output data such as operation results.
  • the communication interface implements communication between system 100 and other devices or communication networks using transceivers such as, but not limited to, transceivers.
  • Bus 118 is used to transfer information between various components of system 100.
  • system 100 shown in FIG. 1 only shows the processor 102, the cache 104, the page table cache 106, the indirect address table cache 108, the nonvolatile memory controller 110, the nonvolatile memory 112, the indirect address table. 114, page table 116 and bus 118, but in a particular implementation, those skilled in the art will appreciate that system 100 also includes other devices necessary to achieve proper operation.
  • system 100 may also include hardware devices that implement other additional functions, depending on the particular needs. Moreover, those skilled in the art will appreciate that system 100 may also only include components necessary to implement embodiments of the present invention without necessarily including all of the devices shown in FIG.
  • FIG. 3 illustrates an NVM access method according to an embodiment of the present invention. As shown in FIG. 3, the method 300 includes:
  • S302 The processor sends a first access request to the NVM controller.
  • the first access request carries the first address information.
  • the first address information is a physical address.
  • the first address information may be a physical address of the memory data to be accessed or a physical address of the page table entry.
  • the processor When the processor generates a Cache miss and needs to access the memory data, the processor needs to convert the virtual address into a physical address before sending the access request to the NVM controller, and the processor looks for the virtual in the TLB.
  • the physical address of the memory data to be accessed is determined based on the physical page number and a partial field of the virtual address (eg, a lower field) as an offset.
  • the processor determines the physical address of the page table entry in which the physical page number is stored according to the partial field of the virtual address of the memory data and the base address of the page table, and sends an access request to the NVM controller to access The request carries the physical address of the page table entry.
  • the processor can obtain the physical page number corresponding to the virtual page number of the memory data to be accessed from the single-level page table by one access request. More specifically, the processor may determine, according to the base address of the page table and a partial field of the virtual address of the memory data (eg, a high-order field, a virtual page number, etc.) as an offset, to determine a page table entry in which the physical page number is saved. The physical address, and the physical page number corresponding to the virtual page number recorded in the page table entry is read according to the physical address of the page table entry.
  • a partial field of the virtual address of the memory data eg, a high-order field, a virtual page number, etc.
  • the physical address of the memory data is determined according to the physical page number and a partial field (for example, a low field) of the virtual address as an offset, and the memory data is accessed according to the physical address of the memory data.
  • a partial field for example, a low field
  • the base address of the page table can be stored in a special register.
  • the base address of the page table can be stored in the control register CR3, and the CR3 contains the physical directory base address of the page directory table, so the register is also called the page directory base address register. (Page-Directory Base address Register, PDBR).
  • PDBR Peage-Directory Base address Register
  • the processor needs to send multiple access requests to the processor according to the number of levels of the page table, so that the physical page number corresponding to the virtual page number of the memory data to be accessed can be obtained.
  • one entry of the primary page table points to a second-level page table, and one entry of the second-level page table records the virtual page number of the memory data. Corresponding physical page number.
  • the processor determines the physical address A according to the base address of the primary page table stored in the CR3 register and the partial field of the virtual address of the memory data as an offset (for example, the high M bit of the virtual address), and according to the determined physical address A
  • the data read at the physical address A is the base address of a secondary page table, and the processor further uses the base address of the secondary page table and the partial field of the virtual address as an offset (for example, in the virtual address N bit), determine the physical address B, and send an access request according to the physical address B.
  • the data read by the physical address B is a page table entry of the secondary page table, and the page table entry records the memory data to be accessed.
  • the physical page number corresponding to the virtual page number.
  • the processor determines the physical address of the memory data to be accessed according to the physical page number and a partial field of the virtual address as an offset (eg, the lower L bits of the virtual address).
  • step S304 After receiving the first access request, the NVM controller determines, according to the first address information, whether the first access request is used to access the page table. If the first access request is not used to access the page table, step S306 is performed. An access request is used to access the page table, and step S308 is performed.
  • the method 300 further includes the NVM controller receiving page table address information from the processor, and the NVM controller can determine, based on the page table address information, whether the received access request is used to access the page table.
  • the page table address information may contain an address stored in a CR3 register or an address of a CR3 register, where the CR3 register is used to store the base address of the page table.
  • a TLB miss must trigger a processor exception.
  • the processor can send the address of the CR3 register of the process that caused the TLB miss or the address stored in the CR3 register to the NVM controller in the exception handler.
  • the NVM controller bases the base address stored in CR3. To track page table access.
  • the processor can also send the address of the CR3 register corresponding to the thread or the address stored in the CR3 register to the NVM controller when a new process is created.
  • the page table address information may also include information on the page table level, the resolution of each level page table, and the size of each page. In this way, the NVM controller can determine whether the access request is access to the page table according to the page table address information. For the multi-level page table, the page table address access can be tracked according to the page table address information until the physical data of the memory data to be accessed is obtained. Page number.
  • the NVM controller can only store a limited number of page table address information.
  • the processor sends more page table address information than the NVM controller can store, it can be replaced by a certain algorithm. For example, it can be based on least recently used (LRU) or least commonly used (Least Frequently Used). , LFU) and other replacement strategies to retain partial page table address information.
  • LRU least recently used
  • LFU least commonly used
  • the NVM controller determines whether the first access request is used to access the page table based on the first address information and the page table address information. Specifically, the NVM controller may determine whether the first access request is used to access the page table by determining whether the first address information falls within a range of the page table address information, if the first address information falls within the range of the page table address information. The first access request is used to access the page table. If the first address information does not fall within the range of the page table address information, the first access request is used to access normal memory data, not for accessing the page table.
  • the NVM controller determines the size of the page table according to the number of page table entries and the size of each page table entry. Then, the address range of the page table is [page table base address, page table base address + page table size), and the NVM controller determines whether the first access request is for access by whether the first address information falls within the address range of the page table. Page table. If the first address information falls within the address range of the page table, the first access request is used to access the page table.
  • the NVM controller may also determine whether the first access request is used to access the page table by using a partial field of the first address information (eg, a high field) and a base address of the page table, if a partial field of the first address information is associated with the NVM controller If the maintained page table base address is the same, it indicates that the first address information falls within the range of the page table address information, indicating that the first access request is used to access the page table.
  • a partial field of the first address information eg, a high field
  • S306 The NVM controller performs a normal access operation on the NVM according to the first access request.
  • the first address information is a physical address of the memory data to be accessed, and the NVM controller performs normal access to the NVM according to the first access request.
  • the NVM controller searches the AIT cache for the NVM device address corresponding to the first address information according to the first address information, and more specifically, the NVM controller searches for the first address information in the AIT cache (for example, the first address
  • the upper field of the information indicates the NVM internal block number corresponding to the physical block number, and accesses the NVM according to the NVM internal block number and the first address information (for example, the lower field of the first address information).
  • the NVM controller obtains the AIT entry corresponding to the second address information from the AIT according to the second address information recorded in the page table entry indicated by the first address information, and caches the AIT entry to the AIT cache.
  • the TLB is deleted by the processor, and the first access request is used to obtain the physical page number corresponding to the virtual page number of the data to be accessed, where the first address information is saved.
  • the physical address of the page table entry for the physical page number.
  • the NVM controller reads the second address information recorded by the page table entry according to the first address information, where the second address information is specifically a physical page number. If there is no AIT entry corresponding to the second address information in the AIT cache, the NVM controller obtains the AIT entry corresponding to the second address information in the AIT, and caches the AIT entry to the AIT cache for subsequent use.
  • the second address information may correspond to one or more AIT entries, and more specifically, the AIT entry corresponding to the second address information is corresponding to one or more physical block numbers distributed by the physical page indicated by the second address information. AIT entry.
  • one physical page The face number can correspond to a physical block number, so that a physical block number can correspond to an AIT entry, and the corresponding NVM internal block number can be directly indexed by using the physical page number.
  • the system can describe the physical page number and the physical block number according to the same field of the physical address, that is, use the same field of the physical address (for example, the high field) to implement indexing of the physical page and the physical block, for example, Assuming that the physical address has 32 bits, and the upper 16 bits are used to indicate the physical page number and the physical block number, the good 16 bits of the physical address can be used as an index of the physical page or as an index of the physical block number.
  • the physical page number can correspond to multiple physical block numbers, so that one physical page can correspond to multiple AIT entries, and multiple AIT entries corresponding to physical page numbers need to be obtained from the AIT.
  • the physical address is 32 bits
  • the upper 16 bits are used to indicate the physical page number
  • the upper 18 bits are used to indicate the physical block number, that is, the high 16 of the physical address is used as the index of the physical page
  • the upper 18 bits are used as the physical block.
  • the index of the number if one physical page corresponds to four physical blocks, you need to obtain four AIT entries corresponding to the physical page number from the AIT.
  • the physical page is smaller than the physical block, multiple physical page numbers may correspond to the same physical block number, and the last few bits of the physical page number may be omitted as an index of the corresponding AIT table.
  • the physical address is 32 bits, wherein the upper 16 bits are used to indicate the physical block number, and the upper 18 bits are used to indicate the physical page number, that is, the upper 16 bits of the physical address is the index of the physical block, and the upper 18 is the index of the physical page. If a physical block corresponds to 4 physical pages, the last two digits of the physical page number are ignored when indexing the AIT table.
  • S310 The NVM controller sends the second address information to the processor.
  • the physical page indicated by the second address information is a physical page to be accessed by the processor, and the NVM controller sends the second address information to the processor.
  • the second address information may be a physical page number of the memory data to be accessed.
  • the second address information may also be the base address of the second level page table.
  • S312 The processor sends a second access request to the NVM controller, where the second access request carries the second address information.
  • the processor receives the second address information (physical page number)
  • the processor also sets the virtual page of the memory data to be accessed. The correspondence between the number and the second address information is stored in the TLB for subsequent use.
  • the processor determines a physical address according to the second address information and a partial field of the virtual address of the to-be-accessed memory data, and carries the physical address in the second access request.
  • the NVM controller determines, according to the second address information of the received second access request and the AIT entry pre-stored in the AIT cache, the NVM device address corresponding to the second address information, and according to the second location The NVM device address corresponding to the address information is accessed to the NVM.
  • the NVM controller has stored the AIT entry corresponding to the second address information in the AIT cache in step S308, after receiving the second access request, the NVM controller can directly search for the second address information in the AIT cache. An AIT entry in which the NVM internal block number to be accessed by the second access request is recorded.
  • the second access request carries the physical address determined by the processor as the base address and the partial field of the to-be-accessed memory data as the offset, and the NVM controller determines the physical location of the physical page indicated by the second address information.
  • the NVM internal block number corresponding to the block number, and the NVM internal address is determined according to the NVM internal block number and a partial field of the physical address as an offset.
  • the second access request can also be used to access the page table, for example, the first access request is used to access the primary page table, the second access request is used to access the secondary page table, and the method 300 is further The method may include: determining, by the NVM controller, whether the second access request is used to access the page table according to the second address information.
  • the NVM controller obtains the NVM device address corresponding to the second address information according to the second address information and the AIT entry corresponding to the second address information stored in the AIT cache, and then the second The AIT entry corresponding to the address information is deleted from the AIT cache.
  • the deleting includes: replacing the AIT entry corresponding to the second address information as an alternative candidate for other AIT entries.
  • the processor stores the correspondence between the virtual page number and the physical page number in the TLB, and the subsequent processor can directly The physical page number corresponding to the virtual page number to be accessed is obtained in the TLB. Therefore, for the access of the page table, the AIT reusability is not high. After the end of the round of access, in order to reduce the pollution to the AIT cache, the AIT entries related to the page table that are not used again can be deleted.
  • the NVM controller can use a dedicated portion of the cache block to cache AIT entries associated with the page table.
  • the method 300 further includes: after destroying a process, the processor sends a page table invalid message to the NVM controller, and the NVM controller receives the page table invalid message from the processor, and the page table address information related to the process invalid.
  • the NVM controller monitors the access of the processor to the page table, and after obtaining the access request of the processor to the page table, parses the content of the page table to obtain a physical page number that may be accessed subsequently. And before the processor actually accesses the physical page number, pre-fetch the AIT entry corresponding to the physical page number from the AIT, and cache the prefetched AIT entry to the AIT cache, thereby reducing the subsequent AIT cache. Missing, increasing the speed of NVM data access.
  • FIG. 5 is a schematic diagram showing the logical structure of a nonvolatile memory access device 500. As shown in FIG. 5, the device 500 includes a receiving unit 502, a determining unit 504, a processing unit 506, and a sending unit 508.
  • the receiving unit 502 is configured to receive a first access request from the processor, where the first access request carries the first address information.
  • the determining unit 504 is configured to determine, according to the first address information, whether the first access request is used to access the page table.
  • the processing unit 506 is configured to obtain the AIT table corresponding to the second address information from the indirect address table AIT according to the second address information recorded in the page table entry indicated by the first address information. And cache the AIT entry to the AIT cache, where the AIT is used to store the mapping relationship between the address information and the NVM device address.
  • the sending unit 508 is configured to send the second address information to the processor.
  • the receiving unit 502 is further configured to receive a second access request from the processor, where the second access request carries the second address information
  • the processing unit 506 is further configured to obtain, according to the second address information and the AIT entry in the AIT cache.
  • the NVM device address corresponding to the second address information and accessing the NVM according to the NVM device address corresponding to the second address information.
  • the determining unit 504 is further configured to determine, according to the second address information, whether the second access request is used to access the page table, and if the second access request is used to access the page table, the processing unit 506 acquires the NVM corresponding to the second address information. After the device address, it is also used to delete the AIT entry from the AIT cache.
  • the receiving unit 502 is further configured to receive page table address information from the processor, and the determining unit 504 is configured to determine, according to the first address information and the page table address information, whether the first access request is used to access the page table.
  • the receiving unit 502 is further configured to receive page table invalidation information from the processor, and the processing unit 506 is further configured to invalidate the page table address information according to the page table invalidation information.
  • the embodiment of the present invention is an apparatus embodiment of the NVM controller, and the feature description of the embodiment of the present invention is applicable to the embodiment of the present invention, and details are not described herein again.
  • FIG. 6 is a schematic diagram showing the hardware structure of a nonvolatile memory access device 600 according to an embodiment of the present invention.
  • the device 600 includes processing logic 602, a memory 604, an input/output interface 606, a communication interface 608, and a bus. 610.
  • the processing logic 602, the memory 604, the input/output interface 606, and the communication interface 608 implement communication connections with each other through the bus 610.
  • the processing logic 602 is a control center of the device 600, and is used to implement the technical solution provided by the embodiment of the present invention.
  • Processing logic 602 can employ a general purpose processor, a microprocessor, an application specific integrated circuit, Or one or more integrated circuits to implement the technical solutions provided by the embodiments of the present invention.
  • processing logic 602 is implemented using a processor
  • the processing logic is used to execute the program code in the memory 604 for implementing the technical solutions provided by the embodiments of the present invention.
  • the memory 604 may be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM).
  • ROM read only memory
  • RAM random access memory
  • the program code for implementing the technical solution provided by the embodiment of the present invention is saved in the memory 604 and executed by the processing logic 602.
  • Memory 604 can be integrated with processing logic 602 or integrated within processing logic 602, or it can be one or more memory units independent of processing logic 602.
  • the program code for processing logic 602 may be stored in an external storage device or memory 604 connected thereto.
  • the memory 604 is a RAM, and program code stored inside the external storage device is copied to the memory 604 for execution by the processing logic 602.
  • a component for performing a specific function for example, processing logic 602 or memory 604, may be implemented by configuring a general-purpose component to perform a corresponding function, or by performing a specific function exclusively.
  • the specific components are implemented, and this application does not limit this.
  • the input/output interface 606 is for receiving input data and information, and outputting data such as operation results.
  • Communication interface 608 implements communication between device 600 and other devices or communication networks using transceivers such as, but not limited to, transceivers.
  • Bus 610 can include a path for communicating information between various components of device 600 (e.g., processing logic 602, memory 604, input/output interface 606, and communication interface 608).
  • the metering device 600 shown in FIG. 6 only shows the processing logic 602, the memory 604, the input/output interface 606, the communication interface 608, and the bus 610, those skilled in the art will appreciate in the specific implementation process.
  • the device 600 also contains other devices necessary to achieve normal operation.
  • device 600 may also include hardware devices that implement other additional functions, depending on the particular needs.
  • device 600 may also only include the components necessary to implement embodiments of the present invention, and does not necessarily include all of the devices shown in FIG.
  • the receiving unit 302 and the transmitting unit 308 shown in FIG. 3 can be implemented by the processing logic 602 shown in FIG. 6 in conjunction with the communication interface 608. More specifically, the program code in the memory 604 can be executed by the processing logic 602 in conjunction with the communication interface 608. to realise.
  • the determining unit 504 and the processing unit 506 shown in FIG. 5 may be processed by the processing logic 602 shown in FIG. Implementation, and more specifically, may be implemented by processing logic 602 executing program code in memory 604.
  • the hardware structure shown in FIG. 6 and the above description are applicable to various non-volatile memory access devices provided by the embodiments of the present invention, and are suitable for performing various non-volatile memory access methods provided by the embodiments of the present invention.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division, and may be implemented in another manner, for example, multiple modules or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, and may be electrical, mechanical or otherwise.
  • the modules described as separate components may or may not be physically separated.
  • the components displayed as modules may or may not be physical modules, that is, may be located in one place, or may be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of hardware plus software function modules.
  • the above-described integrated modules implemented in the form of software function modules can be stored in a computer readable storage medium.
  • the software functional modules described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform some of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a removable hard disk, a read only memory, a random access memory, a magnetic disk, or an optical disk, and the like, which can store program codes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

一种对非易失内存的访问方法，装置和系统。该方法包括：NVM控制器接收来自处理器的第一访问请求，根据第一访问请求中携带的第一地址信息，确定第一访问请求是否用于访问页表，若第一访问请求用于访问页表，NVM控制器读取第一地址信息指示的页表表项，并根据该页表表项中记录的第二地址信息，从AIT中获取第二地址信息对应的AIT表项，并将该AIT表项缓存至AIT缓存。NVM控制器监控处理器对页表的访问，提前从AIT中预取待访问的第二地址信息对应的AIT表项，并将预取的AIT表项缓存至AIT缓存，从而较少了后续的AIT缓存缺失，提高了NVM数据访问的速度。

Description

非易失内存访问方法、装置和系统 技术领域
本发明实施例涉及计算机领域，尤其涉及一种非易失内存访问方法，装置和系统。
背景技术
主机的内存一直是计算机系统的重要的组成部分，是决定系统性能的一个重要的部件。传统的内存一直是用动态随机存取存储器(Dynamic Random Access Memory，DRAM)构成。DRAM组成内存的最大的劣势是不具备非易失性，当主机断电时存放在内存DRAM中的数据将会丢失，造成不可恢复的数据丢失问题。给数据的一致性以及数据的可靠性带来了极大的挑战，为了克服内存的这一缺点，常需采用额外的复杂的数据断电保护措施。除此之外，由于DRAM的物理特性，DRAM每隔一定时间间隔就需要进行数据刷新操作以防止数据的丢失，这就直接导致了DRAM的能耗相当高。
非易失性内存(Non-Volatile Memory，NVM)逐渐成为一个趋势，例如，相变存储器(Phase change memory，PCM)、磁阻式随机存储器(Magneto resistiveRandom-Access Memory，MRAM)、铁电存储器(Ferro electronic RAM，Fe_RAM)和闪存等。NVM具有掉电非易失、存储密度高、不需要频繁的刷新、能耗低等优点。但针对NVM的访问技术还不成熟，当发生页表缓冲(translation look aside buffer，TLB)缺失时，处理器往往需要较长的时间才能实现对NVM的访问。
发明内容
有鉴于此，本发明公开了一种对非易失内存(Non-Volatile Memory，NVM)的访问方法，装置和系统，通过将即将被访问的间接地址表(Address Indirection Table，AIT)表项预取到AIT缓存，减小了内存访问的时延。
第一方面，本申请公开了一种非易失内存的访问方法，该方法包括：NVM控制器接收来自处理器的第一访问请求，并根据第一访问请求中携带的第一地址信息，确定第一访问请求是否用于访问页表，若第一访问请求用于访问页表，NVM控制器读取第一地址信息指示的页表表项，并根据该页表表项中记 录的第二地址信息，从AIT中获取第二地址信息对应的AIT表项，并将该AIT表项缓存至AIT缓存。
第二地址信息可以为物理页面号，用于指示处理器即将访问的物理页面。AIT用于记录物理地址与NVM器件地址的映射关系，更具体的，AIT用于记录物理块号与NVM内部块号之间的映射关系。NVM控制器监控对页表的访问，如果被访问的页表表项记录的物理页面号对应的AIT表项在AIT缓存中不存在，则NMV控制器预取该物理页面号对应的一个或多个AIT表项，并缓存至AIT缓存。后续NVM可以直接从AIT缓存中获取待访问的物理块号对应的NVM内部块号。
根据第一方面，在第一方面第一种可能的实现方式中，该方法还包括：NVM控制器将第二地址信息发送给处理器，并接收来自处理器的第二访问请求，其中，第二访问请求中携带第二地址信息，NVM控制器根据第二地址信息和AIT缓存中的AIT表项获取第二地址信息对应的NVM器件地址，并根据第二地址信息对应的NVM器件地址对NVM进行访问。
更具体的，第二访问请求携带第三地址信息，该第三地址信息的部分字段为第二地址信息，第三地址信息为处理器要访问的物理地址，第二地址信息为物理页面号，第二地址信息对应的NVM器件地址为NVM内部块号，NVM控制器根据该物理页面号和AIT缓存中的AIT表项获取该物理页面号对应的NVM内部块号，并根据该NVM内部块号和第三地址信息的部分字段对NVM进行访问。
根据第一方面第一种可能的实现方式，在第一方面第二种可能的实现方式中，该方法还包括：NVM控制器根据第二地址信息，确定第二访问请求是否用于访问页表，若第二访问请求用于访问页表，NVM控制器获取第二地址信息对应的NVM器件地址之后，将第二地址信息对应的AIT表项从AIT缓存中删除。
如果第一访问请求和第二访问请求均用于访问页表，则说明页表为多级页表，对于页表的访问，因为页表访问后，会将最终的虚拟页面号与物理页面号的对应关系缓存在TLB中，之前缓存的AIT表项的重用性不高，为了节省AIT缓存空间，可以将第二地址信息对应的AIT表项从AIT缓存中删除。应理解，此处的删除可以是将该页表条目无效，或者在下次缓存替换中将其替换出去。
根据第一方面或第一方面以上任一种可能的实现方式，在第一方面第三种可能的实现方式中，NVM控制器确定访问请求是否用于访问页表表项之前，该方法还包括：NVM控制器接收来自处理器的页表地址信息。NVM控制器根据 第一地址信息和页表地址信息确定第一访问请求是否用于访问页表。
具体的，页表地址信息中包含页表基地址和页表大小，NVM控制器可以根据页表基地址和页表大小确定页表的地址范围，NVM控制器可以通过判断第一地址信息是否落入页表的地址范围，来判断第一访问请求是否用于访问页表。
根据第一方面或第一方面以上任一种可能的实现方式，在第一方面第四种可能的实现方式中，该方法还包括：NVM控制器接收来自处理器的页表无效信息，并根据页表无效信息将页表地址信息无效。
处理器在销毁一个进程后，向NVM控制器发送页表无效消息，NVM控制器接收来自处理器的页表无效消息后，将该进程相关的页表地址信息无效。从而节省了NVM控制器侧的存储空间。
第二方面，本申请提供了一种可读介质，包括执行指令，当存储控制器的处理器执行执行指令时，该存储控制器执行第一方面或第一方面的任一种可能的实现方式中的方法。
第二方面，本申请提供了一种NVM存储控制器，包括：处理器、存储器和总线；存储器用于存储执行指令，处理器与存储器通过总线连接，当该NVM存储控制器运行时，处理器执行存储器存储的执行指令，以使该NVM存储控制器执行第一方面或第一方面的任一种可能的实现方式中的方法。
第四方面，本申请提供了一种非易失内存访问装置，该装置包括：接收单元，用于接收来自处理器的第一访问请求，其中，第一访问请求中携带第一地址信息，确定单元，用于根据第一地址信息，确定第一访问请求是否用于访问页表，处理单元，若第一访问请求用于访问页表，处理单元用于读取所述第一地址信息指示的页表表项，并根据所述页表表项中记录的第二地址信息，从间接地址表AIT中获取所述第二地址信息对应的AIT表项，并将所述AIT表项缓存至AIT缓存，其中所述AIT用于记录物理地址与NVM器件地址的映射关系。
根据第四方面，在第四方面第一种可能的实现方式中，该装置还包括发送单元，用于将第二地址信息发送给处理器，接收单元还用于接收来自处理器的第二访问请求，其中，第二访问请求中携带第二地址信息，处理单元还用于根据第二地址信息和AIT缓存中的AIT表项获取第二地址信息对应的NVM器件地址，并根据第二地址信息对应的NVM器件地址对NVM进行访问。
根据四方面第一种可能的实现方式，在第四方面第二种可能的实现方式中，该确定单元还用于根据第二地址信息，确定第二访问请求是否用于访问页 表，若第二访问请求用于访问页表，处理单元获取第二地址信息对应的NVM器件地址之后，还用于将AIT表项从AIT缓存中删除。
根据第四方面或第四方面以上任一种可能的实现方式，在第四方面第三种可能的实现方式中，接收单元还用于接收来自处理器的页表地址信息，确定单元用于根据第一地址信息和页表地址信息确定第一访问请求是否用于访问页表。
根据第四方面第三种可能的实现方式，在第四方面第四种可能的实现方式中，接收单元还用于接收来自处理器的页表无效信息，处理单元还用于根据页表无效信息将页表地址信息无效。
第四方面为第一方面方法对应的装置实现方式，所以第一方面或第一方面任一种可能的实现方式中的描述对应适用于第四方面或第四方面任一种可能的实现方式，在此不再赘述。
第五方面，本申请提供了一种非易失内存访问系统，该系统包括处理器，非易失内存NVM和如第四方面或第四方面任一种可能的实现方式中的非易失内存访问装置。
根据本发明实施例公开的技术方案，NVM控制器监控处理器对页表的访问，当获取到处理器对页表的访问请求后，解析页表内容，获取后续可能被访问的物理页面号，并在处理器真正的访问该物理页面号之前，提前从AIT中预取该物理页面号对应的AIT表项，并将预取的AIT表项缓存至AIT缓存，从而较少了后续的AIT缓存缺失，提高了NVM数据访问的速度。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为依据本发明一实施例的系统逻辑结构示意图；
图2为依据本发明一实施例的地址转换的示范性流程图；
图3为依据本发明一实施例的非易失内存访问方法的示范性流程图；
图4为依据本发明一实施例的的二级页表访问的示范性流程图；
图5为依据本发明一实施例的非易失内存访问装置的逻辑结构示意图；
图6为依据本发明一实施例的非易失内存访问装置的硬件结构示意图。
具体实施方式
下面将结合附图，对本发明实施例进行描述。
在计算机系统中，系统应用使用的是内存的虚拟地址，当处理器访问内存时，需要将虚拟地址映射为物理地址。更具体的，处理器需要将虚拟地址中虚拟页面号转化为物理页面号。页表保存有虚拟页面号对应的物理页面号，处理器可以根据虚拟地址(或虚拟地址的部分字段)在页表中索引到虚拟页面号对应的物理页面号。
页表一般是存储在内存中，对页表的一次访问需要一次内存访问。为了减少访问页表的时延，处理器使用页表缓存(translation look aside buffer，TLB)来缓存一些会被经常使用到的虚拟页面号与物理页面号的映射关系。当处理器需要的虚拟页面号与物理页面号的映射关系在TLB中存在时，即发生了TLB命中；当处理器需要的虚拟页面号与物理页面号的映射关系不在TLB中时，即发生了TLB缺失，处理器需要去页表中索引虚拟页面号对应的物理页面号。
在使用非易失内存(Non-Volatile Memory，NVM)的计算机系统中，处理器发送到NVM控制器的访问请求中携带待访问的物理地址，NVM控制器接收到处理器发送的访问请求后，还需要将待访问的物理地址转化为实际的NVM器件地址，并根据NVM器件地址进行内存访问。更具体的，NVM控制器把物理地址空间和NVM器件地址空间以块为单位进行管理和对应，NVM控制器需要将物理地址中的物理块号转化为NVM内部块号。间接地址表(Address Indirection Table，AIT)存储有物理块号与NVM内部块号之间的对应关系，NVM控制器可以根据物理地址(或物理地址的部分字段)在AIT中索引到物理块号对应的NVM内部块号。为了描述方便，在本发明实施例中，物理地址与NVM器件地址的映射关系可以具体为物理块号与NVM内部块号的映射关系。
同样的，为了减少访问AIT的时延，NVM控制器使用一个AIT缓存来缓存一些会被经常使用到的物理地址与NVM器件地址的映射关系。当NVM控制器需要的物理地址与NVM器件地址的映射关系在AIT缓存中存在时，即发生了AIT缓存命中；当NVM控制器需要的物理地址与NVM器件地址的映射关系在AIT缓存中不存在时，即发生了AIT缓存缺失，NVM控制器需要去AIT中查询物理地址对应的 NVM器件地址。
每次发生AIT缓存缺失，NVM控制器访问AIT都会给内存访问带来较大的时延，为了减少AIT缓存缺失，本发明实施例中，NVM控制器监听处理器对页表的访问事件，当监听到处理器要访问页表时，NVM控制器根据处理器访问的页表表项确定待访问的物理页面号，如果AIT缓存中不存在待访问的物理页面对应的NVM内部块号，则NVM控制器确定待访问的物理页面号对应的AIT表项，并将该AIT表项缓存至AIT缓存。更具体的，NVM控制器确定待访问的物理页面所在的物理块对应的AIT表项，并将该AIT表项缓存至AIT缓存，该AIT表项记录了该物理块号与NVM内部块号之间映射关系。这样就减少或避免了后续的AIT缓存缺失，从而减少了NVM内存访问的时延。
为了描述方便，在本发明实施例中，使用虚拟地址、物理地址和NVM器件地址来多方案进行描述，但应理解，虚拟地址可以是实际虚拟地址的部分字段，物理地址可以实际物理地址的部分字段，NVM器件地址也可以是实际NVM器件地址的部分字段，例如，虚拟页面号是虚拟地址的部分字段，物理页面号是物理地址的部分字段，物理块号也是物理地址的部分字段，NVM内部块号为NVM器件地址的部分字段。
图1为依据本发明一实施例的系统100的逻辑结构示意图，如图1所示，系统100包括：处理器102，缓存104，页表缓存106，间接地址表缓存108，非易失内存控制器110，非易失内存112，间接地址表114，页表116和总线118。
其中，页表116中存储有系统虚拟页面号对应的物理页面号。
页表缓存106中存储有系统经常使用到的虚拟页面号与物理页面号的映射关系。其中，页表缓存106可以配置在处理器102内部，也可以配置在处理器102外部，通过总线118与处理器102互联。
间接地址表114中存储有系统物理地址与NVM器件地址的映射关系。AIT114可以保存在一个独立于非易失内存112的存储空间，对处理器102不透明，例如，AIT 114可以保存在一个挂载在NVM控制器110上的动态随机存取存储器(Dynamic Random Access Memory，DRAM)，但应理解，本发明实施例并不限定AIT 114的保存形式，在某些实现方式中AIT 114也直接保存在NVM 112中一块独立的存储空间。
间接地址表缓存108中存储有系统经常使用到的物理地址与NVM器件地址 之间的映射关系，间接地址表缓存108中存储的数据是间接地址表114中存储的数据的子集。
更具体的，AIT 114或AIT缓存108中存储的物理地址与NVM器件地址的映射关系为物理块号与NVM内部块号的映射关系。
处理器102可以包含一个或者多个处理器核，用于执行系统100的计算机程序指令。处理器102可以采用通用的中央处理器(Central Processing Unit，CPU)，微处理器，应用专用集成电路(Application Specific Integrated Circuit，ASIC)，或者一个或多个集成电路等方式来具体实现。
除非另有说明，在本发明中，一个用于执行特定功能的组件，例如，处理器102，可以通过配置一个通用的组件来执行相应功能来实现，也可以通过一个专门执行特定功能的专用组件来实现，本申请并不对此进行限定。
缓存104可以包含一级或多级缓存，例如缓存104可以包含一个一级(L0)缓存和一个二级(L1)缓存。
非易失内存控制器110用于处理对NVM 112的访问操作，内存控制器可以采用通用的处理器，微处理器，应用专用集成电路，或者一个或多个集成电路等方式来具体实现。
非易失内存112可以直接与非易失内存控制器110互联，如图1所示，也可以直接连接在总线110上，通过总线110与非易失内存控制器110互联。本发明实施例对此并不进行限定。
处理器102生成的涉及到内存访问的请求由非易失内存控制器110来执行，例如内存读，内存写以及预取等。
当处理器102运行内存访问指令时，首先查询TLB 106内部是否包含该内存访问指令要访问的虚拟地址对应到物理地址。如果在TLB 106中找到了该内存访问指令要访问的虚拟地址与物理地址的映射关系，即发生了TLB命中，则发射一个内存访问请求，其中包含待访问的物理地址。如果发生了TLB缺失，则处理器需要去页表116中查找待访问的虚拟页面号对应的物理页面号。
AIT缓存108中维护有部分物理地址与NVM器件地址的映射关系。当NVM控制器110接收到处理器102的访问请求后，首先在AIT缓存108中查找待访问物理地址与NVM器件地址的映射关系，如果发生了AIT缓存命中，则NVM控制器110根据获取到的NVM器件地址访问NVM内存112。如果发生了AIT缺失，则NVM控制器110需要查询AIT 114来获取待访问的物理地址与NVM器件地址 的映射关系。
如图2所示，当NVM控制器110接收到处理器102发送的访问请求后，首先去AIT缓存108中查找物理块号对应的NVM内部块号，如果发生了AIT缓存命中，则NVM根据NVM内部块号和访问请求携带的地址信息的部分字段确定NVM器件地址后，就将访问请求加入到对NVM的访问队列。如果发生了AIT缓存缺失，则NMV控制器110需要去AIT表114中查找物理块号对应的NVM内部块号，然后才能根据NVM内部块号和访问请求携带的地址信息的部分字段确定NVM器件地址，将访问请求加入到对NVM的访问队列。由图2可知，如果发生了AIT缓存缺失，NVM控制器110需要多一个对AIT表114的访问，而对AIT表114的访问相对于对AIT缓存108的访问，十分耗时，会影响内存访问的速度。
可选的，系统100包含输入/输出接口和通信接口(图1未示出)。输入/输出接口用于接收输入的数据和信息，输出操作结果等数据。通信接口使用例如但不限于收发器一类的收发装置，来实现系统100与其他设备或通信网络之间的通信。
总线118用于在系统100的各个部件之间传送信息。
应注意，尽管图1所示的系统100仅仅示出了处理器102，缓存104，页表缓存106，间接地址表缓存108，非易失内存控制器110，非易失内存112，间接地址表114，页表116和总线118，但是在具体实现过程中，本领域的技术人员应当明白，系统100还包含实现正常运行所必须的其他器件。
同时，根据具体需要，本领域的技术人员应当明白，系统100还可包含实现其他附加功能的硬件器件。此外，本领域的技术人员应当明白，系统100也可仅仅包含实现本发明实施例所必须的组件，而不必包含图1中所示的全部器件。
图3为依据本发明一实施例的一种NVM访问方法，如图3所示，方法300包括：
S302：处理器向NVM控制器发送第一访问请求。
其中，第一访问请求中携带第一地址信息。
具体的，第一地址信息为物理地址。该第一地址信息可以为待访问内存数据的物理地址或页表表项的物理地址。
当处理器发生Cache miss，需要访问内存数据时，处理器在向NVM控制器发送访问请求前，需要将虚拟地址转化为物理地址，处理器在TLB中查找虚拟 页面号对应的物理页面号，其中，虚拟页面号可以为内存数据的虚拟地址的部分字段(例如，高位字段)，如果发生了TLB命中，则处理器从TLB中获取内存数据的物理页面号，根据物理页面号和虚拟地址的部分字段(例如，低位字段)作为偏移量，确定要访问的内存数据的物理地址。
当发生TLB缺失时，处理器根据内存数据的虚拟地址的部分字段和页表的基地址，确定保存有该物理页面号的页表表项的物理地址，并向NVM控制器发送访问请求，访问请求中携带该页表表项的物理地址。
对于单级页表，处理器可以通过一次访问请求，从该单级页表中获取待访问的内存数据的虚拟页面号对应的物理页面号。更具体的，处理器可以根据页表的基地址和内存数据的虚拟地址的部分字段(例如，高位字段，虚拟页面号等)作为偏移量，确定保存有该物理页面号的页表表项的物理地址，并根据页表表项的物理地址读取该页表表项中记录的虚拟页面号对应的物理页面号。处理器在根据读取到物理页面号之后，根据物理页面号和虚拟地址的部分字段(例如，低位字段)作为偏移量确定内存数据的物理地址，并根据内存数据的物理地址访问内存数据。
页表的基地址可以存储于一个专门的寄存器，例如，页表的基地址可以存储于控制寄存器CR3，CR3中含有页目录表物理内存基地址，因此该寄存器也被称为页目录基地址寄存器(Page-Directory Base address Register，PDBR)。
对于多级页表，则处理器需要根据页表的级数给处理器发送多次访问请求，才可以获取待访问内存数据的虚拟页面号对应的物理页面号。
例如，当页表分为两级时，如图3所示，一级页表的一个表项指向一个第二级页表，第二级页表的一个表项记录有内存数据的虚拟页面号对应的物理页面号。处理器根据CR3寄存器中存储的一级页表的基地址和内存数据的虚拟地址的部分字段作为偏移量(例如虚拟地址的高M位)，确定物理地址A，并根据确定的物理地址A发送一次访问请求，物理地址A处读出的数据是一个二级页表的基地址，处理器再根据二级页表的基地址和虚拟地址的部分字段作为偏移量(例如虚拟地址的中N位)，确定物理地址B，并根据物理地址B发送一次访问请求，物理地址B读出的数据就是二级页表的一个页表表项，该页表表项中记录有待访问内存数据的虚拟页面号对应的物理页面号。处理器根据该物理页面号和虚拟地址的部分字段作为偏移量(例如虚拟地址的低L位)确定待访问内存数据的物理地址。
S304：NVM控制器接收到第一访问请求后，根据第一地址信息，判断第一访问请求是否用于访问页表，若第一访问请求不是用于访问页表，则执行步骤S306，若第一访问请求用于访问页表，则执行步骤S308。
在步骤S304之前，方法300还包括：NVM控制器接收来自处理器的页表地址信息，NVM控制器可以根据页表地址信息判断接收到的访问请求是否用于访问页表。
页表地址信息可以包含CR3寄存器中存储的地址或CR3寄存器的地址，其中，CR3寄存器用于存储页表的基地址。
TLB缺失必然触发处理器异常，处理器可以在异常处理程序中把引发TLB缺失的进程的CR3寄存器的地址或CR3寄存器中存储的地址发送给NVM控制器，NVM控制器根据CR3中存储的基地址来跟踪页表访问。
处理器也可以在新建一个进程时，就将线程对应的CR3寄存器的地址或CR3寄存器中存储的地址发给NVM控制器。
页表地址信息中还可以包含页表级数，每一级页表的解析方式，每个页的大小等信息。这样NVM控制器可以根据页表地址信息确定访问请求是否是对页表的访问，对于多级页表，还可以根据页表地址信息跟踪各级页表访问，直到取到待访问内存数据的物理页面号。
进一步的，因为应用进程可能很多，NVM控制器只能存储有限个页表地址信息。当处理器发送过来的页表地址信息多于NVM控制器能存储的数量，可以按照一定的算法来替换，例如，可以根据最近最少使用(Least Recently Used，LRU)或最不常用(Least Frequently Used，LFU)等替换策略来保留部分页表地址信息。
NVM控制器根据第一地址信息和页表地址信息判断所述第一访问请求是否用于访问页表。具体的，NVM控制器可以通过判断第一地址信息是否落入页表地址信息的范围，来判断第一访问请求是否用于访问页表，如果第一地址信息落入了页表地址信息的范围，则说明第一访问请求用于访问页表，如果第一地址信息没有落入页表地址信息的范围，则说明第一访问请求用于访问正常的内存数据，不是用于访问页表。
NVM控制器根据页表表项数和每条页表表项的大小确定页表的大小。则页表的地址范围就是[页表基地址，页表基地址+页表大小)，NVM控制器通过第一地址信息是否落在页表的地址范围，判断第一访问请求是否是用于访问页 表。如果第一地址信息落入页表的地址范围，则第一访问请求用于访问页表。
对于多级页表，对于第一级页表，其基地址保存于控制寄存器。对于第二级页表，其基地址保存于第一级页表的某个页表表项，以此类推，直至获取到最后一级页表的基地址，并从最后一级页表中获取待访问内存数据的物理页面号。
NVM控制器还可以通过第一地址信息的部分字段(例如，高位字段)和页表的基地址来判断第一访问请求是否用于访问页表，如果第一地址信息的部分字段与NVM控制器维护的页表基地址相同，则说明第一地址信息落入页表地址信息的范围，说明第一访问请求用于访问页表。
S306：NVM控制器根据第一访问请求对NVM进行正常访问操作。
如果第一访问请求不是用于访问页表，则第一地址信息为待访问内存数据的物理地址，NVM控制器根据第一访问请求对NVM进行正常访问。
具体的，NVM控制器根据第一地址信息，在AIT缓存中查找与第一地址信息对应的NVM器件地址，更具体的，NVM控制器在AIT缓存中查找第一地址信息(例如，第一地址信息的高位字段)指示的物理块号对应的NVM内部块号，并根据NVM内部块号和第一地址信息(例如，第一地址信息的低位字段)对NVM进行访问。
S308：NVM控制器根据第一地址信息指示的页表表项中记录的第二地址信息，从AIT中获取第二地址信息对应的AIT表项，并将该AIT表项缓存至AIT缓存。
如果第一访问请求用于访问页表表项，则说明处理器发生了TLB缺失，第一访问请求用于获取待访问数据的虚拟页面号对应的物理页面号，第一地址信息为保存有该物理页面号的页表表项的物理地址。
NVM控制器根据第一地址信息，读取页表表项记录的第二地址信息，第二地址信息具体为一个物理页面号。如果AIT缓存中没有第二地址信息对应的AIT表项，则NVM控制器在AIT中获取第二地址信息对应的AIT表项，并将AIT表项缓存至AIT缓存，以供后续使用。
其中，第二地址信息可以对应一个或多个AIT表项，更具体的，第二地址信息对应的AIT表项是第二地址信息指示的物理页面所分布的一个或多个物理块号对应的AIT表项。
1、如果物理页面和物理块大小一致(例如，都是4KB)，则一个物理页 面号可以对应一个物理块号，从而一个物理块号可以对应一个AIT表项，可以直接使用物理页面号索引其对应的NVM内部块号。如果二者的大小相同，则系统可以根据物理地址的相同字段描述物理页面号和物理块号，即使用物理地址的相同字段(例如，高位字段)实现对物理页面和物理块的索引，例如，假设物理地址有32位，其中的高16位用于指示物理页面号和物理块号，则物理地址的好16位既可以作为物理页面的索引，又可以作为物理块号的索引。
2、如果物理页面比物理块大，则一个物理页面号可以对应多个物理块号，从而一个物理页面可以对应多个AIT表项，需要从AIT中获取物理页面号对应的多个AIT表项。例如，物理地址为32位，其中的高16位用于指示物理页面号，高18位用于指示物理块号，即物理地址的高16用作物理页面的索引，高18位用作物理块号的索引，一个物理页面对应4个物理块，则需要从AIT中获取物理页面号对应的4个AIT表项。
3、如果物理页面比物理块小，则多个物理页面号可以对应同一个物理块号，可以忽略掉物理页面号最末的几位，作为对应AIT表的索引。例如，物理地址为32位，其中的高16位用于指示物理块号，高18位用于指示物理页面号，即物理地址的高16位为物理块的索引，高18为物理页面的索引，一个物理块对应4个物理页面，则在进行AIT表索引的时候，忽略掉物理页面号的后两位。
S310：NVM控制器将第二地址信息发送给处理器。
第二地址信息指示的物理页面为处理器即将访问的物理页面，NVM控制器获取到第二地址信息后，将其发送给处理器。
第二地址信息可以为待访问内存数据的物理页面号。对于多级页表，第二地址信息也可以为第二级页表的基地址。
S312：处理器向NVM控制器发送第二访问请求，其中第二访问请求中携带该第二地址信息。
因为发生了TLB缺失，处理器接收到第二地址信息(物理页面号)后，如果第二地址信息为待访问内存数据的物理页面号，则处理器还会将待访问的内存数据的虚拟页面号与第二地址信息的对应关系存储于TLB，以供后续使用。
具体的，处理器根据第二地址信息和待访问内存数据的虚拟地址的部分字段作为偏移量，确定一个物理地址，并在第二访问请求中携带该物理地址。
S314：NVM控制器根据接收到的第二访问请求的第二地址信息和AIT缓存中预存的该AIT表项，确定第二地址信息对应的NVM器件地址，并根据第二地 址信息对应的NVM器件地址对NVM进行访问。
因为在步骤S308中，NVM控制器已经将第二地址信息对应的AIT表项存储于AIT缓存，NVM控制器在接收到第二访问请求后，可以直接在AIT缓存中查找到第二地址信息对应的AIT表项，该AIT表项中记录有第二访问请求要访问的NVM内部块号。
第二访问请求中携带的是处理器根据第二地址信息作为基地址和待访问内存数据的部分字段作为偏移量确定的物理地址，NVM控制器确定第二地址信息指示的物理页面所在的物理块号对应的NVM内部块号，并根据NVM内部块号和该物理地址的部分字段作为偏移量确定NVM内部地址。
在多级页表的情况下，第二访问请求也可以用于访问页表，例如，第一访问请求用于访问一级页表，第二访问请求用于访问二级页表，方法300还可以包括：NVM控制器根据第二地址信息判断第二访问请求是否用于访问页表。
若第二访问请求用于访问页表，NVM控制器根据第二地址信息和存储于AIT缓存中的第二地址信息对应的AIT表项获取第二地址信息对应的NVM器件地址之后，将第二地址信息对应的AIT表项从AIT缓存中删除。其中，删除包括：将第二地址信息对应的AIT表项作为其他AIT表项的替换备选。
因为对于多级页表访问，获取待访问内存数据的虚拟页标号对应的物理页标号后，处理器会将该虚拟页面号与物理页面号的对应关系存储于TLB中，后续处理器可以直接在TLB中获取待访问的虚拟页面号对应的物理页面号。所以对于页表的访问，AIT重用性不高，在一轮访问结束后，为了减少对AIT缓存的污染，可以将不会再被用到的页表相关的AIT表项删除。
在另一种实现方式中，为了减少对AIT缓存的污染，NVM控制器可以使用专门的一部分缓存块来缓存与页表相关的AIT表项。
可选的，方法300还包括：处理器在销毁一个进程后，向NVM控制器发送页表无效消息，NVM控制器接收来自处理器的页表无效消息后，将该进程相关的页表地址信息无效。
根据本发明实施例公开的技术方案，NVM控制器监控处理器对页表的访问，当获取到处理器对页表的访问请求后，解析页表内容，获取后续可能被访问的物理页面号，并在处理器真正的访问该物理页面号之前，提前从AIT中预取该物理页面号对应的AIT表项，并将预取的AIT表项缓存至AIT缓存，从而较少了后续的AIT缓存缺失，提高了NVM数据访问的速度。
图5为依据本发明一实施例的非易失内存访问装置500的逻辑结构示意图，如图5所示，装置500包括：接收单元502，确定单元504，处理单元506和发送单元508，其中，
接收单元502，用于接收来自处理器的第一访问请求，其中，第一访问请求中携带第一地址信息。
确定单元504，用于根据第一地址信息，确定第一访问请求是否用于访问页表。
若第一访问请求用于访问页表，处理单元506用于根据第一地址信息指示的页表表项中记录的第二地址信息，从间接地址表AIT中获取第二地址信息对应的AIT表项，并将AIT表项缓存至AIT缓存，其中AIT用于存储地址信息与NVM器件地址的映射关系。
发送单元508，用于将第二地址信息发送给处理器。接收单元502还用于接收来自处理器的第二访问请求，其中，第二访问请求中携带第二地址信息，处理单元506还用于根据第二地址信息和AIT缓存中的AIT表项获取第二地址信息对应的NVM器件地址，并根据第二地址信息对应的NVM器件地址对NVM进行访问。
可选的，确定单元504还用于根据第二地址信息，确定第二访问请求是否用于访问页表，若第二访问请求用于访问页表，处理单元506获取第二地址信息对应的NVM器件地址之后，还用于将AIT表项从AIT缓存中删除。
接收单元502还用于接收来自处理器的页表地址信息，确定单元504用于根据第一地址信息和页表地址信息确定第一访问请求是否用于访问页表。
可选的，接收单元502还用于接收来自处理器的页表无效信息，处理单元506还用于根据页表无效信息将页表地址信息无效。
本发明实施例是NVM控制器的装置实施例，图1-图4实施例部分的特征描述，适用于本发明实施例，在此不再赘述。
图6为依据本发明一实施例的的非易失内存访问装置600的硬件结构示意图，如图6所示，装置600包括处理逻辑602、存储器604、输入/输出接口606、通信接口608和总线610。其中，处理逻辑602、存储器604、输入/输出接口606和通信接口608通过总线610实现彼此之间的通信连接。
处理逻辑602是装置600的控制中心，用于实现本发明实施例所提供的技术方案。处理逻辑602可以采用通用处理器，微处理器，应用专用集成电路， 或者一个或多个集成电路，以实现本发明实施例所提供的技术方案。
更具体的，如果处理逻辑602使用处理器来实现，处理逻辑用于执行存储器604中的程序代码，用于实现本发明实施例所提供的技术方案。
存储器604可以是只读存储器(Read Only Memory，ROM)，静态存储设备，动态存储设备或者随机存取存储器(Random Access Memory，RAM)。在通过软件或者固件来实现本发明实施例提供的技术方案时，用于实现本发明实施例提供的技术方案的程序代码保存在存储器604中，并由处理逻辑602来执行。存储器604可以与处理逻辑602集成在一起或集成在处理逻辑602的内部，也可以是独立于处理逻辑602的一个或多个存储单元。
供处理逻辑602执行的程序代码可以存储在与其连接的外部存储设备中或存储器604中。可选的，存储器604为RAM，存储在外部存储设备内部的程序代码被拷贝到存储器604中，以供处理逻辑602执行。
除非另有说明，在本发明中，一个用于执行特定功能的组件，例如，处理逻辑602或存储器604，可以通过配置一个通用的组件来执行相应功能来实现，也可以通过一个专门执行特定功能的专用组件来实现，本申请并不对此进行限定。
输入/输出接口606用于接收输入的数据和信息，输出操作结果等数据。
通信接口608使用例如但不限于收发器一类的收发装置，来实现装置600与其他设备或通信网络之间的通信。
总线610可包括一通路，在装置600各个部件(例如处理逻辑602、存储器604、输入/输出接口606和通信接口608)之间传送信息。
应注意，尽管图6所示的计装置600仅仅示出了处理逻辑602、存储器604、输入/输出接口606、通信接口608以及总线610，但是在具体实现过程中，本领域的技术人员应当明白，装置600还包含实现正常运行所必须的其他器件。同时，根据具体需要，本领域的技术人员应当明白，装置600还可包含实现其他附加功能的硬件器件。此外，本领域的技术人员应当明白，装置600也可仅仅包含实现本发明实施例所必须的器件，而不必包含图6中所示的全部器件。
图3所示的接收单元302和发送单元308可以由图6所示的处理逻辑602结合通信接口608来实现，更具体的，可以由处理逻辑602执行存储器604中的程序代码，结合通信接口608来实现。
图5所示的确定单元504和处理单元506可以由图6所示的处理逻辑602 来实现，更具体的，可以由处理逻辑602执行存储器604中的程序代码来实现。
图6所示的硬件结构以及上述描述适用于本发明实施例所提供的各种非易失内存访问装置，适用于执行本发明实施例所提供的各种非易失内存访问方法。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，设备和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能模块的形式实现。
上述以软件功能模块的形式实现的集成的模块，可以存储在一个计算机可读取存储介质中。上述软件功能模块存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的部分步骤。而前述的存储介质包括：移动硬盘、只读存储器、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的保护范围。

Claims (13)

  1. 一种非易失内存访问方法，其特征在于，所述方法包括：
    非易失内存NVM控制器接收来自处理器的第一访问请求，其中，所述第一访问请求中携带第一地址信息；
    所述NVM控制器根据所述第一地址信息，确定所述第一访问请求是否用于访问页表；
    若所述第一访问请求用于访问页表，所述NVM控制器读取所述第一地址信息指示的页表表项，并根据所述页表表项中记录的第二地址信息，从间接地址表AIT中获取所述第二地址信息对应的AIT表项，并将所述AIT表项缓存至AIT缓存，其中所述AIT用于记录物理地址与NVM器件地址的映射关系。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    所述NVM控制器将所述第二地址信息发送给所述处理器；
    所述NVM控制器接收来自处理器的第二访问请求，其中，所述第二访问请求中携带所述第二地址信息；
    所述NVM控制器根据所述第二地址信息和所述AIT缓存中的所述AIT表项获取所述第二地址信息对应的NVM器件地址，并根据所述第二地址信息对应的NVM器件地址对所述NVM进行访问。
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    所述NVM控制器根据所述第二地址信息，确定所述第二访问请求是否用于访问页表；
    若所述第二访问请求用于访问页表，所述NVM控制器获取所述第二地址信息对应的NVM器件地址之后，将所述AIT表项从所述AIT缓存中删除。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述NVM控制器确定所述第一访问请求是否用于访问页表表项之前，所述方法还包括：
    所述NVM控制器接收来自所述处理器的页表地址信息；
    所述NVM控制器根据所述第一地址信息，确定所述第一访问请求是否用于访问页表表项包括：
    所述NVM控制器根据所述第一地址信息和所述页表地址信息确定所述第一访问请求是否用于访问页表。
  5. 根据权利要求4所述的方法，其特征在于，所述NVM控制器接收来自 所述处理器的页表指示信息之后，所述方法还包括：
    所述NVM控制器接收来自所述处理器的页表无效信息；
    所述NVM控制器根据所述页表无效信息将所述页表地址信息无效。
  6. 一种非易失内存访问装置，其特征在于，所述装置包括：
    接收单元，用于接收来自处理器的第一访问请求，其中，所述第一访问请求中携带第一地址信息；
    确定单元，用于根据所述第一地址信息，确定所述第一访问请求是否用于访问页表；
    处理单元，若所述第一访问请求用于访问页表，所述处理单元用于读取所述第一地址信息指示的页表表项，并根据所述页表表项中记录的第二地址信息，从间接地址表AIT中获取所述第二地址信息对应的AIT表项，并将所述AIT表项缓存至AIT缓存，其中所述AIT用于记录物理地址与NVM器件地址的映射关系。
  7. 根据权利要求6所述的装置，其特征在于，所述装置还包括发送单元，用于将所述第二地址信息发送给所述处理器；
    所述接收单元还用于接收来自处理器的第二访问请求，其中，所述第二访问请求中携带所述第二地址信息；
    所述处理单元还用于根据所述第二地址信息和所述AIT缓存中的所述AIT表项获取所述第二地址信息对应的NVM器件地址，并根据所述第二地址信息对应的NVM器件地址对所述NVM进行访问。
  8. 根据权利要求7所述的装置，其特征在于，所述确定单元还用于根据所述第二地址信息，确定所述第二访问请求是否用于访问页表；
    若所述第二访问请求用于访问页表，所述处理单元获取所述第二地址信息对应的NVM器件地址之后，还用于将所述AIT表项从所述AIT缓存中删除。
  9. 根据权利要求6-8任一项所述的装置，其特征在于，所述接收单元还用于接收来自所述处理器的页表地址信息；
    所述确定单元用于根据所述第一地址信息和所述页表地址信息确定所述第一访问请求是否用于访问页表。
  10. 根据权利要求9所述的装置，其特征在于，所述接收单元还用于接收来自所述处理器的页表无效信息；
    所述处理单元还用于根据所述页表无效信息将所述页表地址信息无效。
  11. 一种非易失内存访问系统，其特征在于，所述系统包括处理器，非易失内存NVM和如权利6-10任一项所述的非易失内存访问装置。
  12. 一种可读介质，其特征在于，包括执行指令，当内存控制器的处理器执行所述执行指令时，所述内存控制器执行权利要求1-5任一项所述的方法。
  13. 一种内存控制器，其特征在于，包括：处理器、存储器和总线；
    所述存储器用于存储执行指令，所述处理器与所述存储器通过所述总线连接，当所述内存控制器运行时，所述处理器执行所述存储器存储的所述执行指令，以使所述内存控制器执行权利要求1-5任一项所述的方法。
    。
PCT/CN2016/112699 2016-12-28 2016-12-28 非易失内存访问方法、装置和系统 WO2018119773A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP16925965.2A EP3553665B1 (en) 2016-12-28 2016-12-28 Non-volatile memory access method, device, and system
PCT/CN2016/112699 WO2018119773A1 (zh) 2016-12-28 2016-12-28 非易失内存访问方法、装置和系统
CN201680084386.6A CN109219804B (zh) 2016-12-28 2016-12-28 非易失内存访问方法、装置和系统
US16/455,466 US10997078B2 (en) 2016-12-28 2019-06-27 Method, apparatus, and non-transitory readable medium for accessing non-volatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/112699 WO2018119773A1 (zh) 2016-12-28 2016-12-28 非易失内存访问方法、装置和系统

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/455,466 Continuation US10997078B2 (en) 2016-12-28 2019-06-27 Method, apparatus, and non-transitory readable medium for accessing non-volatile memory

Publications (1)

Publication Number Publication Date
WO2018119773A1 true WO2018119773A1 (zh) 2018-07-05

Family

ID=62710808

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/112699 WO2018119773A1 (zh) 2016-12-28 2016-12-28 非易失内存访问方法、装置和系统

Country Status (4)

Country Link
US (1) US10997078B2 (zh)
EP (1) EP3553665B1 (zh)
CN (1) CN109219804B (zh)
WO (1) WO2018119773A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113703660B (zh) * 2020-05-22 2024-03-19 超聚变数字技术有限公司 数据预取方法和数据预取装置
KR20220032808A (ko) 2020-09-08 2022-03-15 삼성전자주식회사 프로세싱-인-메모리, 메모리 액세스 방법 및 메모리 액세스 장치
KR20220049396A (ko) 2020-10-14 2022-04-21 삼성전자주식회사 간접 어드레싱을 위한 시스템, 장치 및 방법
CN114356793B (zh) * 2021-11-25 2024-02-27 苏州浪潮智能科技有限公司 数据处理方法、装置、电子设备及存储介质
CN114610655B (zh) * 2022-05-10 2022-08-05 沐曦集成电路(上海)有限公司 连续数据访问处理装置和芯片
CN114996024A (zh) * 2022-07-29 2022-09-02 阿里巴巴（中国）有限公司 内存带宽监测方法、服务器和计算机可读存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130318288A1 (en) * 2011-12-20 2013-11-28 Jawad B. Khan Method and system for data de-duplication
CN105354152A (zh) * 2014-08-19 2016-02-24 华为技术有限公司 非易失性存储器及磨损均衡方法
CN105786722A (zh) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 基于异构混合内存的nvm内存擦写控制方法和系统
CN105786721A (zh) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 一种内存地址映射管理方法及处理器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1283222C (en) * 1989-09-22 1991-04-16 Howard Gene Sachs Microprocessor having separate instruction and data interfaces
KR101466585B1 (ko) * 2008-07-10 2014-11-28 삼성전자주식회사 메모리 장치 및 메모리 장치의 관리 방법
JP5605238B2 (ja) * 2011-01-25 2014-10-15 ソニー株式会社 メモリシステムおよびその動作方法
US9298606B2 (en) * 2011-09-30 2016-03-29 Intel Corporation Statistical wear leveling for non-volatile system memory
GB2514023B (en) * 2011-12-21 2019-07-03 Intel Corp System and method for intelligently flushing data from a processor into a memory subsystem
US9262336B2 (en) 2011-12-23 2016-02-16 Intel Corporation Page miss handler including wear leveling logic
US10380030B2 (en) * 2012-12-05 2019-08-13 Arm Limited Caching of virtual to physical address translations
CN103164343B (zh) * 2013-02-27 2015-12-09 山东大学 基于相变存储器的分页、ecc校验及多位预取方法及其结构
CN106462504B (zh) * 2013-10-21 2023-09-01 Flc环球有限公司 最终级高速缓存系统和对应的方法
CN103810112B (zh) * 2014-01-28 2016-08-17 华中科技大学 一种非易失性内存系统及其管理方法
KR20150139718A (ko) * 2014-06-03 2015-12-14 에스케이하이닉스 주식회사 불휘발성 메모리를 제어하는 컨트롤러 및 그것을 포함하는 반도체 장치
CN105830059B (zh) * 2014-11-28 2019-09-27 华为技术有限公司 文件访问方法、装置及存储设备
CN105786717B (zh) * 2016-03-22 2018-11-16 华中科技大学 软硬件协同管理的dram-nvm层次化异构内存访问方法及系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130318288A1 (en) * 2011-12-20 2013-11-28 Jawad B. Khan Method and system for data de-duplication
CN105354152A (zh) * 2014-08-19 2016-02-24 华为技术有限公司 非易失性存储器及磨损均衡方法
CN105786722A (zh) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 基于异构混合内存的nvm内存擦写控制方法和系统
CN105786721A (zh) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 一种内存地址映射管理方法及处理器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3553665A4 *

Also Published As

Publication number Publication date
EP3553665A1 (en) 2019-10-16
CN109219804A (zh) 2019-01-15
CN109219804B (zh) 2023-12-29
EP3553665A4 (en) 2020-01-29
US10997078B2 (en) 2021-05-04
US20190324914A1 (en) 2019-10-24
EP3553665B1 (en) 2024-05-15

Similar Documents

Publication Publication Date Title
WO2018119773A1 (zh) 非易失内存访问方法、装置和系统
CN108804350B (zh) 一种内存访问方法及计算机系统
KR102448124B1 (ko) 가상 주소들을 사용하여 액세스된 캐시
KR101009220B1 (ko) 캐시된 메모리 데이터를 가진 메모리 속성 표시자의 캐시
US8037281B2 (en) Miss-under-miss processing and cache flushing
US6782453B2 (en) Storing data in memory
CN109582214B (zh) 数据访问方法以及计算机系统
WO2013163956A1 (zh) 用于处理器的动态组相联高速缓存装置及其访问方法
CN112631961B (zh) 一种内存管理单元、地址转译方法以及处理器
US10078588B2 (en) Using leases for entries in a translation lookaside buffer
CN107870867B (zh) 32位cpu访问大于4gb内存空间的方法与装置
TW201617886A (zh) 指令快取記憶體轉譯管理
WO2019128200A1 (zh) 大容量存储设备的地址转换方法与装置
KR20180008507A (ko) 캐시 태그 압축을 위한 방법 및 장치
CN111858404A (zh) 缓存数据定位系统
CN114063934B (zh) 数据更新装置、方法及电子设备
JP5976225B2 (ja) スティッキー抜去エンジンを伴うシステムキャッシュ
CN111352865B (zh) 存储控制器的写缓存
WO2022222377A1 (zh) 一种内存控制器、数据读取方法以及内存系统
WO2017000124A1 (zh) 目录中表项合并的方法以及设备
CN107870870B (zh) 访问超过地址总线宽度的内存空间
WO2023217255A1 (zh) 数据处理方法、装置、处理器及计算机系统
US11397691B2 (en) Latency hiding for caches
CN111198827B (zh) 页表预取方法及装置
WO2023064609A1 (en) Translation tagging for address translation caching

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16925965

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2016925965

Country of ref document: EP

Effective date: 20190709