WO2018119649A1

WO2018119649A1 - Array substrate and method for preparing array substrate

Info

Publication number: WO2018119649A1
Application number: PCT/CN2016/112343
Authority: WO
Inventors: 尚琼
Original assignee: 深圳市柔宇科技有限公司
Priority date: 2016-12-27
Filing date: 2016-12-27
Publication date: 2018-07-05
Also published as: CN108064418A

Abstract

A method for preparing an array substrate comprises: providing a substrate (101); forming a first metal layer on the surface of the substrate (101), and patterning the first metal layer, so as to form a gate (102) and a first electrode (103), the gate (102) and the first electrode (103) being disposed at an interval; forming a first insulation layer (104) covering the gate (102) and the first electrode (103); forming, on the first insulation layer (104), an active layer (105) disposed corresponding to the gate (102), and annealing the active layer (105); forming a second insulation layer (106) covering the active layer (105); forming a first through hole (1041) corresponding to the first electrode (103), so that a part of the first electrode (103) is exposed through the first through hole (1041), and forming a second through hole (1061) and a third through hole (1062) that are formed at an interval and that corresponds to the active layer (105), so that a part of the active layer (105) is exposed through the second through hole (1061) and the third through hole (1062); and forming a second electrode (107) connected to the first electrode (103) through the first through hole (1041), a source (108) connected to the active layer (105) through the second through hole (1061) and a drain (109) connected to the active layer (105) through the third through hole (1062), the second electrode (107), the source (108) and the drain (109) being disposed at intervals, and the second electrode (107) and the first electrode (103) forming an electrode plate of a capacitor.

Description

Array substrate and preparation method of array substrate

Technical field

The present invention relates to the field of display, and in particular, to a method for preparing an array substrate and an array substrate.

Background technique

Among display devices, Thin Film Transistor display has a dominant position in the current flat panel display device market due to its small size, low power consumption, relatively low manufacturing cost, and low radiation. The array substrate is one of the important components of a thin film transistor display device. A liquid crystal molecular layer is disposed between the array substrate and the color filter substrate, and by applying a voltage to the common electrode and the pixel electrode disposed on the array substrate, the alignment of the liquid crystal molecules can be changed, thereby controlling the transmittance of the light, on each pixel. Different gray voltages can be displayed by setting different voltages and matching the uniform backlight. The combination of different light intensities formed by red, green and blue color resistance on the color filter substrate can show specific Color picture.

The array substrate includes a Thin Film Transistor (TFT) and a capacitor (such as a storage capacitor, etc.), each of which includes a gate, a gate insulating layer, an active layer, a passivation layer, and a source and a drain. Wait. At present, when preparing an array substrate, the array substrate usually prepared has poor performance, for example, when preparing a capacitor, covering an electrode formed at the same time as the gate of the thin film transistor (for convenience of description, referred to as the first electrode) A through hole is formed on the insulating layer, and the through hole is used to expose part of the first electrode. Then, an active layer is formed on the gate insulating layer, and when the active layer is annealed, the capacitor is easily exposed. The first electrode is oxidized, thereby affecting the performance of the capacitor, thereby causing degradation of the performance of the array substrate.

Summary of the invention

The present invention provides a method for fabricating an array substrate, the array substrate comprising a thin film transistor and a capacitor, wherein the method for preparing the array substrate comprises:

101, providing a substrate;

102, forming a first metal layer on a surface of the substrate, and patterning the first metal layer to form a gate and a first electrode, wherein the gate and the first electrode are spaced apart ;

103, forming a first insulating layer covering the gate and the first electrode;

104, forming an active layer corresponding to the gate on the first insulating layer, and annealing the active layer;

105, forming a second insulating layer covering the active layer;

106. The first through hole is opened corresponding to the first electrode, so that a part of the first electrode is exposed through the first through hole, and the second through hole and the third through hole are disposed corresponding to the active layer, so that Part of the active layer is exposed through the second through hole and the third through hole respectively; and

107, forming a second electrode connected to the first electrode through the first through hole, a source connected to the active layer through the second through hole, and passing through the third through hole and the The drain connected to the active layer, the second electrode, the source and the drain are spaced apart, wherein the second electrode and the first electrode constitute one electrode plate of the capacitor.

Compared with the prior art, the method for fabricating the array substrate of the present invention first forms an active layer corresponding to the gate on the first insulating layer, and anneates the active layer, and then corresponds to the The first electrode defines a first through hole, so that a part of the first electrode is exposed through the first through hole, thereby overcoming the formation of the active layer after forming the through hole exposing the first electrode in the prior art. When the active layer is annealed, the technical problem of the oxidation of the exposed first electrode is caused. Therefore, the performance of the array substrate prepared by the method for preparing the array substrate of the present invention is high.

The present invention also provides a method for fabricating an array substrate, the array substrate comprising a thin film transistor and a capacitor, wherein the method for preparing the array substrate comprises:

201, providing a substrate;

202, forming a first metal layer on a surface of the substrate, and patterning the first metal layer to form a gate and a first electrode, wherein the gate and the first electrode are spaced apart ;

203, forming a first insulating layer covering the gate and the first electrode;

204, forming an active layer corresponding to the gate on the first insulating layer, and annealing the active layer;

205, forming a second insulating layer covering the active layer;

206, on the first insulating layer and the second insulating layer respectively corresponding to the first electrode to open a first sub-perforation and a second sub-perforation, the first sub-perforation and the second The through holes communicate to form the first through holes such that a portion of the first electrodes are exposed through the first through holes;

207, forming an organic material layer covering the second insulating layer, and opening a first organic material through hole corresponding to the first electrode on the organic material layer, the first organic material through hole and the first a through hole is communicated, and a second organic material through hole and a third organic material through hole are formed on the organic material layer corresponding to the active layer;

208. A second through hole is formed in the second insulating layer corresponding to the second organic material through hole, so that a part of the active layer is exposed through the second through hole and the second organic material through hole. And a third through hole is formed in the second insulating layer corresponding to the third organic material through hole, so that a part of the active layer is exposed through the third through hole and the third organic material through hole;

209, forming a second electrode connected to the first electrode through the first through hole, a source connected to the active layer through the second through hole, and passing through the third through hole and the The drain connected to the active layer, the second electrode, the source and the drain are spaced apart, wherein the second electrode and the first electrode constitute one electrode plate of the capacitor.

Compared with the prior art, the method for fabricating the array substrate of the present invention first forms an active layer corresponding to the gate on the first insulating layer, and anneates the active layer, and then A first sub-perforation and a second sub-perforation are respectively formed on the first insulating layer and the second insulating layer corresponding to the first electrode, so that a part of the first electrode is exposed through the first through hole, so The technical problem of oxidizing the exposed first electrode caused by forming the through hole which exposes the first electrode and then forming the active layer and annealing the active layer in the prior art is overcome. The array substrate prepared by the method for preparing an array substrate of the present invention has high performance. Further, since the organic material layer is covered on the second insulating layer, the stress of the organic material layer is relatively small, and the organic material layer is not likely to be cracked when the prepared array substrate is bent, thereby functioning in the array substrate. The protection of other layers further enhances the performance of the prepared array substrate.

The present invention also provides an array substrate, the array substrate comprising a thin film transistor and a capacitor, wherein the array substrate comprises:

Substrate

a gate and a first electrode disposed adjacent to the same surface of the substrate, wherein the gate and the first electrode are spaced apart;

Covering the gate and the first insulating layer of the first electrode;

An active layer disposed on a surface of the first insulating layer away from the gate;

Covering the active layer and the second insulating layer of the first insulating layer;

An organic material layer covering the second insulating layer;

a first through hole corresponding to the first electrode is disposed on the first insulating layer, and a second partial through hole corresponding to the first electrode is disposed on the second insulating layer, the second through hole Forming a first through hole in communication with the first through hole, and providing a second through hole and a third through hole disposed on both ends of the active layer on the second insulating layer, the organic material layer Providing a first organic material through hole, a second organic material through hole and a third organic material through hole, wherein the first organic material through hole communicates with the first through hole, and the second organic material through hole and the The second through hole is in communication, and the third organic material through hole is in communication with the third through hole;

a second electrode disposed on the organic material layer and connected to the first electrode through the first organic material through hole and the first through hole;

a source disposed on the organic material layer and connected to one end of the active layer through the second organic material via and the second via; and

a drain disposed on the organic material layer and connected to the other end of the active layer through the third organic material via and the third via, and the drain, the source, and The second electrodes are spaced apart, wherein the second electrode and the first electrode constitute one electrode plate of the capacitor.

Compared with the prior art, the second insulating layer of the array substrate of the present invention is covered with an organic material layer, and the stress of the organic material layer is relatively small, and the organic material layer is not prone to crack when the prepared array substrate is bent. Thereby protecting the other film layers in the array substrate, thereby improving the performance of the array substrate.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a flow chart of a method of fabricating an array substrate according to a first preferred embodiment of the present invention.

2 is a flow chart of a method of fabricating an array substrate according to a first embodiment of the first preferred embodiment of the present invention.

3 to FIG. 11 are cross-sectional views of the array substrate corresponding to the respective steps of the method for fabricating the array substrate in the first embodiment of the first preferred embodiment of the present invention.

12 is a flow chart showing a method of fabricating an array substrate according to a second embodiment of the first preferred embodiment of the present invention.

13 to FIG. 19 are cross-sectional views of the array substrate corresponding to the respective steps of the method for fabricating the array substrate in the second embodiment of the first preferred embodiment of the present invention.

20 is a flow chart showing a method of fabricating an array substrate according to a third embodiment of the first preferred embodiment of the present invention.

21 to 27 are cross-sectional views of the array substrate corresponding to the respective steps of the method for fabricating the array substrate in the third embodiment of the first preferred embodiment of the present invention.

28 is a flow chart showing a method of fabricating an array substrate according to a fourth embodiment of the first preferred embodiment of the present invention.

29 to 39 are cross-sectional views of the array substrate corresponding to the respective steps of the method for fabricating the array substrate in the fourth embodiment of the first preferred embodiment of the present invention.

40 is a flow chart showing a method of fabricating an array substrate according to a fifth embodiment of the first preferred embodiment of the present invention.

41 to FIG. 50 are cross-sectional views of the array substrate corresponding to the respective steps of the method for fabricating the array substrate in the fifth embodiment of the first preferred embodiment of the present invention.

51 is a flow chart showing a method of fabricating an array substrate according to a second preferred embodiment of the present invention.

52 to FIG. 61 are cross-sectional views of an array substrate corresponding to respective steps of a method for fabricating an array substrate according to a second preferred embodiment of the present invention.

FIG. 62 is a cross-sectional structural view of an array substrate according to a preferred embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Please refer to FIG. 1. FIG. 1 is a flow chart of a method for fabricating an array substrate according to a first preferred embodiment of the present invention. Cheng Tu. The array substrate includes a thin film transistor and a capacitor, and the capacitor may be, but not limited to, a storage capacitor. The method for preparing the array substrate includes, but is not limited to, the following steps.

In step S101, a substrate is provided.

Step S102, forming a first metal layer on a surface of the substrate, and patterning the first metal layer to form a gate and a first electrode, wherein the gate and the first electrode are spaced apart Settings.

Step S103, forming a first insulating layer covering the gate and the first electrode.

Step S104, forming an active layer corresponding to the gate on the first insulating layer, and annealing the active layer.

Step S105, forming a second insulating layer covering the active layer.

Step S106, a first through hole is opened corresponding to the first electrode, so that a part of the first electrode is exposed through the first through hole, and a second through hole and a third through hole are formed corresponding to the active layer. So that a portion of the active layer is exposed through the second through hole and the third through hole, respectively.

Step S107, forming a second electrode connected to the first electrode through the first through hole, a source connected to the active layer through the second through hole, and passing through the third through hole and The drain connected to the active layer, the second electrode, the source and the drain are spaced apart, wherein the second electrode and the first electrode constitute one electrode plate of the capacitor.

The preparation method of the array substrate of the present invention will be described in detail below with reference to specific embodiments. The method for preparing the array substrate of the present invention will be described below in combination with a plurality of embodiments. In order to facilitate the differentiation of the plurality of embodiments, the addition of I, II, III, IV, V, VI to the back of the step is indicated as the first aspect of the present invention. The first embodiment of the preferred embodiment, such as step S101-I, represents the step S101 of the first embodiment. Referring to FIG. 2, FIG. 2 is a flowchart of a method for fabricating an array substrate according to a first embodiment of the first preferred embodiment of the present invention. The array substrate includes a thin film transistor and a capacitor, in this embodiment The method for preparing the array substrate includes, but is not limited to, the following steps.

In step S101-I, the substrate 101 is provided. Referring to FIG. 3, the substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to each other. The substrate 101 is a transparent substrate, such as a glass substrate, a plastic substrate, or the like, and may be a flexible substrate.

Step S102-I, forming a first metal layer on the surface of the substrate 101, and patterning the first metal layer to form a gate electrode 102 and a first electrode 103, wherein the gate electrode 102 and The first electrodes 103 are spaced apart. Referring to FIG. 4 , in the embodiment, the first metal layer is directly disposed on the first surface 101 a of the substrate 101 , and the gate electrode 102 and the first electrode are obtained after the first metal layer is patterned. 103 is also disposed directly on the first surface 101a. It is to be understood that, in other embodiments, the first metal layer may also be disposed indirectly on the first surface 101a of the substrate 101. For example, a buffer layer is disposed on the first surface 101a of the substrate 101 ( The first metal layer is disposed on a surface of the buffer layer away from the substrate 101, and the gate electrode and the first electrode 103 obtained by patterning the first metal layer are also disposed in the The buffer layer is away from the surface of the substrate 101. In other embodiments, the first metal layer may also be disposed on the substrate 101 directly or indirectly through a buffer layer. The buffer layer functions to buffer the damage of the substrate 101 to the substrate 101 during the preparation of the respective film layers.

Step S103-I, forming a first insulating layer 104 covering the gate electrode 102 and the first electrode 103. Referring to FIG. 5 , the material of the first insulating layer 104 may be, but not limited to, silicon oxide or silicon nitride.

Step S104-I, forming an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and annealing the active layer 105. Referring to FIG. 6 , the active layer 105 is an oxide semiconductor. For example, the active layer 105 may be, but not limited to, Indium Gallium Zinc Oxide (IGZO).

In step S105-I, a second insulating layer 106 covering the active layer 105 is formed. Specifically, the step S105-I includes: forming a second insulating layer 106 covering only the active layer 105.

Step S106-I, the first through hole 1041 is opened corresponding to the first electrode 103, so that a part of the first electrode 103 is exposed through the first through hole 1041, and a second through hole corresponding to the active layer 105 is opened. 1061 and the third through hole 1062, so that part of the active layer 105 is exposed through the second through hole 1061 and the third through hole 1062, respectively. Specifically, the step S106-I includes the following steps:

Step a-I, opening a first through hole 1041 corresponding to the first electrode 103 on the first insulating layer 104, so that a part of the first electrode 103 is exposed through the first through hole 1041;

In the step b1, a second through hole 1061 and a third through hole 1062 are disposed on the second insulating layer 106 corresponding to the active layer 105, so that a part of the active layer 105 passes through the second through hole 1061 and The third through hole 1062 is exposed.

It can be understood that in other embodiments, step a-I may be performed first, then step S105-I is performed, and then step b-I is performed.

That is, the step aI is performed first: the first through hole 1041 is opened on the first insulating layer 104 corresponding to the first electrode 103, so that a part of the first electrode 103 is exposed through the first through hole 1041, please refer to FIG. The first through hole 1041 may be formed by dry etching.

Step S105-I is further performed: forming a second insulating layer 106 covering the active layer 105. Specifically, the step S105-I includes: forming a second insulating layer 106 covering only the active layer 105. Referring to FIG. 8 , the material of the second insulating layer 106 may be, but not limited to, silicon oxide, silicon nitride, or the like. The second insulating layer 106 covers only the active layer 105 and does not cover the first insulating layer 104 corresponding to the first electrode 103.

Then, the second through hole 1061 and the third through hole 1062 are disposed on the second insulating layer 106 corresponding to the active layer 105, so that part of the active layer 105 passes through the second through. The hole 1061 and the third through hole 1062 are exposed. Please refer to Figure 9.

Step S107-I, forming a second electrode 107 connected to the first electrode 103 through the first through hole 1041, a source 108 connected to the active layer 105 through the second through hole 1061, and The second electrode 107, the source 108, and the drain 109 are spaced apart by the third via 1062 and the drain 109 connected to the active layer 105, wherein the second electrode 107 And the first electrode 103 constitutes one electrode plate of the capacitor. Referring to FIG. 10, in particular, a second metal layer (not shown) is formed on the surface of the first insulating layer 104 and the second insulating layer 106, and the second metal layer covers the exposed first insulation. The layer 104, the second insulating layer 106, the first electrode 103 exposed through the first through hole 1041, and the active layer 105 exposed through the second through hole 1061 and the second through hole 1062, respectively. Next, the second metal layer is patterned to form a source 108 connected to the active layer 105 through the second via 1061, and through the third via 1062 and the active a drain 109 connected to the layer 105, and the second electrode 107, the source 108 and the drain 109 are spaced apart.

Preferably, the method for preparing the array substrate further includes the following steps after the step S107-I:

Step S108-I, forming a passivation layer 110 covering the second electrode 107, the passivation layer 110 constituting the medium of the capacitor.

In step S109-I, a transparent electrode layer 111 is formed on the passivation layer 110, and the transparent electrode layer 111 constitutes another electrode plate of the capacitor. Referring to FIG. 11 , the transparent electrode layer 111 may be, but not limited to, Indium Tin Oxide (ITO).

Compared with the prior art, the method for fabricating the array substrate of the present invention first forms an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and anneals the active layer 105. Opening a first through hole 1041 corresponding to the first electrode 103 on the first insulating layer 104, so that a portion of the first electrode 103 is exposed through the first through hole 1041, thereby overcoming the prior art. The technical problem of oxidizing the exposed first electrode caused by forming the via hole exposing the first electrode and then forming the active layer and annealing the active layer, therefore, preparation of the array substrate of the present invention The performance of the array substrate prepared by the method is high.

The method for fabricating the array substrate of the second embodiment of the present invention is described below. The array substrate includes a thin film transistor and a capacitor. Referring to FIG. 12, FIG. 12 is a first preferred embodiment of the present invention. A flow chart of a method of preparing an array substrate of the second embodiment. The preparation method of the array substrate includes, but is not limited to, the following steps.

In step S101-II, a substrate 101 is provided. Referring to FIG. 13, the substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to each other. The substrate 101 is a transparent substrate, such as a glass substrate, a plastic substrate, or the like, and may be a flexible substrate.

Step S102-II, forming a first metal layer on a surface of the substrate 101, and patterning the first metal layer to form a gate electrode 102 and a first electrode 103, wherein the gate electrode 102 and The first electrodes 103 are spaced apart. Referring to FIG. 14 , in the embodiment, the first metal layer is directly disposed on the first surface 101 a of the substrate 101 , and the gate electrode 102 and the first electrode are obtained after the first metal layer is patterned. 103 is also disposed directly on the first surface 101a. In other embodiments, the first metal layer may also be disposed indirectly on the first surface 101a of the substrate 101. For example, a buffer is disposed on the first surface 101a of the substrate 101. a layer (not shown), the first metal layer is disposed on a surface of the buffer layer away from the substrate 101, and the gate and the first electrode 103 obtained after patterning the first metal layer are also disposed The buffer layer is on a surface away from the substrate 101. In other embodiments, the first metal layer may also be disposed on the substrate 101 directly or indirectly through a buffer layer.

In step S103-II, a first insulating layer 104 covering the gate electrode 102 and the first electrode 103 is formed. The material of the first insulating layer 104 may be, but not limited to, silicon oxide or silicon nitride.

Step S104-II, forming an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and annealing the active layer 105. Referring to FIG. 15 , the active layer 105 is an oxide semiconductor. For example, the active layer 105 may be, but not limited to, Indium Gallium Zinc Oxide (IGZO).

In step S105-II, a second insulating layer 106 covering the active layer 105 is formed. Specifically, the step S105-II includes: forming a second insulating layer 106 covering the active layer 105 and the first insulating layer 104. Please refer to Figure 16.

Step S106-II, the first through hole 1041 is opened corresponding to the first electrode 103, so that a part of the first electrode 103 is exposed through the first through hole 1041, and a second through hole corresponding to the active layer 105 is opened. 1061 and the third through hole 1062, so that part of the active layer 105 is exposed through the second through hole 1061 and the third through hole 1062, respectively. Specifically, the step S106-II includes the following steps.

In the step a-II, the first through hole 1041a and the second through hole 1041b are respectively formed on the first insulating layer 104 and the second insulating layer 106 corresponding to the first electrode 103, the first The through hole 1041a communicates with the second through hole 1041b to form the first through hole 1041 such that a portion of the first electrode 103 is exposed through the first through hole 1041. Referring to FIG. 17, the first through hole 1041a and the second through hole 1041b may be formed by dry etching.

Step b-II, a second through hole 1061 and a third through hole 1062 are formed on the second insulating layer 106 corresponding to the active layer 105 so that a part of the active layer 105 passes through the second through hole respectively. 1061 and the third through hole 1062 are exposed.

Step S107-II, forming a second electrode 107 connected to the first electrode 103 through the first through hole 1041, a source 108 connected to the active layer 105 through the second through hole 1061, and The second electrode 107, the drain electrode 109 connected to the active layer 105 through the third through hole 1062, The source electrode 108 and the drain electrode 109 are spaced apart, wherein the second electrode 107 and the first electrode 103 constitute one electrode plate of the capacitor. Please refer to Figure 18.

Preferably, the method for preparing the array substrate further comprises the following steps after the step S107-II:

In step S108-II, a passivation layer 110 covering the second electrode 107 is formed, and the passivation layer 110 constitutes a medium of the capacitor.

In step S109-II, a transparent electrode layer 111 is formed on the passivation layer 110, and the transparent electrode layer 111 constitutes another electrode plate of the capacitor. Referring to FIG. 19, the transparent electrode layer 111 may be, but not limited to, Indium Tin Oxide (ITO).

Compared with the prior art, the method for fabricating the array substrate of the present invention first forms an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and anneals the active layer 105. Further, the first through hole 1041a and the second through hole 1041b are respectively formed on the first insulating layer 104 and the second insulating layer 106 corresponding to the first electrode 103, so that a part of the first electrode 103 passes through The first through hole 1041 is exposed. Therefore, the pair of exposed holes formed by exposing the first electrode in the prior art is formed, and the active layer is formed and the active layer is annealed. The technical problem of oxidation of the first electrode, therefore, the performance of the array substrate prepared by the method for preparing the array substrate of the present invention is high. And further, overcome the influence of the dry etching process on the contact area between the active layer and the first insulating layer when the first through hole is formed on the first insulating layer covering the first electrode in the prior art, thereby The performance of the thin film transistor in the array substrate is improved. Further, when the second through hole 1061 and the third through hole 1062 are opened on the second insulating layer 106 corresponding to the active layer 105, the active layer 105 is not exposed to the outside, thereby enhancing the array. The performance of thin film transistors in a substrate.

Referring to FIG. 20, FIG. 20 is a flowchart of a method for fabricating an array substrate according to a third embodiment of the first preferred embodiment of the present invention. The array substrate includes a thin film transistor and a capacitor. In the embodiment, the method for preparing the array substrate includes, but is not limited to, the following steps.

In steps S101-III, a substrate 101 is provided. Referring to FIG. 21, the substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to each other. The substrate 101 is a transparent substrate, such as a glass substrate, a plastic substrate, or the like, and may be a flexible substrate.

Steps S102-III, forming a first metal layer on the surface of the substrate 101, and the first The metal layer is patterned to form a gate electrode 102 and a first electrode 103, wherein the gate electrode 102 and the first electrode 103 are spaced apart. Referring to FIG. 22, in the embodiment, the first metal layer is directly disposed on the first surface 101a of the substrate 101, and the gate electrode 102 and the first electrode are obtained after patterning the first metal layer. 103 is also disposed directly on the first surface 101a. It is to be understood that, in other embodiments, the first metal layer may also be disposed indirectly on the first surface 101a of the substrate 101. For example, a buffer layer is disposed on the first surface 101a of the substrate 101 ( The first metal layer is disposed on a surface of the buffer layer away from the substrate 101, and the gate electrode and the first electrode 103 obtained by patterning the first metal layer are also disposed in the The buffer layer is away from the surface of the substrate 101. In other embodiments, the first metal layer may also be disposed on the substrate 101 directly or indirectly through a buffer layer.

Step S103-III, forming a first insulating layer 104 covering the gate electrode 102 and the first electrode 103. Referring to FIG. 23, the material of the first insulating layer 104 may be, but not limited to, silicon oxide or silicon nitride.

Step S104-III, forming an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and annealing the active layer 105. The active layer 105 is an oxide semiconductor. For example, the active layer 105 may be, but not limited to, Indium Gallium Zinc Oxide (IGZO).

In step S105-III, a second insulating layer 106 covering the active layer 105 is formed. In the embodiment, the step S105-III specifically includes: forming a second insulating layer 106 covering the active layer 105 and the first insulating layer 104. Referring to FIG. 24 , the material of the second insulating layer 106 may be, but not limited to, silicon oxide, silicon nitride, or the like.

Step S106-III, the first through hole 1041 is opened corresponding to the first electrode 103, so that a part of the first electrode 103 is exposed through the first through hole 1041, and a second interval corresponding to the active layer 105 is opened. The through hole 1061 and the third through hole 1062 are such that a part of the active layer 105 is exposed through the second through hole 1061 and the third through hole 1062, respectively. The step S106-III specifically includes: forming a first through hole 1041a and a second through hole 1041b corresponding to the first electrode on the first insulating layer 104 and the second insulating layer 106, respectively The first through hole 1041a communicates with the second through hole 1041b to form the first through hole 1041, so that a part of the first electrode 103 is exposed through the first through hole 1041; and in the The two insulating layers 106 correspond to the active layer 105 The second through hole 1061 and the third through hole 1062 are disposed at intervals, so that a part of the active layer 105 is respectively exposed through the second through hole 1061 and the third through hole 1062; wherein the first through hole is formed 1041. The second through hole 1061 and the third through hole 1062 are formed in the same photomask. Please refer to Figure 25.

Step S107-III, forming a second electrode 107 connected to the first electrode 103 through the first through hole 1041, a source connected to the active layer 105 through the second through hole 1061, and passing through The third through hole 1062 and the drain 109 connected to the active layer 105, the second electrode 107, the source 108 and the drain 109 are spaced apart, wherein the second electrode 107 and The first electrode 103 constitutes one electrode plate of the capacitor. Referring to FIG. 26, in particular, a second metal layer (not shown) is formed on the surfaces of the first insulating layer 104 and the second insulating layer 106, and the second metal layer covers the exposed first insulation. The layer 104, the second insulating layer 106, the first electrode 103 exposed through the first through hole 1041, and the active layer 105 exposed through the second through hole 1061 and the second through hole 1062, respectively. Next, the second metal layer is patterned to form a source 108 connected to the active layer 105 through the second via 1061, and through the third via 1062 and the active The drain 105 is connected to the layer 105, and the second electrode 107, the source 108 and the drain 109 are spaced apart.

Preferably, the method for preparing the array substrate further comprises the following steps after the step S107-III:

In step S108-III, a passivation layer 110 covering the second electrode 107 is formed, and the passivation layer 110 constitutes a medium of the capacitor.

In step S109-III, a transparent electrode layer 111 is formed on the passivation layer 110, and the transparent electrode layer 111 constitutes another electrode plate of the capacitor. Referring to FIG. 27, the transparent electrode layer 111 may be, but not limited to, tin indium oxide.

Compared with the prior art, the method for fabricating the array substrate of the present invention first forms an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and anneals the active layer 105. Further, the first through hole 1041a and the second through hole 1041b are respectively formed on the first insulating layer 104 and the second insulating layer 106 corresponding to the first electrode 103, so that a part of the first electrode 103 passes through The first through hole 1041 is exposed. Therefore, the pair of exposed holes formed by exposing the first electrode in the prior art is formed, and the active layer is formed and the active layer is annealed. The technical problem of oxidation of the first electrode, therefore, the preparation method of the array substrate of the present invention is prepared The performance of the resulting array substrate is high. And further, overcome the influence of the dry etching process on the contact area between the active layer and the first insulating layer when the first through hole is formed on the first insulating layer covering the first electrode in the prior art, thereby The performance of the thin film transistor in the array substrate is improved. Further, when the second through hole 1061 and the third through hole 1062 are opened on the second insulating layer 106 corresponding to the active layer 105, the active layer 105 is not exposed to the outside, thereby enhancing the array. The performance of thin film transistors in a substrate. The first through hole 1041, the second through hole 1061 and the third through hole 1062 are formed in the same reticle, which reduces the number of the reticle.

28 is a flow chart showing a method of fabricating an array substrate according to a fourth embodiment of the first preferred embodiment of the present invention. The array substrate includes a thin film transistor and a capacitor. In the embodiment, the method for preparing the array substrate includes, but is not limited to, the following steps.

In steps S101-IV, a substrate 101 is provided. Referring to FIG. 29, the substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to each other. The substrate 101 is a transparent substrate, such as a glass substrate, a plastic substrate, or the like, and may be a flexible substrate.

Steps S102-IV, forming a first metal layer on a surface of the substrate 101, and patterning the first metal layer to form a gate electrode 102 and a first electrode 103, wherein the gate electrode 102 and The first electrodes 103 are spaced apart. Referring to FIG. 30, in the embodiment, the first metal layer is directly disposed on the first surface 101a of the substrate 101, and the gate electrode 102 and the first electrode are obtained after patterning the first metal layer. 103 is also disposed directly on the first surface 101a. It is to be understood that, in other embodiments, the first metal layer may also be disposed indirectly on the first surface 101a of the substrate 101. For example, a buffer layer is disposed on the first surface 101a of the substrate 101 ( The first metal layer is disposed on a surface of the buffer layer away from the substrate 101, and the gate electrode and the first electrode 103 obtained by patterning the first metal layer are also disposed in the The buffer layer is away from the surface of the substrate 101. In other embodiments, the first metal layer may also be disposed on the substrate 101 directly or indirectly through a buffer layer.

In steps S103-IV, a first insulating layer 104 covering the gate electrode 102 and the first electrode 103 is formed. Referring to FIG. 31, the material of the first insulating layer 104 may be, but not limited to, silicon oxide or silicon nitride.

Step S104-IV, forming an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and annealing the active layer 105. Referring to FIG. 32, the active layer 105 is oxygen. For example, the active layer 105 may be, but not limited to, indium gallium zinc oxide or the like.

In step S105-IV, a second insulating layer 106 covering the active layer 105 is formed. Specifically, the step S105-IV includes: forming a second insulating layer 106 covering the active layer 105 and the first insulating layer 104. Referring to FIG. 33, the material of the second insulating layer 106 may be, but not limited to, silicon oxide or silicon nitride.

Steps S106-IV, the first through hole 1041 is opened corresponding to the first electrode 103, so that a part of the first electrode 103 is exposed through the first through hole 1041, and a second interval corresponding to the active layer 105 is opened. The through hole 1061 and the third through hole 1062 are such that a part of the active layer 105 is exposed through the second through hole 1061 and the third through hole 1062, respectively. Specifically, the steps S106-IV include the following steps.

In steps a-IV, a photoresist layer 112 covering the second insulating layer 106 is formed. Please refer to Figure 34.

Step b-IV, forming a first photoresist via 1121 on the photoresist layer 112 corresponding to the first electrode 103 by using a half tone mask process, in the light corresponding to the active layer 105 A first groove 112a and a second groove 112b are formed on the resistive layer 112, and the first insulating layer 104 and the second insulating layer 106 are corresponding to the first photoresist via 1121. A first through hole 1041 of an electrode 103. Please refer to Figure 35.

Step c-IV, forming a second photoresist via 1122 at a position of the first recess 112a, forming a third photoresist via 1123 at a position of the second recess 112b, and corresponding to the second light The via hole 1122 forms a second through hole 1061 on the second insulating layer 106, and a third through hole 1062 is formed on the second insulating layer 106 corresponding to the third photoresist via 1123. Please refer to Figure 36.

In step d-IV, the remaining photoresist layer 112 is removed. Please refer to Figure 37.

Steps S107-IV, forming a second electrode 107 connected to the first electrode 103 through the first through hole 1041, a source 108 connected to the active layer 105 through the second through hole 1061, and The second electrode 107, the source 108, and the drain 109 are spaced apart by the third via 1062 and the drain 109 connected to the active layer 105, wherein the second electrode 107 And the first electrode 103 constitutes one electrode plate of the capacitor. Referring to FIG. 38, in particular, a second metal layer (not shown) is formed on the surface of the first insulating layer 104 and the second insulating layer 106, and the second metal layer covers the exposed first insulation. a layer 104, a second insulating layer 106, a first electrode 103 exposed through the first through hole 1041, and a second through hole 1061 and the first The active layer 105 is exposed by the through hole 1062. Next, the second metal layer is patterned to form a source 108 connected to the active layer 105 through the second via 1061, and through the third via 1062 and the active The drain 105 is connected to the layer 105, and the second electrode 107, the source 108 and the drain 109 are spaced apart.

Preferably, the method for preparing the array substrate further comprises the following steps after the step S107-IV:

Steps S108-IV form a passivation layer 110 covering the second electrode 107, and the passivation layer 110 constitutes a medium of the capacitor.

In step S109-IV, a transparent electrode layer 111 is formed on the passivation layer 110, and the transparent electrode layer 111 constitutes another electrode plate of the capacitor. Referring to FIG. 39, the transparent electrode layer 111 may be, but not limited to, tin indium oxide.

40 is a flow chart showing a method of fabricating an array substrate according to a fifth embodiment of the first preferred embodiment of the present invention. The array substrate includes a thin film transistor and a capacitor. In the embodiment, the method for preparing the array substrate includes, but is not limited to, the following steps.

In step S101-V, the substrate 101 is provided. Referring to FIG. 41, the substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to each other. The substrate 101 is a transparent substrate, such as a glass substrate, a plastic substrate, or the like, and may be a flexible substrate.

Step S102-V, forming a first metal layer on a surface of the substrate 101, and patterning the first metal layer to form a gate electrode 102 and a first electrode 103, wherein the gate electrode 102 and The first electrodes 103 are spaced apart. Referring to FIG. 42 , in the embodiment, the first metal layer is directly disposed on the first surface 101 a of the substrate 101 , and the gate electrode 102 and the first electrode are obtained after patterning the first metal layer. 103 is also disposed directly on the first surface 101a. It is to be understood that, in other embodiments, the first metal layer may also be disposed indirectly on the first surface 101a of the substrate 101. For example, a buffer layer is disposed on the first surface 101a of the substrate 101 ( The first metal layer is disposed on a surface of the buffer layer away from the substrate 101, and the gate electrode and the first electrode 103 obtained by patterning the first metal layer are also disposed in the The buffer layer is away from the surface of the substrate 101. In other embodiments, the first metal layer may also be disposed on the substrate 101 directly or indirectly through a buffer layer.

Step S103-V, forming a first insulation covering the gate 102 and the first electrode 103 Layer 104. Referring to FIG. 43 , the material of the first insulating layer 104 may be, but not limited to, silicon oxide or silicon nitride.

Step S104-V, forming an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and annealing the active layer 105. Referring to FIG. 44, the active layer 105 is an oxide semiconductor. For example, the active layer 105 may be, but not limited to, indium gallium zinc oxide or the like.

In step S105-V, a second insulating layer 106 covering the active layer 105 is formed. Specifically, the step S105-V includes: forming a second insulating layer 106 covering the active layer 105 and the first insulating layer 104. Referring to FIG. 45, the material of the second insulating layer 106 may be, but not limited to, silicon oxide, silicon nitride, or the like.

In step S10a-V, an organic material layer 113 covering the second insulating layer 106 is formed. Referring to FIG. 46, the organic material layer 113 may be, but not limited to, an organic resin.

Step S10b-V, a first organic material via hole 1131 is formed on the organic material layer 113 corresponding to the first electrode 103, and a second interval is formed on the organic material layer 113 corresponding to the active layer 105. The organic material through hole 1132 and the third organic material through hole 1133. Referring to FIG. 47, the first organic material through hole 1131, the second organic material through hole 1132, and the third organic material through hole 1133 are through holes formed in the organic material layer 113. Such names are only intended to distinguish them from other through holes and through holes in the present invention.

Step S106-V, the first through hole 1041 is opened corresponding to the first electrode 103, so that a part of the first electrode 103 is exposed through the first through hole 1041, and a second interval corresponding to the active layer 105 is opened. The through hole 1061 and the third through hole 1062 are such that a part of the active layer 105 is exposed through the second through hole 1061 and the third through hole 1062, respectively. Referring to FIG. 48, in the embodiment, the step S106-V is specifically corresponding to the first organic material through hole 1131, respectively on the first insulating layer 104 and the second insulating layer 106. Corresponding to the first electrode 103, a first through hole 1041a and a second through hole 1041b are formed, and the first through hole 1041a communicates with the second through hole 1041b to form the first through hole 1041. So that a portion of the first electrode 103 is exposed through the first through hole 1041 and the first organic material through hole 1131, and a second through hole is formed in the second insulating layer 106 corresponding to the second organic material through hole 1132. 1061, such that a portion of the active layer 105 is exposed through the second through hole 1061 and the second organic material through hole 1132, and corresponding to the third organic material through hole 1133 on the second insulating layer 106 Opening a third through hole 1062 to make a portion The active layer 105 is exposed through the third through hole 1062 and the third organic material through hole 1133.

Step S107-V, forming a second electrode 107 connected to the first electrode 103 through the first through hole 1041, a source 108 connected to the active layer 105 through the second through hole 1061, and The second electrode 107, the source 108, and the drain 109 are spaced apart by the third via 1062 and the drain 109 connected to the active layer 105, wherein the second electrode 107 And the first electrode 103 constitutes one electrode plate of the capacitor. Specifically, referring to FIG. 49, the step S107-V includes: forming a second metal layer (not shown) on the surface of the organic material layer 113, and patterning the second metal layer metal to form Forming a second organic material through hole 1132 and the second through hole 1061 through the first organic material through hole 1131 and the first through hole 1041 and the second electrode 107 connected to the first electrode 103 The source layer 108 connected to the active layer 105 and the drain 109 connected to the active layer 105 through the third organic material via 1133 and the third via 1062.

Preferably, the method for preparing the array substrate further includes the following steps after the step S107-V:

In step S108-V, a passivation layer 110 covering the second electrode 107 is formed, and the passivation layer 110 constitutes a medium of the capacitor.

In step S109-V, a transparent electrode layer 111 is formed on the passivation layer 110, and the transparent electrode layer 111 constitutes another electrode plate of the capacitor. Referring to FIG. 50, the transparent electrode layer 111 may be, but not limited to, tin indium oxide.

Compared with the prior art, the method for fabricating the array substrate of the present invention first forms an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and anneals the active layer 105. Further, the first through hole 1041a and the second through hole 1041b are respectively formed on the first insulating layer 104 and the second insulating layer 106 corresponding to the first electrode 103, so that a part of the first electrode 103 passes through The first through hole 1041 is exposed. Therefore, the pair of exposed holes formed by exposing the first electrode in the prior art is formed, and the active layer is formed and the active layer is annealed. The technical problem of oxidation of the first electrode, therefore, the performance of the array substrate prepared by the method for preparing the array substrate of the present invention is high. Further, since the organic material layer 113 is covered on the second insulating layer 106, the stress of the organic material layer 113 is relatively small, and the organic material layer 113 is less likely to be cracked when the prepared array substrate is bent, thereby Protection of other layers in the array substrate effect.

51 is a flow chart showing a method of fabricating an array substrate according to a second preferred embodiment of the present invention. The array substrate includes a thin film transistor and a capacitor. In the embodiment, the method for preparing the array substrate includes, but is not limited to, the following steps.

In step S201, the substrate 101 is provided. Referring to FIG. 52, the substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to each other. The substrate 101 is a transparent substrate, such as a glass substrate, a plastic substrate, or the like, and may be a flexible substrate.

Step S202, forming a first metal layer on a surface of the substrate, and patterning the first metal layer to form a gate and a first electrode, wherein the gate and the first electrode are spaced apart Settings. Referring to FIG. 53, in the embodiment, the first metal layer is directly disposed on the first surface 101a of the substrate 101, and the gate electrode 102 and the first electrode are obtained after patterning the first metal layer. 103 is also disposed directly on the first surface 101a. It is to be understood that, in other embodiments, the first metal layer may also be disposed indirectly on the first surface 101a of the substrate 101. For example, a buffer layer is disposed on the first surface 101a of the substrate 101 ( The first metal layer is disposed on a surface of the buffer layer away from the substrate 101, and the gate electrode and the first electrode 103 obtained by patterning the first metal layer are also disposed in the The buffer layer is away from the surface of the substrate 101. In other embodiments, the first metal layer may also be disposed on the substrate 101 directly or indirectly through a buffer layer.

In step S203, a first insulating layer 104 covering the gate electrode 102 and the first electrode 103 is formed. Referring to FIG. 54 , the material of the first insulating layer 104 may be, but not limited to, silicon oxide or silicon nitride.

Step S204, forming an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and annealing the active layer 105. Referring to FIG. 55, the active layer 105 is an oxide semiconductor. For example, the active layer 105 may be, but not limited to, indium gallium zinc oxide or the like.

Step S205, forming a second insulating layer 106 covering the active layer 105 and the first insulating layer 104. Referring to FIG. 56, the material of the second insulating layer 106 may be, but not limited to, silicon oxide or silicon nitride.

Step S206, opening a first through hole 1041a and a second through hole 1401b corresponding to the first electrode 103 on the first insulating layer 104 and the second insulating layer 106, respectively, the first sub-through The hole 1041a communicates with the second through hole 1041b to form the first through hole 1041 such that a portion of the first electrode 103 is exposed through the first through hole 1041. Please refer to Figure 57.

Step S207, forming an organic material layer 113 covering the second insulating layer 106, and opening a first organic material via hole 1131 corresponding to the first electrode 103 on the organic material layer 113, the first organic material passing through The hole 1131 communicates with the first through hole 1041, and a second organic material through hole 1132 and a third organic material through hole 1133 are formed on the organic material layer 113 corresponding to the active layer 105. Referring to FIG. 58, the first organic material through hole 1131, the second organic material through hole 1132, and the third organic material through hole 1133 are through holes formed in the organic material layer 113. Such names are only intended to distinguish them from other through holes and through holes in the present invention.

Step S208, a second through hole 1061 is formed in the second insulating layer 106 corresponding to the second organic material through hole 1132, so that a part of the active layer 105 passes through the second through hole 1061 and the second organic A material through hole 1132 is formed, and a third through hole 1062 is formed in the second insulating layer 106 corresponding to the third organic material through hole 1133, so that a part of the active layer 105 passes through the third through hole 1062 and The third organic material through hole 1133 is exposed. Referring to FIG. 59, in the embodiment, the first through hole 1041a, the second through hole 1041b, the second through hole 1061, and the third through hole 1062 are formed by a dry etching process. .

Step S209, forming a second electrode 107 connected to the first electrode 103 through the first through hole 1041, a source 108 connected to the active layer 105 through the second through hole 1061, and a pass through the a third through hole 1062 and a drain 109 connected to the active layer 105, the second electrode 107, the source 108 and the drain 109 are spaced apart, wherein the second electrode 107 and the The first electrode 103 constitutes one electrode plate of the capacitor. Specifically, referring to FIG. 60, the step S209 includes: forming a second metal layer (not shown) on the surface of the organic material layer 113, and patterning the second metal layer to form a pass through The first through hole 1041 and the first organic material through hole 1131 are connected to the first electrode 103, and the second electrode 107 is formed through the second through hole 1061 and the second organic material through hole 1132. A source 108 connected to the active layer 105, and a drain connected to the active layer 105 through the third through hole 1062 and the third organic material via 1133.

Preferably, after the step S209, the method for preparing the array substrate further comprises the following steps.

Step S210, forming a passivation layer 110 covering the second electrode, and the passivation layer 110 constitutes The medium of the capacitor.

In step S211, a transparent electrode layer 111 is formed on the passivation layer 110, and the transparent electrode layer 111 constitutes another electrode plate of the capacitor. Referring to FIG. 61, the transparent electrode layer 111 may be, but not limited to, tin indium oxide.

Compared with the prior art, the method for fabricating the array substrate of the present invention first forms an active layer 105 corresponding to the gate electrode 102 on the first insulating layer 104, and anneals the active layer 105. Further, the first through hole 1041a and the second through hole 1041b are respectively formed on the first insulating layer 104 and the second insulating layer 106 corresponding to the first electrode 103, so that a part of the first electrode 103 passes through The first through hole 1041 is exposed. Therefore, the pair of exposed holes formed by exposing the first electrode in the prior art is formed, and the active layer is formed and the active layer is annealed. The technical problem of oxidation of the first electrode, therefore, the performance of the array substrate prepared by the method for preparing the array substrate of the present invention is high. Further, since the organic material layer 113 is covered on the second insulating layer 106, the stress of the organic material layer 113 is relatively small, and the organic material layer 113 is less likely to be cracked when the prepared array substrate is bent, thereby Protection of other layers in the array substrate.

The array substrate of the present invention will be described below in conjunction with the various embodiments described above and the method for fabricating the array substrate in the respective embodiments. Referring to FIG. 62, FIG. 62 is a cross-sectional structural view of the array substrate according to a preferred embodiment of the present invention. The array substrate 100 includes a thin film transistor 100a and a capacitor 100b. The array substrate 100 includes:

Substrate 101;

a gate 102 and a first electrode 103 disposed adjacent to the same surface of the substrate 101, wherein the gate 102 and the first electrode 103 are spaced apart;

Covering the gate electrode 102 and the first insulating layer 104 of the first electrode 103;

An active layer 105 disposed on a surface of the first insulating layer 104 away from the gate 102;

Covering the active layer 105 and the second insulating layer 106 of the first insulating layer 104;

An organic material layer 113 covering the second insulating layer 106;

The first insulating layer 104 is provided with a first through hole 1041a corresponding to the first electrode 103, and the second insulating layer 106 is provided with a second through hole 1041b corresponding to the first electrode 103. The second through hole 1041b communicates with the first through hole 1041a to form a first through hole 1041, and the A second through hole 1061 and a third through hole 1062 disposed at opposite ends of the active layer 105 are disposed on the second insulating layer 106. The organic material layer 113 is provided with a first organic material through hole 1131 and a second organic layer. a material through hole 1132 and a third organic material through hole 1133, the first organic material through hole 1131 is in communication with the first through hole 1041, and the second organic material through hole 1132 is in communication with the second through hole 1061 The third organic material through hole 1133 is in communication with the third through hole 1062;

a second electrode 107 is disposed on the organic material layer 113 and connected to the first electrode 103 through the first organic material through hole 1131 and the first through hole 1041;

a source 108 disposed on the organic material layer 113 and connected to one end of the active layer 105 through the second organic material via 1132 and the second through hole 1061;

a drain electrode 1009 is disposed on the organic material layer 113 and connected to the other end of the active layer 105 through the third organic material via 1133 and the third through hole 1062, and the drain 109 The source electrode 108 and the second electrode 107 are spaced apart, wherein the second electrode 107 and the first electrode 103 constitute one electrode plate of the capacitor 100b.

In this embodiment, the array substrate 100 further includes:

a passivation layer 110 covering the second electrode 107; and

a transparent electrode layer 111 covering the passivation layer 110 and corresponding to the second electrode 107, wherein the passivation layer 110 constitutes a medium of the capacitor 100b, and the transparent electrode layer 111 constitutes the Another electrode plate of capacitor 100b.

In the present embodiment, the active layer 105 is an oxide semiconductor. For example, the active layer 105 may be, but not limited to, Indium Gallium Zinc Oxide (IGZO). The organic material layer 113 may be, but not limited to, an organic resin.

The array substrate 100 further includes a buffer layer 114 disposed on a surface of the substrate 110. Then, the gate electrode 102 and the first electrode 103 are disposed on the same surface of the buffer layer 110 away from the substrate.

Compared with the prior art, the second insulating layer 106 of the array substrate 100 of the present invention is covered with the organic material layer 113. The stress of the organic material layer 113 is relatively small, and the organic material layer 113 is bent when the prepared array substrate is bent. Cracks are less likely to occur, thereby protecting other film layers in the array substrate, thereby improving the performance of the array substrate 100.

The above disclosure is only a few preferred embodiments of the present invention, and of course, the present invention cannot be limited thereto. The scope of the invention is to be understood by those of ordinary skill in the art that the present invention may be

Claims

A method for fabricating an array substrate, the array substrate comprising a thin film transistor and a capacitor, wherein the method for preparing the array substrate comprises:

101, providing a substrate;

102, forming a first metal layer on a surface of the substrate, and patterning the first metal layer to form a gate and a first electrode, wherein the gate and the first electrode are spaced apart ;

103, forming a first insulating layer covering the gate and the first electrode;

104, forming an active layer corresponding to the gate on the first insulating layer, and annealing the active layer;

105, forming a second insulating layer covering the active layer;

106. The first through hole is opened corresponding to the first electrode, so that a part of the first electrode is exposed through the first through hole, and the second through hole and the third through hole are disposed corresponding to the active layer, so that Part of the active layer is exposed through the second through hole and the third through hole respectively; and

107, forming a second electrode connected to the first electrode through the first through hole, a source connected to the active layer through the second through hole, and passing through the third through hole and the The drain connected to the active layer, the second electrode, the source and the drain are spaced apart, wherein the second electrode and the first electrode constitute one electrode plate of the capacitor.
The method of preparing an array substrate according to claim 1, wherein the step 105 comprises:

Forming a second insulating layer covering only the active layer;

The step 106 includes:

Opening a first through hole corresponding to the first electrode on the first insulating layer, so that a part of the first electrode is exposed through the first through hole;

a second through hole and a third through hole are disposed on the second insulating layer corresponding to the active layer, so that a part of the active layer is exposed through the second through hole and the third through hole respectively;

The step 107 includes:

Forming a second metal layer on a surface of the second insulating layer and the first insulating layer, and patterning the second metal layer to form a first via hole connected to the first electrode Second electric a second electrode, the active layer, a source connected to the active layer through the second through hole, and a drain connected through the third through hole and the active layer And the drain are spaced apart, wherein the second electrode and the first electrode constitute one electrode plate of the capacitor.
The method of preparing an array substrate according to claim 1, wherein the step 105 comprises:

Forming a second insulating layer covering the active layer and the first insulating layer;

The step 106 includes:

Opening a first sub-perforation and a second sub-perforation corresponding to the first electrode on the first insulating layer and the second insulating layer, the first sub-perforation and the second sub-peripheral Connecting the holes to form the first through holes such that a portion of the first electrodes are exposed through the first through holes;

A second through hole and a third through hole are formed on the second insulating layer corresponding to the active layer so that a part of the active layer is exposed through the second through hole and the third through hole respectively.
The method of fabricating an array substrate according to claim 3, wherein the first through holes and the second through holes are formed by a dry etching process.
The method of preparing an array substrate according to claim 1, wherein the step 105 comprises:

Forming a second insulating layer covering the active layer and the first insulating layer;

The step 106 includes:

Opening a first sub-perforation and a second sub-perforation corresponding to the first electrode on the first insulating layer and the second insulating layer, the first sub-perforation and the second sub-peripheral The holes are connected to form the first through holes such that a portion of the first electrodes are exposed through the first through holes; and a second through hole is formed on the second insulating layer corresponding to the active layer And a third through hole, so that a part of the active layer is exposed through the second through hole and the third through hole respectively; wherein the first through hole, the second through hole and the third through hole are formed at Formed in the same mask.
The method of fabricating an array substrate according to claim 1, wherein the step 105 include:

Forming a second insulating layer covering the active layer and the first insulating layer;

The step 106 includes:

Forming a photoresist layer covering the second insulating layer;

Forming a first photoresist via on the photoresist layer corresponding to the first electrode by using a half gray mask process, and forming a first groove and a second gap on the photoresist layer corresponding to the active layer a first through hole corresponding to the first electrode, wherein the first insulating layer and the second insulating layer correspond to the first photoresist via;

Forming a second photoresist via at a position of the first recess, forming a third photoresist via at a position of the second recess, and corresponding to the second barrier at the second insulation a second through hole is formed on the layer, and a third through hole is formed on the second insulating layer corresponding to the third photoresist through hole;

Remove the remaining photoresist layer.
The method of preparing an array substrate according to claim 1, wherein

The step 105 includes: forming a second insulating layer covering the active layer and the first insulating layer;

Between the step 105 and the step 106, the method for preparing the array substrate further includes:

Forming an organic material layer covering the second insulating layer;

Disposing a first organic material through hole corresponding to the first electrode on the organic material layer, and a second organic material through hole and a third organic material opening corresponding to the active layer on the organic material layer hole;

The step 106 includes:

Corresponding to the first organic material through hole, respectively, on the first insulating layer and the second insulating layer, respectively, the first through hole and the second through hole are respectively opened corresponding to the first electrode, the first The through hole communicates with the second through hole to form the first through hole, so that a part of the first electrode is exposed through the first through hole and the first organic material through hole, corresponding to the second organic a material through hole defines a second through hole on the second insulating layer, so that a part of the active layer is exposed through the second through hole and the second organic material through hole, and corresponding to the third organic material The through hole defines a third through hole on the second insulating layer, so that a part of the active layer is exposed through the third through hole and the third organic material through hole;

The step 107 includes:

Forming a second metal layer on a surface of the organic material layer, and patterning the second metal layer metal to form a through hole through the first organic material and the first through hole and the first electrode a second electrode connected to form a source connected to the active layer through the second organic material via and the second via, and formed through the third organic material via and the third via a drain connected to the active layer.
The method of preparing an array substrate according to claim 1, wherein the method for preparing the array substrate further comprises:

Forming a passivation layer covering the second electrode, the passivation layer forming a medium of the capacitor;

A transparent electrode layer corresponding to the second electrode is formed on the passivation layer, and the transparent electrode layer constitutes another electrode plate of the capacitor.
A method for fabricating an array substrate, the array substrate comprising a thin film transistor and a capacitor, wherein the method for preparing the array substrate comprises:

201, providing a substrate;

202, forming a first metal layer on a surface of the substrate, and patterning the first metal layer to form a gate and a first electrode, wherein the gate and the first electrode are spaced apart ;

203, forming a first insulating layer covering the gate and the first electrode;

204, forming an active layer corresponding to the gate on the first insulating layer, and annealing the active layer;

205, forming a second insulating layer covering the active layer and the first insulating layer;

206, on the first insulating layer and the second insulating layer respectively corresponding to the first electrode to open a first sub-perforation and a second sub-perforation, the first sub-perforation and the second The through holes communicate to form the first through holes such that a portion of the first electrodes are exposed through the first through holes;

207, forming an organic material layer covering the second insulating layer, and opening a first organic material through hole corresponding to the first electrode on the organic material layer, the first organic material through hole and the first a through hole is communicated, and a second organic material through hole and a third organic material through hole are formed on the organic material layer corresponding to the active layer;

208. A second through hole is formed in the second insulating layer corresponding to the second organic material through hole, so that a part of the active layer is exposed through the second through hole and the second organic material through hole. And a third through hole is formed in the second insulating layer corresponding to the third organic material through hole, so that a part of the active layer is exposed through the third through hole and the third organic material through hole;

209, forming a second electrode connected to the first electrode through the first through hole, a source connected to the active layer through the second through hole, and passing through the third through hole and the The drain connected to the active layer, the second electrode, the source and the drain are spaced apart, wherein the second electrode and the first electrode constitute one electrode plate of the capacitor.
The method of preparing an array substrate according to claim 9, wherein the step 209 comprises:

Forming a second metal layer on a surface of the organic material layer, and patterning the second metal layer to form a through hole and the first electrode through the first through hole and the first organic material a second electrode connected to form a source connected to the active layer through the second through hole and the second organic material through hole, and through the third through hole and the third organic material through hole The drain connected to the active layer.
The method of preparing an array substrate according to claim 9, wherein the method for preparing the array substrate further comprises:

Forming a passivation layer covering the second electrode, the passivation layer forming a medium of the capacitor;

A transparent electrode layer is formed on the passivation layer, and the transparent electrode layer constitutes another electrode plate of the capacitor.
The method of fabricating an array substrate according to claim 9, wherein the first through hole, the second through hole, the second through hole, and the third through hole are dried by a dry etching process form.
An array substrate comprising a thin film transistor and a capacitor, wherein the array substrate comprises:

Substrate

a gate and a first electrode disposed adjacent to the same surface of the substrate, wherein the gate and the first electrode are spaced apart;

Covering the gate and the first insulating layer of the first electrode;

An active layer disposed on a surface of the first insulating layer away from the gate;

Covering the active layer and the second insulating layer of the first insulating layer;

An organic material layer covering the second insulating layer;

a first through hole corresponding to the first electrode is disposed on the first insulating layer, and a second partial through hole corresponding to the first electrode is disposed on the second insulating layer, the second through hole Forming a first through hole in communication with the first through hole, and providing a second through hole and a third through hole disposed on both ends of the active layer on the second insulating layer, the organic material layer Providing a first organic material through hole, a second organic material through hole and a third organic material through hole, wherein the first organic material through hole communicates with the first through hole, and the second organic material through hole and the The second through hole is in communication, and the third organic material through hole is in communication with the third through hole;

a second electrode disposed on the organic material layer and connected to the first electrode through the first organic material through hole and the first through hole;

a source disposed on the organic material layer and connected to one end of the active layer through the second organic material via and the second via; and

a drain disposed on the organic material layer and connected to the other end of the active layer through the third organic material via and the third via, and the drain, the source, and The second electrodes are spaced apart, wherein the second electrode and the first electrode constitute one electrode plate of the capacitor.
The array substrate according to claim 13, wherein the array substrate further comprises:

a passivation layer overlying the second electrode; and

a transparent electrode layer covering the passivation layer and corresponding to the second electrode, wherein the passivation layer constitutes a medium of the capacitor, and the transparent electrode layer constitutes another electrode plate of the capacitor .
The array substrate according to claim 13, wherein the organic material layer comprises an organic resin.