CN101101893A - Pixel structure and its making method - Google Patents
Pixel structure and its making method Download PDFInfo
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- CN101101893A CN101101893A CNA2007101400232A CN200710140023A CN101101893A CN 101101893 A CN101101893 A CN 101101893A CN A2007101400232 A CNA2007101400232 A CN A2007101400232A CN 200710140023 A CN200710140023 A CN 200710140023A CN 101101893 A CN101101893 A CN 101101893A
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Abstract
The invention is concerned with the pixel structure and the making method. It is to the back overcast consists of the guiding layer made of molybdenum, the dielectric layer made of oxidized silicon, and the aluminum layer on the dielectric layer of the grid, next is to conduct equal tropism etching technique to remove the aluminum layer in horizontal and vertical direction at the same time. By applying this method, the invention can simplified the three step mask to only two for forming the source electrode/drain electrode section that achieves cost saving. It also improves the storing capability of the capacitance by forming the double layers stacking structure.
Description
Technical field
The present invention relates to a kind of dot structure and preparation method thereof.
Background technology
LCD has replaced the main product that the conventional cathode ray tube display becomes the monitor market owing to have characteristics such as compact, low radiation and low power consumption.In general, display panels mainly comprises array base palte, the colored filter substrate of thin-film transistor, and is filled in the layer of liquid crystal molecule between array base palte and the colored filter substrate.Array base palte comprises a plurality of pixels that are arrayed, and each pixel is to utilize many parallel scanning beams to form with many panel data line definition vertical with scan line, and with thin-film transistor as switch element, utilize pixel electrode to drive the liquid crystal molecule do rotation in various degree of each pixel top to adjust the brightness of each pixel, simultaneously by on the colored filter substrate with the redness of the corresponding setting of each pixel, greenly make each pixel produce redness, green and the blue ray of different brightness with blue color filter, and then export the chromatic image of high image quality.
Please refer to Fig. 1 to Fig. 6, Fig. 1 to Fig. 6 is the method for known making dot structure.As described in Figure 1, at first provide substrate 12, and have at least one transistor area 14 and capacitive region 16 in the substrate 12.Form patterned polysilicon layer 18 then in transistor area 14 and capacitive region 16.Wherein, the patterned polysilicon layer 18 of transistor area 14 is to be used for forming transistorized regions and source in subsequent technique, and the patterned polysilicon layer 18 of capacitive region 16 is then as capacitor lower electrode.Secondly, the step that forms patterned polysilicon layer 18 can be finished according to the standard step of general making low-temperature polycrystalline silicon layer.For example can form amorphous silicon layer (figure does not show) earlier and, carry out quasi-molecule laser annealing (excimerlaser anneal) technology then, make amorphous silicon layer be converted into polysilicon layer in substrate 1 surface.And then carry out Patternized technique again, remove the part polysilicon layer, in substrate 12, to form patterned polysilicon layer 18.
Then as shown in Figure 2, formation by gate dielectric 20 that silica constituted in substrate 12 surface and overlay pattern polysilicon layers 18, form patterning photoresist layer 22 then on gate dielectric 20, and utilize patterning photoresist layer 22 to be used as mask and carry out ion implantation technology, with the patterned polysilicon layer 18 on P type or N type admixture injection substrate 12 surfaces, in the patterned polysilicon layer 18 of transistor area 14, to form regions and source 24.
As shown in Figure 3, form the conductive layer that constitutes by molybdenum (figure does not show) then on gate dielectric 20, and carry out Patternized technique, remove the partially conductive layer, with in forming grid 26 on the gate dielectric 20 of transistor area 14 and on the gate dielectric 20 of capacitive region 16, forming electric capacity top electrode 28.Then utilize grid 26 to be used as mask and carry out ion implantation technology, with the patterned polysilicon layer 18 on P type or N type admixture injection substrate 12 surfaces, in the patterned polysilicon layer 18 of transistor area 14, to form light dope source electrode/drain electrode 30.So far the making of promptly finishing transistor and finishing electric capacity in capacitive region 16 in transistor area 14.
Subsequently as shown in Figure 4, form dielectric layer 32, carry out Patternized technique then, in dielectric layer 32 and gate dielectric 20, to form a plurality of contacts hole 34 in gate dielectric 20 surface and cover gate 26 and electric capacity top electrodes 28.
As shown in Figure 5, then form patterned metal layer on dielectric layer 32 and fill up and respectively contact hole 34, connect regions and source 24 to form many leads 36.
Then as shown in Figure 6, form another dielectric layer 38 on lead 36, be used as flatness layer, and carry out another Patternized technique, for example utilize patterning photoresist layer (figure does not show) to be used as mask and carry out etch process, in dielectric layer 38, to form at least one opening 40.Then form patterned transparent conductive layer on dielectric layer 38 and fill up opening 40, forming corresponding pixel electrode 42, and then finish the making of known pixel structure.
It should be noted that above-mentioned processes well known generally need use the making that at least seven road masks just can be finished dot structure, cause cost to increase easily.In addition, the known capacitance structure that completes together with transistor is all by polysilicon layer, formed by dielectric layer that silica constituted and by the conductive layer that molybdenum constituted.Though the design of this electric capacity can reach the demand of general dot structure, still can't provide satisfied storage volume under many circumstances.Therefore, the storage capacity of how effectively to save the step of technology and promoting electric capacity is important topic now.
Summary of the invention
The purpose of this invention is to provide a kind of method of making dot structure, to solve above-mentioned known problem.
The present invention discloses a kind of method of making dot structure, it provides substrate earlier, have at least one transistor area and capacitive region in this substrate, form patterned semiconductor layer more respectively in this transistor area and this capacitive region, and form gate dielectric in this substrate surface and cover this patterned semiconductor layer.Form in regular turn subsequently conductive layer, dielectric layer and electrode layer for example aluminium lamination in this substrate, then form a plurality of patterning photoresist layers this aluminium lamination surface in this transistor area and this capacitive region, and carry out isotropic etching technology, utilize these a plurality of patterning photoresist layers to be used as mask, evenly to remove this aluminium lamination of part in level and vertical direction simultaneously.Carry out first etch process then, utilize these a plurality of patterning photoresist layers to be used as mask and remove this dielectric layer of part and this conductive layer, carry out first ion implantation technology again, utilize these a plurality of patterning photoresist layers to be used as mask, in this patterned semiconductor layer of this transistor area, to form regions and source.Remove this patterning photoresist layer of this transistor area afterwards, and carry out second etch process, utilize this patterned aluminium layer to be used as mask, remove this dielectric layer of part and this conductive layer, then carry out second ion implantation technology, utilize these a plurality of patterning photoresist layers to be used as mask, in this patterned semiconductor layer of each this transistor area, to form light dope source electrode/drain electrode.Carry out the 3rd etch process subsequently, utilize this pattern photoresist layer of this capacitive region to be used as the aluminium lamination that mask is removed this transistor area, remove this patterning photoresist layer of this capacitive region afterwards, form first dielectric layer again in this substrate, and form a plurality of first contact holes in this first dielectric layer.Form patterned metal layer then on this first dielectric layer and fill up each this first contact hole,, form second dielectric layer again on these a plurality of first leads, and form a plurality of first and be opened in this second dielectric layer to form many first leads.Form patterned transparent conductive layer at last on this second dielectric layer and fill up each this first opening, to form a plurality of pixel electrodes.
Aforesaid method, the step that wherein forms each this patterned semiconductor layer also comprises: form amorphous silicon layer in this substrate surface; Carry out quasi-molecule laser annealing technology, make this amorphous silicon layer be converted into polysilicon layer; And carry out Patternized technique, remove this polysilicon layer of part, in this substrate, to form these a plurality of patterned semiconductor layer.
Aforesaid method, wherein the material of this conductive layer comprises molybdenum.
Aforesaid method, wherein the material of this electrode layer comprises aluminium.
Aforesaid method, wherein about 4000 dust to 10000 dusts of the thickness of this electrode layer.
Aforesaid method, wherein this method comprised also that before forming a plurality of patterning photoresist layers forming semi-transparency type is masked in this transistor area, and this semi-transparency type mask is to this patterning photoresist layer that should transistor area.
Aforesaid method, wherein this transparency conducting layer comprises indium tin oxide layer or indium zinc oxide layer.
The invention also discloses a kind of dot structure, be formed in the substrate, this substrate has transistor area and capacitive region, this dot structure comprises: patterned semiconductor layer, be located at this transistor area, this patterned semiconductor layer has channel region, and the source/drain regions that is positioned at these channel region both sides; First capacitance electrode is located at this capacitive region; Gate dielectric is located in this substrate and is covered this patterned semiconductor layer and this first capacitance electrode; Grid is located on this channel region of this patterned semiconductor layer; Second capacitance electrode, first dielectric layer and aluminium lamination capacitance electrode are located on this gate dielectric of this capacitive region; First dielectric layer is located in this substrate and is covered this grid and this aluminium lamination capacitance electrode; At least one first lead is located in this first dielectric layer, electrically connects this source/drain regions and this aluminium lamination capacitance electrode of this semiconductor layer; Second dielectric layer is located on these a plurality of first leads; And first transparency conducting layer be located on this second dielectric layer and connect these a plurality of first leads.
Aforesaid dot structure, wherein this second capacitance electrode comprises molybdenum.
Aforesaid dot structure, wherein this first dielectric layer comprises silica.
Aforesaid dot structure, wherein about 4000 dust to 10000 dusts of the thickness of this aluminium lamination capacitance electrode.
Aforesaid dot structure, wherein this first transparency conducting layer is indium tin oxide layer or indium zinc oxide layer.
Aforesaid dot structure, wherein this substrate also comprises the contact mat district, this patterned semiconductor layer is located in this substrate in this contact mat district; This gate dielectric is located in this substrate in this contact mat district and is covered this patterned semiconductor layer; And this dot structure also comprises: the conductive layer and second dielectric layer, be located on this gate dielectric, and wherein, this first dielectric layer is located in this substrate and is covered this second dielectric layer; Second lead is located in this first dielectric layer and is connected this conductive layer, and wherein, this second dielectric layer is located on this second lead; And second transparency conducting layer, be located on this second dielectric layer and connect this second lead.
Aforesaid dot structure, wherein this conductive layer comprises molybdenum.
Aforesaid dot structure, wherein this second dielectric layer comprises silica.
Aforesaid dot structure, wherein this second transparency conducting layer is indium tin oxide layer or indium zinc oxide layer.
The invention also discloses a kind of method of making dot structure, comprising: substrate is provided, has transistor area, capacitive region and contact mat district at least in this substrate; Form patterned semiconductor layer respectively in this transistor area, this capacitive region and this contact mat district; The formation gate dielectric is in this substrate surface and cover this patterned semiconductor layer; Form conductive layer, dielectric layer and aluminium lamination in regular turn in this substrate; Form a plurality of patterning photoresist floor this aluminium lamination surface in this transistor area, this capacitive region and this contact mat district; Carry out isotropic etching technology, utilize these a plurality of patterning photoresist layers to be used as mask, evenly to remove this aluminium lamination of part in level and vertical direction simultaneously; Carry out first etch process, utilize these a plurality of patterning photoresist layers to be used as mask and remove this dielectric layer of part and this conductive layer; Carry out first ion implantation technology, utilize these a plurality of patterning photoresist layers to be used as mask, in this patterned semiconductor layer of this transistor area, to form regions and source; Remove this patterning photoresist floor in this transistor area and this contact mat district; Carry out second etch process, utilize this patterned aluminium layer to be used as mask, remove this dielectric layer of part and this conductive layer; Carry out the 3rd etch process, utilize this patterning photoresist floor of this capacitive region to be used as this aluminium lamination that mask is removed this transistor area and this contact mat district; Remove this patterning photoresist layer of this capacitive region; Form first dielectric layer in this substrate and form a plurality of first the contact holes in this first dielectric layer; The formation patterned metal layer is on this first dielectric layer and fill up each this first contact hole, to form many first leads; Form second dielectric layer on these a plurality of first leads, and form a plurality of first and be opened in this second dielectric layer; And form patterned transparent conductive layer on this second dielectric layer and fill up each this first opening, to form a plurality of pixel electrodes.
Aforesaid method, the step that wherein forms this patterned semiconductor layer also comprises: form amorphous silicon layer in this substrate surface; Carry out quasi-molecule laser annealing technology, make this amorphous silicon layer be converted into polysilicon layer; And carry out Patternized technique, remove this polysilicon layer of part, in this substrate, to form this patterned semiconductor layer.
Aforesaid method, wherein this conductive layer comprises molybdenum.
Aforesaid method, wherein this dielectric layer comprises silica.
Aforesaid method, wherein about 4000 dust to 10000 dusts of the thickness of this aluminium lamination.
Aforesaid method, wherein this method comprises also that in forming between these a plurality of patterning photoresist floor forming semi-transparency type respectively is masked in this transistor area and this contact mat district, and each this semi-transparency type mask is to should transistor area and this patterning photoresist floor in this contact mat district.
Aforesaid method, wherein this patterned transparent conductive layer comprises indium tin oxide layer or indium zinc oxide layer.
Aforesaid method wherein carries out also comprising and carrying out second ion implantation technology after this second etch process, utilizes this patterned aluminium layer to be used as mask, to form light dope source electrode/drain electrode in this patterned semiconductor layer of this transistor area.
The present invention mainly provides a kind of method of making dot structure, it particularly earlier forms the back at gate dielectric and covers by the dielectric layer that conductive layer, silica constituted that molybdenum constituted and aluminium lamination on gate dielectric, carry out isotropic etching technology then, evenly to remove this aluminium lamination of part in level and vertical direction simultaneously.Because generally being used for the etchant of etching aluminium lamination has the characteristic of isotropic etching, therefore in the etching aluminium lamination, not only the bottom of aluminium lamination can be etched to, and the sidewall of aluminium lamination also can be etched goes out follow-up needed light dope source electrode drain electrode length.In other words, the present invention can be reduced to twice with needed three road masks before being known in the formation regions and source by this manufacture method, and then reaches cost-effective purpose.In addition, according to a further embodiment of the invention, the present invention goes up at general capacitance electrode (that is above-mentioned by conductive layer that molybdenum constituted) again and forms the stacked structure that is made of silica and aluminium lamination, promotes the storage capacity of electric capacity then by this two-layer structure of piling up.
Description of drawings
Fig. 1 to Fig. 6 is the method for known making dot structure.
Fig. 7 to Figure 15 makes the method for dot structure for preferred embodiment of the present invention.
Wherein, description of reference numerals is as follows:
12 substrates, 14 transistor area
16 capacitive region, 18 patterned polysilicon layers
20 gate dielectrics, 22 patterning photoresist layers
24 regions and source, 26 grids
28 electric capacity top electrodes, 30 light dopes source electrode/drain electrode
32 dielectric layers, 34 contact holes
36 leads, 38 dielectric layers
40 openings, 42 pixel electrodes
62 substrates, 64 transistor area
66 capacitive region, 68 contact mat districts
70 patterned semiconductor layer, 72 gate dielectrics
74 conductive layers, 76 dielectric layers
78 electrode layers, 80 patterning photoresist layers
82 semi-transparency type masks areas, 83 full-transparency type masks areas
84 full shielded type masks area 86 regions and source
88 light dopes source electrode/drain electrode 90 dielectric layers
92 contact holes, 94 leads
96 dielectric layers, 98 openings
100 pixel electrodes
Embodiment
Please refer to Fig. 7 to Figure 15, Fig. 7 to Figure 15 makes the method for dot structure for preferred embodiment of the present invention.As described in Figure 7, at first provide substrate 62, substrate such as clear glass for example, and have at least one transistor area 64, capacitive region 66 and contact mat district 68 in the substrate 62.Form patterned semiconductor layer 70 then respectively in the substrate 62 in transistor area 64, capacitive region 66 and contact mat district 68.Wherein, the patterned semiconductor layer 70 of transistor area 64 is to be used for forming transistorized regions and source in subsequent technique, and the patterned semiconductor layer 70 of capacitive region 66 is then as capacitor lower electrode.Secondly, the step that forms patterned semiconductor layer 70 for example can be finished according to the standard step of general making low-temperature polycrystalline silicon layer.For example can form amorphous silicon layer (figure does not show) earlier and, carry out quasi-molecule laser annealing (excimer laser anneal) technology then, make amorphous silicon layer be converted into polysilicon layer in substrate 62 surfaces.Carry out Patternized technique subsequently again, remove the part polysilicon layer, in substrate 62, to form the patterned polysilicon layer.
Then as shown in Figure 8, form gate dielectric 72 earlier in substrate 62 surface and overlay pattern semiconductor layers 70, gate dielectric 72 for example is made of silica.Form conductive layer 74, dielectric layer 76 and electrode layer 78 then in regular turn on gate dielectric 72.Wherein, conductive layer 74 is made of the material of moisture-proof formula etch process, for example comprise that the molybdenum by about 2000 dusts of thickness is constituted, dielectric layer 76 for example comprises that the silica by about 500 dusts of thickness is constituted, and electrode layer 78 is made of the material that can wait tropism's Wet-type etching, be preferably aluminium lamination, for example about 4000 dust to 10000 dusts of the thickness of aluminium lamination.
As shown in Figure 9, then use etchant to wait tropism (isotropic) wet etch process, etchant for example is the mixed solution that utilizes phosphoric acid, acetic acid and nitric acid to form, and utilize patterning photoresist layer 80 to be used as mask, evenly to remove segment electrode layer 78 in level and vertical direction simultaneously.
Then as shown in figure 10, carry out etch process, utilize patterning photoresist layer 80 to be used as mask once more and remove part dielectric layer 76 and conductive layer 74, and then carry out ion implantation technology, utilize patterning photoresist layer 80 to be used as mask, with the patterned semiconductor layer 70 on P type or N type admixture injection substrate 62 surfaces, in the patterned semiconductor layer 70 of transistor area 64, to form regions and source 86.
Then as shown in figure 11, remove the patterning photoresist floor 80 in transistor area 64 and contact mat district 68 earlier, carry out another etch process then, utilize the electrode layer 78 in transistor area 64 and contact mat district 68 to be used as dielectric layer 76 and the conductive layer 74 that mask removes part in transistor area 64 and the contact mat district 68.Carry out another ion implantation technology subsequently, utilize the patterning photoresist floor 80 of remaining dielectric layer 76 of transistor area 64 and conductive layer 74, capacitive region 66 and touch pad district 68 remaining electrode layer 78, dielectric layer 76 and conductive layers 74 and be used as mask, in the patterned semiconductor layer 70 of transistor area 64, to form light dope source electrode/drain region 88.
As shown in figure 12, then carry out etch process, utilize the patterning photoresist floor 80 of capacitive region 66 to be used as the electrode layer 78 that mask removes transistor area 64 and contact mat district 68 earlier, and then remove the patterning photoresist layer 80 of capacitive region 66.So far the making of promptly finishing transistor, finishing electric capacity and finish contact mat in contact mat district 68 in capacitive region 66 in transistor area 64.
It should be noted that, because the present invention is used for the etchant of etched electrodes layer 78 and has the characteristic of isotropic etching, therefore when the use etchant comes electrode layer 78 to about 4000 dust to 10000 dusts of thickness to carry out etching, not only the bottom of electrode layer 78 can be etched to, and the sidewall of electrode layer 78 also can be etched goes out required lightly doped drain length (about 0.7 micron).In other words, be used for the etch process of control electrode layer 78 thickness by adjustment and can control the length of follow-up formation light dope source electrode/drain electrode again indirectly.According to preferred embodiment of the present invention, manufacture method of the present invention is except being reduced to required mask before being known in the formation regions and source the twice by three roads, can on the electrode of electric capacity, form the stacked structure of forming by silica and aluminium lamination again, and promote the storage capacity of electric capacity by this two-layer stacked structure.
Subsequently as shown in figure 13, form dielectric layer 90 in substrate 62, carry out Patternized technique then, for example utilize patterning photoresist layer (figure does not show) to be used as mask and carry out etch process, in dielectric layer 90, to form a plurality of contacts hole 92.Described in figure, respectively contact regions and source 86, the electrode layer 78 of capacitive region 66 and the conductive layer 74 in contact mat district 68 that hole 92 can expose transistor area 64 respectively in the dielectric layer 90.
Then as shown in figure 14, form patterned metal layer on dielectric layer 90 and fill up and respectively contact hole 92, to form many leads 94.
Then as shown in figure 15, form another dielectric layer 96 on lead 94, be used as flatness layer, and carry out Patternized technique, for example utilize patterning photoresist layer (figure does not show) to be used as mask and carry out etch process, in dielectric layer 96, to form a plurality of openings 98.Form the patterned transparent conductive layer that constituted by tin indium oxide or indium zinc oxide etc. subsequently on dielectric layer 96 and fill up each opening 98, to form corresponding pixel electrode 100.So far promptly finish the making of the dot structure of preferred embodiment of the present invention.
According to shown in Figure 15, the present invention discloses a kind of dot structure again and is formed in the substrate 62, and substrate 62 has transistor area 64 and capacitive region 66.Wherein, this dot structure includes: patterned semiconductor layer 70 is located at transistor area 64, and patterned semiconductor layer 70 has channel region, and the regions and source 86 that is positioned at these channel region both sides; First capacitance electrode (being the patterned semiconductor layer 70 of capacitive region 66) is located at capacitive region 66; Gate dielectric 72 is located in the substrate 62 and the patterned semiconductor layer 70 of covering transistor district 64 and capacitive region 66; Grid (being the conductive layer 74 of transistor area 64) is located on the channel region of patterned semiconductor layer 70; Second capacitance electrode (being the conductive layer 74 of capacitive region 66), dielectric layer 76 and the electrode layer 78 that aluminium constituted are located on the gate dielectric 72 of capacitive region 66; Dielectric layer 90 is located in the substrate 62 and is covered this grid and electrode layer 78; At least one lead 94 is located in the dielectric layer 90 and is electrically connected the source/drain regions 86 and electrode layer 80 of semiconductor layer 70; Dielectric layer 96 is located on the lead 94; And pixel electrode 100 is located on the dielectric layer 96 and is connected lead 94.
In sum, the present invention mainly provides a kind of method of making dot structure, it particularly earlier forms the back at gate dielectric and covers by the dielectric layer that conductive layer, silica constituted that molybdenum constituted and aluminium lamination on gate dielectric, carry out isotropic etching technology then, evenly to remove this aluminium lamination of part in level and vertical direction simultaneously.Because generally being used for the etchant of etching aluminium lamination has the characteristic of isotropic etching, therefore in the etching aluminium lamination, not only the bottom of aluminium lamination can be etched to, and the sidewall of aluminium lamination also can be etched goes out follow-up needed light dope source electrode/drain electrode length.In other words, the present invention can be reduced to twice with required mask before being known in the formation regions and source by three roads by this manufacture method, and then reaches cost-effective purpose.In addition, according to a further embodiment of the invention, the present invention again can be when making electric capacity goes up at capacitance electrode (that is above-mentioned by conductive layer that molybdenum constituted) and forms the stacked structure that is made of silica and aluminium lamination, and promotes the storage capacity of electric capacity by this two-layer structure of piling up.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (24)
1. method of making dot structure comprises:
Substrate is provided, has at least one transistor area and capacitive region in this substrate;
Form patterned semiconductor layer respectively in this transistor area and this capacitive region;
The formation gate dielectric is in this substrate surface and cover this patterned semiconductor layer;
Form conductive layer, dielectric layer and electrode layer in regular turn in this substrate;
Form a plurality of patterning photoresist layers in this electrode layer surface of this transistor area and this capacitive region;
Carry out isotropic etching technology, utilize these a plurality of patterning photoresist layers to be used as mask, evenly to remove this electrode layer of part in level and vertical direction simultaneously;
Carry out first etch process, utilize these a plurality of patterning photoresist layers to be used as mask and remove this dielectric layer of part and this conductive layer;
Carry out first ion implantation technology, utilize these a plurality of patterning photoresist layers to be used as mask, in this patterned semiconductor layer of this transistor area, to form regions and source;
Remove this patterning photoresist layer of this transistor area;
Carry out second etch process, utilize this patterned electrode layer to be used as mask, remove this dielectric layer of part and this conductive layer;
Carry out second ion implantation technology, utilize these a plurality of patterning photoresist layers to be used as mask, in this patterned semiconductor layer of each this transistor area, to form light dope source electrode/drain electrode;
Carry out the 3rd etch process, utilize this pattern photoresist layer of this capacitive region to be used as this electrode layer that mask is removed this transistor area;
Remove this patterning photoresist layer of this capacitive region;
Form first dielectric layer in this substrate, and form a plurality of first contact holes in this first dielectric layer;
The formation patterned metal layer is on this first dielectric layer and fill up each this first contact hole, to form many first leads;
Form second dielectric layer on these a plurality of first leads, and form a plurality of first and be opened in this second dielectric layer; And
The formation patterned transparent conductive layer is on this second dielectric layer and fill up each this first opening, to form a plurality of pixel electrodes.
2. the method for claim 1, the step that wherein forms each this patterned semiconductor layer also comprises:
Form amorphous silicon layer in this substrate surface;
Carry out quasi-molecule laser annealing technology, make this amorphous silicon layer be converted into polysilicon layer; And
Carry out Patternized technique, remove this polysilicon layer of part, in this substrate, to form these a plurality of patterned semiconductor layer.
3. the method for claim 1, wherein the material of this conductive layer comprises molybdenum.
4. the method for claim 1, wherein the material of this electrode layer comprises aluminium.
5. the method for claim 1, wherein about 4000 dust to 10000 dusts of the thickness of this electrode layer.
6. the method for claim 1, wherein this method comprised also that before forming a plurality of patterning photoresist layers forming semi-transparency type is masked in this transistor area, and this semi-transparency type mask is to this patterning photoresist layer that should transistor area.
7. the method for claim 1, wherein this transparency conducting layer comprises indium tin oxide layer or indium zinc oxide layer.
8. a dot structure is formed in the substrate, and this substrate has transistor area and capacitive region, and this dot structure comprises:
Patterned semiconductor layer is located at this transistor area, and this patterned semiconductor layer has channel region, and the source/drain regions that is positioned at these channel region both sides;
First capacitance electrode is located at this capacitive region;
Gate dielectric is located in this substrate and is covered this patterned semiconductor layer and this first capacitance electrode;
Grid is located on this channel region of this patterned semiconductor layer;
Second capacitance electrode, first dielectric layer and aluminium lamination capacitance electrode are located on this gate dielectric of this capacitive region;
First dielectric layer is located in this substrate and is covered this grid and this aluminium lamination capacitance electrode;
At least one first lead is located in this first dielectric layer, electrically connects this source/drain regions and this aluminium lamination capacitance electrode of this semiconductor layer;
Second dielectric layer is located on these a plurality of first leads; And
First transparency conducting layer is located on this second dielectric layer and these a plurality of first leads of connection.
9. dot structure as claimed in claim 8, wherein this second capacitance electrode comprises molybdenum.
10. dot structure as claimed in claim 8, wherein this first dielectric layer comprises silica.
11. dot structure as claimed in claim 8, wherein about 4000 dust to 10000 dusts of the thickness of this aluminium lamination capacitance electrode.
12. dot structure as claimed in claim 8, wherein this first transparency conducting layer is indium tin oxide layer or indium zinc oxide layer.
13. dot structure as claimed in claim 8, wherein this substrate also comprises the contact mat district, and this patterned semiconductor layer is located in this substrate in this contact mat district; This gate dielectric is located in this substrate in this contact mat district and is covered this patterned semiconductor layer; And this dot structure also comprises:
The conductive layer and second dielectric layer are located on this gate dielectric, and wherein, this first dielectric layer is located in this substrate and is covered this second dielectric layer;
Second lead is located in this first dielectric layer and is connected this conductive layer, and wherein, this second dielectric layer is located on this second lead; And
Second transparency conducting layer is located on this second dielectric layer and is connected this second lead.
14. dot structure as claimed in claim 13, wherein this conductive layer comprises molybdenum.
15. dot structure as claimed in claim 13, wherein this second dielectric layer comprises silica.
16. dot structure as claimed in claim 13, wherein this second transparency conducting layer is indium tin oxide layer or indium zinc oxide layer.
17. a method of making dot structure comprises:
Substrate is provided, has transistor area, capacitive region and contact mat district at least in this substrate;
Form patterned semiconductor layer respectively in this transistor area, this capacitive region and this contact mat district;
The formation gate dielectric is in this substrate surface and cover this patterned semiconductor layer;
Form conductive layer, dielectric layer and aluminium lamination in regular turn in this substrate;
Form a plurality of patterning photoresist floor this aluminium lamination surface in this transistor area, this capacitive region and this contact mat district;
Carry out isotropic etching technology, utilize these a plurality of patterning photoresist layers to be used as mask, evenly to remove this aluminium lamination of part in level and vertical direction simultaneously;
Carry out first etch process, utilize these a plurality of patterning photoresist layers to be used as mask and remove this dielectric layer of part and this conductive layer;
Carry out first ion implantation technology, utilize these a plurality of patterning photoresist layers to be used as mask, in this patterned semiconductor layer of this transistor area, to form regions and source;
Remove this patterning photoresist floor in this transistor area and this contact mat district;
Carry out second etch process, utilize this patterned aluminium layer to be used as mask, remove this dielectric layer of part and this conductive layer;
Carry out the 3rd etch process, utilize this patterning photoresist floor of this capacitive region to be used as this aluminium lamination that mask is removed this transistor area and this contact mat district;
Remove this patterning photoresist layer of this capacitive region;
Form first dielectric layer in this substrate and form a plurality of first the contact holes in this first dielectric layer;
The formation patterned metal layer is on this first dielectric layer and fill up each this first contact hole, to form many first leads;
Form second dielectric layer on these a plurality of first leads, and form a plurality of first and be opened in this second dielectric layer; And
The formation patterned transparent conductive layer is on this second dielectric layer and fill up each this first opening, to form a plurality of pixel electrodes.
18. method as claimed in claim 17, the step that wherein forms this patterned semiconductor layer also comprises:
Form amorphous silicon layer in this substrate surface;
Carry out quasi-molecule laser annealing technology, make this amorphous silicon layer be converted into polysilicon layer; And
Carry out Patternized technique, remove this polysilicon layer of part, in this substrate, to form this patterned semiconductor layer.
19. method as claimed in claim 17, wherein this conductive layer comprises molybdenum.
20. method as claimed in claim 17, wherein this dielectric layer comprises silica.
21. method as claimed in claim 17, wherein about 4000 dust to 10000 dusts of the thickness of this aluminium lamination.
22. method as claimed in claim 17, wherein comprise also that in forming between these a plurality of patterning photoresist floor forming semi-transparency type respectively is masked in this transistor area and this contact mat district, and each this semi-transparency type mask is to should transistor area and this patterning photoresist floor in this contact mat district.
23. method as claimed in claim 17, wherein this patterned transparent conductive layer comprises indium tin oxide layer or indium zinc oxide layer.
24. method as claimed in claim 17, wherein carry out after this second etch process, also comprise and carry out second ion implantation technology, utilize this patterned aluminium layer to be used as mask, in this patterned semiconductor layer of this transistor area, to form light dope source electrode/drain electrode.
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| CNB2007101400232A CN100521164C (en) | 2007-08-07 | 2007-08-07 | Pixel structure and its making method |
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| CNB2007101400232A CN100521164C (en) | 2007-08-07 | 2007-08-07 | Pixel structure and its making method |
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| CN101101893A true CN101101893A (en) | 2008-01-09 |
| CN100521164C CN100521164C (en) | 2009-07-29 |
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| CN (1) | CN100521164C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315230A (en) * | 2010-07-01 | 2012-01-11 | 三星移动显示器株式会社 | Array substrate and manufacturing approach thereof and display device |
| CN103383989A (en) * | 2013-03-25 | 2013-11-06 | 友达光电股份有限公司 | Manufacturing method of pixel structure and structure thereof |
| CN102315230B (en) * | 2010-07-01 | 2016-12-14 | 三星显示有限公司 | Array substrate and manufacture method thereof and display device |
| CN107706198A (en) * | 2017-07-25 | 2018-02-16 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
| WO2018119649A1 (en) * | 2016-12-27 | 2018-07-05 | 深圳市柔宇科技有限公司 | Array substrate and method for preparing array substrate |
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2007
- 2007-08-07 CN CNB2007101400232A patent/CN100521164C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315230A (en) * | 2010-07-01 | 2012-01-11 | 三星移动显示器株式会社 | Array substrate and manufacturing approach thereof and display device |
| CN102315230B (en) * | 2010-07-01 | 2016-12-14 | 三星显示有限公司 | Array substrate and manufacture method thereof and display device |
| CN103383989A (en) * | 2013-03-25 | 2013-11-06 | 友达光电股份有限公司 | Manufacturing method of pixel structure and structure thereof |
| US9224868B2 (en) | 2013-03-25 | 2015-12-29 | Au Optronics Corp. | Pixel structure |
| CN103383989B (en) * | 2013-03-25 | 2016-01-27 | 友达光电股份有限公司 | Manufacturing method of pixel structure and structure thereof |
| WO2018119649A1 (en) * | 2016-12-27 | 2018-07-05 | 深圳市柔宇科技有限公司 | Array substrate and method for preparing array substrate |
| CN107706198A (en) * | 2017-07-25 | 2018-02-16 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
| US10615195B2 (en) | 2017-07-25 | 2020-04-07 | Au Optronics Corporation | Array substrate with openings in insulation layer for auxiliary elecrode |
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| Publication number | Publication date |
|---|---|
| CN100521164C (en) | 2009-07-29 |
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