WO2018118082A1 - Revêtements graphitiques pour dispositifs à circuits intégrés - Google Patents

Revêtements graphitiques pour dispositifs à circuits intégrés Download PDF

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Publication number
WO2018118082A1
WO2018118082A1 PCT/US2016/068512 US2016068512W WO2018118082A1 WO 2018118082 A1 WO2018118082 A1 WO 2018118082A1 US 2016068512 W US2016068512 W US 2016068512W WO 2018118082 A1 WO2018118082 A1 WO 2018118082A1
Authority
WO
WIPO (PCT)
Prior art keywords
liner
conductive
graphene
conductive material
insulating material
Prior art date
Application number
PCT/US2016/068512
Other languages
English (en)
Inventor
Kanwaljit SINGH
Jasmeet S. Chawla
Jessica M. TORRES
Roman CAUDILLO
Kevin L. Lin
Aranzazu MAESTRE CARO
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2016/068512 priority Critical patent/WO2018118082A1/fr
Publication of WO2018118082A1 publication Critical patent/WO2018118082A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

L'invention concerne des revêtements graphitiques pour des dispositifs à circuit intégré (IC), ainsi que des dispositifs et des procédés associés. Par exemple, l'invention concerne des revêtements qui comprennent du graphène ayant un gradient de qualité, des revêtements multicouches (par exemple, comprenant des couches de métal et de graphène), et des revêtements qui relient les parois latérales d'un trou d'interconnexion tout en laissant un fond du trou d'interconnexion ouvert pour un contact direct avec une structure conductrice inférieure.
PCT/US2016/068512 2016-12-23 2016-12-23 Revêtements graphitiques pour dispositifs à circuits intégrés WO2018118082A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2016/068512 WO2018118082A1 (fr) 2016-12-23 2016-12-23 Revêtements graphitiques pour dispositifs à circuits intégrés

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2016/068512 WO2018118082A1 (fr) 2016-12-23 2016-12-23 Revêtements graphitiques pour dispositifs à circuits intégrés

Publications (1)

Publication Number Publication Date
WO2018118082A1 true WO2018118082A1 (fr) 2018-06-28

Family

ID=62627654

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2016/068512 WO2018118082A1 (fr) 2016-12-23 2016-12-23 Revêtements graphitiques pour dispositifs à circuits intégrés

Country Status (1)

Country Link
WO (1) WO2018118082A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030129826A1 (en) * 2000-03-07 2003-07-10 Werkhoven Christiaan J. Graded thin films
US20040014320A1 (en) * 2002-07-17 2004-01-22 Applied Materials, Inc. Method and apparatus of generating PDMAT precursor
US20130015581A1 (en) * 2011-07-13 2013-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for high performance interconnect
US20130113102A1 (en) * 2011-11-08 2013-05-09 International Business Machines Corporation Semiconductor interconnect structure having a graphene-based barrier metal layer
US20140145332A1 (en) * 2012-11-26 2014-05-29 Globalfoundries Inc. Methods of forming graphene liners and/or cap layers on copper-based conductive structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030129826A1 (en) * 2000-03-07 2003-07-10 Werkhoven Christiaan J. Graded thin films
US20040014320A1 (en) * 2002-07-17 2004-01-22 Applied Materials, Inc. Method and apparatus of generating PDMAT precursor
US20130015581A1 (en) * 2011-07-13 2013-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for high performance interconnect
US20130113102A1 (en) * 2011-11-08 2013-05-09 International Business Machines Corporation Semiconductor interconnect structure having a graphene-based barrier metal layer
US20140145332A1 (en) * 2012-11-26 2014-05-29 Globalfoundries Inc. Methods of forming graphene liners and/or cap layers on copper-based conductive structures

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