WO2018111289A1 - Interconnexions fournies par dépôt à base d'espaceur métallique soustractif - Google Patents

Interconnexions fournies par dépôt à base d'espaceur métallique soustractif Download PDF

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Publication number
WO2018111289A1
WO2018111289A1 PCT/US2016/067069 US2016067069W WO2018111289A1 WO 2018111289 A1 WO2018111289 A1 WO 2018111289A1 US 2016067069 W US2016067069 W US 2016067069W WO 2018111289 A1 WO2018111289 A1 WO 2018111289A1
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Prior art keywords
interconnect
electrically conductive
interconnects
metallization stack
elements
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PCT/US2016/067069
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English (en)
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Robert L. Bristol
Kevin L. Lin
Florian Gstrein
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Intel Corporation
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Priority to PCT/US2016/067069 priority Critical patent/WO2018111289A1/fr
Publication of WO2018111289A1 publication Critical patent/WO2018111289A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

Definitions

  • FIG. 1 is a cross-sectional side view of a metallization stack including a plurality of electrically conductive interconnects, in accordance with various embodiments.
  • FIGS. 2-11 illustrate various example stages in the manufacture of a metallization stack including a plurality of electrically conductive interconnects, in accordance with various
  • FIGS. 12A-12B are cross-sectional side views of portions of example metallization stacks with interconnects formed by subtractive metal spacer based deposition, in accordance with various embodiments.
  • FIG. 13 is a flow diagram of an example method of manufacturing a metallization stack including a plurality of electrically conductive interconnects by subtractive metal spacer based deposition, in accordance with various embodiments.
  • FIGS. 14A and 14B are top views of a wafer and dies that include one or more metallization stacks with interconnects formed by subtractive metal spacer based deposition in accordance with any of the embodiments disclosed herein.
  • FIG. 15 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more metallization stacks with interconnects formed by subtractive metal spacer based deposition in accordance with any of the embodiments disclosed herein.
  • IC integrated circuit
  • FIG. 16 is a cross-sectional side view of an IC device assembly that may include one or more metallization stacks with interconnects formed by subtractive metal spacer based deposition in accordance with any of the embodiments disclosed herein.
  • FIG. 17 is a block diagram of an example computing device that may include one or more metallization stacks with interconnects formed by subtractive metal spacer based deposition in accordance with any of the embodiments disclosed herein. Detailed Description
  • a method of forming a semiconductor device may include providing a pattern of sacrificial elements over an interconnect support layer, depositing an electrically conductive material on sidewalls of the sacrificial elements, and removing the sacrificial elements so that the remaining portions of the electrically conductive material form a pattern of electrically conductive elements which can serve as interconnects of a metallization stack of the semiconductor device.
  • the performance of a semiconductor electronic device may depend on the number of factors.
  • One factor is the resistance of the metal interconnects that provide electrical connectivity for the device.
  • An interconnect with a lower resistance enables charge carriers to move more quickly in response to a given electric field than an interconnect with a higher resistance; thus, decreased resistance of interconnects may be associated with improved performance.
  • interconnects fabricated according to the methods disclosed herein are made of electrically conductive materials deposited as a continuous sheet, this sheet can then be annealed to form relatively large grains. Once the interconnects are subtractively formed from this sheet, there will be relatively fewer grain boundaries, which means that current traveling along a given interconnect encounters less such boundaries along the length of the interconnect. Having reduced amount of grain boundaries is associated with smaller resistivity of the electrically conductive material, leading to decreased resistance of an interconnect formed of such a material.
  • Another advantage enabled by the methods described herein is the ability to see alignment and metrology marks in the frame of the die during deposition of interconnects.
  • such marks provide guidance as to the exact locations where e.g. interconnects of a particular layer of a metallization stack are to be provided, so that the interconnects correctly line up with devices or/and other interconnects in a layer below or a layer above.
  • Prior art methods of providing interconnects by, first, depositing a layer of metal, and then patterning the metal to form interconnects of desired shapes and in desired patterns did not allow taking a full advantage of the alignment and metrology marks because they could not be seen behind the layer of metal.
  • Interconnects and metallization stacks are described herein may be used for providing electrical connectivity to one or more components associated with an integrated circuit (IC) or/and between various such components.
  • components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc.
  • Components associated with an IC may include those that are mounted on IC or those connected to an IC.
  • the IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC.
  • the IC may be employed as part of a chipset for executing one or more related functions in a computer.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term "between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • a "high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide.
  • a term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide.
  • interconnect is used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components.
  • the "interconnect” may refer to both trenches (also sometimes referred to as "lines") and vias.
  • a term “trench” is used to describe an electrically conductive element isolated by an interconnect support layer typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such trenches are typically stacked into several levels.
  • via is used to describe an electrically conductive element that interconnects two or more trenches of different levels. To that end, vias are provided substantially perpendicularly to the plane of an IC chip.
  • a via may interconnect two trenches in adjacent levels or two trenches in not adjacent levels.
  • a term “metallization stack” refers to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip.
  • the terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art.
  • FIG. 1 is a cross-sectional side view of a metallization stack 100 including an interconnect support layer 102 housing a plurality of electrically conductive interconnects 104, in accordance with various embodiments. Only one interconnect 104 is labeled with a reference numeral in FIG. 1 for ease of illustration, but eight are illustrated in FIG. 1. Although eight interconnects 104 are illustrated in FIG. 1, this is also simply for ease of illustration, and more, or less, than eight interconnects 104 may be provided on the interconnect support layer 102 according to various embodiments of the present disclosure. Furthermore, note that the metallization stack 100 shown in FIG. 1, as well as structures illustrated in FIGS. 2-8A are intended to show relative arrangements of the components therein, and that various metallization stacks, or portions thereof, may include other components that are not illustrated (e.g., electrical contacts to the interconnects 104).
  • implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V, group ll-VI, or group IV materials.
  • the interconnect support layer 102 may include any such substrate, possibly with some layers and/or devices already formed thereon, that provides a suitable surface for providing the interconnects 104 on.
  • an etch stop layer 106 is shown to be disposed over the interconnect support layer 102, which layer may serve to prevent or minimize etching into the underlying interconnect support layer 102 during fabrication of the interconnects 104 or any further components associated with an integrated circuit.
  • presence of such a layer is entirely optional and embodiments of the present disclosure may be carried out on the interconnect support layer 102 within the etch stop layer 106 shown in FIGS. 1- 8A.
  • interconnect support layer 102 may be provided on at least some portions of the interconnect support layer 102 prior to the deposition of the interconnects 104, such as e.g. an insulating layer, such as an oxide isolation layer.
  • interconnects 104 of the metallization stack may be provided over the interconnects 104 of the metallization stack.
  • One such material is a dielectric material, e.g. including one or more interlayer dielectrics (ILD) layers, that may be deposited over the and in between the interconnects 104 of the metallization stack 100.
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
  • FIGS. 2-11 illustrate various example stages in the manufacture of a metallization stack including a plurality of electrically conductive interconnects, such as e.g. the metallization stack 100 with the interconnects 104, in accordance with various embodiments.
  • FIG. 2 illustrates a cross-sectional view of an assembly 202 including an interconnect support layer 102 and an etch stop layer 106 provided thereon. Discussions provided above with respect to the interconnect support layer 102 and the etch stop layer 106 are applicable here and, therefore, in the interests of brevity, are not repeated here.
  • FIG. 3 illustrates a cross-sectional view of an assembly 204 subsequent to providing a pattern of sacrificial elements 108 over the interconnect support layer 102 of the assembly 202 (FIG. 2). Only one sacrificial element 108 is labeled with a reference numeral in FIG. 3 for ease of illustration, but four are illustrated in FIG. 3. Although four sacrificial elements 108 are illustrated in FIG. 3, this is also simply for ease of illustration, and more, or less, than four sacrificial elements 108 may be provided on the interconnect support layer 102 according to various embodiments of the present disclosure.
  • the pattern of sacrificial elements 108 may be a plurality of parallel lines having a height (i.e. the dimension in the z-direction of an exemplary reference coordinate system shown in FIG. 3) between 5 and 1000 nanometers, including all values and ranges therein, and a width (i.e. the dimension in the y-direction of the exemplary reference coordinate system shown in FIG. 3) between 5 and 300 nanometers, including all values and ranges therein.
  • any other suitable pattern may be used, selected/designed so that, in subsequent fabrication steps, the electrically conductive material deposited on the sidewalls (i.e. the faces of the elements 108 which are substantially perpendicular to the interconnect support layer 102) of the sacrificial elements 108 will form appropriately shaped and appropriately located interconnects.
  • the aspect ratio (i.e. a ratio of height to width) of the sacrificial elements 108 could be between 1 and 10, e.g. between 1 and 5 or between 1 and 3.
  • the sacrificial elements 108 may be spaced by any suitable spacing that would allow depositing electrically conductive material of the desired thickness on the sidewalls of the sacrificial elements 108 so that the electrically conductive material on adjacent sidewalls of two adjacent elements 108 is not touching one another.
  • the distance between different sacrificial elements 108 may be above 30 nanometers, e.g. above 50 nanometers.
  • the sacrificial elements 108 may be formed of a non-metallic material. Since the sacrificial elements 108 will need to later be etched to leave the electrically conductive material deposited on their sidewalls, e.g. using anisotropic etching, etching properties of potential candidate materials are to be considered when selecting a suitable material to be used as the sacrificial elements 108. In addition, etching properties of a potential candidate material for the sacrificial elements 108 should are to be considered in view of a potential candidate electrically conductive material for forming the interconnects as described herein.
  • the material for the sacrificial elements 108 and the electrically conductive material for the future interconnects 104 have sufficiently distinct etching properties so that etch of the sacrificial elements 108 will not affect, or will only have an adequately small effect, on the electrically conductive material (i.e. these two materials should have high etch selectivity with respect to one another).
  • etching properties some other considerations in selecting a suitable material for the sacrificial elements 108 may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability).
  • Examples of materials that could be used to form the sacrificial elements 108 include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane, polytetrafluoroethylene or poly(methyl methacrylate) (PMMA), fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the sacrificial elements 108 may be provided over the interconnect support layer 102 using e.g. chemical vapor deposition or/and plasma-enhanced chemical vapor deposition, in combination with patterning (either before or after the deposition of the material of the sacrificial elements 108), as typically done in conventional processing.
  • patterning may include any patterning technique employing photoresist or other masks defining the dimensions and location of the sacrificial elements 108 over the interconnect support layer 102.
  • patterning may include any mask-less patterning technique, such as e.g.
  • FIG. 4 illustrates a cross-sectional view of an assembly 206 subsequent to conformally depositing a layer 110 of electrically conductive material on the sidewalls and in openings between the sacrificial elements 108 of the assembly 204 (FIG. 3).
  • Conformal deposition generally refers to deposition of a certain coating (in this case - the electrically conductive material that will form the interconnects 104) on any exposed surface of a given structure (in this case - the interconnect support layer with the sacrificial elements 108 of the assembly 204), including on the sidewalls and bottom of any opening formed in/on the structure.
  • a conformal coating may, therefore, be understood as a coating that is applied to exposed surfaces of a given structure, and not, for example, just to horizontal surfaces.
  • the coating may exhibit a variation in thickness of less than 35%, including all values and ranges from 1% to 35%, such as 10% or less, 15% or less, 20% of less, 25% or less, etc.
  • the conformal coating process may be selected from processes such as e.g. chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • a thickness of the layer 110 in particular the thickness of the layer 110 on the sidewalls of the sacrificial elements 108 (i.e. the dimension in the y-direction of an exemplary reference coordinate system shown in FIG. 3), may take on any suitable values so that, in subsequent fabrication steps, the electrically conductive material deposited on the sidewalls of the sacrificial elements 108 will form interconnects 104 of appropriate dimensions, the latter described in greater detail below.
  • an annealing process may be carried out on the layer 110 after its deposition to improve the quality of the electrically conductive material for the future interconnects 104.
  • the electrically conductive material of the layer 110 may include one or more of aluminum, copper, tungsten, cobalt, ruthenium, nickel, iron, and molybdenum, and/or one or more alloys comprising aluminum, copper, tungsten, cobalt, ruthenium, manganese, magnesium, boron, phosphorus, nitrogen, carbon, and sulfur.
  • FIG. 5 illustrates a cross-sectional view of an assembly 208 subsequent to anisotropic etch of the layer 110 of the electrically conductive material deposited on the sidewalls and in the openings between the sacrificial elements 108 in the assembly 206 (FIG. 4).
  • Any suitable anisotropic etching technique i.e. etching uniformly in vertical direction
  • Dry etching techniques such as e.g.
  • the layer 110 made of metallic aluminum (Al) can be readily and anisotropically etched with chlorine (CI) plasma by forming volatile AI2C , where volatile AhC is removed, resulting in patterned Al that remains only on the sidewalls, and possibly on top of, the sacrificial elements 108.
  • CI chlorine
  • FIGS. 4 and 5 illustrate one exemplary embodiment for depositing an electrically conductive material on the sidewalls of the sacrificial elements 108.
  • other techniques may be used. For example, instead of a conformal deposition process shown in FIG. 4, other processes may be used that would deposit the electrically conductive material directly only, or substantially only, on the sidewalls of the sacrificial elements 108.
  • Such alternative processed may e.g. include physical vapor deposition (PVD) processes such as, magnetron sputtering with a high re- sputter rate with no net deposition on horizontal surfaces and only sidewall deposition , evaporative deposition or e-beam deposition, and may directly result in the assembly 208 as shown in FIG. 5 without the need for the anisotropic etch described above.
  • PVD physical vapor deposition
  • planarization of the assembly 208 may be subsequently performed, in order to expose the material of the sacrificial elements 108 for the subsequent etching of this material.
  • Planarization may be performed using either wet or dry planarization processes.
  • planarization is performed using chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden of the electrically conductive material which may cover upper surfaces of the sacrificial elements 108 to expose such surfaces for the subsequent etch.
  • CMP chemical mechanical planarization
  • FIG. 6 illustrates a cross-sectional view of an assembly 210 subsequent to the removal of the sacrificial elements 108 from between the electrically conductive material deposited on the sidewalls of the sacrificial elements 108 in the assembly 208 (FIG. 5).
  • a removal may include anisotropic etch to vertically etch away the material of the sacrificial elements 108.
  • Etchants used in this etch would be different from those described above for etching the electrically conductive material, because this time, preferably, the electrically conductive material would not be etched. Any substance suitable for anisotropically etching the sacrificial elements 108 may be used in forming the assembly 210.
  • each interconnect 104 may be between 5 and 30 nanometers, while an average height of each interconnect may be between 5 and 1000 nanometers, including all values and ranges therein.
  • the interconnects 104 may have a pitch, i.e.
  • a distance between the centerlines of two interconnects 104 next to one another of between 10 and 100 nanometers, including all values and ranges therein, e.g. between 10 and 45 nanometers or between 20 and 40 nanometers.
  • An average width and an average height of each interconnect 104 may be specified in terms of the pitch, e.g. the width could be substantially half of the pitch, while the height could be substantially 1.5 times of the pitch.
  • FIG. 7 illustrates a cross-sectional view of an assembly 212 subsequent to filling the spaces between the interconnects 104 of the assembly 210 (FIG. 6) with a suitable dielectric material 112, such as e.g. any of the ILD materials described herein.
  • the dielectric material 112 may be provided into the spaces between the interconnects 104 using e.g. CVD and/or plasma- enhanced CVD, as typically done in conventional processing.
  • the dielectric material 112 may include a dielectric material formed in the spaces between the interconnects 104 using coating techniques involving cross-linking of liquid precursors into solid dielectric materials.
  • some or all of the surfaces of the interconnects 104 of the assembly 210 may be cleaned or treated prior to applying the dielectric 112, e.g. to reduce surface contamination, minimize interface traps, promote adhesion, and/or decrease interdiffusion of materials.
  • the surfaces of the interconnects 104 may be cleaned using chemical or plasma clean, or applying heat in a controlled environment.
  • an "interface layer” may be applied between on the interconnects 104 of the assembly 210, in particular on the sidewalls of the interconnects 104, to prevent, decrease, or minimize spontaneous and uncontrolled formation of other interfacial layers.
  • an adhesion promoter or adhesion layer may be applied prior to application of the dielectric 112, in order to promote adhesion between the electrically conductive material of the interconnects 104 and the material(s) of the dielectric 112 filling the space between the interconnects 104.
  • Example materials which could be used to form an adhesion layer between the electrically conductive material of the interconnects and the dielectric 112 include, but are not limited to molecular species such as self-assembled monolayers (SAMs). These molecules typically include a head group, an alkane chain, and an end group. The head group could be a thiol or nitrile which forms a bond with the conductive material. The end group could be an amine, silane, ethoxy silane, chloro silane or amino silane which forms bonds with the dielectric.
  • a diffusion barrier layer may be conformally deposited, using any suitable conformal deposition techniques as described herein, on the sidewalls of at least some, preferably all, of the interconnects 104, for preventing diffusion of the electrically conductive material of the interconnects 104 out of these elements and into the surrounding dielectric material 112.
  • a diffusion barrier layer may be electrically conductive
  • the diffusion barrier layer examples include, but are not limited to, one or more of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium ( u), cobalt (Co), silicon nitride (SiN), silicon carbide (SiC), silicon dioxide (Si02), aluminum oxide (AI203), and the like.
  • the method may further include providing a barrier-dielectric adhesion layer on sidewalls of at least some of the interconnects 104 covered with a diffusion barrier layer, in order to promote adhesion between the material of the diffusion barrier layer and the material(s) of the dielectric 112 that will fill the space between the interconnects 104.
  • Example materials which could be used to form a barrier-dielectric adhesion layer include, but are not limited to, tantalum, titanium, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, and the like.
  • planarization may be performed again, e.g. using any of the planarization techniques described above, to expose the upper surfaces of the interconnects 104 so that the interconnects 104 may be electrically connected to further circuit elements (not specifically shown in FIG. 7).
  • FIG. 8 illustrates a cross-sectional view of an assembly 214 subsequent to providing a layer of cover material 114 over the assembly 212 of FIG. 7.
  • the layer of cover material 114 may e.g. be one of the electrically conductive materials described herein and may be deposited using any suitable method, such as e.g. sputtering, CVD, ALD, PVD, etc.
  • FIG. 9 illustrates a cross-sectional view of an assembly 216 subsequent to providing an opening 116 in the layer of cover material 114 of the assembly 214 of FIG. 8.
  • the opening 116 may be formed using any patterning techniques as known in the art, such as e.g. lithographic patterning and etching.
  • the opening 116 may expose at least one interconnect 104. While FIG. 9 illustrates only a single opening 116, exposing a single interconnect 104, in other embodiments, multiple such openings, each opening exposing more than a single interconnect 104, may be provided.
  • FIG. 10 illustrates a cross-sectional view of an assembly 218 subsequent to removing the material of the exposed interconnect 104 through the opening 116, thus forming an extended opening 118 that extends down to the substrate 102 or the etch-stop layer 106, as shown.
  • the extended opening 118 may be formed using any suitable technique as known in the art, such as e.g. anisotropic etching.
  • FIG. 11 illustrates a cross-sectional view of an assembly 220 subsequent to filling the extended opening 118 of the assembly 218 (FIG. 10) with a suitable dielectric material 120, such as e.g. any of the ILD materials described herein.
  • the dielectric material 120 may be provided into the extended opening 118 using e.g. CVD and/or plasma-enhanced CVD, as typically done in conventional processing.
  • the dielectric material 120 may include a dielectric material formed in the extended opening 118 using coating techniques involving cross-linking of liquid precursors into solid dielectric materials.
  • the dielectric material 118 may be the same as the surrounding dielectric material 112.
  • these two dielectric materials may be different dielectric materials.
  • the dielectric material 120 provided into openings such as the opening 118 forms what can be seen as a "plug" among the interconnects 104, forming a break or a cut in the electrically conductive wire as to electrically isolate two regions of a circuit, as needed for a particular design. Therefore, dimensions of such plugs would typically be comparable or substantially the same as the dimensions of the removed interconnects 104.
  • fabricating the interconnects 104 by depositing the electrically conductive material of the interconnects 104, typically a metal, in a spacer-like fashion (i.e. as a "spacer" around the sacrificial elements 108), followed by the removal of the sacrificial elements 108, as described above, justifies the name "subtractive metal spacer based deposition” given to the methods of fabricating interconnects described herein. Implementing these methods may allow realizing several advantages, in particular when compared to conventional methods of providing interconnects by, first, depositing a layer of metal, and then patterning the metal to form interconnects of desired shapes and in desired patterns.
  • One advantage is that the methods described herein do not obscure alignment and metrology marks in the frame of the die during deposition of interconnects.
  • a width of an individual interconnect i.e. the dimension in the y- direction of the exemplary reference system shown in the FIGS.
  • a height of that interconnect may vary by less than 10 percent, preferably less than 5%, e.g. less than 3 or 2%, of an average width of the interconnect along the height of the interconnect.
  • Having a width of an interconnect varying by less than a certain, relatively small, amount compared to the average width along the height of the interconnect indicates that the sidewalls of the interconnect have relatively low surface roughness.
  • Such relatively slow surface roughness may be advantageously achieved using the methods of forming electrically conductive interconnects as described herein and was not possible to achieve using prior art fabrication techniques.
  • Metallization stacks as descried herein may be particularly advantageous when used in the metal layers of a microprocessor device for analog circuitry, logic circuitry, or memory circuitry, and may be formed along with existing complementary metal oxide semiconductor (CMOS) processes.
  • CMOS complementary metal oxide semiconductor
  • FIG. 12A depicts a cross-sectional side view of a metallization stack 100 with the dielectric material disposed between the interconnects 104, except that only six of the interconnects 104 are shown, labeled as interconnects 104-1, 104-2, 104-3, 104-4, 104-5, and 104-6.
  • FIG. 12A illustrates the interconnect support layer 102, the optional etch stop layer 106, and the dielectric material 112 surrounding the interconnects 104, as described above.
  • FIG. 12A is drawn to reflect example real-world process limitations, in that the features are not drawn with precise right angles and straight lines. Such limitations could e.g. be observed in transmission electron microscopy (TEM) images of cross-sections of metallization stacks.
  • TEM transmission electron microscopy
  • One example real-world process limitation is rounding of some upper corners of the interconnects, as labeled in FIG. 12A with corners 114 and 120 of the interconnects 104-1 and 104-4, respectively.
  • the other upper corners of the interconnects are not rounded, as labeled in FIG. 12A with corners 116 and 118 of the interconnects 104-1 and 104-4, respectively.
  • all interconnects shown in FIG. 12A illustrate this pattern. This rounding of one corner of each interconnect but not the other may be explained as follows.
  • both upper corners of each sacrificial element covered with the electrically conductive material may be rounded.
  • each corner belongs to a different interconnect - e.g. interconnects 104-1 and 104-2 were formed around the first sacrificial element between them, interconnects 104-3 and 104-4 were formed around the second sacrificial element between them, and interconnects 104-5 and 104-6 were formed around the third sacrificial element between them.
  • each interconnect which were closest to the respective sacrificial element are not rounded because they are formed by vertical etching of the sacrificial material.
  • Another example that may be observed in some characteristic metallization stacks formed according to the methods described herein is that distances between the different interconnects may periodically repeat in a pattern, as a consequence of the periodicity in the pattern of sacrificial elements which may be used to form the interconnects.
  • the distance between a first pair of interconnects may be dl, as shown in FIG. 12A for the interconnects 104-1 and 104-2, while the distance between the interconnects 104-2 and 104-3 may be d2, as also shown in FIG. 12A.
  • FIG. 12A This pair of distances between three neighboring interconnects 104-1, 104-2, and 104-3 is labeled in FIG. 12A as a set of distances 122. The same pair of distances may repeat itself for the next three neighboring interconnects, as labeled in FIG. 12A with the set of distances 122 for the interconnects 104-3, 104-4, and 104-5.
  • FIG. 12A provides just one illustrative example. In other embodiments, there may be regions in which dl and d2 are purposefully designed to be very different than shown in FIG. 12A. In addition, depending on the pattern of the sacrificial elements and how they were provided in the first place, e.g.
  • the repeating pattern of the interconnects can be significantly more complicated, e.g. taking on a form with three or more distinct subsets of interconnects within the plurality of resulting interconnects.
  • Also characteristic of the methods disclosed herein is the relatively low surface roughness of the sidewalls 124 of the interconnects 104 (labeled in FIG. 12A only for one sidewall of the first interconnect, 104-1, in order to not clutter the FIG.), resulting in that the variation in the width of each interconnect (i.e. the y-axis dimension of the reference coordinate system shown in FIG. 12A) along the height of that interconnect is relatively small, e.g. less than 10% or less than 5% of the average width of that interconnect.
  • FIG. 12A further illustrates a liner 126 which may also be seen in a cross-section of an exemplary metallization stack formed according to the methods disclosed herein, labeled only for the last pair of interconnects, the interconnects 104-5 and 104-6, in order to not clutter the FIG.
  • the liner 126 could be provided to improve adhesion of the electrically conductive material to the sacrificial elements for the deposition of the electrically conductive material on the sidewalls of the sacrificial elements, or/and to reduce interdiffusion of materials (i.e. the liner 126 could be a diffusion barrier).
  • FIG. 12A also illustrates a liner 128, which may also be seen in a cross-section of an exemplary metallization stack formed according to the methods disclosed herein, labeled only for the very last interconnect shown in FIG. 12A, the interconnect 104-6, in order to not clutter the FIG.
  • the liner 128 could be provided to improve adhesion of the electrically conductive material to the surrounding dielectric 112, or/and to reduce interdiffusion of materials (i.e. the liner 128 could be a diffusion barrier). Because liners 126 and 128 of each interconnect 104 are provided in different deposition processes, at different times, and possibly of different composition, differences may be observed in their composition, thickness, shape, and structure.
  • the grains of the electrically conductive material of the interconnects will have a characteristic alignment and size, as shown in FIG. 12B as an enlarged version of part of a portion 130 of the first
  • interconnect 104-1 of FIG. 12A As can be seen in the example illustration of FIG. 12B with grains 132, the grain alignment, distribution, and size may be very distinctive.
  • the grain size (i.e. measurement in the largest dimension of the grain) labeled in FIG. 12B for one exemplary grain 132 as d3, may be noticeably larger than the width of the interconnect defining the critical dimension (CD) of the interconnect, labeled in FIG. 12B as d4.
  • CD critical dimension
  • a longest dimension of at least 70%, preferably at least 80%, e.g. at least 85% or at least 90 or 95% of metal grains of the interconnect may be greater than the average width of the interconnect 104.
  • FIG. 12B also illustrates that most of the grains of the interconnect are aligned substantially vertically.
  • directions of alignment of at least 80%, preferably at least 90%, e.g. at least 95% or at least 98% of metal grains of the interconnects 104 would deviate from a vertical direction with respect to (i.e. a line perpendicular to) the interconnect support layer 102 by less than 40 degrees, preferably by less than 20 degrees, e.g. less than 10 or 5 degrees, or even less than 1 degree.
  • FIG. 12B further illustrates that most grain boundaries may be encountered in the horizontal direction (i.e. the direction of the y-axis) than in the vertical direction (i.e. the direction of the z-axis).
  • FIG. 13 is a flow diagram of an example method 1000 of manufacturing a metallization stack (e.g. the metallization stack 100 including a plurality of electrically conductive interconnects 104), summarizing the subtractive metal spacer based deposition described herein, in accordance with various embodiments.
  • a metallization stack e.g. the metallization stack 100 including a plurality of electrically conductive interconnects 104
  • the operations of the method 1000 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture multiple patterns of interconnects substantially simultaneously. In another example, planarization operations may be performed in a different order, as needed.
  • an interconnect support layer may be provided.
  • the interconnect support layer provided at 1002 may take the form of any of the embodiments of the interconnect support layer 102 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the metallization stack 100 or any of the assemblies shown in FIGS. 2-11).
  • a pattern of sacrificial non-metal elements may be provided.
  • the sacrificial non- metal elements provided at 1004 may take the form of, and be provided according to, any of the embodiments of the sacrificial elements 108 disclosed herein, for example.
  • the sacrificial elements may be provided at 1004 so as to be in contact with the interconnect support layer of 1002.
  • an intermediate material may be disposed between the interconnect support layer and the sacrificial elements, e.g. an etch stop layer or an insulating layer.
  • electrically conductive material e.g. a metal
  • the electrically conductive material provided at 1006 on the sidewalls of the sacrificial elements may take the form of, and be provided according to, any of the embodiments disclosed herein.
  • the sacrificial elements may be removed from between the electrically conductive material provided on their sidewalls. Removal of the sacrificial elements at 1008 may be performed according to any of the embodiments disclosed herein.
  • a diffusion barrier liner may be deposited over the electrically conductive elements remaining after the removal of the sacrificial elements at 1008.
  • the diffusion barrier liner provided at 1010 may take the form of, and be provided according to, any of the embodiments of the diffusion barrier liner disclosed herein.
  • a dielectric material e.g. an ILD
  • the dielectric material may, optionally, be planarized to expose the upper surfaces of the electrically conductive elements from the surrounding dielectric.
  • the dielectric material provided at 1012, as well as the planarization thereof, may take the form of, and be provided and/or planarized according to, any of the embodiments of the dielectric material 112 disclosed herein.
  • the method 1000 may further include other manufacturing operations related to fabrication of other components of a metallization stack 100 or any devices that include such a stack.
  • the method 1000 may various cleaning operations, and/or operations for incorporating the metallization stack 100 in, or with, an IC component.
  • FIGS. 14-17 illustrate various examples of apparatuses that may include one or more of the metallization stacks disclosed herein.
  • FIGS. 14A-B are top views of a wafer 1100 and dies 1102 that may include one or more metallization stacks in accordance with any of the embodiments disclosed herein.
  • the wafer 1100 may be composed of semiconductor material and may include one or more dies 1102 having IC structures formed on a surface of the wafer 1100.
  • Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more components that include one or more metallization stacks 100).
  • ICs including one or more components that include one or more metallization stacks 100.
  • the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product.
  • devices that include a metallization stack as disclosed herein may take the form of the wafer 1100 (e.g., not singulated) or the form of the die 1102 (e.g., singulated).
  • the die 1102 may include one or more transistors (e.g., one or more of the transistors 1240 of FIG.
  • the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 1402 of FIG. 17) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • a memory device e.g., a static random access memory (SRAM) device
  • a logic device e.g., an AND, OR, NAND, or NOR gate
  • Multiple ones of these devices may be combined on a single die 1102.
  • a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 1402 of FIG. 17) or other logic that
  • FIG. 15 is a cross-sectional side view of an IC device 1200 that may include one or more metallization stacks in accordance with any of the embodiments disclosed herein.
  • the IC device 1200 may be formed on a substrate 1202 (e.g., the wafer 1100 of FIG. 14A) and may be included in a die (e.g., the die 1102 of FIG. 14B).
  • the substrate 1202 may be any substrate as described herein.
  • the substrate 1202 may be part of a singulated die (e.g., the dies 1102 of FIG. 14B) or a wafer (e.g., the wafer 1100 of FIG. 14A).
  • the IC device 1200 may include one or more device layers 1204 disposed on the substrate 1202.
  • the device layer 1204 may include features of one or more transistors 1240 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1202.
  • the device layer 1204 may include, for example, one or more source and/or drain (S/D) regions 1220, a gate 1222 to control current flow in the transistors 1240 between the S/D regions 1220, and one or more S/D contacts 1224 to route electrical signals to/from the S/D regions 1220.
  • the transistors 1240 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like.
  • the transistors 1240 are not limited to the type and configuration depicted in FIG. 15 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both.
  • Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all- around gate transistors, such as nanoribbon and nanowire transistors.
  • Each transistor 1240 may include a gate 1222 formed of at least two layers, a gate electrode layer and a gate dielectric layer.
  • the gate electrode layer may be formed on the gate interconnect support layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor, respectively.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer or/and an adhesion layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 electron Volts (eV) and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross section of the transistor 1240 along the source-channel-drain direction, may be formed as a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may be implemented as a combination of U-shaped structures and planar, non-U- shaped structures.
  • the gate electrode may be implemented as one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • the gate electrode may consist of a V-shaped structure (e.g., when a fin of a FinFET transistor does not have a "flat" upper surface, but instead has a rounded peak).
  • the gate dielectric layer of a transistor 1240 may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material.
  • the high-k dielectric material included in the gate dielectric layer of the transistor 1240 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the S/D regions 1220 may be formed within the substrate 1202 adjacent to the gate 1222 of each transistor 1240, using any suitable processes known in the art.
  • the S/D regions 1220 may be formed using either an implantation/diffusion process or a deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion- implanted into the substrate 1202 to form the S/D regions 1220.
  • An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1202 may follow the ion implantation process.
  • an epitaxial deposition process may provide material that is used to fabricate the S/D regions 1220.
  • the S/D regions 1220 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the S/D regions 1220 may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the S/D regions 1220.
  • an etch process may be performed before the epitaxial deposition to create recesses in the substrate 1202 in which the material for the S/D regions 1220 is deposited.
  • Electrical signals such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 1240 of the device layer 1204 through one or more interconnect layers disposed on the device layer 1204 (illustrated in FIG. 15 as interconnect layers 1206-1210).
  • interconnect layers 1206-1210 electrically conductive features of the device layer 1204 (e.g., the gate 1222 and the S/D contacts 1224) may be electrically coupled with the interconnect structures 1228 of the interconnect layers 1206-1210.
  • the one or more interconnect layers 1206-1410 may form an interlayer dielectric (ILD) stack 1219 of the IC device 1200.
  • ILD interlayer dielectric
  • One or more of the interconnect layers 1206-1210 may take the form of any of the embodiments of the metallization stacks disclosed herein, for example any of the embodiments discussed herein with reference to the metallization stack 100 or any of the assemblies shown in FIGS. 2-8.
  • the interconnect structures 1228 may be arranged within the interconnect layers 1206-1410 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1228 depicted in FIG. 16). Although a particular number of interconnect layers 1206-1410 is depicted in FIG. 16, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.
  • the interconnect structures 1228 may include trench structures 1228a (sometimes referred to as "lines") and/or via structures 1228b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal.
  • the trench structures 1228a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1202 upon which the device layer 1204 is formed.
  • the trench structures 1228a may route electrical signals in a direction in and out of the page from the perspective of FIG. 15.
  • the via structures 1228b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1202 upon which the device layer 1204 is formed.
  • the via structures 1228b may electrically couple trench structures 1228a of different interconnect layers 1206-1410 together.
  • the interconnect layers 1206-1210 may include a dielectric material 1226 disposed between the interconnect structures 1228, as shown in FIG. 15.
  • the dielectric material 1226 may take the form of any of the embodiments of the dielectric material provided between the interconnects of the metallization stacks disclosed herein, for example any of the embodiments discussed herein with reference to the dielectric material 112, the metallization stack 100 or any of the assemblies shown in FIGS. 2-8.
  • the dielectric material 1226 disposed between the interconnect structures 1228 in different ones of the interconnect layers 1206-1210 may have different compositions. In other embodiments, the composition of the dielectric material 1226 between different interconnect layers 1206-1210 may be the same.
  • a first interconnect layer 1206 (referred to as Metal 1 or “Ml”) may be formed directly on the device layer 1204.
  • the first interconnect layer 1206 may include trench structures 1228a and/or via structures 1228b, as shown.
  • the trench structures 1228a of the first interconnect layer 1206 may be coupled with contacts (e.g., the S/D contacts 1224) of the device layer 1204.
  • a second interconnect layer 1208 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 1206.
  • the second interconnect layer 1208 may include via structures 1228b to couple the trench structures 1228a of the second interconnect layer 1208 with the trench structures 1228a of the first interconnect layer 1206.
  • the trench structures 1228a and the via structures 1228b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1208) for the sake of clarity, the trench structures 1228a and the via structures 1228b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
  • a third interconnect layer 1210 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1208 according to similar techniques and configurations described in connection with the second interconnect layer 1208 or the first interconnect layer 1206.
  • M3 Metal 3
  • the IC device 1200 may include a solder resist material 1234 (e.g., polyimide or similar material) and one or more bond pads 1236 formed on the interconnect layers 1206-1210.
  • the bond pads 1236 may be electrically coupled with the interconnect structures 1228 and configured to route the electrical signals of the transistor(s) 1240 to other external devices.
  • solder bonds may be formed on the one or more bond pads 1236 to mechanically and/or electrically couple a chip including the IC device 1200 with another component (e.g., a circuit board).
  • the IC device 1200 may have other alternative configurations to route the electrical signals from the interconnect layers 1206-1210 than depicted in other embodiments.
  • the bond pads 1236 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.
  • FIG. 16 is a cross-sectional side view of an IC device assembly 1300 that may include components having or being associated with (e.g. being electrically connected by means of) one or more metallization stacks in accordance with any of the embodiments disclosed herein.
  • the IC device assembly 1300 includes a number of components disposed on a circuit board 1302 (which may be, e.g., a motherboard).
  • the IC device assembly 1300 includes components disposed on a first face 1340 of the circuit board 1302 and an opposing second face 1342 of the circuit board 1302; generally, components may be disposed on one or both faces 1340 and 1342.
  • any suitable ones of the components of the IC device assembly 1300 may include any of the
  • the circuit board 1302 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1302.
  • the circuit board 1302 may be a non-PCB substrate.
  • the IC device assembly 1300 illustrated in FIG. 16 includes a package-on-interposer structure 1336 coupled to the first face 1340 of the circuit board 1302 by coupling components 1316.
  • the coupling components 1316 may electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302, and may include solder balls (as shown in FIG. 16), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 1336 may include an IC package 1320 coupled to an interposer 1304 by coupling components 1318.
  • the coupling components 1318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1316. Although a single IC package 1320 is shown in FIG. 16, multiple IC packages may be coupled to the interposer 1304; indeed, additional interposers may be coupled to the interposer 1304.
  • the interposer 1304 may provide an intervening substrate used to bridge the circuit board 1302 and the IC package 1320.
  • the IC package 1320 may be or include, for example, a die (the die 1102 of FIG. 14B), an IC device (e.g., the IC device 1200 of FIG.
  • the interposer 1304 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 1304 may couple the IC package 1320 (e.g., a die) to a ball grid array (BGA) of the coupling components 1316 for coupling to the circuit board 1302.
  • BGA ball grid array
  • the IC package 1320 and the circuit board 1302 are attached to opposing sides of the interposer 1304; in other embodiments, the IC package 1320 and the circuit board 1302 may be attached to a same side of the interposer 1304.
  • BGA ball grid array
  • three or more components may be interconnected by way of the interposer 1304.
  • the interposer 1304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 1304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1306.
  • TSVs through-silicon vias
  • the interposer 1304 may further include embedded devices 1314, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency ( F) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1304.
  • the package-on-interposer structure 1336 may take the form of any of the package-on-interposer structures known in the art.
  • the IC device assembly 1300 may include an IC package 1324 coupled to the first face 1340 of the circuit board 1302 by coupling components 1322.
  • the coupling components 1322 may take the form of any of the embodiments discussed above with reference to the coupling components 1316
  • the IC package 1324 may take the form of any of the embodiments discussed above with reference to the IC package 1320.
  • the IC device assembly 1300 illustrated in FIG. 16 includes a package-on-package structure 1334 coupled to the second face 1342 of the circuit board 1302 by coupling components 1328.
  • the package-on-package structure 1334 may include an IC package 1326 and an IC package 1332 coupled together by coupling components 1330 such that the IC package 1326 is disposed between the circuit board 1302 and the IC package 1332.
  • the coupling components 1328 and 1330 may take the form of any of the embodiments of the coupling components 1316 discussed above, and the IC packages 1326 and 1332 may take the form of any of the embodiments of the IC package 1320 discussed above.
  • the package-on-package structure 1334 may be configured in accordance with any of the package-on-package structures known in the art.
  • FIG. 17 is a block diagram of an example computing device 1400 that may include one or more components including one or more metallization stacks in accordance with any of the embodiments disclosed herein.
  • any suitable ones of the components of the computing device 1400 may include a die (e.g., the die 1102 of FIG. 14B) having one or more metallization stacks 100.
  • Any one or more of the components of the computing device 1400 may include, or be included in, an IC device 1200 (FIG. 15).
  • Any one or more of the components of the computing device 1400 may include, or be included in, an IC device assembly 1300 (FIG. 16).
  • FIG. 17 A number of components are illustrated in FIG. 17 as included in the computing device 1400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 1400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.
  • SoC system-on-a-chip
  • the computing device 1400 may not include one or more of the components illustrated in FIG. 17, but the computing device 1400 may include interface circuitry for coupling to the one or more components.
  • the computing device 1400 may not include a display device 1406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1406 may be coupled.
  • the computing device 1400 may not include an audio input device 1424 or an audio output device 1408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1424 or audio output device 1408 may be coupled.
  • the computing device 1400 may include a processing device 1402 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices.
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 1402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the computing device 1400 may include a memory 1404, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid state memory
  • solid state memory solid state memory
  • a hard drive e.g., solid state memory, and/or a hard drive.
  • the memory 1404 may include memory that shares a die with the processing device 1402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-M RAM).
  • eDRAM embedded dynamic random access memory
  • STT-M RAM spin transfer torque magnetic random-access memory
  • the computing device 1400 may include a communication chip 1412 (e.g., one or more communication chips).
  • the communication chip 1412 may be configured for managing wireless communications for the transfer of data to and from the computing device 1400.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UM B) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and
  • the communication chip 1412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • High Speed Packet Access HSPA
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 1412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 1412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 1412 may operate in accordance with other wireless protocols in other embodiments.
  • the computing device 1400 may include an antenna 1422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
  • the communication chip 1412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1412 may include multiple communication chips. For instance, a first communication chip 1412 may be dedicated to shorter-range wireless
  • a second communication chip 1412 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • a first communication chip 1412 may be dedicated to wireless communications
  • a second communication chip 1412 may be dedicated to wired communications.
  • the computing device 1400 may include battery/power circuitry 1414.
  • the battery/power circuitry 1414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 1400 to an energy source separate from the computing device 1400 (e.g., AC line power).
  • the computing device 1400 may include a display device 1406 (or corresponding interface circuitry, as discussed above).
  • the display device 1406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • the computing device 1400 may include an audio output device 1408 (or corresponding interface circuitry, as discussed above).
  • the audio output device 1408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the computing device 1400 may include an audio input device 1424 (or corresponding interface circuitry, as discussed above).
  • the audio input device 1424 may include any device that generates a signal representative of a sound, such as microphones, m icrophone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M IDI) output).
  • M IDI musical instrument digital interface
  • the computing device 1400 may include a global positioning system (GPS) device 1418 (or corresponding interface circuitry, as discussed above).
  • GPS global positioning system
  • the GPS device 1418 may be in
  • the computing device 1400 may include another output device 1410 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 1410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the computing device 1400 may include another input device 1420 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 1420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • the computing device 1400 may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • the computing device 1400 may be any other electronic device that processes data.
  • Example 1 provides a method of forming a semiconductor device, the method including providing a pattern of sacrificial elements over an interconnect support layer; depositing an electrically conductive material on sidewalls of the sacrificial elements; and removing the sacrificial elements, where remaining portions of the electrically conductive material form a pattern of electrically conductive elements.
  • Example 2 provides the method according to Example 1, where the sacrificial elements are formed of a non-metallic material.
  • Example 3 provides the method according to Examples 1 or 2, where the pattern of sacrificial elements is a plurality of parallel lines having a height between 5 and 1000 nanometers and a width between 5 and 300 nanometers.
  • Example 4 provides the method according to any one of Examples 1-3, where depositing the electrically conductive material on the sidewalls of the sacrificial elements includes using atomic layer deposition (ALD) or chemical vapor deposition (CVD) to conformally deposit the electrically conductive material on the sidewalls and in openings between the sacrificial elements, and using anisotropic etch to vertically etch away the electrically conductive material deposited in the openings between the sacrificial elements.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • Example 5 provides the method according to any one of Examples 1-3, where depositing the electrically conductive material on the sidewalls of the sacrificial elements includes using physical vapor deposition (PVD) to deposit the electrically conductive material only on the sidewalls of the sacrificial elements.
  • PVD physical vapor deposition
  • Example 6 provides the method according to any one of the preceding Examples, where removing the sacrificial elements includes using a selective dry etch to remove the sacrificial elements but not the electrically conductive elements (i.e. the etchant should be selected such that it etches the material of the sacrificial elements but does not substantially etch the electrically conductive material deposited on the sidewalls of said sacrificial elements).
  • Example 7 provides the method according to any one of the preceding Examples, further including, after removing the sacrificial elements, filling in spaces between the electrically conductive elements with a dielectric material, e.g. with an interlayer dielectric (ILD) material.
  • a dielectric material e.g. with an interlayer dielectric (ILD) material.
  • ILD interlayer dielectric
  • Example 8 provides the method according to Example 7, further including, after filling in spaces between the electrically conductive elements with the dielectric material, performing planarization to expose upper surfaces of the electrically conductive elements.
  • Example 9 provides the method according to Examples 7 or 8, further including, after removing the sacrificial elements and before filling in spaces between the electrically conductive elements with the dielectric material, conformally depositing a diffusion barrier layer on sidewalls of at least some of the electrically conductive elements.
  • Example 10 provides the method according to any one of the preceding Examples, where the electrically conductive material includes one or more of aluminum, copper, tungsten, cobalt, ruthenium, nickel, iron, and molybdenum, and/or one or more alloys including aluminum, copper, tungsten, cobalt, ruthenium, manganese, magnesium, boron, phosphorus, nitrogen, carbon, and sulfur.
  • the electrically conductive material includes one or more of aluminum, copper, tungsten, cobalt, ruthenium, nickel, iron, and molybdenum, and/or one or more alloys including aluminum, copper, tungsten, cobalt, ruthenium, manganese, magnesium, boron, phosphorus, nitrogen, carbon, and sulfur.
  • Example 11 provides the method according to any one of the preceding Examples, where the electrically conductive elements are interconnects of a metallization stack of the semiconductor device.
  • Example 12 provides a metallization stack for providing electrical connectivity, including a plurality of electrically conductive interconnects provided over an interconnect support layer, where, for each interconnect a width of the interconnect along a height of the interconnect varies less than 10 percent, preferably less than 5%, of an average width of the interconnect along the height of the interconnect.
  • Example 13 provides the metallization stack according to Example 12, where directions of alignment of at least 80%, preferably at least 90%, e.g. at least 95% or at least 98% of metal grains of the interconnect deviate from a vertical direction with respect to (i.e. a line perpendicular to) the interconnect support layer by less than 40 degrees, preferably by less than 20 degrees, e.g. less than 10 or 5 degrees, or even less than 1 degree (i.e. most of the metal grains of each interconnect are aligned substantially vertically with respect to the interconnect support layer).
  • Example 14 provides the metallization stack according to Examples 12 or 13, where a longest dimension of at least 70%, preferably at least 80%, e.g. at least 85% or at least 90 or 95% of metal grains of the interconnect is greater than the average width of the interconnect.
  • the largest dimension of most of the metal grains of each interconnect is characteristically larger than the critical dimension (in this case, width) of the interconnect features themselves.
  • Example 15 provides the metallization stack according to any one of Examples 12-14, where the average width of each interconnect is between 5 and 30 nanometers.
  • Example 16 provides the metallization stack according to any one of Examples 12-14, where the average width of each interconnect is between 5 and 15 nanometers (i.e. substantially half a pitch).
  • Example 17 provides the metallization stack according to any one of Examples 12-16, where an average height of each interconnect is between 5 and 1000 nanometers.
  • Example 18 provides the metallization stack according to any one of Examples 12-16, where an average height of each interconnect is between 15 and 45 nanometers (i.e., substantially 1.5 times a pitch).
  • Example 19 provides the metallization stack according to any one of Exam ples 12-18, where an electrically conductive material of the plurality of interconnects includes one or more of aluminum, copper, tungsten, cobalt, ruthenium, nickel, iron, and molybdenum, and/or one or more alloys including aluminum, copper, tungsten, cobalt, ruthenium, manganese, magnesium, boron, phosphorus, nitrogen, carbon, and sulfur.
  • Example 20 provides the metallization stack according to any one of Examples 12-19, further including a diffusion barrier layer provided on sidewalls of at least some of the plurality of interconnects.
  • Example 21 provides the metallization stack according to any one of Examples 12-20, where a center-to-center distance (i.e. a pitch) between each pair of two adjacent interconnects of the plurality of interconnects is between 10 and 100 nanometers, e.g. between 20 and 40 nanometers.
  • a center-to-center distance i.e. a pitch
  • Example 22 provides the metallization stack according to any one of Examples 12-21, where sides of the plurality of electrically conductive interconnects are enclosed by a dielectric material.
  • Example 23 provides the metallization stack according to Example 22, where the dielectric material is a first dielectric material and the metallization stack further includes a plug structure of a second dielectric material provided (inserted) in place of one of the plurality of electrically conductive interconnects.
  • Example 24 provides the metallization stack according to Example 23, wherein the second dielectric material is different from the first dielectric material.
  • Example 25 provides the metallization stack according to any one of Examples 12-24, where a center-to-center distance between at least some pairs of two adjacent interconnects of the plurality of interconnects is between 10 and 45 nanometers, an average width of each interconnect is between 5 and 15 nanometers, an average height of each interconnect is between 15 and 45 nanometers, sides of the plurality of electrically conductive interconnects are enclosed by a first dielectric material, and the metallization stack further includes a plug structure of a second dielectric material provided in place of at least one of the plurality of electrically conductive interconnects.
  • the metallization stack may further include a barrier-dielectric adhesion layer provided on sidewalls of at least some of the plurality interconnects, in order to promote adhesion between the material of the diffusion barrier layer and the material(s) of the interlayer dielectric which may fill the space between the plurality interconnects.
  • Example 26 provides an integrated circuit package, including a component; and a metallization stack for providing electrical connectivity to the component.
  • the metallization stack may be a metallization stack according to any one of the preceding Examples.
  • the metallization stack may include a plurality of electrically conductive interconnects provided over an interconnect support layer, where, for each interconnect a width of the interconnect along a height of the interconnect varies less than 10 percent, preferably less than 5%, of an average width of the interconnect along the height of the interconnect.
  • Example 27 provides the integrated circuit package according to Example 26, where the component includes a transistor, a die, a sensor, a processing device, or a memory device.
  • Example 28 provides a computing device, including a substrate; and an integrated circuit (IC) die coupled to the substrate.
  • the IC die includes a semiconductor device having a component, and a metallization stack for providing electrical connectivity to the component.
  • the metallization stack may be a metallization stack according to any one of the preceding Examples.
  • the metallization stack may include a plurality of electrically conductive interconnects provided over an interconnect support layer, where, for each interconnect, directions of alignment of at least 80%, preferably at least 90%, of metal grains of the interconnect deviate from a vertical direction with respect to (i.e. a line perpendicular to) the interconnect support layer by less than 40 degrees, preferably by less than 20 degrees.
  • Example 29 provides the computing device according to Example 28, where, for each interconnect, a thickness of the interconnect along a height of the interconnect varies less than 10 percent, preferably less than 5%, of an average thickness of the interconnect along the height of the interconnect.
  • Example 30 provides the computing device according to Examples 28 or 29, where the computing device is a wearable or handheld computing device.
  • Example 31 provides the computing device according to any of Examples 28-30, where the computing device further includes one or more communication chips and an antenna.
  • Example 32 provides the computing device according to any of Examples 28-31, where the substrate is a motherboard.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

L'invention concerne des procédés de fabrication d'un empilement de métallisation comprenant une pluralité d'interconnexions électroconductrices par dépôt à base d'espaceur métallique soustractif, et des dispositifs à semiconducteur associés. Par exemple, dans certains modes de réalisation, un procédé de formation d'un dispositif à semiconducteur peut comprendre la fourniture d'un motif d'éléments sacrificiels sur une couche de support d'interconnexion, le dépôt d'un matériau électroconducteur sur les parois latérales des éléments sacrificiels, et le retrait des éléments sacrificiels de telle sorte que les parties restantes du matériau électroconducteur forment un motif d'éléments électroconducteurs qui peuvent servir d'interconnexions d'un empilement de métallisation du dispositif à semiconducteur.
PCT/US2016/067069 2016-12-16 2016-12-16 Interconnexions fournies par dépôt à base d'espaceur métallique soustractif WO2018111289A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10361353B2 (en) 2018-02-08 2019-07-23 Intel Corporation Sidewall metal spacers for forming metal gates in quantum devices
CN110783257A (zh) * 2018-07-24 2020-02-11 爱思开海力士有限公司 具有对称的导电互连图案的半导体器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448113A (en) * 1993-03-08 1995-09-05 Ricoh Company, Ltd. Micro metal-wiring structure having stress induced migration resistance
US20090093121A1 (en) * 2007-10-04 2009-04-09 Hynix Semiconductor Inc. Method for Fabricating a Fine Pattern
US20100112797A1 (en) * 2008-10-31 2010-05-06 Macronix International Co., Ltd. Method for forming a memory array
US20160020099A1 (en) * 2014-07-21 2016-01-21 Kabushiki Kaisha Toshiba Pattern forming method and method of manufacturing semiconductor device
US20160293419A1 (en) * 2015-04-06 2016-10-06 Yun Suk NAM Method of forming fine patterns in a semiconductor device and method of manufacturing an electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448113A (en) * 1993-03-08 1995-09-05 Ricoh Company, Ltd. Micro metal-wiring structure having stress induced migration resistance
US20090093121A1 (en) * 2007-10-04 2009-04-09 Hynix Semiconductor Inc. Method for Fabricating a Fine Pattern
US20100112797A1 (en) * 2008-10-31 2010-05-06 Macronix International Co., Ltd. Method for forming a memory array
US20160020099A1 (en) * 2014-07-21 2016-01-21 Kabushiki Kaisha Toshiba Pattern forming method and method of manufacturing semiconductor device
US20160293419A1 (en) * 2015-04-06 2016-10-06 Yun Suk NAM Method of forming fine patterns in a semiconductor device and method of manufacturing an electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10361353B2 (en) 2018-02-08 2019-07-23 Intel Corporation Sidewall metal spacers for forming metal gates in quantum devices
CN110783257A (zh) * 2018-07-24 2020-02-11 爱思开海力士有限公司 具有对称的导电互连图案的半导体器件
US11456252B2 (en) 2018-07-24 2022-09-27 SK Hynix Inc. Semiconductor device having symmetric conductive interconnection patterns
CN110783257B (zh) * 2018-07-24 2023-11-17 爱思开海力士有限公司 具有对称的导电互连图案的半导体器件

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