WO2018107677A1 - 一种电子标签的电源整流电路 - Google Patents

一种电子标签的电源整流电路 Download PDF

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Publication number
WO2018107677A1
WO2018107677A1 PCT/CN2017/087968 CN2017087968W WO2018107677A1 WO 2018107677 A1 WO2018107677 A1 WO 2018107677A1 CN 2017087968 W CN2017087968 W CN 2017087968W WO 2018107677 A1 WO2018107677 A1 WO 2018107677A1
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WO
WIPO (PCT)
Prior art keywords
transistor
voltage
circuit
output
gate
Prior art date
Application number
PCT/CN2017/087968
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English (en)
French (fr)
Inventor
符令
何洋
胡毅
王小曼
杨小坤
赵东艳
王于波
张海峰
Original Assignee
北京智芯微电子科技有限公司
国网信息通信产业集团有限公司
国家电网公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 北京智芯微电子科技有限公司, 国网信息通信产业集团有限公司, 国家电网公司 filed Critical 北京智芯微电子科技有限公司
Priority to AU2017374541A priority Critical patent/AU2017374541B2/en
Priority to KR1020197020479A priority patent/KR102256810B1/ko
Publication of WO2018107677A1 publication Critical patent/WO2018107677A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

Definitions

  • the present invention relates to the field of electronic circuit technologies, and in particular, to a power rectifier circuit for an electronic tag.
  • RFID radio frequency identification
  • RFID is often used in conjunction with readers to enable energy transfer and data exchange. After the electronic tag enters the magnetic field, it receives the RF signal from the reader, and sends the product information stored in the chip or actively transmits a signal of a certain frequency by the energy obtained by the induced current.
  • Electronic tags mainly include chips and antennas.
  • the chip includes a rectifier circuit and a voltage adjustment circuit.
  • the rectifier circuit receives the AC signal of the antenna, converts the AC signal, and transmits the output voltage to the voltage adjustment circuit, and the voltage adjustment circuit rectifies according to the working voltage range of the chip.
  • the output voltage of the circuit is adjusted and the chip is powered using the adjusted voltage.
  • the rectifier circuit and the voltage adjustment circuit are independent two-part circuits, the circuit structure design is complicated, and a large chip area is occupied.
  • the technical problem to be solved by the embodiments of the present invention is how to provide a power rectifying circuit for an electronic tag, which can simplify the circuit structure and reduce the chip volume.
  • an embodiment of the present invention provides a power rectification circuit for an electronic tag, including: a control circuit, a first rectification and voltage adjustment circuit, a second rectification and voltage adjustment circuit, a power supply detection circuit, and a stable Pressure capacitor
  • the first input end of the control circuit is configured to receive the first antenna signal
  • the second input end is configured to receive the second antenna signal
  • the first output end and the second output end of the control circuit are respectively associated with the first rectification And the voltage adjustment circuit is connected;
  • the first output end and the second output end of the control circuit are respectively connected to the second rectification and voltage adjustment circuit;
  • the input end of the first rectification and voltage adjustment circuit is configured to receive a first antenna signal, and the control end of the first rectification and voltage adjustment circuit is configured to receive a first output signal of the first output end of the control circuit;
  • the input end of the second rectification and voltage adjustment circuit is configured to receive a second antenna signal, and the control end of the second rectification and voltage adjustment circuit is configured to receive a second output signal of the second output end of the control circuit;
  • the first end of the voltage stabilizing capacitor is respectively connected to an output end of the first rectifying and voltage adjusting circuit and an output end of the second rectifying and voltage adjusting circuit, and a second end of the stabilizing capacitor is grounded;
  • the input end of the power detecting circuit is connected to the first end of the voltage stabilizing capacitor, configured to collect the voltage of the first end of the voltage stabilizing capacitor, and the output of the power detecting circuit and the feedback of the control circuit Connected to the terminal, configured to send a feedback signal to the control circuit according to a voltage of the first end of the voltage stabilizing capacitor;
  • the control circuit is configured to control the first rectifying and voltage adjusting circuit or the second rectifying and voltage adjusting circuit to charge the stabilizing capacitor according to the feedback signal, the first antenna signal and the second antenna signal;
  • the voltage of the first end of the voltage stabilizing capacitor is an output voltage of the power rectifier circuit.
  • control circuit includes: a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first AND gate, and a second AND gate;
  • the first NOT gate is configured to receive a first antenna signal, the input end of the second NOT gate is coupled to an output end of the first NOT gate, and the first input end of the second AND gate is An output end of the second NOT gate is connected; an output signal of the second AND gate is a second output signal of the second output end of the control circuit;
  • the third NOT gate is configured to receive a second antenna signal, the input end of the fourth NOT gate is connected to the output end of the third NOT gate, and the first input end of the first AND gate is An output of the fourth NOT gate is coupled; an output signal of the first AND gate is a first output signal of the first output of the control circuit.
  • the first rectifying and voltage adjusting circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor;
  • the first transistor input end and the control end are configured to receive a first antenna signal, and the first transistor output end is respectively connected to the first end of the first capacitor and the input end of the second transistor; a control end of the transistor is connected to the first output end of the control circuit, and an output end of the second transistor is connected to the first end of the voltage stabilizing capacitor;
  • the second end of the first capacitor is respectively connected to the third transistor input end and the fourth transistor input end; the third transistor output end is connected to the first end of the voltage stabilizing capacitor; The third transistor control terminal is coupled to the second output terminal of the control circuit; the fourth transistor output terminal is coupled to ground, and the fourth transistor control terminal is coupled to the first output terminal of the control circuit.
  • the first rectifying and voltage adjusting circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor;
  • the fifth transistor input end and the control end are configured to receive a second antenna signal, and the fifth transistor output end is respectively connected to the first end of the second capacitor and the input end of the sixth transistor; a control end of the transistor is connected to the second output end of the control circuit, and an output end of the sixth transistor is connected to the first end of the voltage stabilizing capacitor;
  • a second end of the second capacitor is respectively connected to the seventh transistor input end and the eighth transistor input end; the seventh transistor output end is connected to the first end of the voltage stabilizing capacitor;
  • the seventh transistor control terminal is coupled to the first output terminal of the control circuit; the eighth transistor output terminal is coupled to ground, and the eighth transistor control terminal is coupled to the second output terminal of the control circuit.
  • the power detection circuit includes a comparator, a first resistor, and a second resistor;
  • One end of the first resistor is connected to the first end of the voltage stabilizing capacitor, and the other end of the first resistor is connected in series with the second resistor and grounded;
  • a first input of the comparator is coupled to a common end of the first resistor and the second resistor, a second input of the comparator is configured to receive a reference voltage; an output of the comparator is The feedback terminals of the control circuit are connected.
  • the output end of the comparator is connected to the feedback end of the control circuit, and includes: an output end of the comparator and a second input end of the first AND gate, respectively The second is connected to the second input of the gate.
  • the comparator is a hysteresis comparator.
  • the method further includes: calculating an output voltage of the power rectifier circuit by using a formula, where the formula one is:
  • VDD is the output voltage of the power rectifier circuit
  • VREF is the reference voltage of the hysteresis comparator
  • VM is the downward flipping hysteresis voltage
  • VM + is the upward flipping hysteresis voltage
  • R1 is the resistance of the first resistor.
  • Value is the resistance value of the second resistor.
  • the input end, the control end, and the output end of the transistor sequentially correspond to the collector, the base, and the emitter of the triode.
  • an input end, a control end, and an output end of the transistor sequentially correspond to a drain, a gate, and a source of the FET.
  • the power rectifying circuit of the electronic tag collects the voltage of the first end of the stabilizing capacitor through a power detecting circuit, and sends a feedback signal to the control circuit according to the voltage of the first end of the stabilizing capacitor .
  • the control circuit is configured to control the first rectifying and voltage adjusting circuit or the second rectifying and voltage adjusting circuit to charge the stabilizing capacitor according to the feedback signal, the first antenna signal and the second antenna signal, and pass the power source
  • the detection circuit controls the voltage at the first end of the voltage stabilizing capacitor within the required range of the chip operation, the circuit structure is simple and the chip area is reduced.
  • FIG. 1 is a schematic structural diagram of a power rectifying circuit of an electronic tag according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a power rectifying circuit of an electronic tag according to another embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a power rectifying circuit of an electronic tag according to an embodiment of the present invention. As shown, the method includes: a control circuit 10, a first rectifying and voltage adjusting circuit 30, and a second rectifying and voltage adjusting circuit. 20. A power supply detecting circuit 40 and a voltage stabilizing capacitor 50.
  • the first input end of the control circuit 10 is configured to receive the first antenna signal ANT1, the second input end is configured to receive the second antenna signal ANT2, and the first output end and the second output end of the control circuit 10 respectively
  • a rectifying and voltage adjusting circuit 30 is connected; the first output end and the second output end of the control circuit 10 are respectively connected to the second rectifying and voltage adjusting circuit 20.
  • the input end of the first rectification and voltage adjustment circuit 30 is configured to receive the first antenna signal ANT1, and the control end of the first rectification and voltage adjustment circuit 30 is configured to receive the control power A first output signal of the first output of the path 10.
  • An input end of the second rectification and voltage adjustment circuit 20 is configured to receive a second antenna signal ANT2, and a control end of the second rectification and voltage adjustment circuit 20 is configured to receive a second output signal of the second output end of the control circuit 10 .
  • the first end of the voltage stabilizing capacitor 50 is respectively connected to the output end of the first rectifying and voltage adjusting circuit 30 and the output end of the second rectifying and voltage adjusting circuit 20, and the second end of the stabilizing capacitor 50 Ground.
  • An input end of the power detecting circuit 40 is connected to the first end of the voltage stabilizing capacitor 50, and is configured to collect a voltage of the first end of the voltage stabilizing capacitor 50, that is, an output voltage VDD, and an output end of the power detecting circuit 40
  • the feedback end of the control circuit 10 is connected to be configured to send a feedback signal to the control circuit 10 according to the voltage of the first end of the voltage stabilizing capacitor 50.
  • the voltage of the first end of the voltage stabilizing capacitor is the output voltage of the power rectifier circuit of the electronic tag.
  • the control circuit 10 is configured to control the first rectifying and voltage adjusting circuit 30 or the second rectifying and voltage adjusting circuit 20 to the stabilizing capacitor according to the feedback signal, the first antenna signal ANT1 and the second antenna signal ANT2 50 to charge.
  • the first antenna signal ANT1 and the second antenna signal ANT2 are not high at the same time.
  • the first antenna signal ANT1 and the second antenna signal ANT2 are voltage signals received by the electronic tag, and may specifically be a voltage signal coupled from the card reader to the electronic tag, that is, two input ends of the rectification adjusting circuit and the electronic device.
  • the two ends of the tag antenna are connected; at this time, the signal coupled by the electronic tag is a sine wave, that is, the first input terminal of the rectification adjusting circuit receives the forward voltage in a half cycle, and the second input end receives the other half cycle. Forward Voltage.
  • VDD is the output voltage of the power supply rectifier circuit of the electronic tag, that is, the voltage supplied to the chip.
  • the power rectifying circuit of the electronic tag provided by the embodiment passes through the power detecting circuit
  • the voltage of the first end of the voltage stabilizing capacitor 50 is collected, and a feedback signal is sent to the control circuit 10 according to the voltage of the first end of the voltage stabilizing capacitor 50.
  • the control circuit 10 is configured to control the first rectifying and voltage adjusting circuit 30 or the second rectifying and voltage adjusting circuit 20 to the stabilizing capacitor according to the feedback signal, the first antenna signal ANT1 and the second antenna signal ANT2 50 is charged, and the voltage of the first end of the voltage stabilizing capacitor 50 is controlled by the power detecting circuit within the required range of the chip operation, the circuit structure is simple and the chip area is reduced.
  • FIG. 2 is a schematic structural diagram of a power rectifying circuit of an electronic tag according to another embodiment of the present invention. This embodiment is further limited based on the first embodiment.
  • the first rectifying and voltage adjusting circuit 30 includes: a first transistor M1a, a second transistor M2a, a third transistor M3a, a fourth transistor M4a, and a first capacitor C1a.
  • the input end of the first transistor M1a and the control end are configured to receive the first antenna signal, and the output ends of the first transistor M1a are respectively connected to the first end of the first capacitor C1a and the input end of the second transistor M2a.
  • the control terminal of the second transistor M2a is connected to the first output end of the control circuit 10, and the output end of the second transistor M2a is connected to the first end of the voltage stabilizing capacitor CL.
  • the second end of the first capacitor C1a is respectively connected to the input end of the third transistor M3a and the input end of the fourth transistor M4a; the output end of the third transistor M3a is opposite to the first end of the stabilizing capacitor CL Connecting; the control terminal of the third transistor M3a is connected to the second output end of the control circuit 10; the output end of the fourth transistor M4a is grounded, and the control terminal of the fourth transistor M4a is opposite to the control circuit 10 An output is connected.
  • the first rectifying and voltage adjusting circuit 30 includes: a fifth transistor M1b, a sixth transistor M2b, a seventh transistor M3b, an eighth transistor M4b, and a second capacitor C1b;
  • the input end of the fifth transistor M1b and the control end are configured to receive the second antenna signal ANT2, and the output end of the fifth transistor M1b is respectively connected to the first end of the second capacitor C1b and the input end of the sixth transistor M2b;
  • the control terminal of the sixth transistor M2b is connected to the second output terminal of the control circuit 10, and the output terminal of the sixth transistor M2b is connected to the first terminal of the voltage stabilizing capacitor CL.
  • the second end of the second capacitor C1b is respectively connected to the input end of the seventh transistor M3b and the input end of the eighth transistor M4b; the output end of the seventh transistor M3b and the first end of the stabilizing capacitor CL
  • the terminal of the seventh transistor M3b is connected to the first output end of the control circuit 10; the output end of the eighth transistor M4b is grounded, and the control terminal of the eighth transistor M4b and the control circuit 10 The second output is connected.
  • the transistor may be a triode or a field effect transistor.
  • the input, control and output of the transistor are the collector, base and emitter of the triode in turn;
  • the transistor is a FET, the input, control and output of the transistor are in turn The drain, gate, and source of the effect transistor.
  • the present embodiment can increase the output efficiency by using a DC-DC circuit structure in the rectification and voltage adjustment circuit.
  • control circuit 10 includes: a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, a fourth NOT gate N4, a first AND gate A1, and a second AND gate. A2;
  • the first NOT gate N1 is configured to receive the first antenna signal
  • the input end of the second NOT gate N2 is connected to the output end of the first NOT gate N1
  • the second AND gate A2 is An input is coupled to the output of the second NOT gate N2; an output signal of the second AND gate A2 is a second output signal of the second output of the control circuit.
  • the third NOT gate N3 is configured to receive the second antenna signal, the input end of the fourth NOT gate N4 is connected to the output end of the third NOT gate N3, and the first input end of the first AND gate A1 is An output end of the fourth NOT gate N4 is connected; an output signal of the first AND gate A1 is the control power The first output signal of the first output of the road.
  • the invention connects the first AND gate A1 and the second AND gate A2 through the two non-gates through the first antenna signal ANT1 and the second antenna signal ANT2, and can convert the antenna signal into a relatively standard square wave signal, thereby avoiding Possible errors in the antenna signal.
  • the power supply circuit 40 includes a comparator detecting the COM, a first resistor R 1 and a second resistor R 2; a first terminal of the first resistor R one end of the stabilizing capacitance CL 1 Connected, the other end of the first resistor R 1 is connected in series with the second resistor R 2 and grounded.
  • a first input of the comparator COM is connected to a common end of the first resistor R 1 and the second resistor R 2 , a second input of the comparator COM is configured to receive a reference voltage; The output is coupled to the feedback terminal of the control circuit 10.
  • the output end of the comparator COM is connected to the feedback end of the control circuit 10, including: an output end of the comparator COM and a second input end of the first AND gate A1 and the first The second is connected to the second input of the door A2.
  • the comparator COM may be a hysteresis comparator.
  • the voltage on the second resistor is the voltage dividing of the voltage stabilizing capacitor, and it is determined whether the capacitor CL needs to be charged by the relationship between the voltage of the second resistor and the reference voltage VREF.
  • the comparator When the voltage of the second resistor is less than the reference voltage VREF, the comparator outputs a high level to charge the capacitor CL; when the voltage of the second resistor is greater than the reference voltage VREF, the comparator outputs a low level to discharge the capacitor CL.
  • the range of the voltage at the VDD output terminal can be calculated by Equation 1, the formula one for:
  • U is the output voltage of the hysteresis comparator
  • VREF is the reference voltage of the hysteresis comparator
  • VM - is the downward flipping hysteresis voltage
  • VM + is the upward flipping hysteresis voltage
  • R 1 is the first The resistance value of a resistor
  • R 2 is the resistance value of the second resistor.
  • ANT1 is high and ANT2 is low, the first AND gate A1 output is low and the second AND gate A2 is high.
  • M1a, M3a, M2b, and M4b are turned on, CL and C1b are connected in parallel, CL1 and C1b are connected in series and C1a, ANT1 is charged by C1a by M1a, and C1b is charged by CL.
  • ANT1 is low and ANT2 is high, the first AND gate A1 output is high and the second AND gate A2 is low.
  • M2a, M4a, M1b, and M3b are turned on, CL and C1a are connected in parallel, and C1b is connected in series and CL and C1a, ANT2 is charged by C1b by M1b, and C1a is charged by CL.
  • the rectification adjusting circuit transfers the antenna energy to the VDD terminal stabilizing capacitor CL through the form of capacitor charging and discharging.
  • the circuit controls the charging and discharging of the antenna pairs C1a and C1b by using the antenna voltage signals ANT1 and ANT2. If the frequency of the RF signal of the chip is F S , the frequency of the capacitor moving charge is 2 ⁇ F S , and the maximum load capacity of the circuit is:
  • I max 2 ⁇ F S ⁇ C1 ⁇ (Vant-Vth - 2VDD) (2)
  • C1 is a capacitance value of the first capacitor C1a or the second capacitor C1b, where the capacitance values of C1a and C1b are the same; Vant is the antenna voltage, and Vth is the turn-on voltage or the threshold voltage, which is M1a or M1b in this embodiment. Turn-on voltage.
  • the efficiency of the rectifier circuit is improved by increasing the voltage of the tag antenna.
  • the higher the Vant the higher the rectification efficiency of the tag.
  • the circuit provided in this embodiment can increase the Vant voltage to greater than 2 VDD to improve the rectification efficiency.
  • the power rectifier circuit of the electronic tag provided by the embodiment provides the rectification and voltage adjustment through the control circuit, the first rectification and voltage adjustment circuit, the second rectification and voltage adjustment circuit, the power supply detection circuit, and the voltage stabilization capacitor. In a circuit, there is no need to separately set two circuits to reduce the volume.
  • the voltage stabilizing capacitor is charged under the control of the power detecting circuit, so that the voltage VDD of the first end of the stabilizing capacitor is within a desired range;
  • the DC-DC structure is used in the circuit to improve the rectification efficiency of the circuit at low field strength; the chip area is small, the circuit requires less C1 capacitance, and a large amount of high-voltage voltage-stabilizing capacitor area is omitted; the process dependency is small, and the circuit characteristics are The ratio of the capacitor and the on-resistance of the switch determine that the process requirements are low; the circuit concentrates on the rectification and voltage adjustment circuit of the high-frequency electronic tag and the voltage-stabilizing capacitor, and has a simple structure, which can ensure the stable and reliable output of the tag rectification output and fast load response.
  • the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, ie may be located A place, or it can be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without deliberate labor.
  • the voltage of the first end of the voltage stabilizing capacitor is collected by the power detecting circuit, and the feedback signal is sent to the control circuit according to the voltage of the first end of the stabilizing capacitor.
  • the control circuit is configured to control the first rectifying and voltage adjusting circuit or the second rectifying and voltage adjusting circuit to charge the stabilizing capacitor according to the feedback signal, the first antenna signal and the second antenna signal, and pass the power source
  • the detection circuit controls the voltage at the first end of the voltage stabilizing capacitor within the required range of the chip operation, the circuit structure is simple and the chip area is reduced.

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Abstract

本发明实施例涉及一种电子标签的电源整流电路，包括：控制电路、第一整流及电压调整电路、第二整流及电压调整电路、电源检测电路以及稳压电容；通过电源检测电路采集所述稳压电容的第一端的电压，根据所述稳压电容的第一端的电压向所述控制电路发送反馈信号；控制电路配置为根据所述反馈信号、第一天线信号和第二天线信号控制所述第一整流及电压调整电路或所述第二整流及电压调整电路对所述稳压电容进行充电，通过电源检测电路控制稳压电容第一端的电压在芯片工作的所需范围内，电路结构简单并且减少芯片面积。

Description

一种电子标签的电源整流电路
相关申请的交叉引用
本申请基于申请号为201611140950.X、申请日为2016年12月12日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及电子电路技术领域，尤其涉及一种电子标签的电源整流电路。
背景技术
电子标签又称射频标签、应答器、数据载体，电子标签是射频识别(RFID，Radio Frequency Identification)的俗称。RFID通常与阅读器配合使用，用来实现能量的传递和数据交换。电子标签进入磁场后，接收解读器发出的射频信号，凭借感应电流所获得的能量发送出存储在芯片中的产品信息或者主动发送某一频率的信号。
电子标签主要包括芯片和天线。现有技术中，芯片中包括整流电路以及电压调整电路，整流电路接收天线的交流信号，对交流信号进行转化，并将输出电压传输给电压调整电路，电压调整电路根据芯片的工作电压范围对整流电路的输出电压进行调整，使用调整后的电压为芯片供电。
采用现有技术，至少存在如下问题：
现有的电路结构中，整流电路以及电压调整电路为独立的两部分电路，电路结构设计复杂，并且占用较大的芯片面积。
公开于该背景技术部分的信息仅仅旨在增加对本发明的总体背景的理 解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域一般技术人员所公知的现有技术。
发明内容
有鉴于此，本发明实施例要解决的技术问题是，如何提供一种电子标签的电源整流电路，能够简化电路结构进而减小芯片体积。
为解决以上技术问题，本发明实施例在第一方面提供一种电子标签的电源整流电路，包括：控制电路、第一整流及电压调整电路、第二整流及电压调整电路、电源检测电路以及稳压电容；
所述控制电路的第一输入端配置为接收第一天线信号，第二输入端配置为接收第二天线信号，所述控制电路的第一输出端、第二输出端分别与所述第一整流及电压调整电路相连接；所述控制电路的第一输出端、第二输出端分别与所述第二整流及电压调整电路相连接；
所述第一整流及电压调整电路的输入端配置为接收第一天线信号，所述第一整流及电压调整电路的控制端配置为接收所述控制电路的第一输出端的第一输出信号；
所述第二整流及电压调整电路的输入端配置为接收第二天线信号，所述第二整流及电压调整电路的控制端配置为接收所述控制电路的第二输出端的第二输出信号；
所述稳压电容的第一端分别与所述第一整流及电压调整电路的输出端以及所述第二整流及电压调整电路的输出端相连接，所述稳压电容的第二端接地；
所述电源检测电路的输入端与所述稳压电容的第一端相连，配置为采集所述稳压电容的第一端的电压，所述电源检测电路的输出端与所述控制电路的反馈端相连，配置为根据所述稳压电容的第一端的电压向所述控制电路发送反馈信号；
所述控制电路配置为根据所述反馈信号、第一天线信号和第二天线信号控制所述第一整流及电压调整电路或所述第二整流及电压调整电路对所述稳压电容进行充电；
其中，所述稳压电容的第一端的电压为所述电源整流电路的输出电压。
在一种可能的实现方式中，所述控制电路包括：第一非门、第二非门、第三非门、第四非门、第一与门以及第二与门；
所述第一非门配置为接收第一天线信号，所述第二非门的输入端与所述第一非门的输出端相连接，所述第二与门的第一输入端与所述第二非门的输出端相连接；所述第二与门的输出信号为所述控制电路的第二输出端的第二输出信号；
所述第三非门配置为接收第二天线信号，所述第四非门的输入端与所述第三非门的输出端相连接，所述第一与门的第一输入端与所述第四非门的输出端相连接；所述第一与门的输出信号为所述控制电路的第一输出端的第一输出信号。
在一种可能的实现方式中，所述第一整流及电压调整电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第一电容；
所述第一晶体管输入端以及控制端配置为接收第一天线信号，所述第一晶体管输出端分别与第一电容的第一端以及所述第二晶体管的输入端相连接；所述第二晶体管的控制端与所述控制电路的第一输出端相连接，所述第二晶体管的输出端与所述稳压电容的第一端相连接；
所述第一电容的第二端分别与所述第三晶体管输入端以及所述第四晶体管输入端相连接；所述第三晶体管输出端与所述稳压电容的第一端相连接；所述第三晶体管控制端与所述控制电路的第二输出端相连接；所述第四晶体管输出端接地，所述第四晶体管控制端与所述控制电路的第一输出端相连接。
在一种可能的实现方式中，所述第一整流及电压调整电路包括：第五晶体管、第六晶体管、第七晶体管、第八晶体管以及第二电容；
所述第五晶体管输入端以及控制端配置为接收第二天线信号，所述第五晶体管输出端分别与第二电容的第一端以及所述第六晶体管的输入端相连接；所述第六晶体管的控制端与所述控制电路的第二输出端相连接，所述第六晶体管的输出端与所述稳压电容的第一端相连接；
所述第二电容的第二端分别与所述第七晶体管输入端以及所述第八晶体管输入端相连接；所述第七晶体管输出端与所述稳压电容的第一端相连接；所述第七晶体管控制端与所述控制电路的第一输出端相连接；所述第八晶体管输出端接地，所述第八晶体管控制端与所述控制电路的第二输出端相连接。
在一种可能的实现方式中，所述电源检测电路包括比较器、第一电阻和第二电阻；
所述第一电阻的一端与所述稳压电容的第一端相连，所述第一电阻另一端串接所述第二电阻后接地；
所述比较器第一输入端与所述第一电阻和所述第二电阻的公共端相连，所述比较器的第二输入端配置为接收参考电压；所述比较器的输出端与所述控制电路的反馈端相连。
在一种可能的实现方式中，所述比较器的输出端与所述控制电路的反馈端相连，包括：所述比较器的输出端分别与所述第一与门的第二输入端以及所述第二与门的第二输入端相连接。
在一种可能的实现方式中，所述比较器为磁滞比较器。
在一种可能的实现方式中，包括：通过公式一计算所述电源整流电路的输出电压，所述公式一为：
Figure PCTCN2017087968-appb-000001
其中，VDD为所述电源整流电路的输出电压，VREF为所述磁滞比较器的参考电压，VM为向下翻转磁滞电压，VM+为向上翻转磁滞电压，R1为第一电阻的电阻值，R2为第二电阻的电阻值。
在一种可能的实现方式中，当所述晶体管为三极管时，晶体管的输入端、控制端、输出端依次对应三极管的集电极、基极、发射极。
在一种可能的实现方式中，当所述晶体管为场效应管时，晶体管的输入端、控制端、输出端依次对应场效应管的漏极、栅极、源极。
本发明实施例提供的电子标签的电源整流电路，通过电源检测电路采集所述稳压电容的第一端的电压，根据所述稳压电容的第一端的电压向所述控制电路发送反馈信号。控制电路配置为根据所述反馈信号、第一天线信号和第二天线信号控制所述第一整流及电压调整电路或所述第二整流及电压调整电路对所述稳压电容进行充电，通过电源检测电路控制稳压电容第一端的电压在芯片工作的所需范围内，电路结构简单并且减少芯片面积。
根据下面参考附图对示例性实施例的详细说明，本发明的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本发明的示例性实施例、特征和方面，并且用于解释本发明的原理。
图1示出本发明一实施例提供的电子标签的电源整流电路的结构示意图；
图2示出本发明另一实施例提供的电子标签的电源整流电路的结构示意图。
具体实施方式
下面结合附图，对本发明的具体实施方式进行详细描述，但应当理解 本发明的保护范围并不受具体实施方式的限制。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。除非另有其它明确表示，否则在整个说明书和权利要求书中，术语“包括”或其变换如“包含”或“包括有”等等将被理解为包括所陈述的元件或组成部分，而并未排除其它元件或其它组成部分。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本发明，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本发明同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件未作详细描述，以便于凸显本发明的主旨。
实施例1
图1示出本发明一实施例提供的电子标签的电源整流电路的结构示意图，如图所示，该方法包括：控制电路10、第一整流及电压调整电路30、第二整流及电压调整电路20、电源检测电路40以及稳压电容50。
控制电路10的第一输入端配置为接收第一天线信号ANT1，第二输入端配置为接收第二天线信号ANT2，所述控制电路10的第一输出端、第二输出端分别与所述第一整流及电压调整电路30相连接；所述控制电路10的第一输出端、第二输出端分别与所述第二整流及电压调整电路20相连接。
第一整流及电压调整电路30的输入端配置为接收第一天线信号ANT1，所述第一整流及电压调整电路30的控制端配置为接收所述控制电 路10的第一输出端的第一输出信号。
第二整流及电压调整电路20的输入端配置为接收第二天线信号ANT2，所述第二整流及电压调整电路20的控制端配置为接收所述控制电路10的第二输出端的第二输出信号。
稳压电容50的第一端分别与所述第一整流及电压调整电路30的输出端以及所述第二整流及电压调整电路20的输出端相连接，所述稳压电容50的第二端接地。
电源检测电路40的输入端与所述稳压电容50的第一端相连，配置为采集所述稳压电容50的第一端的电压即输出电压VDD，所述电源检测电路40的输出端与所述控制电路10的反馈端相连，配置为根据所述稳压电容50的第一端的电压向所述控制电路10发送反馈信号。
所述稳压电容的第一端的电压为所述电子标签的电源整流电路的输出电压。
控制电路10配置为根据所述反馈信号、第一天线信号ANT1和第二天线信号ANT2控制所述第一整流及电压调整电路30或所述第二整流及电压调整电路20对所述稳压电容50进行充电。
其中，第一天线信号ANT1和第二天线信号ANT2不同时为高电平。具体的，第一天线信号ANT1和第二天线信号ANT2为电子标签接收到的电压信号，其具体可以为从读卡器耦合至电子标签的电压信号，即整流调整电路的两个输入端与电子标签天线的两端相连即可；此时电子标签耦合的信号为正弦波，即在半个周期内整流调整电路的第一输入端接收正向电压，在另半个周期内第二输入端接收正向电压。
VDD为电子标签的电源整流电路的输出电压，也就是为芯片提供的电压。
由此，本实施例提供的电子标签的电源整流电路，通过电源检测电路 40采集所述稳压电容50的第一端的电压，根据所述稳压电容50的第一端的电压向所述控制电路10发送反馈信号。控制电路10配置为根据所述反馈信号、第一天线信号ANT1和第二天线信号ANT2控制所述第一整流及电压调整电路30或所述第二整流及电压调整电路20对所述稳压电容50进行充电，通过电源检测电路控制稳压电容50第一端的电压在芯片工作的所需范围内，电路结构简单并且减少芯片面积。
实施例2
图2示出本发明另一实施例提供的电子标签的电源整流电路的结构示意图，本实施例在实施例一的基础上，进行进一步限定。
在一种可能的实现方式中，所述第一整流及电压调整电路30包括：第一晶体管M1a、第二晶体管M2a、第三晶体管M3a、第四晶体管M4a以及第一电容C1a。
具体地，第一晶体管M1a输入端以及控制端配置为接收第一天线信号，所述第一晶体管M1a输出端分别与第一电容C1a的第一端以及所述第二晶体管M2a的输入端相连接；所述第二晶体管M2a的控制端与所述控制电路10的第一输出端相连接，所述第二晶体管M2a的输出端与所述稳压电容CL的第一端相连接。
第一电容C1a的第二端分别与所述第三晶体管M3a输入端以及所述第四晶体管M4a输入端相连接；所述第三晶体管M3a输出端与所述稳压电容CL的第一端相连接；所述第三晶体管M3a控制端与所述控制电路10的第二输出端相连接；所述第四晶体管M4a输出端接地，所述第四晶体管M4a控制端与所述控制电路10的第一输出端相连接。
在一种可能的实现方式中，所述第一整流及电压调整电路30包括：第五晶体管M1b、第六晶体管M2b、第七晶体管M3b、第八晶体管M4b以及第二电容C1b；
第五晶体管M1b输入端以及控制端配置为接收第二天线信号ANT2，所述第五晶体管M1b输出端分别与第二电容C1b的第一端以及所述第六晶体管M2b的输入端相连接；所述第六晶体管M2b的控制端与所述控制电路10的第二输出端相连接，所述第六晶体管M2b的输出端与所述稳压电容CL的第一端相连接。
所述第二电容C1b的第二端分别与所述第七晶体管M3b输入端以及所述第八晶体管M4b输入端相连接；所述第七晶体管M3b输出端与所述稳压电容CL的第一端相连接；所述第七晶体管M3b控制端与所述控制电路10的第一输出端相连接；所述第八晶体管M4b输出端接地，所述第八晶体管M4b控制端与所述控制电路10的第二输出端相连接。
本发明实施例中，晶体管具体可以为三极管或场效应管。当晶体管为三极管时，晶体管的输入端、控制端、输出端依次为三极管的集电极、基极、发射极；当晶体管为场效应管时，晶体管的输入端、控制端、输出端依次为场效应管的漏极、栅极、源极。
由此，本实施例通过在整流及电压调整电路中使用DC-DC电路结构，可以增加输出效率。
在一种可能的实现方式中，所述控制电路10包括：第一非门N1、第二非门N2、第三非门N3、第四非门N4、第一与门A1以及第二与门A2；
具体地，第一非门N1配置为接收第一天线信号，所述第二非门N2、的输入端与所述第一非门N1的输出端相连接，所述第二与门A2的第一输入端与所述第二非门N2的输出端相连接；所述第二与门A2的输出信号为所述控制电路的第二输出端的第二输出信号。
第三非门N3配置为接收第二天线信号，所述第四非门N4的输入端与所述第三非门N3的输出端相连接，所述第一与门A1的第一输入端与所述第四非门N4的输出端相连接；所述第一与门A1的输出信号为所述控制电 路的第一输出端的第一输出信号。
本发明通过第一天线信号ANT1以及第二天线信号ANT2通过两个非门，分别与第一与门A1以及第二与门A2相连接，可以将天线信号转换为较为标准的方波信号，避免天线信号中可能存在的误差。
在一种可能的实现方式中，电源检测电路40包括比较器COM、第一电阻R1和第二电阻R2；所述第一电阻R1的一端与所述稳压电容CL的第一端相连，所述第一电阻R1另一端串接所述第二电阻R2后接地。
比较器COM第一输入端与所述第一电阻R1和所述第二电阻R2的公共端相连，所述比较器COM的第二输入端配置为接收参考电压；所述比较器COM的输出端与所述控制电路10的反馈端相连。
具体地，所述比较器COM的输出端与所述控制电路10的反馈端相连，包括：所述比较器COM的输出端分别与所述第一与门A1的第二输入端以及所述第二与门A2的第二输入端相连接。
其中，所述比较器COM可以为磁滞比较器。
电源检测电路中，第二电阻上的电压为稳压电容的分压，通过第二电阻的电压和参考电压VREF大小关系判断是否需要对电容CL充电。当第二电阻的电压小于参考电压VREF时，比较器输出高电平，对电容CL充电；当第二电阻的电压大于参考电压VREF时，比较器输出低电平，对电容CL放电。
其中，当
Figure PCTCN2017087968-appb-000002
时(R1和R2分别为第一电阻和第二电阻的阻值)，此时输出电压VDD过高，即电源检测电路输出反馈信号为低电平。当
Figure PCTCN2017087968-appb-000003
时，此时需要提高输出电压VDD，比较器输出高电平，由整流调整电路为CL充电。
具体地可以通过公式一计算所述VDD输出端电压的范围，所述公式一 为：
Figure PCTCN2017087968-appb-000004
其中，U为所述磁滞比较器的输出端电压，VREF为所述磁滞比较器的参考电压，VM-为向下翻转磁滞电压，VM+为向上翻转磁滞电压，R1为第一电阻的电阻值，R2为第二电阻的电阻值。
由此，可以通过设置比较器，当VDD大于充电阈值时停止对CL充电；当VDD小于放电阈值时对CL进行充电，将电路的输出电压VDD，控制在所需范围内，对输出电压更好的进行控制。
本实施例中，当比较器输出高电平时，电路的工作过程为：
若当ANT1为高电平，ANT2为低电平时，第一与门A1输出为低电平，第二与门A2输出为高电平。此时，M1a、M3a、M2b、M4b导通，CL、C1b并联，C1a串联并联后的CL以及C1b，ANT1通过M1a为C1a充电，C1b为CL充电。
若当ANT1为低电平，ANT2为高电平时，第一与门A1输出为高电平，第二与门A2输出为低电平。此时，M2a、M4a、M1b、M3b导通，CL、C1a并联，C1b串联并联后的CL以及C1a，ANT2通过M1b为C1b充电，C1a为CL充电。
本发明实施例中，整流调整电路将天线能量通过电容充放电的形式转移到VDD端稳压电容CL上，该电路利用天线电压信号ANT1和ANT2控制天线对C1a和C1b的充电和放电。若芯片射频信号频率为FS时，电容搬移电荷的频率为2×FS，电路的最大带负载能力为：
Imax＝2×FS×C1×(Vant-Vth-2VDD)       (2)
其中，C1为第一电容C1a或第二电容C1b的电容值，此处以C1a和C1b的电容值相同为例；Vant为天线电压，Vth为开启电压或阈值电压，本实施例中为M1a或M1b的开启电压。
对于同一场强和标签线圈环境，标签所能获得的功率固定。整流及电压调整电路上的损耗是导致效率下降的主要原因。设整流及电压调整电路上的压降为ΔV，假设流过相同的电流，整流效率为：
Figure PCTCN2017087968-appb-000005
该结构中通过提高标签天线电压的方法提高整流电路效率，对于同样的ΔV，Vant越高，标签的整流效率越高。本实施例提供的电路可以将Vant电压提高到大于2VDD，以提高整流效率。
由此，本实施例提供的电子标签的电源整流电路，通过控制电路、第一整流及电压调整电路、第二整流及电压调整电路、电源检测电路以及稳压电容，将整流以及电压调整设置在一个电路中，不需要单独设置两个电路，减小体积，另外，在电源检测电路的控制下对稳压电容进行充电，使稳压电容第一端的电压VDD在所需范围内；在整流电路中使用DC-DC结构，提高了电路在低场强下的整流效率；芯片面积小，电路对C1电容要求较小，省去了大量高压稳压电容面积；工艺依赖性小，电路特性由电容的比例和开关的导通电阻决定，对工艺的要求低；电路集中了高频电子标签的整流和电压调整电路及稳压电容，结构简单，可保证标签整流输出电源稳定、负载响应快。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现，当然也可以通 过硬件。基于这样的理解，上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
前述对本发明的具体示例性实施方案的描述是为了说明和例证的目的。这些描述并非想将本发明限定为所公开的精确形式，并且很显然，根据上述教导，可以进行很多改变和变化。对示例性实施例进行选择和描述的目的在于解释本发明的特定原理及其实际应用，从而使得本领域的技术人员能够实现并利用本发明的各种不同的示例性实施方案以及各种不同的选择和改变。本发明的范围意在由权利要求书及其等同形式所限定。
工业实用性
采用本发明实施例，是通过电源检测电路采集所述稳压电容的第一端的电压，根据所述稳压电容的第一端的电压向所述控制电路发送反馈信号。控制电路配置为根据所述反馈信号、第一天线信号和第二天线信号控制所述第一整流及电压调整电路或所述第二整流及电压调整电路对所述稳压电容进行充电，通过电源检测电路控制稳压电容第一端的电压在芯片工作的所需范围内，电路结构简单并且减少芯片面积。

Claims (10)

  1. 一种电子标签的电源整流电路，包括：控制电路、第一整流及电压调整电路、第二整流及电压调整电路、电源检测电路以及稳压电容；
    所述控制电路的第一输入端配置为接收第一天线信号，第二输入端配置为接收第二天线信号，所述控制电路的第一输出端、第二输出端分别与所述第一整流及电压调整电路相连接；所述控制电路的第一输出端、第二输出端分别与所述第二整流及电压调整电路相连接；
    所述第一整流及电压调整电路的输入端配置为接收第一天线信号，所述第一整流及电压调整电路的控制端配置为接收所述控制电路的第一输出端的第一输出信号；
    所述第二整流及电压调整电路的输入端配置为接收第二天线信号，所述第二整流及电压调整电路的控制端配置为接收所述控制电路的第二输出端的第二输出信号；
    所述稳压电容的第一端分别与所述第一整流及电压调整电路的输出端以及所述第二整流及电压调整电路的输出端相连接，所述稳压电容的第二端接地；
    所述电源检测电路的输入端与所述稳压电容的第一端相连，配置为采集所述稳压电容的第一端的电压，所述电源检测电路的输出端与所述控制电路的反馈端相连，配置为根据所述稳压电容的第一端的电压向所述控制电路发送反馈信号；
    所述控制电路配置为根据所述反馈信号、第一天线信号和第二天线信号控制所述第一整流及电压调整电路或所述第二整流及电压调整电路对所述稳压电容进行充电；
    其中，所述稳压电容的第一端的电压为所述电源整流电路的输出电压。
  2. 根据权利要求1所述的电源整流电路，其中，所述控制电路包括：
    第一非门、第二非门、第三非门、第四非门、第一与门以及第二与门；
    所述第一非门配置为接收第一天线信号，所述第二非门的输入端与所述第一非门的输出端相连接，所述第二与门的第一输入端与所述第二非门的输出端相连接；所述第二与门的输出信号为所述控制电路的第二输出端的第二输出信号；
    所述第三非门配置为接收第二天线信号，所述第四非门的输入端与所述第三非门的输出端相连接，所述第一与门的第一输入端与所述第四非门的输出端相连接；所述第一与门的输出信号为所述控制电路的第一输出端的第一输出信号。
  3. 根据权利要求1所述的电源整流电路，其中，所述第一整流及电压调整电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第一电容；
    所述第一晶体管输入端以及控制端配置为接收第一天线信号，所述第一晶体管输出端分别与第一电容的第一端以及所述第二晶体管的输入端相连接；所述第二晶体管的控制端与所述控制电路的第一输出端相连接，所述第二晶体管的输出端与所述稳压电容的第一端相连接；
    所述第一电容的第二端分别与所述第三晶体管输入端以及所述第四晶体管输入端相连接；所述第三晶体管输出端与所述稳压电容的第一端相连接；所述第三晶体管控制端与所述控制电路的第二输出端相连接；所述第四晶体管输出端接地，所述第四晶体管控制端与所述控制电路的第一输出端相连接。
  4. 根据权利要求1所述的电源整流电路，其中，所述第一整流及电压调整电路包括：第五晶体管、第六晶体管、第七晶体管、第八晶体管以及第二电容；
    所述第五晶体管输入端以及控制端配置为接收第二天线信号，所述第 五晶体管输出端分别与第二电容的第一端以及所述第六晶体管的输入端相连接；所述第六晶体管的控制端与所述控制电路的第二输出端相连接，所述第六晶体管的输出端与所述稳压电容的第一端相连接；
    所述第二电容的第二端分别与所述第七晶体管输入端以及所述第八晶体管输入端相连接；所述第七晶体管输出端与所述稳压电容的第一端相连接；所述第七晶体管控制端与所述控制电路的第一输出端相连接；所述第八晶体管输出端接地，所述第八晶体管控制端与所述控制电路的第二输出端相连接。
  5. 根据权利要求2所述的电源整流电路，其中，所述电源检测电路包括比较器、第一电阻和第二电阻；
    所述第一电阻的一端与所述稳压电容的第一端相连，所述第一电阻另一端串接所述第二电阻后接地；
    所述比较器第一输入端与所述第一电阻和所述第二电阻的公共端相连，所述比较器的第二输入端配置为接收参考电压；所述比较器的输出端与所述控制电路的反馈端相连。
  6. 根据权利要求5所述的电源整流电路，其中，所述比较器的输出端与所述控制电路的反馈端相连，包括：
    所述比较器的输出端分别与所述第一与门的第二输入端以及所述第二与门的第二输入端相连接。
  7. 根据权利要求6所述的电源整流电路，其中，所述比较器为磁滞比较器。
  8. 根据权利要求7所述的电源整流电路，其中，包括：
    通过公式一计算所述电源整流电路的输出电压，所述公式一为：
    Figure PCTCN2017087968-appb-100001
    其中，VDD为所述电源整流电路的输出电压，VREF为所述磁滞比较 器的参考电压，VM_为向下翻转磁滞电压，VM+为向上翻转磁滞电压，R1为第一电阻的电阻值，R2为第二电阻的电阻值。
  9. 根据权利要求3或4所述的电源整流电路，其中，当所述晶体管为三极管时，所述晶体管的输入端、控制端、输出端依次对应三极管的集电极、基极、发射极。
  10. 根据权利要求3或4所述的电源整流电路，其中，当所述晶体管为场效应管时，所述晶体管的输入端、控制端、输出端依次对应场效应管的漏极、栅极、源极。
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