WO2018106215A1

WO2018106215A1 - Quantum circuit components with planar josephson junctions

Info

Publication number: WO2018106215A1
Application number: PCT/US2016/065041
Authority: WO
Inventors: Roman CAUDILLO; James S. Clarke; Zachary R. YOSCOVITS; Jeanette M. Roberts; Nicole K. THOMAS; Ravi Pillarisetty; Payam AMIN; Hubert C. GEORGE
Original assignee: Intel Corporation
Priority date: 2016-12-06
Filing date: 2016-12-06
Publication date: 2018-06-14

Abstract

Quantum circuit components that include Josephson Junctions are disclosed. An exemplary Josephson Junction includes a first superconductor element disposed over a first area of a substrate, a second superconductor element disposed over a second area, and a tunneling link element configured to serve as the weak link of the Josephson Junction coupling the first and the second superconductor elements. The tunneling link element is provided over a third area of the substrate, between the first area and the second area. Thus, the first superconductor element, the second superconductor element, and the tunneling link element forming a Josephson Junction are provided in the same plane, over different, non-overlapping, areas of the substrate. Such Josephson Junctions may be efficiently used in large-scale manufacturing, widen the range of materials which could be used for their fabrication, and may be fabricated with reduced variability in performance between individual end devices.

Description

QUANTUM CIRCUIT COMPONENTS WITH PLANAR JOSEPHSON JUNCTIONS

Technical Field

[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to Josephson Junctions for use in quantum circuits and to methods of fabricating thereof.

Background

[0002] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0003] To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying figures, wherein like reference numerals represent like parts, in which:

[0004] FIG. 1A provides a schematic illustration of a superconducting quantum circuit, according to some embodiments of the present disclosure.

[0005] FIG. IB provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit, according to some embodiments of the present disclosure.

[0006] FIG. 1C provides a schematic illustration of an exemplary transmon according to some embodiments of the present disclosure.

[0007] FIG. 2 provides a schematic illustration of an exemplary quantum computing device according to some embodiments of the present disclosure.

[0008] FIGs. 3A-3C provide a schematic illustration of a photoresist mask provided over a substrate for fabricating a Josephson Junction using a double-angle shadow evaporation approach.

[0009] FIGs. 4A-4C provide a schematic illustration of fabricating Josephson Junctions using a conventional double-angle shadow evaporation approach. [0010] FIG. 5 provides a schematic illustration of a mid-constricted planar Josephson Junction according to some embodiments of the present disclosure.

[0011] FIG. 6 provides a schematic illustration of a thinning-constricted planar Josephson Junction according to a first embodiment of the present disclosure.

[0012] FIG. 7 provides a schematic illustration of a thinning-constricted planar Josephson Junction according to a second embodiment of the present disclosure.

[0013] FIG. 8 provides a schematic illustration of a thinning-constricted planar Josephson Junction according to a third embodiment of the present disclosure.

[0014] FIG. 9 provides a flow chart of a method for fabricating a mid-constricted planar Josephson Junction, according to some embodiments of the present disclosure.

[0015] FIG. 10 provides a flow chart of a method for fabricating a thinning-constricted planar

Josephson Junction according to a first embodiment of the present disclosure.

[0016] FIG. 11 provides a flow chart of a first method for fabricating a thinning-constricted planar Josephson Junction according to the second embodiment of the present disclosure.

[0017] FIG. 12 provides a flow chart of a second method for fabricating a thinning-constricted planar Josephson Junction according to the second embodiment of the present disclosure.

[0018] FIG. 13 provides a flow chart of a method for fabricating a thinning-constricted planar

Josephson Junction according to a third embodiment of the present disclosure.

Detailed Description

Overview

[0019] As previously described herein, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e.

superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum- mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).

[0020] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics). Classical computers encode data into binary values, commonly referred to as bits. At any given time, a bit is always in only one of two states - it is either 0 or 1. Quantum computers use so- called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.

[0021] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being about 10. One of the main challenges resides in protecting qubits from decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results. For this reason, materials, structures, and fabrication methods used for building qubits should continuously focus on reducing spurious (i.e. unintentional and undesirable) two- level systems (TLS's), thought to be the dominant source of qubit decoherence. In general, as used in quantum mechanics, a two-level (also referred to as "two-state") system is a system that can exist in any quantum superposition of two independent and physically distinguishable quantum states. Also for the reason of protection from decoherence, qubits are often operated at cryogenic temperatures, typically just a few degrees or even just a few millidegrees above absolute zero because cryogenic temperatures minimize the detrimental effects of spurious TLS's. None of these challenges ever had to be addressed for classical computers. [0022] As the foregoing illustrates, ability to manipulate and read out quantum states, making quantum-mechanical phenomena visible and traceable, and ability to deal with and improve on the fragility of quantum states of a qubit present unique challenges not found in classical computers. These challenges explain why so many current efforts of the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits. Physical systems for implementing qubits that have been explored until now include e.g. superconducting qubits, single trapped ion qubits, Silicon (Si) quantum dot qubits, photon polarization qubits, etc.

[0023] Out of the various physical implementations of qubits listed above, superconducting qubits are promising candidates for building a quantum computer.

[0024] All of superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction. Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.

[0025] In general, a Josephson Junction includes two superconductors coupled by a so-called weak link that weakens the superconductivity between the two superconductors. In quantum circuits, the weak links of Josephson Junctions have conventionally been implemented by providing a thin layer of an insulating material, typically referred to as a barrier or a tunnel barrier, sandwiched, in a stack-like arrangement, between two layers of superconductor. A method typically employed to fabricate such Josephson Junctions is known as a "double-angle shadow evaporation" method (also sometimes referred to as "double-angle shadow evaporation" or "hanging resist" method). The name "double- angle shadow evaporation/evaporation" reflects the fact that the method involves metal deposition, typically carried out by metal evaporation, at two different angles of incidence with respect to the substrate (hence, double-angle). The name further reflects the fact that metal deposition is performed through a hanging photoresist mask which casts a shadow on at least a part of the substrate, obscuring metal deposition on that part (hence, shadow evaporation/evaporation).

[0026] Such a conventional double-angle shadow evaporation method has several drawbacks. One is that it includes fabrications steps, such as e.g. lift-off and shadow-angle evaporation, that are not suitable for large-scale manufacturing. Another is that the specific fabrication steps of this method limit the choice of materials which may be used to form a Josephson Junction. Yet another drawback is that this method is highly susceptible to unintentional variations from one Josephson Junction to another, resulting in non-negligible variability in performance of individual final Josephson Junctions.

[0027] Embodiments of the present disclosure propose Josephson Junctions, and methods for fabricating thereof, that could improve on one or more of the drawbacks described above. In one aspect of the present disclosure, a quantum circuit component, e.g. a superconducting qubit, that includes one or more Josephson Junctions provided over a substrate is disclosed. Each Josephson Junction includes a first superconductor element disposed over a first area of the substrate, a second superconductor element disposed over a second area, and a tunneling link element configured to serve as the Josephson Junction weak link coupling the first superconductor element and the second superconductor element. The tunneling link element is provided over a third area of the substrate, between the first area and the second area. Because the first superconductor element, the second superconductor element, and the tunneling link element are provided in the same plane, over different, non-overlapping areas of the substrate, deposition and patterning of these elements is simplified compared to the double-angle shadow evaporation method. In particular, such Josephson Junctions may be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to previously used methods which included fabrications steps which were not suitable for implementing with larger wafer sizes used by leading edge device manufactures. In addition, proposed Josephson Junctions widen the range of materials which could be used for their fabrication. Furthermore, proposed Josephson Junctions may be fabricated with reduced variability in performance between individual Josephson Junctions.

[0028] In order to highlight the differences from conventional Josephson Junctions used in quantum circuits where a Josephson Junction is formed as a stack of a base superconductor, a thin insulating barrier, and a top superconductor, extending away from a substrate, Josephson Junctions proposed herein are referred to as "planar Josephson Junctions."

[0029] For the purposes of the present disclosure, the terms such as "upper," "lower," "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers. [0030] The phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0031] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale.

[0032] As used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious two-level systems (TLS's) may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. One metric of interest may be the decay rate associated with these losses (e.g. losses either from TLS's or residual resistance), and as long as the decay rate associated with these mechanisms is not worse than needed in order to achieve a fault-tolerant quantum calculation, then the losses are deemed acceptable and the idealized terms (e.g. superconducting or lossless) - appropriate. Specific values associated with an acceptable decay are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher decay rates. An adapted version of this metric, as well as other metrics suitable for a particular application in determining whether certain behavior may be referred to using idealized terms, are within the scope of the present disclosure.

[0033] Furthermore, while the present disclosure includes references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 5-10 gigahertz (GHz) range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. However, advantageously, because excitation energy of qubits is controlled by the circuit elements, qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.

[0034] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0035] Furthermore, in the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well- known features are omitted or simplified in order not to obscure the illustrative implementations.

[0036] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment(s). Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

Basics of Josephson Junctions

[0037] As previously briefly explained above, quantum computing refers to the use of quantum mechanical properties to perform calculations. Some of these properties include superposition and entanglement. Just as classical computers are composed of bits that can either be in a 1 or a 0 state, a quantum computer is composed of quantum bits (i.e., qubits) which have states of |0) and | 1).

Quantum mechanics allows for superpositions of the | 0) and | 1) states with a general form of

a| 0) + b \ l) where a and b are complex numbers. When a qubit state is measured, it collapses to either state |0) with a probability of that happening being | a | ², or to state | 1) with a probability of the latter being | b | ². Taking into account the fact that | a 1 ²+ 1 b 1 ²=1 (since the total probability must sum to unity) and ignoring an overall phase factor which does not have any observable effects, the general state can θ θ

be re-written as cos - 10) +e^l<p sin - where φ is the phase difference between the two states. [0038] Entanglement occurs when the interaction between two particles (e.g. two qubits) is such that the states of the two cannot be specified independently, but rather can only be specified for the whole system. This causes the states of the two qubits to be linked together such that measurement of one of the qubits, causes the state of the other qubit to collapse.

[0039] In order to realize a quantum computer, a physical system that can act as a qubit is needed. Such a system needs to have at least two states to act as 0 and 1 states. Note that it is not necessary to have a system with exactly only two states if the spacing between each energy level is different, such that each level can be addressed individually. As previously described herein, one type of physical system that could be used to implement qubits is based on use of superconducting materials

(superconducting/superconductive qubits).

[0040] In some implementations, namely when superconducting qubits are implemented as transmon qubits, two basic elements of superconducting quantum circuits are inductors and capacitors.

However, circuits made using only these two elements cannot make a system with two energy levels because, due to the even spacing between the system's energy levels, such circuits will produce harmonic oscillators with a ladder of equivalent states. A nonlinear element is needed to have an effective two-level quantum state system, or qubit. Josephson Junction is an example of such nonlinear, non-dissipative circuit element. Therefore, Josephson Junctions may form the central circuit elements of a superconducting quantum computer.

[0041] In general, a Josephson Junction acts as a superconducting tunnel junction. Cooper pairs tunnel across the barrier from one superconducting layer to the other. The electrical characteristics of this tunneling are governed by so-called Josephson relations which provide the basic equations governing the dynamics of the Josephson effect:

I = I_c sin ψ (1) w V =— ^h φ^■

2e ^Ύ (2)

[0042] In these equations, φ is the phase difference in the superconducting wave function across the junction, l_c (the critical current) is the maximum current that can tunnel through the junction, which depends on the barrier thickness and the area of the junction, V is the voltage across the Josephson Junction, I is the current flowing through the Josephson Junction, h is the reduced Planck's constant, and e is electron's charge. Equations (1) and (2) can be combined to give an equation (3): h

V = I

2eI_ccoscp (3) [0043] Equation (3) looks like the equation for an inductor with inductance L:

2eI_ccoscp

[0044] Since inductance is a function of φ, which itself is a function of I, the inductance of a Josephson Junction is non-linear, which makes an LC circuit formed using a Josephson Junction as the inductor have uneven spacing between its energy states.

Exemplary quantum circuits

[0045] The foregoing provides an illustration of using a Josephson Junction in a transmon, which is one type of superconducting qubit. In other classes of superconducting qubits, Josephson Junctions combined with other circuit elements have similar functionality of providing the non-linearity necessary for forming an effective two-level quantum state, or qubit. In other words, when implemented in combination with other circuit elements (e.g. capacitors in transmons or superconducting loops in flux qubits), one or more Josephson Junctions allow realizing a quantum circuit element which has uneven spacing between its energy levels resulting in a unique ground and excited state system for the qubit. This is illustrated in FIG. 1A, providing a schematic illustration of a superconducting quantum circuit 100, according to some embodiments of the present disclosure. As shown in FIG. 1A, an exemplary superconducting quantum circuit 100 includes two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element). Each of the superconducting qubits 102 may include one or more Josephson Junctions 104 connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear circuit providing a unique two-level quantum state for the qubit. The circuit elements 106 could be e.g. capacitors in transmons or superconducting loops in flux qubits.

[0046] As also shown in FIG. 1A, an exemplary superconducting quantum circuit 100 typically includes means 108 for providing external control of qubits 102 and means 110 for providing internal control of qubits 102. In this context, "external control" refers to controlling the qubits 102 from outside of, e.g, an integrated circuit (IC) chip comprising the qubits, including control by a user of a quantum computer, while "internal control" refers to controlling the qubits 102 within the IC chip. For example, if qubits 102 are transmon qubits, external control may be implemented by means of flux bias lines (also known as "flux lines" and "flux coil lines") and by means of readout and drive lines (also known as "microwave lines" since qubits are typically designed to operate with microwave signals), described in greater detail below. On the other hand, internal control lines for such qubits may be implemented by means of resonators, e.g., coupling and readout resonators, also described in greater detail below.

[0047] Any one of the qubits 102, the external control means 108, and the external control means 110 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1A).

[0048] As previously described herein, within superconducting qubit implementations, three classes are typically distinguished: charge qubits, flux qubits, and phase qubits. Transmons, a type of charge qubits with the name being an abbreviation of "transmission line shunted plasma oscillation qubits", are particularly encouraging because they exhibit reduced sensitivity to charge noise. FIG. IB provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit 100B where qubits are implemented as transmons, according to some embodiments of the present disclosure.

[0049] Similar to FIG. 1A, FIG. IB illustrates two qubits 102. In addition, FIG. IB illustrates flux bias lines 112, microwave lines 114, a coupling resonator 116, a readout resonator 118, and wirebonding pads 120 and 122. The flux bias lines 112 and the microwave lines may be viewed as examples of the external control means 108 shown in FIG. 1A. The coupling resonator 116 and the readout resonator 118 may be viewed as examples of the internal control means 110 shown in FIG. 1A.

[0050] Running a current through the flux bias lines 112, provided from the wirebonding pads 120, allows tuning (i.e. changing) the frequency of the corresponding qubits 102 to which each line 112 is connected. In general, it operates in the following manner. As a result of running the current in a particular flux bias line 112, magnetic field is created around the line. If such a magnetic field is in sufficient proximity to the qubit 102, e.g. by a portion of the flux bias line 112 being provided next to the qubit 102, the magnetic field couples to the qubit, thereby changing the spacing between the energy levels of the qubit. This, in turn, changes the frequency of the qubit since the frequency is directly related to the spacing between the energy levels via Planck's equation. The Planck's equation is E=hv, where E is the energy (in this case the energy difference between energy levels of a qubit), h is the Planck's constant and v is the frequency (in this case the frequency of the qubit). As this equation illustrates, if E changes, then v changes. Provided there is sufficient multiplexing, different currents can be sent down each of the flux lines allowing for independent tuning of the various qubits.

[0051] The state(s) of each qubit 102 may be read by way of its corresponding readout resonator 118. As explained below, the qubit 102 induces a resonant frequency in the readout resonator 118. This resonant frequency is then passed to the microwave lines 114 and communicated to the pads 122. [0052] To that end, a readout resonator 118 may be provided for each qubit. The readout resonator 118 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance), with the resonant frequency of the oscillations being close to the frequency of the qubit. The readout resonator 118 is coupled to the qubit by being in sufficient proximity to the qubit 102, more specifically in sufficient proximity to the capacitor of the qubit 102, when the qubit is implemented as a transmon, either through capacitive or inductive coupling. Due to a coupling between the readout resonator 118 and the qubit 102, changes in the state of the qubit 102 result in changes of the resonant frequency of the readout resonator 118. In turn, because the readout resonator 118 is in sufficient proximity to the microwave line 114, changes in the resonant frequency of the readout resonator 118 induce changes in the current in the microwave line 114, and that current can be read externally via the wire bonding pads 122.

[0053] The coupling resonator 116 allows coupling different qubits together in order to realize quantum logic gates. The coupling resonator 116 is similar to the readout resonator 118 in that it is a transmission line that includes capacitive connections to ground on both sides (i.e. a half wavelength resonator), which also results in oscillations within the coupling resonator 116. Each side of the coupling resonator 116 is coupled (again, either capacitively or inductively) to a respective qubit by being in sufficient proximity to the qubit, namely in sufficient proximity to the capacitor of the qubit, when the qubit is implemented as a transmon. Because each side of the coupling resonator 116 has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator 116. In this manner, state of one qubit depends on the state of the other qubit, and the other way around. Thus, coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit.

[0054] In some implementations, the microwave line 114 may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits. When a single microwave line is used for this purpose, the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits. In other implementations, microwave lines such as the line 114 shown in FIG. IB may be used to only readout the state of the qubits as described above, while separate drive lines such as e.g. drive lines 124 shown in FIG. IB, may be used to control the state of the qubits. In such implementations, the microwave lines used for readout may be referred to as readout lines (e.g. readout line 114), while microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g. drive lines 124). The drive lines 124 may control the state of their respective qubits 102 by providing, using e.g. wirebonding pads 126 as shown in FIG. IB, a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the 0 and 1 state of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the 0 and 1 states of the qubit.

[0055] Flux bias lines, microwave lines, coupling resonators, drive lines, and readout resonators, such as e.g. those described above, together form interconnects for supporting propagation of microwave signals. Further, any other connections for providing direct electrical interconnection between different quantum circuit elements and components, such as e.g. connections from electrodes of Josephson Junctions to plates of the capacitors or to superconducting loops of superconducting quantum interference devices (SQUIDS) or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects. Still further, the term "interconnect" may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non-quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical

interconnections between various non-quantum circuit elements provided in a quantum circuit.

Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.

[0056] In various embodiments, the interconnects as shown in FIG. IB could have different shapes and layouts. For example, some interconnects may comprise more curves and turns while other interconnects may comprise less curves and turns, and some interconnects may comprise substantially straight lines. In some embodiments, various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other. As long as these interconnects operate in accordance with use of these interconnects as known in the art for which some exemplary principles were described above, quantum circuits with different shapes and layouts of the interconnects than those illustrated in FIG. IB are all within the scope of the present disclosure.

[0057] Coupling resonators and readout resonators may be configured for capacitive coupling to other circuit elements at one or both ends in order to have resonant oscillations, whereas flux bias lines and microwave lines may be similar to conventional microwave transmission lines because there is no resonance in these lines. Each one of these interconnects may be implemented as any suitable architecture of a microwave transmission line, such as e.g. a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line. Typical materials to make the interconnects include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and niobium titanium nitride (NbTiN), all of which are particular types of superconductors. However, in various embodiments, other suitable superconductors and alloys of superconductors may be used as well.

[0058] FIG. 1C illustrates an exemplary transmon 128 which could be used as any one of the qubits 102, according to some embodiments of the present disclosure. Presence of a capacitor 130 of such a size that capacitive energy is significantly larger than the Josephson energy in a qubit of FIG. 1C indicates that the qubit is a transmon. The capacitor 130 is configured to store energy in an electrical field as charges between the plates of the capacitor.

[0059] The capacitor 130 is depicted as an interdigitated capacitor, a particular shape of capacitor that provides a large capacitance with a small area, however, in various embodiments, other shapes and types of capacitors may be used as well. For example, such a capacitor could be implemented simply as two parallel plates with vacuum in between. Furthermore, in various embodiments, the capacitor 130 may be arranged in any direction with respect to the SQUID or a single Josephson Junction, not necessarily as shown in FIG. 1C.

[0060] In addition, the transmon illustrated in FIG. 1C includes two Josephson Junctions 132 incorporated into a superconducting loop 134. The two Josephson Junctions 132 and the

superconducting loop 134 together form a superconducting quantum interference device (SQUID). Magnetic fields generated by the flux bias line 112 connected to the qubit extend to the SQUID (i.e. current in the flux bias line 112 create magnetic fields around the SQUID), which, in turn, tunes the frequency of the qubit.

[0061] In other embodiments, a SQUID could include only one Josephson Junction, or a transmon could be implemented with a single Josephson Junction without the superconducting loop. A single Josephson Junction without the SQUID is insensitive to magnetic fields, and thus, in such an implementation, flux bias lines 112 may not be used to control the frequency of the transmon.

[0062] While FIGs. 1A and IB illustrate examples of quantum circuits comprising only two qubits 102, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure. At least some of the one or more qubits 102 shown in FIGs. 1A-1C may include planar Josephson Junctions as described herein.

[0063] While FIGs. IB and 1C illustrate embodiments specific to transmons, subject matter disclosed herein is not limited in this regard and may include other embodiments of quantum circuits implementing other types of superconducting qubits that would also utilize Josephson Junctions as described herein, all of which are within the scope of the present disclosure. Furthermore, fabrication methods and resulting planar Josephson Junctions disclosed herein may be used in quantum circuits implementing qubits other than superconducting qubits as well as in non-quantum circuit components (such as e.g. Rapid single flux quantum (RSFQ) log, low voltage RSFQ (LV-RSFQ), reciprocal quantum logic (RQL), all of which are also within the scope of the present disclosure.

[0064] In various embodiments, circuits employing planar Josephson Junctions described herein, e.g. quantum circuits such as the one shown in FIGs. 1A-1C as well as non-quantum (i.e. classical) circuits as known in the art, may be used to implement components associated with an integrated circuit (IC). Such components may include those that are mounted on or embedded in an IC, or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., as well as in a number of applications within or associated with non-quantum systems, depending on the components associated with the integrated circuit. The integrated circuit may be employed as part of a chipset for executing one or more related functions in a system.

Exemplary quantum computing device

[0065] FIG. 2 provides an illustration of an exemplary quantum computing device 200, e.g. a quantum computer, according to some embodiments of the present disclosure. The quantum computing device 200 may include any of the Josephson Junctions described herein, e.g. planar Josephson Junctions described herein.

[0066] A number of components are illustrated in FIG. 2 as included in the quantum computing device 200, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 200 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 200 may not include one or more of the components illustrated in FIG. 2, but the quantum computing device 200 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 200 may not include a display device 206, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 206 may be coupled. In another set of examples, the quantum computing device 200 may not include an audio input device 218 or an audio output device 208, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 218 or audio output device 208 may be coupled. [0067] The quantum computing device 200 may include a processing device 202 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 202 may include a quantum processing device 226 (e.g., one or more quantum processing devices), and a non-quantum processing device 228 (e.g., one or more non-quantum processing devices). The quantum processing device 226 may include one or more of the quantum circuits 100 disclosed herein, and may perform data processing by performing operations on the qubits 102 that may be generated in the quantum circuits 100, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of qubits may be read (e.g., by another qubit via a coupling resonator or externally via a readout resonator). The quantum processing device 226 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 226 may execute algorithms that are particularly suitable for quantum computers, such as

cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 226 may also include support circuitry to support the processing capability of the quantum processing device 226, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to- digital converters.

[0068] As noted above, the processing device 202 may include a non-quantum processing device 228. In some embodiments, the non-quantum processing device 228 may provide peripheral logic to support the operation of the quantum processing device 226. For example, the non-quantum processing device 228 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 228 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 226. For example, the non-quantum processing device 228 may interface with one or more of the other components of the quantum computing device 200 (e.g., the communication chip 212 discussed below, the display device 206 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 226 and conventional components. The non-quantum processing device 228 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), crypto processors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. [0069] In some embodiments, the non-quantum processing device 228 may include any of the

Josephson Junctions described herein, e.g. planar Josephson Junctions described herein. Furthermore, in some embodiments, such a non-quantum processing device with planar Josephson Junctions as described herein may be included in a computing device similar to the computing device 200 but which is not a quantum computing device. In such embodiments, a non-quantum processing device with planar Josephson Junctions as described herein may be included in a device as the computing device 200 described herein but without the quantum processing device 226 and the cooling apparatus 224.

[0070] The quantum computing device 200 may include a memory 204, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 226 may be read and stored in the memory 204. In some embodiments, the memory 204 may include memory that shares a die with the non-quantum processing device 228. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0071] The quantum computing device 200 may include a cooling apparatus 224. The cooling apparatus 224 may maintain the quantum processing device 226 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 226. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 228 (and various other components of the quantum computing device 200) may not be cooled by the cooling apparatus 224, and may instead operate at room temperature. The cooling apparatus 224 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0072] In some embodiments, the quantum computing device 200 may include a communication chip 212 (e.g., one or more communication chips). For example, the communication chip 212 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0073] The communication chip 212 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long- Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 212 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 212 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 212 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 200 may include an antenna 222 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0074] In some embodiments, the communication chip 212 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 212 may include multiple communication chips. For instance, a first communication chip 212 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 212 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some

embodiments, a first communication chip 212 may be dedicated to wireless communications, and a second communication chip 212 may be dedicated to wired communications.

[0075] The quantum computing device 200 may include battery/power circuitry 214. The

battery/power circuitry 214 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 200 to an energy source separate from the quantum computing device 200 (e.g., AC line power).

[0076] The quantum computing device 200 may include a display device 206 (or corresponding interface circuitry, as discussed above). The display device 206 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example. [0077] The quantum computing device 200 may include an audio output device 208 (or corresponding interface circuitry, as discussed above). The audio output device 208 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0078] The quantum computing device 200 may include an audio input device 218 (or corresponding interface circuitry, as discussed above). The audio input device 218 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M IDI) output).

[0079] The quantum computing device 200 may include a global positioning system (GPS) device 216 (or corresponding interface circuitry, as discussed above). The GPS device 216 may be in

communication with a satellite-based system and may receive a location of the quantum computing device 200, as known in the art.

[0080] The quantum computing device 200 may include an other output device 210 (or corresponding interface circuitry, as discussed above). Examples of the other output device 210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0081] The quantum computing device 200 may include an other input device 220 (or corresponding interface circuitry, as discussed above). Examples of the other input device 220 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0082] The quantum computing device 200, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

Detailed description of proposed structures and methods of fabrication thereof

[0083] In order to highlight the advantages offered by the planar Josephson Junction structures as proposed herein, it would be helpful to first explain how conventional Josephson Junctions are fabricated using a double-angle shadow evaporation method. [0084] FIGs. 3A-3C provide a schematic illustration of one example of a photoresist mask 300 provided over a substrate 302 for fabricating Josephson Junctions using a double-angle shadow evaporation approach. Each of FIGs. 3A-3C provides a view of the same photoresist mask 300 over the substrate 302, but perspectives of these views are different. FIG. 3A provides a top-down view (i.e. a view from a point above the substrate 302). FIG. 3B provides a cross-sectional view with a cross-section of the structure of FIG. 3A taken along a horizontal dashed line shown in FIG. 3A. Finally, FIG. 3C provides a cross-sectional view with a cross-section of the structure of FIG. 3A taken along a vertical dashed line shown in FIG. 3A. A legend provided within a dashed box at the bottom of FIGs. 3A-3C illustrates patterns used to indicate different elements shown in FIGs. 3A-3C, so that the FIGs are not cluttered by many reference numerals.

[0085] Josephson Junctions may be created by a double-angle shadow evaporation approach using a two-layer photoresist mask 300 that includes a bottom photoresist layer 304 and a top photoresist layer 306 as shown in FIGs. 3A-3C. The bottom layer 306 is undercut from the top layer 304 in that some portions of the top layer 304 hang, or are suspended, over the bottom layer 306. The bottom layer 306 is undercut in such a manner that the top layer 304 of photoresist forms a suspended bridge 308, known as a Dolan bridge, over a section of the substrate 302. Ways for fabricating such undercuts in photoresist are well-known in the art of photolithographic processing and, therefore, are not described here in detail.

[0086] In order to form a Josephson Junction, metals are then deposited through the photoresist mask 300 with the suspended bridge. Conventionally, this is done as illustrated in FIGs. 4A-4C. Each of FIGs. 4A-4C illustrates a result of different subsequent fabrication steps. FIG. 4C provides two views of the same structure. The view on the right side of FIG. 4C is a top-down view (i.e. a view similar to that shown in FIG. 3A). The view on the left side of FIG. 4C is a cross-sectional view with a cross-section of the structure of FIG. 4C taken along a horizontal dashed line shown in FIG. 4C (i.e. a view similar to that shown in FIG. 3B). Each of FIGs. 4A and 4B only provide a cross-sectional view similar to that of the left side of FIG. 4C but at an earlier fabrication step. Similar to FIGs. 3A-3C, a legend provided within a dashed box at the bottom of FIGs. 4A-4C illustrates patterns used in the figures to indicate different elements shown in FIGs. 4A-4C. Moreover, similar reference numerals in FIGs. 3A-3C and FIGs. 4A-4C are used to illustrate analogous elements in the figures. For example, reference numerals 302 and 402, shown, respectively, in FIGs. 3 and 4 refer to a substrate, reference numerals 304 and 404 - to a bottom mask layer, and so on. When provided with reference to one of the FIGs. 3A-3C and FIGs. 4A-4C, discussions of these elements are applicable to other figures, unless stated otherwise. Thus, in the interests of brevity, discussions of similar elements are not repeated for each of the figures but, rather, the differences between the figures are described. [0087] As previously described herein, Josephson Junctions for quantum circuits have conventionally been fabricated by providing a thin layer of dielectric sandwiched between two layers of

superconductors, the dielectric layer acting as the barrier in a superconducting tunnel junction.

According to the double-angle shadow evaporation approach, such a device is fabricated by, first, depositing a layer of a first superconductor 410 on the substrate 402, as shown in FIG. 4A, through the two-layer mask such as e.g. the one shown in FIGs. 3A-3C. The first superconductor is deposited at an angle with respect to the substrate 402, as shown in FIG. 4A with an angle Θ1. Slanted dotted-dashed lines in FIG. 4A illustrate the direction of deposition of the first superconductor 410. A layer of the first superconductor 410 may have a thickness between e.g. 10 and 300 nanometers (nm), e.g. between 40 and 100 nm.

[0088] The first superconductor 410 forms a base electrode of the future Josephson Junction. A layer of insulator 411 (also referred to herein as a "dielectric layer 411" or a "dielectric 411"), shown in FIGs. 4B and 4C, is then provided over the first superconductor 410 to form a tunnel barrier of the future Josephson Junction. The tunnel barrier is formed by oxidizing the first superconductor 410, thus creating a layer of first superconductor oxide on its surface. Such an oxide may have a thickness between e.g. 1 and 5 nm, typically for qubit applications between 1 and 2 nm.

[0089] The fact that the choice of a tunnel barrier in a double-angle shadow evaporation method is constrained to an oxide of the base electrode superconductor limits the choice of the superconductor used as the first superconductor 410 in that the superconductor must be such that a controlled layer of oxide may be created on it. In practice, aluminum oxide is the only controlled oxide that may be formed from a metal. Therefore, currently aluminum is the only superconducting metal that is used for the base electrode of Josephson Junctions fabricated using the double-angle shadow evaporation technique.

[0090] After the layer of dielectric 411 is provided on the first superconductor 410, a second superconductor 412 is deposited through the mask but at a different angle with respect to the substrate 402 than Θ1. FIG. 4B illustrates the second angle as an angle Θ2 and slanted dotted-dashed lines in FIG. 4B illustrate the direction of deposition of the second superconductor 412. In some embodiments, the first and the second superconductors 410, 412 are deposited at the opposite angles, if measured with respect to a normal to the substrate 402. Conventionally, the second superconductor 420 has been aluminum because the first superconductor must be aluminum, as described above (using the same metal for evaporation is easier for fabrication). A layer of the second superconductor 412 may have a thickness between e.g. 10 and 300 nm, typically between 40 and 100 nm. The second superconductor 412 forms a counter electrode (i.e. counter to the base electrode formed by the first superconductor 410) of the future Josephson Junction. The first and second superconductors 410, 412 are usually deposited using a non-conformal process, such as e.g. evaporative deposition. After deposition of the second superconductor 412, the deposition mask is removed, removing with it any first and/or second superconductor 410, 412 deposited on top of it.

[0091] In general, the above-described process of creating patterned structures of one or more target materials (in this case, structures made of the first and second superconductors 410, 412) on the surface of a substrate using a sacrificial material such as photoresist is referred to as a lift-off method. Lift-off is a type of an additive technique, as opposed to subtractive techniques like etching, and may be applied in cases where a direct etching of structural material would have undesirable effects on one or more layers below.

[0092] After the deposition mask is removed, the resulting Josephson Junction is left on the substrate 402 as shown in FIG. 4C as a Junction 414. The Junction 414 is formed by the small region of overlap under the photoresist bridge 408 (i.e. the area under the bridge 408 where the first superconductor 410, covered with a layer of a thin insulating material is overlapped by the second superconductor 412). Dimensions of the Junction 414 along x-axis and y-axis, shown in FIG. 4C as d_x and d_v, respectively, are typically between 50 and 1000 nm for any of d_x and d_v.

[0093] Furthermore, as a result of performing the double-angle shadow evaporation as described above, junctions of the first and second superconductors may also form on each side of the Josephson Junction 414, such junctions shown in FIGs. 4B and 4C as Junctions 416. However, because these junctions are of much larger dimensions than the Josephson Junction 414, e.g. measured several thousands of nm in the x-direction and hundreds of nm or more in the y-direction, they are essentially infinite for the Josephson effect to take place and, therefore, act as superconductors rather than Josephson Junctions.

[0094] One problem with the double-angle shadow evaporation fabrication approach described above is that it includes steps that are not suitable for manufacturing on the larger wafer sizes used in the semiconductor industry. For example, angled metal deposition step does not produce a uniform film across the wafer and would prohibit uniform qubit performance across large area. Moreover, the fabrication approach described above relies on lift-off of metal films to produce wires remaining on the wafer. The lift-off technique is not amenable to the chemical waste systems of wafer cleaning tools and would not facilitate high volume manufacturing or even an extension to many qubits on a single wafer.

[0095] Another problem with the double-angle shadow evaporation approach described above is that it limits materials that may be employed in forming Josephson Junctions. As described above, Josephson Junctions fabricated the double-angle shadow evaporation approach can only use Al as the superconductor for the base electrode. This may be problematic because interconnects in quantum circuits are typically made from other superconducting materials such as e.g. Nb, TiN and NbTiN and interfaces between the different superconducting materials used for Josephson Junctions and interconnects present yet another source of losses. Any losses are especially significant in context of quantum circuits where, sometimes, energy as small as that of a single photon is to be transmitted, making loss tolerance very low.

[0096] FIGS. 5-8 provide schematic illustrations of arrangements 500-800, respectively, including planar Josephson Junctions according to various embodiments of the present disclosure and FIGS. 9-13 provide flow charts of methods for fabricating such Josephson Junctions. The Josephson Junctions described below improve on some of the challenges of the existing structures described above. For one, their fabrication processes described herein are more suitable for large-scale manufacturing at least in that they do not require angled evaporation and lift-off. In addition, using the planar architecture as described herein advantageously extends the arsenal of superconducting materials which may be employed as the superconductor elements of Josephson Junctions to include those besides aluminum employed in the previously used double-shadow angle evaporation method.

Furthermore, some of the fabrications methods described herein allow relaxing some of the critical dimension requirements, leading to reduced variability due to manufacturing variations in the final individual Josephson Junctions.

[0097] A legend provided within a dashed box at the bottom of FIGS. 5-8 illustrates patterns used to indicate various materials which may be used in the structures of FIGS. 5-8, so that these FIGS are not cluttered by many reference numerals. Furthermore, each of FIGS. 5-8 provides two views of the same structure. Namely, the view on the right side of each of FIGS. 5-8 is a top-down view of a Josephson Junction, i.e. a view in an x-y plane of an example reference coordinate system shown at the bottom of each of FIGS. 5-8. On the other hand, the view on the left side of each of FIGS. 5-8 is a cross-sectional view of a Josephson Junction, with a cross-section taken along a y-z plane as indicated with a dashed line AA in the view on the right side of each of FIGS. 5-8.

[0098] Although a single Josephson Junction is illustrated in each of FIGS. 5-8, this is simply for ease of illustration, and any number of Josephson Junctions may be provided in a single device, e.g. in a single superconducting qubit, according to various embodiments of the present disclosure. Furthermore, the arrangements 500-800 are intended to show relative arrangements of some of the

element/components therein, and, in various embodiments, the arrangement 500-800, or portions thereof, may include other components that are not illustrated (e.g., electrical contacts to the superconductors of the Josephson Junctions or additional layers such as e.g. any additional layers provided on the substrate prior to fabrication of a Josephson Junction thereon, etc.).

[0099] In general, implementations of the present disclosure may be formed or carried out on a substrate, such as e.g. the substrate 502 shown in FIG. 5. The substrate 502 may comprise any substrate suitable for realizing quantum circuit components described herein. In one implementation, the substrate 502 may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure. Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.

[0100] In some embodiments, the substrate 502 may be cleaned to remove surface-bound organic and metallic contaminants, as well as subsurface contamination, prior to provision of Josephson Junction(s) thereon. In some embodiments, cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)).

[0101] FIG. 5 illustrates a Josephson Junction provided over the substrate 502, the Josephson Junction including a first superconductor element 504-1, a second superconductor element 504-2 (collectively referred to herein as the superconductor elements 504), and a tunneling link element 506 provided between the first and second superconductor elements 504. As can be seen in FIG. 5, the first and second superconductor elements 504 and the tunneling link element 506 are provided in a single plane over the substrate 502, over different, non-overlapping areas of the substrate 502 indicated in FIG. 5, respectively, as a first area Al, a second area A2, and a third area A3.

[0102] Each of the first and second superconductor elements 504 can be made from a suitable superconductive material. While each of FIGS. 5-8 illustrate the first and second superconductor elements 504 made of the same superconductive material 514, in other embodiments, the

superconductive material of the first superconductor element 504-1 can be different from the superconductive material of the second superconductor element 504-2. In some embodiments, all of the first and second superconductor elements 504 and the tunneling link element 506 may be made of the same material, e.g. the same superconductive material. In other embodiments, each of these elements may be made of different materials, e.g. of different superconductive materials. Materials referred to herein as superconductive materials may include any conducting or superconducting material suitable for serving as an interconnect in a quantum circuit, such as e.g. aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), molybdenum rhenium (Mo e), etc., or any alloy of two or more superconducting/conducting materials.

[0103] Because the first and second superconductor elements 504 and the tunneling link element 506 are provided in a single plane over the substrate 502, they do not overlap one another in a stack-like manner. Such an arrangement for a Josephson Junction is in stark contrast to conventional Josephson Junctions used in quantum circuits, such as the ones formed by the double-angle shadow evaporation method described above or other Josephson Junctions formed by providing an insulator tunneling barrier sandwiched between two superconductors. Instead of being made of an insulator, the tunneling link element 506 can be made of a superconductive or any electrically conductive material 514.

Nevertheless, the tunneling link element 506 can implement the weak link of the Josephson Junction of FIG. 5, i.e. weaken the superconductivity between the first and second superconductors 504, by being constricted (i.e. made narrower) compared to the dimensions of the first and second superconductors 504. The constriction can be seen in the view on the right side of FIG. 5 illustrating that a width of the tunneling link element 506, labeled in FIGS. 5-8 as a width W_ti, is smaller than a width of each of the first and second superconductor element 504, labeled in FIGS. 5-8 as a width Wsc. As used herein, the "width" of these elements refers to a dimension of an element within a plane of the element (i.e. a plane parallel to the plane of the substrate - the x-y plane for the example coordinate system shown in FIGS. 5-8), measured in a direction perpendicular to the shortest line connecting the first and second superconductor elements 504 (i.e. the x-direction for the example coordinate system shown in FIGS. 5- 8). In some embodiments, the width of the tunneling link element 506 is at least two times smaller than the width of each of the first and second superconductor elements 504. For example, the width of the tunneling link element 506 may be between 1 and 20 nanometers, including all values and ranges therein (e.g. between 1 and 15 nanometers, or between 3 and 10 nanometers), while the width of each of the first and second superconductor elements 504 may be between 50 nanometers and several micrometers, including all values and ranges therein (e.g. between 50 and 500 nanometers, or between 100 and 1000 nanometers).

[0104] Due to the constriction of the tunneling link element 506 in the middle of the Josephson Junction, Josephson Junctions such as the one shown in FIG. 5 are referred to herein as "mid- constricted planar Josephson Junction," in order to differentiate those from planar Josephson Junctions where constriction is achieved by making the tunneling link element thinner. The latter planar

Josephson Junctions described below are referred to herein as "thinning-constricted planar Josephson Junctions."

[0105] In the example illustration of FIG. 5, a thickness of the tunneling link element 504, labeled in FIGS. 5-8 as a thickness T_ti, is substantially equal to a thickness of each of the first and second superconductor elements 504, labeled in FIGS. 5-8 as a thickness Tsc. As used herein, the "thickness" of these elements refers to a dimension of an element measured in a direction perpendicular to the plane of the substrate (i.e. the z-direction for the example coordinate system shown in FIGS. 5-8). The thicknesses being "substantially equal" refers to the thicknesses of the tunneling link element, the first superconductor element, and the second superconductor element deviating from one another by less than 10%, e.g. less than 5% or less than 3%. In some embodiments, the thickness of the tunneling link element 506 may be between 10 and 1000 nanometers, including all values and ranges therein (e.g. between 20 and 250 nanometers, or between 50 and 200 nanometers).

[0106] In other embodiments of a mid-constricted Josephson Junction such as the one illustrated in FIG. 5, further weakening of the superconductivity between the first and second superconductor elements 504 may be achieved by reducing the thickness of the tunneling element 506, compared to the thicknesses of the first and second superconductor elements 504, as e.g. described with reference to the arrangements shown in FIGS. 6-8.

[0107] A length of the tunneling link element 504, labeled in FIGS. 5-8 as a length L_ti, would depend on the materials 514 and 516 used, and may be in the range between 1 nanometer and hundreds of nanometers, including all values and ranges therein. As used herein, the "length" of various elements described herein refers to a dimension of an element in the direction of the shortest line connecting the first and second superconductor elements (i.e. the y-direction for the example coordinate system shown in FIGS. 5-8).

[0108] For the arrangement 500 shown in FIG. 5, the width of the tunneling link element 504 W_ti, may be considered to be the critical dimension that defines how the tunneling link element weakens the superconductivity between the first and second superconductors of the Josephson Junction.

[0109] Each of FIGS. 6-8 illustrate arrangements 600-800 of different embodiments of thinning- constricted planar Josephson Junctions. Similar reference numerals in FIGs. 6-8 and FIG. 5 are used to illustrate analogous elements in the figures. For example, reference numerals 602, 702, and 802 shown, respectively, in FIGS. 6-8 refer to a substrate analogous to the substrate 502 shown in FIG. 5, reference numerals 604, 704, and 804 shown, respectively, in FIGS. 6-8 refer to superconductor elements of a Josephson Junction analogous to the superconductor elements 504 shown in FIG. 5, and so on. When provided with reference to one of the FIGS. 5-8, discussions of these elements are applicable to other figures, unless stated otherwise. Thus, in the interests of brevity, discussions of similar elements are not repeated for each of the figures but, rather, the differences between the figures are described.

[0110] Similar to the arrangement 500 shown in FIG. 5, in the arrangement 600, the first and second superconductor elements 604 and the tunneling link element 606 are provided in a single plane over the substrate, over different, non-overlapping areas labeled in FIG. 6 as areas Al, A2, and A3, and may be formed of the same or different superconductive materials. [0111] The tunneling link element 606 can implement the weak link of the Josephson Junction of FIG. 6 by being made thinner compared to the thicknesses of the first and second superconductors 604. Such a "constriction by thinning" can be seen in the view on the left side of FIG. 6 illustrating that the thickness of the tunneling link element 606, T_ti, is smaller than the thickness of each of the first and second superconductor element 604, Tsc. In some embodiments, the thickness of the tunneling link element 606 may be at least two times smaller than the thickness of each of the first and second superconductor elements 604. For example, the thickness of the tunneling link element 606 may be between 0.5 and 20 nanometers, including all values and ranges therein (e.g. between 1 and 15 nanometers, or between 3 and 10 nanometers), while the thickness of each of the first and second superconductor elements 604 may be between 10 and 300 nanometers, including all values and ranges therein (e.g. between 20 and 250 nanometers, or between 50 and 200 nanometers).

[0112] In the example illustration of FIG. 6, the width of the tunneling link element 604, W_ti, is substantially equal to the width of each of the first and second superconductor elements 604, Wsc. The widths being "substantially equal" refers to the widths of the tunneling link element, the first superconductor element, and the second superconductor element deviating from one another by less than 10%, e.g. less than 5% or less than 3%. In some embodiments, the widths of the tunneling link element 606 may be between 25 nanometers and several micrometers, including all values and ranges therein (e.g. between 25 and 500 nanometers, or between 100 and 1000 nanometers).

[0113] In other embodiments of thinning-constricted Josephson Junction such as the one illustrated in FIG. 6, further weakening of the superconductivity between the first and second superconductor elements 604 may be achieved by reducing the width of the tunneling element 606, compared to the widths of the first and second superconductor elements 604, as e.g. described with reference to the arrangement 500 shown in FIG. 5.

[0114] A length of the tunneling link element 604, length , would depend on the materials used for forming the first and second superconductor elements and the tunneling link element, and may be in the range between 1 nanometer and hundreds of nanometers, including all values and ranges therein.

[0115] Referring now to FIG. 7, similar to the arrangement 600 shown in FIG. 6, in the arrangement 700, the first and second superconductor elements 704 and the tunneling link element 706 are provided in a single plane over the substrate, over different, non-overlapping areas labeled in FIG. 7 as areas Al, A2, and A3, and may be formed of the same or different superconductive materials.

[0116] Also similar to the arrangement 600 shown in FIG. 6, the tunneling link element 706 can implement the weak link of the Josephson Junction of FIG. 7 by being made thinner compared to the thicknesses of the first and second superconductors 704. Such a "constriction by thinning" can be seen in the view on the left side of FIG. 7 illustrating that the thickness of the tunneling link element 706, T_ti, is smaller than the thickness of each of the first and second superconductor element 704, Tsc. [0117] Considerations regarding the thicknesses, widths, and lengths of the first and second superconductors and the tunneling link elements provided with reference to FIG. 6 are applicable to those shown in FIG. 7, in view of the following difference. As shown in FIG. 7, for the arrangement 700, the thickness of each of the first and second superconductor elements 704, Tsc, is viewed to include a sum of thicknesses of a layer of the superconductive material 714 of which the majority of the first and second superconductor elements 704 are formed and a layer of the superconductive material 716 of which the tunneling link element 706 is formed.

[0118] Referring now to FIG. 8, similar to the arrangement 700 shown in FIG. 7, in the arrangement 800, the first and second superconductor elements 804 and the tunneling link element 806 are provided in a single plane over the substrate, over different, non-overlapping areas labeled in FIG. 8 as areas Al, A2, and A3, and may be formed of the same or different superconductive materials.

[0119] Also similar to the arrangement 700 shown in FIG. 7, the tunneling link element 806 can implement the weak link of the Josephson Junction of FIG. 8 by being made thinner compared to the thicknesses of the first and second superconductors 804. Such a "constriction by thinning" can be seen in the view on the left side of FIG. 8 illustrating that the thickness of the tunneling link element 806, T_ti, is smaller than the thickness of each of the first and second superconductor element 804, Tsc.

Considerations regarding the thicknesses, widths, and lengths of the first and second superconductors and the tunneling link elements provided with reference to FIG. 7 are applicable to those shown in FIG. 8.

[0120] For the arrangements shown in FIGS. 6-8, the thickness of the tunneling link element T_ti, may be considered to be the critical dimension that defines how the tunneling link element weakens the superconductivity between the first and second superconductors of the Josephson Junction.

[0121] The arrangements 500, 600, 700, and 800 disclosed herein may be manufactured using any suitable techniques. FIGS. 9-13 provide flow charts of exemplary methods for fabricating planar Josephson Junctions as shown in FIGS. 5-8, according to various embodiments of the present disclosure. Although the particular manufacturing operations discussed below with reference to FIGS. 9-13 are illustrated as manufacturing particular embodiments of the arrangements shown in FIGS. 5-8, these operations may be applied to manufacture many different embodiments of the arrangements shown in FIGS. 5-8, as discussed herein. Any of the elements discussed below with reference to FIGS. 9-13 may take the form of any of the embodiments of those elements discussed above (or otherwise disclosed herein). Furthermore, although the operations discussed below with reference to the methods shown in FIGS. 9-13 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the methods 900-1300 may be illustrated with reference to one or more of the embodiments discussed above, but the methods 900- 1300 may be used to manufacture any suitable circuit element, either quantum circuit element or non- quantum circuit element, comprising one or more planar Josephson Junctions according to any embodiments disclosed herein.

[0122] FIG. 9 provides a flow chart of a method 900 suitable for fabricating a mid-constricted planar Josephson Junction such as the one shown in FIG. 5, according to some embodiments of the present disclosure.

[0123] With reference to FIG. 9, the method 900 may begin with process 902, where a layer of a superconductor material is deposited over a substrate, e.g. over the substrate 502 shown in FIG. 5. The layer may include any conducting or superconducting material suitable for use in a quantum circuit, such as e.g. aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), molybdenum rhenium (Mo e), etc., or any alloy of two or more

superconducting/conducting materials. Such a layer may be deposited over the substrate using any known techniques for depositing conducting/superconducting materials, such as e.g. atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating. For ease of fabrication, the first and second superconductor elements 504 and the weak link 506 may be made from the same material, referred to in the remainder of the description of the method 900 as the superconductive material 514/516.

[0124] At 904, lithography to define the desired shape of the first and second superconductor elements 504 of a Josephson Junction may be carried out using any known lithographic techniques. For example, a patterning technique employing photoresist or other masks defining the dimensions and location of the first and second superconductor elements of a Josephson Junction may be used. An exemplary photoresist patterning technique could include depositing a photoresist over the layer of interest, in this case - over the surface of the superconductive material 514/516 deposited in the process 902. The photoresist may be a positive or negative resist and may include for example, poly(methyl methacrylate), poly(methyl glutarimide), DNQ/novolac, or SU-8 (an expoxy based negative resist). The photoresist may be chemically amplified containing a photoacid generator and may be based on polymers or co-polymers which contain aromatic rings or alicyclic norbornene derivatives (e.g. for etch resistance), and have protecting groups such as t-butyl. The polymers may include polystyrene or acrylate polymers. The photoresist may be deposited by a casting process such as, for example, spin- coating. The photoresist may then be patterned by optically projecting an image of a desired pattern onto the photoresist using photolithography, such as optical photolithography, immersion

photolithography, deep UV lithography, extreme UV lithography, or other techniques. A developer, such as tetramethylammonium hydroxide TMAH (with or without surfactant) at a concentration of in the range of 0.1 N to 0.3 N, may be applied to the photoresist, such as by spin-coating, and portions of the photoresist are removed to expose regions of the underlying layer correlating to the desired pattern. In some embodiments, baking of the substrate may occur before or after any of the above actions. For example, the substrate may be prebaked to remove surface water. After application of the photoresist, a post application bake may occur, wherein at least a portion of the solvents in the photoresist are driven off. After exposure to light, a post-exposure bake may occur to induce chemical reactions, such as de-protecting the photoresist. After patterning, the resist may be hard baked.

[0125] Once lithographic patterning has been done to expose portions of the underlying surface of the layer of the superconductive material 514/516 in a patterned mask that defines location and arrangement of the future first and second superconductor elements 504, exposed portions of the underlying layer of the superconductive material 514/516 are then chemically etched, in process 906. During the etch, the exposed portions of the layer of the superconductive material 514/516 are removed up to the substrate 502 (or whichever layer that may be present on the substrate underneath the first and second superconductor elements 504), thus forming the first and second superconductor elements 504.

[0126] At 908, lithography to define the desired shape of the tunneling junction 506 of a Josephson Junction may be carried out using any known lithographic techniques, e.g. as described above. At 910, once lithographic patterning has been done to expose portions of the underlying surface of the layer of the superconductive material 514/516 in a patterned mask that defines location and arrangement of the future tunneling junction 506, exposed portions of the underlying layer of the superconductive material 514/516 are then chemically etched, e.g. as described above, thus forming the tunneling junction 506.

[0127] If photoresist patterning is used for creating the masks for forming the first and second superconductors 504 and the tunneling junction 506, the remaining photoresist may then optionally removed via e.g. a process such as ashing, where the photoresist is exposed to oxygen or fluorine, which combines with the photoresist to form ash. This also applies to other processes described herein that use photoresist patterning.

[0128] FIG. 10 provides a flow chart of a method 1000 suitable for fabricating a thinning-constricted planar Josephson Junction such as the one shown in FIG. 6, according to some embodiments of the present disclosure.

[0129] With reference to FIG. 10, the method 1000 may begin with process 1002, where a layer of a superconductor material is deposited over a substrate, e.g. over the substrate 602 shown in FIG. 6. For ease of fabrication, the first and second superconductor elements 604 and the tunneling junction 606 may be made from the same material, referred to in the remainder of the description of the method 1000 as the superconductive material 614/616. At 1004, lithography to define the desired shape of the first and second superconductor elements 604 of a Josephson Junction is carried out. At 1006, once lithographic patterning has been done to expose portions of the underlying surface of the layer of the superconductive material 614/616 in a patterned mask that defines location and arrangement of the future first and second superconductor elements 604, exposed portions of the underlying layer of the superconductive material 614/616 are then chemically etched down to the substrate 602, in process 1006. Discussions provided above with reference to processes 902, 904, and 906 are applicable to the processes 1002, 1004, and 1006, and, therefore, not repeated here.

[0130] At 1008, lithography to define the desired shape of the tunneling junction 606 of a Josephson Junction may be carried out in a manner analogous to that described above for the process 908. At 1010, once lithographic patterning has been done to expose portions of the underlying surface of the layer of the superconductive material 614/616 in a patterned mask that defines location and arrangement of the future tunneling junction 606, exposed portions of the underlying layer of the superconductive material 614/616 are then chemically etched to form the tunneling junction 606 of a desired thickness.

[0131] FIG. 11 provides a flow chart of a first method, a method 1100, suitable for fabricating a thinning-constricted planar Josephson Junction such as the one shown in FIG. 7, according to some embodiments of the present disclosure.

[0132] With reference to FIG. 11, the method 1100 may begin with a process 1102, where a layer of a first superconductor material is deposited over a substrate. In FIGS. 11-13 references are made to "thin" and "thick" superconductor layers. In context of these FIGS, the terms "thin" and "thick" refer to relative thicknesses of the layers with respect to one another. In particular, "thin" refers to the range of thicknesses suitable for implementing a tunneling link element of a planar Josephson Junction as described herein (T_ti) and "thick" refers to the range of thicknesses suitable for implementing first and second superconductor elements of a Josephson Junction as described herein (Tsc). Thus, in process 1102, a layer of the material 716 having a thickness T_ti is deposited over the substrate 702 shown in FIG. 7. ALD deposition may be particularly advantageous for the deposition of "thin" SC layers because it allows high level of control over the thickness and uniformity of the layer.

[0133] The method 1100 may then proceed with a process 1104, where a "thick" layer of a second superconductor material is deposited over the layer of the first superconductor material deposited in process 1102. For example, at 1104, a layer of the material 714, having a thickness Tsc, is deposited over the layer of the material 716 shown in FIG. 7. In this scenario, the "thin" and the "thick" superconductor materials are different materials, more specifically materials having different etch characteristics (i.e. etch selective with respect to one another), which will be necessary for process 1108 described below.

[0134] At 1106, lithography to define the desired shape of the first and second superconductor elements 704 of a Josephson Junction is carried out, as described above. Once lithographic patterning has been done to expose portions of the underlying surface of the layer of the superconductive material 714 in a patterned mask that defines location and arrangement of the future first and second superconductor elements 704, exposed portions of the underlying layer of the superconductive material 714 are then chemically etched down to the superconductive material 716, in process 1108. Preferably the SC material 716 is such that etchants used to etch the material 714 in process 1108 do not etch the material 716. In other words, 716 acts as an etch stop for the etch process used to etch 714. A lithographic process and corresponding etch to define Wsc can be done before or after 1106 and 1108. This etch could use an etch chemistry that can etch through both 714 and 716, or alternatively the same etch as used in 1108, followed by a different etch targeted for 716.

[0135] FIG. 12 provides a flow chart of a second method, a method 1200, suitable for fabricating a thinning-constricted planar Josephson Junction such as the one shown in FIG. 7, according to some embodiments of the present disclosure. The method 1200 is alternative to the method 1100.

[0136] The method 1200 may begin with a process 1202, where a "thin" layer of a superconductor material is deposited over a substrate, e.g. the superconductor material 716 on the substrate 702, which may be done as in the process 1102.

[0137] The method 1200 may then proceed with a process 1204, where lithography is carried out to provide a mask of a sacrificial dielectric material over the substrate with the thin layer of the superconductor 716 on it at a location where the tunneling junction 706 will be. Examples of dielectric materials that may be used as the sacrificial material in process 1204 include, but are not limited to, silicon dioxide (SiC ), carbon doped oxide (CDO), silicon nitride, organic polymers such as

perfluorocyclobutane, polytetrafluoroethylene or poly(methyl methacrylate) (PM MA), fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. In some embodiments, the sacrificial material may be deposited using e.g. chemical vapor deposition or/and plasma-enhanced chemical vapor deposition, as typically done in conventional processing. In still other embodiments, the sacrificial material may include a dielectric material formed using coating techniques involving cross-linking of liquid precursors into solid dielectric materials.

[0138] Then, in a process 1206, a "thick" layer of a second superconductor material is deposited over the substrate 702 with the "thin" layer of the superconductor material 716 and the patterned sacrificial material. For example, at 1206, a layer of the material 714, having a thickness Tsc, is deposited. In this scenario, the "thin" and the "thick" superconductor materials may be either different or the same materials.

[0139] At 1208, the sacrificial material deposited in the process 1204 is removed, removing with it the "thick" superconductor material 714, leaving behind the opening that forms the tunneling junction 706. In some embodiments, removal of the sacrificial material may be carried out by an etching process, such as e.g. an isotropic etch, where the sacrificial material under the "thick" superconductor material 714 is also etched even though it is not exposed (i.e. at least a portion of the sacrificial material under the "thick" superconductor material 714 is undercut). Isotropic etching etches in multiple directions (both vertically and horizontally), unlike e.g. dry etching which only etches in a single direction, and, therefore, can be used to achieve undercutting of the sacrificial material under the "thick" superconductor material 714, thereby providing a void or a gap that allows removal of the "thick" superconductor material 714 over the sacrificial material.

[0140] FIG. 13 provides a flow chart of a method 1300 suitable for fabricating a thinning-constricted planar Josephson Junction such as the one shown in FIG. 8, according to some embodiments of the present disclosure.

[0141] The method 1300 may begin with a process 1302, where a "thick" layer of a superconductor material is deposited over a substrate, e.g. the superconductor material 814 on the substrate 802, which may be done as in the process 1104.

[0142] At 1304, lithography to define the desired shape of the first and second superconductor elements 804 of a Josephson Junction is carried out, as described above. At 1306, once lithographic patterning has been done to expose portions of the underlying surface of the layer of the

superconductive material 814 in a patterned mask that defines location and arrangement of the future first and second superconductor elements 804, exposed portions of the underlying layer of the superconductive material 814 are then chemically etched down to the substrate 802, in process 1306, as described above. Then, in a process 1308, a "thin" layer of a second superconductor material is deposited over the substrate 802 with the "thick" layer of the patterned superconductor material 814 on it. For example, at 1308, a layer of the material 816, having a thickness T_ti, is deposited. In this scenario, the "thin" and the "thick" superconductor materials may be either different or the same materials.

[0143] Some Examples in accordance with various embodiments of the present disclosure are now described.

[0144] Example 1 provides a quantum circuit component. The component includes a substrate; a Josephson Junction provided over the substrate, the Josephson Junction comprising a first superconductor element disposed over a first area of the substrate, a second superconductor element disposed over a second area, and a tunneling link element configured to electrically couple the first superconductor element and the second superconductor element by being provided over a third area of the substrate, the third area being between the first area and the second area (the first, second, and third areas being different, non-overlapping areas of the substrate).

[0145] Example 2 provides the quantum circuit component according to Example 1, where the first superconductor element, the second superconductor element, and the tunneling link element are in a single plane over the substrate (i.e. these elements are in the same plane). [0146] Example 3 provides the quantum circuit component according to any one of the preceding Examples, where the first superconductor element, the second superconductor element, and the tunneling link element do not overlap (in contrast to JJs formed by conventional techniques where at least portions of these elements of a JJ are provided on top of one another).

[0147] Example 4 provides the quantum circuit component according to any one of Examples 1-3, where a width of the tunneling link element is at least two times smaller than a width of each of the first superconductor element and the second superconductor element.

[0148] Example 5 provides the quantum circuit component according to Example 4, where the width of the tunneling link element is between 1 nanometer and 20 nanometers.

[0149] Example 6 provides the quantum circuit component according to Examples 4 or 5, where a thickness of the tunneling link element is substantially equal to a thickness of each of the first superconductor element and the second superconductor element.

[0150] Example 7 provides the quantum circuit component according to any one of Examples 1-3, where a thickness of the tunneling link element is at least two times smaller than a thickness of each of the first superconductor element and the second superconductor element.

[0151] Example 8 provides the quantum circuit component according to Example 7, where the thickness of the tunneling link element is between 0.5 nanometer and 20 nanometers.

[0152] Example 9 provides the quantum circuit component according to Examples 7 or 8, where the thickness of each of the first superconductor element and the second superconductor element is between 10 nanometers and 300 nanometers.

[0153] Example 10 provides the quantum circuit component according to any one of Examples 7-9, where a width of the tunneling link element is substantially equal to a width of each of the first superconductor element and the second superconductor element.

[0154] Example 11 provides the quantum circuit component according to any one of the preceding Examples, where the tunneling link element is formed of a material different from a material of the first superconductor element and the second superconductor element.

[0155] Example 12 provides the quantum circuit component according to any one of the preceding Examples, where the first superconductor element and the second superconductor element are coupled to one or more further components of the quantum circuit.

[0156] Example 13 provides the quantum circuit component according to Example 12, where the one or more further components of the quantum circuit include elements of a superconducting quantum interference device (SQUID).

[0157] Example 14 provides the quantum circuit component according to Example 12, where the one or more further components of the quantum circuit include a capacitor of a superconducting qubit. [0158] In various embodiments, planar Josephson Junctions as described above could be a part of a superconducting qubit, e.g. a part of a charge qubit, in particular a part of a transmon, or a part of a flux qubit.

[0159] Example A provides a quantum integrated circuit package, including a substrate and a first superconductive qubit and a second superconductive qubit provided over the substrate, where each of the first superconductive qubit and the a second superconductive qubit includes a Josephson Junction according to any one of the preceding Examples.

[0160] Example A2 provides the quantum integrated circuit package according to Example Al, where the first superconductive qubit and the second superconductive qubit are coupled by a coupling resonator.

[0161] Example A3 provides a quantum computing device, including one or more integrated circuit packages according to Examples Al or A2.

[0162] Example A4 provides the quantum computing device according to Example A3, further including a cooling apparatus configured to maintain the first superconductive qubit and the second

superconductive qubit at a cryogenic temperature during operation of the first superconductive qubit and the second superconductive qubit.

[0163] Example 15 provides an electronic, non-quantum circuit, component. The component includes a substrate; a Josephson Junction provided over the substrate, the Josephson Junction including a first superconductor element disposed over a first area of the substrate, a second superconductor element disposed over a second area, and a tunneling link element configured to couple the first superconductor element and the second superconductor element by being provided over a third area of the substrate, the third area being between the first area and the second area, where a thickness of the tunneling link element is at least two times smaller than a thickness of each of the first superconductor element and the second superconductor element.

[0164] Example 16 provides the electronic component according to Example 15, where the thickness of the tunneling link element is between 0.5 nanometer and 20 nanometers.

[0165] Example 17 provides the electronic component according to Examples 15 or 16, where the thickness of each of the first superconductor element and the second superconductor element is between 10 nanometers and 300 nanometers.

[0166] Example 18 provides the electronic component according to any one of Examples 15-17, where a width of the tunneling link element is substantially equal to a width of each of the first

superconductor element and the second superconductor element.

[0167] Example 19 provides a method for fabricating at quantum circuit component including a Josephson Junction, the method including providing, over a substrate, a layer of an electrically conductive material; performing lithography to define a first area within the layer as an area for forming a first superconductor element of the Josephson Junction, a second area within the layer as an area for forming a second superconductor element of the Josephson Junction, and a third area within the layer as an area for forming a tunneling link element of the Josephson Junction; and removing the electrically conductive material provided over the substrate in all areas of the layer except for the first area, the second area, and the third area.

[0168] Example 20 provides the method according to Example 19, where removing the electrically conductive material includes etching the electrically conductive material to the substrate.

[0169] Example 21 provides the method according to Example 20, where etching includes an anisotropic etch of the electrically conductive material.

[0170] Example 22 provides the method according to any one of Exam ples 19-21, further including reducing a thickness of the electrically conductive material provided over the substrate in the third area.

[0171] Example 23 provides the method according to Example 22, where reducing the thickness includes perform ing an anisotropic etch of the electrically conductive material in the third area until a thickness of the electrically conductive material in the third area is at least two times smaller than a thickness of the electrically conductive material in each of the first area and the second area.

[0172] Example 24 provides a method for fabricating at quantum circuit component including a Josephson Junction, the method including providing, over a substrate, a layer of a first electrically conductive material, the first layer having a thickness between 0.5 nanometers and 20 nanometers; providing, over the layer of the first electrically conductive material, a layer of a second electrically conductive material, the second layer having a thickness between 10 nanometers and 300 nanometers; performing lithography to define an area over the substrate for forming a tunneling link element of the Josephson Junction; and removing the first electrically conductive material in the area defined for forming a tunneling link element.

[0173] Example 25 provides the method according to Example 24, where providing the layer of the first electrically conductive material includes performing atomic layer deposition (ALD) of the first electrically conductive material.

[0174] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0175] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following Examples should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A quantum circuit component comprising:

a substrate;

a Josephson Junction provided over the substrate, the Josephson Junction comprising a first superconductor element disposed over a first area of the substrate,

a second superconductor element disposed over a second area, and

a tunneling link element configured to couple the first superconductor element and the second superconductor element by being provided over a third area of the substrate, the third area being between the first area and the second area.

2. The quantum circuit component according to claim 1, wherein the first superconductor element, the second superconductor element, and the tunneling link element are in a single plane over the substrate.

3. The quantum circuit component according to claim 1, wherein the first superconductor element, the second superconductor element, and the tunneling link element do not overlap.

4. The quantum circuit component according to any one of claims 1-3, wherein a width of the tunneling link element is at least two times smaller than a width of each of the first superconductor element and the second superconductor element.

5. The quantum circuit component according to claim 4, wherein the width of the tunneling link element is between 1 nanometer and 20 nanometers.

6. The quantum circuit component according to claim 4, wherein a thickness of the tunneling link element is substantially equal to a thickness of each of the first superconductor element and the second superconductor element.

7. The quantum circuit component according to any one of claims 1-3, wherein a thickness of the tunneling link element is at least two times smaller than a thickness of each of the first superconductor element and the second superconductor element.

8. The quantum circuit component according to claim 7, wherein the thickness of the tunneling link element is between 0.5 nanometer and 20 nanometers.

9. The quantum circuit component according to claim 7, wherein the thickness of each of the first superconductor element and the second superconductor element is between 10 nanometers and 300 nanometers.

10. The quantum circuit component according to claim 7, wherein a width of the tunneling link element is substantially equal to a width of each of the first superconductor element and the second superconductor element.

11. The quantum circuit component according to any one of claims 1-3, wherein the tunneling link element is formed of a material different from a material of the first superconductor element and the second superconductor element.

12. The quantum circuit component according to any one of claims 1-3, wherein the first superconductor element and the second superconductor element are coupled to one or more further components of the quantum circuit.

13. The quantum circuit component according to claim 12, wherein the one or more further components of the quantum circuit comprise elements of a superconducting quantum interference device (SQUID).

14. The quantum circuit component according to claim 12, wherein the one or more further components of the quantum circuit comprise a capacitor of a superconducting qubit.

15. An electronic component comprising:

a substrate;

a second superconductor element disposed over a second area, and

a tunneling link element configured to couple the first superconductor element and the second superconductor element by being provided over a third area of the substrate, the third area being between the first area and the second area,

wherein a thickness of the tunneling link element is at least two times smaller than a thickness of each of the first superconductor element and the second superconductor element.

16. The electronic component according to claim 15, wherein the thickness of the tunneling link element is between 0.5 nanometer and 20 nanometers.

17. The electronic component according to claim 15, wherein the thickness of each of the first superconductor element and the second superconductor element is between 10 nanometers and 300 nanometers.

18. The electronic component according to any one of claims 15-17, wherein a width of the tunneling link element is substantially equal to a width of each of the first superconductor element and the second superconductor element.

19. A method for fabricating at quantum circuit component comprising a Josephson Junction, the method comprising:

providing, over a substrate, a layer of an electrically conductive material;

performing lithography to define

a first area within the layer as an area for forming a first superconductor element of the Josephson Junction,

a second area within the layer as an area for forming a second superconductor element of the Josephson Junction, and

a third area within the layer as an area for forming a tunneling link element of the Josephson Junction; and

removing the electrically conductive material provided over the substrate in all areas of the layer except for the first area, the second area, and the third area.

20. The method according to claim 19, wherein removing the electrically conductive material comprises etching the electrically conductive material to the substrate.

21. The method according to claim 20, wherein etching comprises an anisotropic etch of the electrically conductive material.

22. The method according to any one of claims 19-21, further comprising:

reducing a thickness of the electrically conductive material provided over the substrate in the third area.

23. The method according to claim 22, wherein reducing the thickness comprises performing an anisotropic etch of the electrically conductive material in the third area until a thickness of the electrically conductive material in the third area is at least two times smaller than a thickness of the electrically conductive material in each of the first area and the second area.

24. A method for fabricating at quantum circuit component comprising a Josephson Junction, the method comprising:

providing, over a substrate, a layer of a first electrically conductive material, the first layer having a thickness between 0.5 nanometers and 20 nanometers;

providing, over the layer of the first electrically conductive material, a layer of a second electrically conductive material, the second layer having a thickness between 10 nanometers and 300 nanometers;

performing lithography to define an area over the substrate for forming a tunneling link element of the Josephson Junction; and

removing the first electrically conductive material in the area defined for forming a tunneling link element.

25. The method according to claim 24, wherein providing the layer of the first electrically conductive material comprises performing atomic layer deposition (ALD) of the first electrically conductive material.