WO2017217958A1

WO2017217958A1 - Superconducting qubits with caps on superconductors

Info

Publication number: WO2017217958A1
Application number: PCT/US2016/037132
Authority: WO
Inventors: Zachary R. YOSCOVITS; David J. MICHALAK; Jeanette M. ROBERTS; Ravi Pillarisetty; James S. CLARKE
Original assignee: Intel Corporation
Priority date: 2016-06-13
Filing date: 2016-06-13
Publication date: 2017-12-21

Abstract

In one aspect of the present disclosure, a superconducting quantum circuit provided over a substrate is disclosed. The superconducting quantum circuit includes at least one quantum circuit element comprising a superconducting material; and a cap layer at least partially enclosing the superconducting material, the cap layer configured to minimize oxidation of at least a portion of the superconducting material being enclosed by the cap layer.

Description

SUPERCONDUCTING QUBITS WITH CAPS ON SUPERCONDUCTORS

Technical Field

[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to superconducting materials for use in quantum circuits and to methods of protecting such materials from oxidation.

Background

[0002] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0003] To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying figures, wherein like reference numerals represent like parts, in which:

[0004] FIG. 1A provides a schematic illustration of a superconducting quantum circuit, according to some embodiments of the present disclosure.

[0005] FIG. IB provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit, according to some embodiments of the present disclosure.

[0006] FIG. 1C provides a schematic illustration of an exemplary transmon, according to some embodiments of the present disclosure.

[0007] FIG. 2 provides a schematic illustration of quantum computing device, according to some embodiments of the present disclosure. [0008] FIG. 3 provides a schematic illustration of a structure comprising an oxidized superconductor.

[0009] FIG. 4 provides a schematic illustration of a structure comprising a superconductor covered with a protective cap, according to some embodiments of the present disclosure.

[0010] FIG. 5 provides a flow chart of an oxidation protection method, according to some embodiments of the present disclosure.

[0011] FIG. 6 provides a schematic illustration of a real-life structure comprising a superconductor covered with a protective cap described herein, according to some embodiments of the present disclosure.

Detailed Description

[0012] As previously described herein, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum- mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum- mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described

independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).

[0013] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics).

Classical computers encode data into binary values, commonly referred to as bits. At any given time, a bit is always in only one of two states - it is either 0 or 1. Quantum computers use so-called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.

[0014] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being about 10. One of the main challenges resides in protecting qubits from decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results. For this reason, materials, structures, and fabrication methods used for building qubits should continuously focus on reducing spurious (i.e. unintentional and undesirable) two-level systems (TLS's), thought to be the dominant source of qubit decoherence. In general, as used in quantum mechanics, a two-level (also referred to as "two-state") system is a system that can exist in any quantum superposition of two independent and physically distinguishable quantum states. Also for the reason of protection from decoherence, qubits are often operated at cryogenic temperatures, typically just a few degrees or even just a few millidegrees above absolute zero because cryogenic temperatures minimize the detrimental effects of spurious TLS's. None of these challenges ever had to be addressed for classical computers.

[0015] As the foregoing illustrates, ability to manipulate and read out quantum states, making quantum-mechanical phenomena visible and traceable, and ability to deal with and improve on the fragility of quantum states of a qubit present unique challenges not found in classical computers. These challenges explain why so many current efforts of the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits. Physical systems for implementing qubits that have been explored until now include e.g.

superconducting qubits, single trapped ion qubits, Silicon (Si) quantum dot qubits, photon polarization qubits, etc.

[0016] Out of the various physical implementations of qubits listed above, superconducting qubits are promising candidates for building a quantum computer. As the name implies, such qubits employ superconducting materials. Oxidation of such materials presents a source of loss, and, therefore, decoherence of superconducting qubits. Improvements with respect to this issue would be desirable.

[0017] As the foregoing description illustrates, building a quantum computer presents unique challenges not encountered in classical computing. The challenges are unique due to, both, the physics of data manipulation being different from that of classical computers (e.g. superposition, entanglement, and collapse), and the physical systems suitable to build quantum circuits of a quantum computer being different (e.g. the systems should be able to provide substantially lossless connectivity and be able to operate at cryogenic

temperatures). Described herein are structures that include superconducting materials for use in quantum circuits and methods of protecting such superconducting materials from oxidation.

[0018] In one aspect of the present disclosure, a superconducting quantum circuit provided over a substrate is disclosed. The superconducting quantum circuit includes at least one quantum circuit element comprising a superconducting material; and a cap layer at least partially enclosing the superconducting material, the cap layer configured to minimize oxidation of at least a portion of the superconducting material being enclosed by the cap layer.

[0019] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration,

embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0020] Furthermore, in the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well- known features are omitted or simplified in order not to obscure the illustrative

implementations.

[0021] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment(s). Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0022] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0023] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0024] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to

embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale.

[0025] As used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious TLS's may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. One metric of interest may be the decay rate associated with these losses (e.g. losses either from TLS's or residual resistance), and as long as the decay rate associated with these mechanisms is not worse than needed in order to achieve a fault-tolerant quantum calculation, then the losses are deemed acceptable and the idealized terms (e.g. superconducting or lossless) - appropriate. Specific values associated with an acceptable decay are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher decay rates. An adapted version of this metric, as well as other metrics suitable for a particular application in determining whether certain behavior may be referred to using idealized terms, are within the scope of the present disclosure.

[0026] As previously briefly explained above, quantum computing refers to the use of quantum mechanical properties to perform calculations. Some of these properties include superposition and entanglement. Just as classical computers are composed of bits that can either be in a 1 or a 0 state, a quantum computer is composed of quantum bits (i.e., qubits) which have states of |0) and | 1). Quantum mechanics allows for superpositions of the |0) and | 1) states with a general form of a|0) + b \ l) where a and b are complex numbers. When a qubit state is measured, it collapses to either state |0) with a probability of that happening being | a | ², or to state 11) with a probability of the latter being | b | ². Taking into account the fact that | a 1²+ 1 b 1²=1 (since the total probability must sum to unity) and ignoring an overall phase factor which does not have any observable effects, the general θ ' Θ

state can be re-written as cos - 10) +e^{l p} sin - 11), where φ is the phase difference between the two states.

[0027] Entanglement occurs when the interaction between two particles (e.g. two qubits) is such that the states of the two cannot be specified independently, but rather can only be specified for the whole system. This causes the states of the two qubits to be linked together such that measurement of one of the qubits, causes the state of the other qubit to collapse.

[0028] In order to realize a quantum computer, a physical system that can act as a qubit is needed. Such a system needs to have at least two states to act as 0 and 1 states. Note that it is not necessary to have a system with exactly only two states if the spacing between each energy level is different, such that each level can be addressed individually. As previously described herein, one type of physical system that could be used to implement qubits is based on use of superconducting materials (superconducting qubits).

[0029] In some implementations, namely when superconducting qubits are implemented as transmon qubits, two basic elements of superconducting quantum circuits are inductors and capacitors. However, circuits made using only these two elements cannot make a system with two energy levels because, due to the even spacing between the system's energy levels, such circuits will produce harmonic oscillators with a ladder of equivalent states. A nonlinear element is needed to have an effective two-level quantum state system, or qubit. Josephson Junction is an example of such non-linear, non-dissipative circuit element.

[0030] Josephson Junctions may form the central circuit elements of a superconducting quantum computer. A Josephson Junction may include a thin layer of insulator, typically referred to as a barrier or a tunnel barrier, sandwiched between two layers of

superconductor. The Josephson Junction acts as a superconducting tunnel junction. Cooper pairs tunnel across the barrier from one superconducting layer to the other. The electrical characteristics of this tunneling are governed by so-called Josephson relations which provide the basic equations governing the dynamics of the Josephson effect:

/ = l_c sin φ (1)

V =—tf φ .

2e ^Ύ (2)

[0031] In these equations, φ is the phase difference in the superconducting wave function across the junction, l_c (the critical current) is the maximum current that can tunnel through the junction, which depends on the barrier thickness and the area of the junction, V is the voltage across the Josephson Junction, I is the current flowing through the Josephson Junction, h is the reduced Planck's constant, and e is electron's charge. Equations (1) and (2) can be combined to give an equation (3): ft

V = I

2el_ccos(p (3)

[0032] Equation (3) looks like the equation for an inductor with inductance L:

2eI_ccos(p

[0033] Since inductance is a function of φ, which itself is a function of I, the inductance of a Josephson Junction is non-linear, which makes an LC circuit formed using a Josephson Junction as the inductor have uneven spacing between its energy states.

[0034] The foregoing provides an illustration of using a Josephson Junction in a transmon, which is one type of superconducting qubit. In other classes of superconducting qubits, Josephson Junctions combined with other circuit elements have similar functionality of providing the non-linearity necessary for forming an effective two-level quantum state, or qubit. In other words, when implemented in combination with other circuit elements (e.g. capacitors in transmons or superconducting loops in flux qubits), one or more Josephson Junctions allow realizing a quantum circuit element which has uneven spacing between its energy levels resulting in a unique ground and excited state system for the qubit. This is illustrated in FIG. 1A, providing a schematic illustration of a superconducting quantum circuit 100, according to some embodiments of the present disclosure. As shown in FIG. 1A, an exemplary superconducting quantum circuit 100 includes two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element). Each of the superconducting qubits 102 may include one or more Josephson Junctions 104 connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a nonlinear circuit providing a unique two-level quantum state for the qubit. The circuit elements 106 could be e.g. capacitors in transmons or superconducting loops in flux qubits.

[0035] As also shown in FIG. 1A, an exemplary superconducting quantum circuit 100 typically includes means 108 for providing external control of qubits 102 and means 110 for providing internal control of qubits 102. In this context, "external control" refers to controlling the qubits 102 from outside of, e.g, an integrated circuit (IC) chip comprising the qubits, including control by a user of a quantum computer, while "internal control" refers to controlling the qubits 102 within the IC chip. For example, if qubits 102 are transmon qubits, external control may be implemented by means of flux bias lines (also known as "flux lines" and "flux coil lines") and by means of readout and drive lines (also known as

"microwave lines" since qubits are typically designed to operate with microwave signals), described in greater detail below. On the other hand, internal control lines for such qubits may be implemented by means of resonators, e.g., coupling and readout resonators, also described in greater detail below.

[0036] Any one of the qubits 102, the external control means 108, and the external control means 110 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1A). A substrate may include any substrate suitable for realizing quantum circuit components, as described above. In one

implementation, the substrate may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure. Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.

[0037] As previously described herein, within superconducting qubit implementations, three classes are typically distinguished: charge qubits, flux qubits, and phase qubits.

Transmons, a type of charge qubits with the name being an abbreviation of "transmission line shunted plasma oscillation qubits", are particularly encouraging because they exhibit reduced sensitivity to charge noise. FIG. IB provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit 100B where qubits are implemented as transmons, according to some embodiments of the present disclosure.

[0038] Similar to FIG. 1A, FIG. IB illustrates two qubits 102. In addition, FIG. IB illustrates flux bias lines 112, microwave lines 114, a coupling resonator 116, a readout resonator 118, and wirebonding pads 120 and 122. The flux bias lines 112 and the microwave lines may be viewed as examples of the external control means 108 shown in FIG. 1A. The coupling resonator 116 and the readout resonator 118 may be viewed as examples of the internal control means 110 shown in FIG. 1A.

[0039] Running a current through the flux bias lines 112, provided from the wirebonding pads 120, allows tuning (i.e. changing) the frequency of the corresponding qubits 102 to which each line 112 is connected. In general, it operates in the following manner. As a result of running the current in a particular flux bias line 112, magnetic field is created around the line. If such a magnetic field is in sufficient proximity to the qubit 102, e.g. by a portion of the flux bias line 112 being provided next to the qubit 102, the magnetic field couples to the qubit, thereby changing the spacing between the energy levels of the qubit. This, in turn, changes the frequency of the qubit since the frequency is directly related to the spacing between the energy levels via Planck's equation. The Planck's equation is E=hv, where E is the energy (in this case the energy difference between energy levels of a qubit), h is the Planck's constant and v is the frequency (in this case the frequency of the qubit). As this equation illustrates, if E changes, then v changes. Provided there is sufficient multiplexing, different currents can be sent down each of the flux lines allowing for independent tuning of the various qubits. [0040] The state(s) of each qubit 102 may be read by way of its corresponding readout resonator 118. As explained below, the qubit 102 induces a resonant frequency in the readout resonator 118. This resonant frequency is then passed to the microwave lines 114 and communicated to the pads 122.

[0041] To that end, a readout resonator 118 may be provided for each qubit. The readout resonator 118 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance), with the resonant frequency of the oscillations being close to the frequency of the qubit. The readout resonator 118 is coupled to the qubit by being in sufficient proximity to the qubit 102, more specifically in sufficient proximity to the capacitor of the qubit 102, when the qubit is implemented as a transmon, either through capacitive or inductive coupling. Due to a coupling between the readout resonator 118 and the qubit 102, changes in the state of the qubit 102 result in changes of the resonant frequency of the readout resonator 118. In turn, because the readout resonator 118 is in sufficient proximity to the microwave line 114, changes in the resonant frequency of the readout resonator 118 induce changes in the current in the microwave line 114, and that current can be read externally via the wirebonding pads 122.

[0042] The coupling resonator 116 allows coupling different qubits together in order to realize quantum logic gates. The coupling resonator 116 is similar to the readout resonator 118 in that it is a transmission line that includes capacitive connections to ground on both sides (i.e. a half wavelength resonator), which also results in oscillations within the coupling resonator 116. Each side of the coupling resonator 116 is coupled (again, either capacitively or inductively) to a respective qubit by being in sufficient proximity to the qubit, namely in sufficient proximity to the capacitor of the qubit, when the qubit is implemented as a transmon. Because each side of the coupling resonator 116 has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator 116. In this manner, state of one qubit depends on the state of the other qubit, and the other way around. Thus, coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit. [0043] In some implementations, the microwave line 114 may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits. When a single microwave line is used for this purpose, the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits. In other implementations, microwave lines such as the line 114 shown in FIG. IB may be used to only readout the state of the qubits as described above, while separate drive lines such as e.g. drive lines 124 shown in FIG. IB, may be used to control the state of the qubits. In such implementations, the microwave lines used for readout may be referred to as readout lines (e.g. readout line 114), while microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g. drive lines 124). The drive lines 124 may control the state of their respective qubits 102 by providing, using e.g. wirebonding pads 126 as shown in FIG. IB, a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the 0 and 1 state of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the 0 and 1 states of the qubit.

[0044] Flux bias lines, microwave lines, coupling resonators, drive lines, and readout resonators, such as e.g. those described above, together form interconnects for supporting propagation of microwave signals. Further, any other connections for providing direct electrical interconnection between different quantum circuit elements and components, such as e.g. connections from electrodes of Josephson Junctions to plates of the capacitors or to superconducting loops of superconducting quantum interference devices (SQUIDS) or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects. Still further, the term "interconnect" may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non- quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit. Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc. [0045] In various embodiments, the interconnects as shown in FIG. IB could have different shapes and layouts. For example, some interconnects may comprise more curves and turns while other interconnects may comprise less curves and turns, and some interconnects may comprise substantially straight lines. In some embodiments, various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other. As long as these interconnects operate in accordance with use of these interconnects as known in the art for which some exemplary principles were described above, quantum circuits with different shapes and layouts of the interconnects than those illustrated in FIG. IB are all within the scope of the present disclosure.

[0046] Coupling resonators and readout resonators may be configured for capacitive coupling to other circuit elements at one or both ends in order to have resonant oscillations, whereas flux bias lines and microwave lines may be similar to conventional microwave transmission lines because there is no resonance in these lines. Each one of these interconnects may be implemented as a coplanar waveguide, which is one type of transmission line. A stripline is another type of transmission line. Typical materials to make the interconnects include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and niobium titanium nitride (NbTiN), all of which are particular types of superconductors. However, in various embodiments, other suitable superconductors may be used as well.

[0047] As previously described herein, FIG. IB illustrates an embodiment specific to transmons. Subject matter is not limited in this regard and may include other embodiments of quantum circuits implementing other types of superconducting qubits that would also utilize Josephson Junctions as described herein, all of which are within the scope of the present disclosure.

[0048] FIG. 1C illustrates an exemplary transmon 128 which could be used as any one of the qubits 102, according to some embodiments of the present disclosure. Presence of a capacitor 130 of such a size that capacitive energy is significantly larger than the Josephson energy in a qubit of FIG. 1C indicates that the qubit is a transmon. The capacitor 130 is configured to store energy in an electrical field as charges between the plates of the capacitor. [0049] The capacitor 130 is depicted as an interdigitated capacitor, a particular shape of capacitor that provides a large capacitance with a small area, however, in various embodiments, other shapes and types of capacitors may be used as well. For example, such a capacitor could be implemented simply as two parallel plates with vacuum in between. Furthermore, in various embodiments, the capacitor 130 may be arranged in any direction with respect to the SQUID or a single Josephson Junction, not necessarily as shown in FIG. IC.

[0050] In addition, the transmon illustrated in FIG. IC includes two Josephson Junctions 132 incorporated into a superconducting loop 134. The two Josephson Junctions 132 and the superconducting loop 134 together form a superconducting quantum interference device (SQUID). Magnetic fields generated by the flux bias line 112 connected to the qubit extend to the SQUID (i.e. current in the flux bias line 112 create magnetic fields around the SQUID), which in turn tunes the frequency of the qubit.

[0051] In other embodiments, a SQUID could include only one Josephson Junction, or a transmon could be implemented with a single Josephson Junction without the

superconducting loop. A single Josephson Junction without the SQUID is insensitive to magnetic fields, and thus, in such an implementation, flux bias lines 112 may not be used to control the frequency of the transmon.

[0052] While FIGs. 1A and IB illustrate examples of quantum circuits comprising only two qubits 102, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure. At least some of the one or more qubits 102 shown in FIGs. 1A-1C may comprise Josephson Junction structures fabricated using the Damascene fabrication approach as described herein.

[0053] Furthermore, while the present disclosure includes references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of superconducting qubits are in 5-10 gigahertz (GHz) range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. However, advantageously, because excitation energy of superconducting qubits is controlled by the circuit elements, these qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.

[0054] In various embodiments, quantum circuits such as the one shown in FIGs. 1A-1B may be used to implement components associated with a quantum integrated circuit (IC). Such components may include those that are mounted on or embedded in a quantum IC, or those connected to a quantum IC. The quantum IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the integrated circuit. The integrated circuit may be employed as part of a chipset for executing one or more related functions in a quantum system.

[0055] FIG. 2 provides an illustration of quantum computing device, e.g. a quantum computer, 200, according to some embodiments of the present disclosure. The computing device 200 may be any electronic device that processes quantum information. In some embodiments, the computing device 200 may include a number of components, including, but not limited to, a quantum processor 202, a memory 204, and a cryogenic apparatus 206, as shown in FIG. 2. Each of the quantum processor 202 and the memory 204 may include one or more quantum circuits comprising suspended Josephson Junction structures as described herein, e.g. quantum circuits and Josephson Junctions as illustrated in FIGs. 1A- 1C.

[0056] The processor 202 may be a universal quantum processor or a specialized quantum processor configured to run quantum simulations, or one or more of particular quantum algorithms. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. In some embodiments, the processor 202 may be configured to execute algorithms that may be particularly suitable for quantum computers, such as e.g. cryptographic algorithms that utilize prime factorization, algorithms to optimize chemical reactions, or protein folding Igorithms. The term "processor" may refer to any device or portion of a device that rocesses quantum information.

[0057] In various embodiments, the computing device 200 may include other components not shown in FIG. 2, such as e.g. one or more of a controller, I/O channels/devices, supplementary microwave control electronics, multiplexer, signal mixers, a user interface, as well as other quantum devices such as e.g. quantum amplifiers, quantum sensors, which quantum devices may also implement certain embodiments of the present dislcosure.

[0058] In various embodiments, the computing device 200 may be included within a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an

entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 200 may be any other quantum electronic device that processes data by utilizing quantum mechanical phenomena.

[0059] In order to highlight the advantages offered by the structures proposed herein, it would be helpful to first explain how superconductors are treated in conventional approaches. FIG. 3 provides a schematic illustration of a structure 300 that includes a substrate 302 over which a superconductor 304 is disposed. The superconductor 304 could be any element of a superconducting quantum circuit that needs to be superconducting at typical qubit operating temperatures, such as e.g. a top electrode of a Josephson Junction, a resonator, a drive line, etc. In case the superconductor 304 is an interconnect of a superconducting quantum circuit, once an interconnect is provided, formed of a

superconducting material such as e.g. niobium titanium nitride (NbTiN), the superconductor is then exposed to air where the surface will oxidize and oxygen may diffuse into the superconductor 304 and cause losses. This is illustrated in FIG. 3 with a layer of oxide 306 shown over the superconductor 304, where portions 308 of the oxide 306 are diffused into the superconductor 304. Losses due to the presence of oxide portions 308 within the superconductor 304 may lead to decoherence of already very fragile qubits. In general, any losses are especially significant in context of quantum circuits where, sometimes, energy as small as that of a single photon is to be transmitted, making loss tolerance very low. [0060] Embodiments of the present disclosure are based on an insight that protecting superconductors used in superconducting quantum circuits from oxidation using a protective cap disposed over the superconductors could improve on the decoherence problem of superconducting qubits. However, directly applying conventional integrated circuit techniques for protecting materials from oxidation to superconducting quantum circuit components is not appropriate because, as previously described herein, building quantum circuits presents unique challenges not encountered in classical computing. Thus, embodiments of the present disclosure are further based on recognition that issues unique to quantum circuits have to be taken in consideration when evaluating applicability of conventional integrated circuit techniques to building superconducting quantum circuits, and, in particular, to selecting materials used for protecting superconducting materials of such circuits from oxidation.

[0061] One such issue is e.g. presence of spurious TLS's. As described above, one major source of loss, and thus decoherence in superconducting qubits are spurious TLS's caused by defects in the areas surrounding interconnects, Josephson Junctions and other quantum circuit elements such as e.g. capacitors of transmon qubits. Such defects could include e.g. defects in the crystal structure of a material or defects in a form of polar impurities such as hydroxyl (OH- ) groups.

[0062] FIG. 4 provides a schematic illustration of a structure 400 comprising a

superconductor 404, disposed over a substrate 402 and covered with a protective cap 410, according to some embodiments of the present disclosure. The protective cap 410 encloses the superconductor 404 at least partially, but preferably as little of the superconductor 404 is exposed to air as possible, thus preventing or at least reducing oxidation of the superconductor 404. Preferably, material used for the protective cap 410 is such that it has a limited amount of spurious TLS's, at least less than the native oxide 306 shown in FIG. 3.

[0063] One class of materials which could be used as protective caps 410 include non-oxide dielectrics, such as e.g. e.g. Silicon Nitride (SiN), Silicon Carbide (SiC), etc. thought to have fewer spurious TLS's than a native oxide of typical superconductors employed in

superconducting quantum circuits. Thickness and density of such materials would be selected to prevent oxygen diffusion through the protective cap. For example, a density equal to or greater than 2.2 gram (g) per cubic centimeter (cm³) and/or a thickness of 5 nanometers (nm) or greater could be appropriate.

[0064] Another class of materials to be used for forming the protective caps 410 include metals which are relatively noble against oxidation, i.e. metals that do not easily oxidize or corrode, such as e.g. tungsten (W), ruthenium (Ru), gold (Au), platinum (Pt), etc, possibly in combination with other elements that do not easily oxidize (e.g. some nitrides or carbides of such metals).

[0065] In various embodiments, such metals may but do not have to be superconducting (e.g. copper may be used, which not a superconductor).

[0066] In some embodiments, such materials could include metals with a lower melting point, such as e.g. copper (Cu), that could flow into possible crevices around the

superconductor, thus following the topology of the superconductor and ensuring sufficient coverage against oxidation.

[0067] In some embodiments, such materials could include refractory metals, i.e. metals that exhibit resistance to changing under high temperatures, such as e.g. Ru or W. In general, the term "refractory metal" refers to metals that exhibit resistance to changing under high temperatures, while the term "noble metal" refers to metals that do not easily oxidize or corrode. There is a large overlap between refractory and noble metals in the periodic table of elements, i.e. some metals are both noble and refractory. Using refractory metals as the protective caps 410 may be advantageous because such materials may later undergo further fabrication processes that require higher temperatures without

compromising their functionality.

[0068] Yet another class of materials which could be used for forming the protective caps 410 include hermetic self-terminating oxide layers, such as e.g. aluminum (Al), amorphous Silicon (a-Si), etc. When such materials are used, the top of the protective cap 410 may oxidize without affecting the superconductor 404 underneath because the material of the protective cap 410 is self-limiting in terms of its oxidation in that it will only form an oxide of a certain thickness before the oxidation process stops. [0069] Capping a superconductor with a layer, e.g. a film, of a protective material allows eliminating or at least substantially reducing oxidation of the superconductor, so that the superconductor does not have any substantial oxidation within the bulk, leading to an improved performance of a quantum circuit. Providing a protective cap layer that conforms to a topography of the superconducting material being protected from oxidation may ensure optimal protection.

[0070] Examples of superconducting materials that may benefit from being protected from oxidation using a protective cap as described herein include, but are not limited to aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), molybdenum rhenium (MoRe), etc., or any alloy of two or more superconducting materials.

[0071] FIG. 5 provides a flow chart of an oxidation protection method 500, according to some embodiments of the present disclosure.

[0072] The method may begin with a quantum circuit element comprising a

superconductor, e.g. the superconductor 404, being provided over a substrate, e.g. the substrate 402 (box 502). The superconductor may be provided e.g. on the substrate or on an interconnect support layer that may be provided on top of a substrate. Such a substrate or the interconnect support layer may include any material suitable for realizing quantum circuit components as those described herein, e.g. components as described with reference to FIGs. 1A-1C and FIG. 2. In some implementations, the interconnect support layer may comprise a crystalline material such as, but not limited to silicon or sapphire. In other implementations, the interconnect support layer may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure for use as the interconnect support layer/substrate.

[0073] Once the superconductor is provided, a protective cap at least partially

encapsulating the superconductor is disposed (box 504). One approach could be to cap the superconductor in-situ to the processing tool used to form the quantum circuit. In such an approach, once the superconductor is disposed over a wafer in one chamber of a processing tool, typically under vacuum, the wafer is moved, without breaking the vacuum, to another chamber of this tool. In the second chamber, the protective cap is provided over the superconductor. Another approach could be to allow an air break between deposition of the superconductor and deposition of the protective cap, but sputter off the oxide or damage layer of the superconductor with a plasma before depositing the protective cap, also in-situ.

[0074] FIG. 6 provides a schematic illustration of a real-life structure comprising a superconductor covered with a protective cap described herein, according to some embodiments of the present disclosure. As can be seen, FIG. 6 is drawn to reflect example real world process limitations, in that the features are not drawn with precise right angles and straight lines. As shown, FIG. 6 represents a cross-section view similar to that shown in FIG. 4. FIG. 6 illustrates a structure comprising a superconductor 604 provided over a substrate 602 and capped with a protective cap 610, as could be visible in e.g. a scanning electron microscopy (SEM) image or a transmission electron miscroscope (TEM) image. In such an image of a real structure, possible processing defects could also be visible, such as e.g. particles in the film, discontinuities in the cap layer, egregious surface roughness that would degrade superconductivity, voids, and intermixing between layers (i.e. non-discrete interfaces).

[0075] A legend provided within a dashed box at the bottom of FIG. 4, as well as a legend provided at the bottom of FIG. 3, is used to indicate different elements shown in FIGs. 3 and 4, so that these figures are not cluttered by many reference numerals. Moreover, similar reference numerals in FIGs. 4 and 6 are used to illustrate analogous elements in the figures. When provided with reference to one of the figures, discussions of these elements are applicable to other figures, unless stated otherwise. Thus, in the interests of brevity, discussions of similar elements are not repeated for each of the figures.

[0076] Some Examples in accordance with various embodiments of the present disclosure are now described.

[0077] Example 1 provides a superconducting quantum circuit provided over a substrate, the superconducting quantum circuit including: at least one quantum circuit element including a superconducting material; and a cap layer at least partially enclosing the superconducting material, the cap layer configured to minimize oxidation of at least a portion of the superconducting material being enclosed by the cap layer.

[0078] Example 2 provides the superconducting quantum circuit according to Example 1, where the cap layer includes a layer of a non-oxide dielectric material.

[0079] Example 3 provides the superconducting quantum circuit according to Examples 1 or

2, where the cap layer includes a layer of a dielectric material having fewer spurious two- level systems than a native oxide of the superconducting material.

[0080] Example 4 provides the superconducting quantum circuit according to Examples 2 or

3, where a density of a material of the cap layer is greater than 2.2 gram (g) per cubic centimeter (cm³).

[0081] Example 5 provides the superconducting quantum circuit according to any one of Examples 1-4, where a thickness of the cap layer is greater than 5 nanometers (nm).

[0082] Example 6 provides the superconducting quantum circuit according to Example 1, where the cap layer includes a layer of noble metal.

[0083] Example 7 provides the superconducting quantum circuit according to Example 1, where the cap layer includes a layer of material including one or more hermetic self- terminating oxide layers.

[0084] Example 8 provides the superconducting quantum circuit according to any one of the preceding Examples, where the cap layer conforms to a topography of the superconducting material of the at least one quantum circuit element.

[0085] Example 9 provides the superconducting quantum circuit according to any one of Examples 1-8, where the at least one quantum circuit element includes a Josephson Junction provided over the substrate, the Josephson Junction including a base electrode layer, a top electrode layer, and a tunnel barrier layer provided between the base electrode layer and the top electrode layer, and where the superconducting material of the at least one quantum circuit element is the top electrode layer of the Josephson Junction. [0086] Example 10 provides the superconducting quantum circuit according to any one of Examples 1-8, where the at least one quantum circuit element is a flux bias line, a microwave line, a drive line, or a resonator.

[0087] Example 11 provides the superconducting quantum circuit according to any one of Examples 1-8, where the superconducting material of the at least one quantum circuit element is at least a portion of a SQUID loop of the superconducting quantum circuit.

[0088] Example 12 provides the superconducting quantum circuit according to any one of the preceding Examples, where the superconducting material of the at least one quantum circuit element is included in at least one charge qubit of the superconducting quantum circuit.

[0089] Example 13 provides the superconducting quantum circuit according to any one of the preceding Examples, where the superconducting material of the at least one quantum circuit element is included in at least one transmon qubit of the superconducting quantum circuit.

[0090] Example 14 provides the superconducting quantum circuit according to any one of Examples 1-11, where the superconducting material of the at least one quantum circuit element is included in at least one flux qubit of the superconducting quantum circuit.

[0091] Example 15 provides a quantum integrated circuit package, including a substrate; a first superconducting qubit provided over the substrate; a second superconducting qubit provided over the substrate; and a superconducting material either included within the first or/and the second superconducting qubits or providing electrical connectivity to or/and between the first or/and the second superconducting qubits, where at least a part of the superconducting material is enclosed with a cap layer, the cap layer configured to minimize oxidation of at least a portion of the superconducting material being enclosed by the cap layer.

[0092] Example 16 provides the quantum integrated circuit package according to Example 15, where the cap layer includes a layer of a non-oxide dielectric material. [0093] Example 17 provides the quantum integrated circuit package according to Examples

15 or 16, where the cap layer includes a layer of a dielectric material having fewer spurious two-level systems than a native oxide of the superconducting material.

[0094] Example 18 provides the quantum integrated circuit package according to Examples

16 or 17, where a density of a material of the cap layer is greater than 2.2 gram (g) per cubic centimeter (cm³).

[0095] Example 19 provides the quantum integrated circuit package according to any one of Examples 15-18, where a thickness of the cap layer is greater than 5 nanometers (nm).

[0096] Example 20 provides the quantum integrated circuit package according to Example 15, where the cap layer includes a layer of noble metal.

[0097] Example 21 provides a quantum computing device, including one or more integrated circuit packages according to any one of Examples 15-20.

[0098] Example 22 provides the quantum computing device according to Example 21, further including a cryogenic apparatus configured to maintain the first superconducting qubit and the second superconducting qubit at a cryogenic temperature during operation of the first superconducting qubit and the second superconducting qubit.

[0099] Example 23 provides a method for fabricating a superconducting quantum circuit, the method including: providing, over a substrate, at least one quantum circuit element including a superconducting material; providing a cap layer at least partially enclosing the superconducting material, the cap layer configured to minimize oxidation of at least a portion of the superconducting material being enclosed by the cap layer.

[00100] Example 24 provides the method according to Example 23, where the superconducting material is provided by being deposited under vacuum and where the cap layer is provided without exposing the superconducting material to air.

[00101] Example 25 provides the method according to Example 23, further including exposing the superconducting material to air after providing the superconducting material over the substrate and before providing the cap layer; and removing a top layer of the superconducting material exposed to air prior to depositing the cap layer. [00102] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[00103] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A superconducting quantum circuit provided over a substrate, the superconducting quantum circuit comprising: at least one quantum circuit element comprising a superconducting material; and a cap layer at least partially enclosing the superconducting material, the cap layer configured to minimize oxidation of at least a portion of the superconducting material being enclosed by the cap layer.

2. The superconducting quantum circuit according to claim 1, wherein the cap layer comprises a layer of a non-oxide dielectric material.

3. The superconducting quantum circuit according to claim 1, wherein the cap layer comprises a layer of a dielectric material having fewer spurious two-level systems than a native oxide of the superconducting material.

4. The superconducting quantum circuit according to claim 2, wherein a density of a material of the cap layer is greater than 2.2 gram (g) per cubic centimeter (cm³).

5. The superconducting quantum circuit according to claim 1, wherein a thickness of the cap layer is greater than 5 nanometers (nm).

6. The superconducting quantum circuit according to claim 1, wherein the cap layer comprises a layer of noble metal.

7. The superconducting quantum circuit according to claim 1, wherein the cap layer comprises a layer of material comprising one or more hermetic self-terminating oxide layers.

8. The superconducting quantum circuit according to any one of the preceding claims, wherein the cap layer conforms to a topography of the superconducting material of the at least one quantum circuit element.

9. The superconducting quantum circuit according to any one of claims 1-7, wherein the at least one quantum circuit element comprises a Josephson Junction provided over the substrate, the Josephson Junction comprising a base electrode layer, a top electrode layer, and a tunnel barrier layer provided between the base electrode layer and the top electrode layer, and wherein the superconducting material of the at least one quantum circuit element is the top electrode layer of the Josephson Junction.

10. The superconducting quantum circuit according to any one of claims 1-7, wherein the at least one quantum circuit element is a flux bias line, a microwave line, a drive line, or a resonator.

11. The superconducting quantum circuit according to any one of claims 1-7, wherein the superconducting material of the at least one quantum circuit element is at least a portion of a SQUID loop of the superconducting quantum circuit.

12. The superconducting quantum circuit according to any one of claims 1-7, wherein the superconducting material of the at least one quantum circuit element is included in at least one charge qubit of the superconducting quantum circuit.

13. The superconducting quantum circuit according to any one of claims 1-7, wherein the superconducting material of the at least one quantum circuit element is included in at least one transmon qubit of the superconducting quantum circuit.

14. The superconducting quantum circuit according to any one of claims 1-7, wherein the superconducting material of the at least one quantum circuit element is included in at least one flux qubit of the superconducting quantum circuit.

15. A quantum integrated circuit package, comprising: a substrate; a first superconducting qubit provided over the substrate; a second superconducting qubit provided over the substrate; and a superconducting material either included within the first or/and the second superconducting qubits or providing electrical connectivity to or/and between the first or/and the second superconducting qubits, wherein at least a part of the superconducting material is enclosed with a cap layer, the cap layer configured to minimize oxidation of at least a portion of the superconducting material being enclosed by the cap layer.

16. The quantum integrated circuit package according to claim 15, wherein the cap layer comprises a layer of a non-oxide dielectric material.

17. The quantum integrated circuit package according to claim 15, wherein the cap layer comprises a layer of a dielectric material having fewer spurious two-level systems than a native oxide of the superconducting material.

18. The quantum integrated circuit package according to claim 17, wherein a density of a material of the cap layer is greater than 2.2 gram (g) per cubic centimeter (cm³).

19. The quantum integrated circuit package according to claim 15, wherein a thickness of the cap layer is greater than 5 nanometers (nm).

20. The quantum integrated circuit package according to claim 15, wherein the cap layer comprises a layer of noble metal.

21. A quantum computing device, comprising one or more integrated circuit packages according to any one of claims 15-20.

22. The quantum computing device according to claim 21, further comprising a cryogenic apparatus configured to maintain the first superconducting qubit and the second superconducting qubit at a cryogenic temperature during operation of the first

superconducting qubit and the second superconducting qubit.

23. A method for fabricating a superconducting quantum circuit, the method comprising: providing, over a substrate, at least one quantum circuit element comprising a superconducting material; providing a cap layer at least partially enclosing the superconducting material, the cap layer configured to minimize oxidation of at least a portion of the superconducting material being enclosed by the cap layer.

24. The method according to claim 23, wherein the superconducting material is provided by being deposited under vacuum and wherein the cap layer is provided without exposing the superconducting material to air.

25. The method according to claim 23, further comprising: exposing the superconducting material to air after providing the superconducting material over the substrate and before providing the cap layer; and removing a top layer of the superconducting material exposed to air prior to depositing the cap layer.