WO2018103556A1

WO2018103556A1 - Quasi-cyclic ldpc code data processing apparatus and processing method

Info

Publication number: WO2018103556A1
Application number: PCT/CN2017/113414
Authority: WO
Inventors: 李立广; 徐俊; 许进
Original assignee: 中兴通讯股份有限公司
Priority date: 2016-12-09
Filing date: 2017-11-28
Publication date: 2018-06-14
Also published as: CN108234064B; CN108234064A

Abstract

Disclosed in the present application are a quasi-cyclic LDPC code data processing apparatus and processing method, the apparatus comprising a storage module, configured to store a fundamental matrix and a set of boost values used for quasi-cyclic LDPC coding; a coding module, configured to acquire the fundamental matrix and a boost value from the storage module and, on the basis of the acquired fundamental matrix and boost value, implement quasi-cyclic LDPC coding of an information sequence to be encoded to obtain an LDPC coding output sequence; and a rate matching module, configured to select a rate matching output sequence from the LDPC coding output sequence.

Description

Quasi-cyclic LDPC code data processing device and processing method

Technical field

The present application relates to the field of communications, such as a quasi-cyclic LDPC code data processing apparatus and processing method.

Background technique

Currently, a common Forward Error Correction (FEC) code includes a convolutional code, a Turbo code, and a Low Density Parity Check (LDPC) code.

In the FEC encoding process, the information sequence of the bit number k is FEC-encoded to obtain an n-bit FEC encoded codeword (redundant bits are n-k), and the FEC encoding rate (abbreviated as code rate) is k/n. LDPC code is a linear block code that can be defined by a very sparse parity check matrix or bipartite graph. It is the sparseness of its check matrix that can realize low complexity codec, which makes LDPC practical. . After various practices and theoretical proofs, the LDPC code is the most excellent channel coding under the Additive White Gaussian Noise (AWGN) channel, and the performance is very close to the Shannon limit.

Quasi-cyclic LDPC codes have been widely used in many standards, although the coding factor can be shortened by changing the spreading factor to obtain flexible code rate and code length design, and the flexibility of LDPC codes is improved, but performance is abnormal, that is, in some Performance deteriorates at code length and bit rate, and it appears as a glitch on the performance curve.

Summary of the invention

The following is an overview of the topics detailed in this document. This Summary is not intended to limit the scope of the claims.

In order to overcome the deficiencies of the related art, the present disclosure provides a quasi-cyclic LDPC code data processing apparatus and processing method for solving at least the problem of lack of flexibility in the LDPC encoding and decoding process in the related art.

The present disclosure provides a quasi-cyclic LDPC code data processing apparatus, including: a storage module, an encoding module, and a rate matching module.

The storage module is configurable to store a base matrix and a set of boost values used by the quasi-cyclic LDPC encoding; the base matrix is a matrix of mb rows and nb columns, the base matrix containing elements for indicating the all-zero square matrix and An element indicating a shift size of the cyclic shift of the unit array, each of the set of boost values being used to indicate the number of rows of the all-zero square matrix or the unit matrix, each of the boost values Is an integer greater than 0, the mb is an integer greater than 0, and the nb is an integer greater than mb.

The encoding module is configured to acquire the basic matrix and a lifting value from the storage module, perform quasi-cyclic LDPC encoding on the sequence of information to be encoded based on the obtained basic matrix and the lifting value, to obtain an LDPC encoded output sequence.

The rate matching module is configured to select a rate matching output sequence from the LDPC coded output sequence.

Embodiments of the present disclosure provide a quasi-cyclic LDPC code data processing apparatus, including a processor and a storage device, wherein the storage device stores a base matrix and a set of boost values used for quasi-cyclic LDPC encoding, and stores multiple The instructions are to implement an LDPC code data processing method, the processor being configured to execute the plurality of instructions to:

Acquiring the basic matrix and a lifting value from the storage device, performing quasi-cyclic LDPC encoding on the sequence of the information to be encoded based on the obtained basic matrix and the lifting value, to obtain an LDPC encoding output sequence; the basic matrix is an mb a matrix of rows nb columns, the base matrix including elements for indicating an all-zero square matrix and elements for indicating a shift size of the unit array cyclic shift, the boost value being used to indicate the all-zero square matrix Or the number of rows of the unit array, the boost value is an integer greater than 0, the mb is an integer greater than 0, and the nb is an integer greater than mb;

From the LDPC coded output sequence, a rate matching output sequence is selected.

An embodiment of the present disclosure provides a quasi-cyclic LDPC code data processing method, including:

Acquiring the basic matrix and a lifting value from a base matrix and a set of lifting values used in pre-stored quasi-cyclic LDPC encoding; the basic matrix is a matrix of mb rows and nb columns, and the basic matrix includes And an element for indicating an all-zero square matrix and an element for indicating a shift size of the unit array cyclic shift, wherein the boost value is used to indicate the number of rows of the all-zero square matrix or the unit matrix, the boost value Is an integer greater than 0, the mb is an integer greater than 0, and the nb is an integer greater than mb;

Performing a quasi-cyclic LDPC encoding on the encoded information sequence based on the obtained basic matrix parameter and the lifting value, to obtain an LDPC mother codeword sequence;

From the LDPC mother codeword sequence, a rate matching output sequence is selected.

Embodiments of the present disclosure provide a computer readable storage medium storing computer executable instructions configured to perform the above methods.

The beneficial effects of the present disclosure are as follows: The apparatus and method in the present disclosure effectively solve the problem of lack of flexibility in the LDPC encoding and decoding process in the related art, support flexible code length and code rate, and maintain good performance.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF abstract

FIG. 1 is a schematic structural diagram of a quasi-cyclic LDPC code data processing apparatus according to an embodiment of the present disclosure.

2 is a schematic structural diagram of a related digital communication system in an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of a girth of 4 in a parity check matrix corresponding to a basic matrix in an embodiment of the present disclosure.

4 is a schematic diagram of a basic matrix in an embodiment of the present disclosure.

FIG. 5 is a flowchart of a method for processing LDPC code data in an embodiment of the present disclosure.

FIG. 6 is a performance comparison diagram of an LDPC code data processing method in an embodiment of the present disclosure.

detailed description

The embodiments of the present disclosure provide a quasi-cyclic LDPC code data processing apparatus and a processing method thereof. The present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the disclosure, The embodiments of the present disclosure and the features of the embodiments may be combined with one another in a suitable manner; the terms "first", "second", etc. in the specification and claims and the above figures are used to distinguish similar objects without Used to describe a specific order or order.

The quasi-cyclic LDPC code data processing apparatus and processing method in the embodiments of the present disclosure may be used in an LTE mobile communication system or a future fifth-generation mobile communication system or other wireless wired communication system, and the data transmission direction is that the base station sends data to the mobile user (downstream) Transmitting service data), or data transmission direction for mobile users to send data to the base station (uplink transmission service data). Mobile users include: mobile devices, as access terminals, user terminals, subscriber stations, subscriber units, mobile stations, remote stations, remote terminals, user agents, user devices, user equipment, or some other terminology. The base station includes an access point (AP), or may be called a node B, a radio network controller (RNC), an evolved Node B (eNB), and a base station controller. (Base Station Controller, BSC), Base Transceiver Station (BTS), Base Station (BS), Transceiver Function (TF), Radio Router, Radio Transceiver, Basic Service Set (Basic Service Set, BSS), extended service set (ESS), radio base station (RBS), or some other terminology.

The data processing apparatus and processing method of the quasi-cyclic LDPC code in the embodiment of the present disclosure can also be applied to the enhanced mobile broadband (eMBB) in the new radio access technology (New Radio Access Technology, referred to as new RAT). Scenario, Ultra-Reliable and Low Latency Communications (URLLC) scenario or Massive Machine Type Communications (MMTC) scenario. The maximum downlink throughput in the eMBB scenario can reach 20 Gbps, and the maximum throughput of the uplink data can reach 10 Gbps. In the URLLC, the BLER (Block Error Rate) with a minimum reliability of 10e-5 and the shortest delay of the uplink and downlink can reach 0.5. Milliseconds; and mMTC enables the device battery to be used for years without power.

As shown in FIG. 1 , an embodiment of the present disclosure provides a quasi-cyclic LDPC code data processing apparatus, including: a storage module 110, an encoding module 120, and a rate matching module 130.

The storage module 110 is configured to store a base matrix and a set of spreading factor values used for quasi-cyclic LDPC encoding; the basic matrix is a matrix of mb rows and nb columns, and the basic matrix includes elements for indicating an all-zero square matrix And an element for indicating a shift size of the unit array cyclic shift, each of the set of spread factor values being used to indicate the number of rows of the all zero square matrix or the unit array, each of An expansion factor value is an integer greater than 0, the mb is an integer greater than 0, and the nb is an integer greater than mb.

The quasi-cyclic LDPC encoding module (abbreviated as encoding module) 120 is configured to acquire the basic matrix and an expansion factor value from the storage module, and perform quasi-cyclic LDPC on the sequence of the information to be encoded based on the obtained basic matrix and the spreading factor value. Encoding to obtain an LDPC coded output sequence.

The rate matching module 130 is configured to select a rate matching output sequence from the LDPC encoded output sequence.

For example, the spreading factor parameter is {4 6 8 10 12 14 16 20 24 28 32 40 48 56 64 80 96 112 128 160 192 224 256 320 384 448 512 640 768 896 1024}.

The apparatus in the embodiments of the present disclosure supports flexible code length and code rate and maintains good performance.

For a better understanding of embodiments of the present disclosure, a digital communication system is briefly described below.

As shown in FIG. 2, the digital communication system generally includes three parts: a transmitting end, a channel, and a receiving end. The transmitting end may perform channel coding on the information sequence to obtain an encoded codeword, interleave the encoded codeword, and map the interleaved bits into modulation symbols, and then process and transmit the modulation symbols according to the communication channel information. In the channel, due to factors such as multipath, motion, etc., the specific channel response will be distorted, and the data transmission will be further deteriorated due to noise and interference. The receiving end receives the modulation symbol data after passing through the channel, and the modulation symbol data at this time is already distorted, and specific processing is required to restore the original information sequence.

According to the encoding method of the information sequence by the transmitting end, the receiving end can perform corresponding processing on the received data to reliably restore the original information sequence. The encoding method must be visible at both ends of the transceiver. Generally, the encoding processing method is based on forward error correction (referred to as Forward Error Correction, referred to as FEC) coding in which forward error correction coding adds some redundant information to the information sequence. The receiving end can utilize this redundant information to reliably recover the original information sequence.

At the transmitting end, the transport block to be transmitted is subjected to code block partitioning to obtain a plurality of small transport blocks, and then FEC encoding is performed on the plurality of small transport blocks respectively, and the length of the transport block to be transmitted is a transport block size TBS (Transport Block) Size), the FEC code rate is generally defined as the ratio of the number of bits entering the encoder to the number of bits actually transmitted. In the LTE (Long Term Evolution) system, a very flexible transport block size can support various packet size requirements of the LTE system, and a Modulation and Coding Scheme (MCS) is adopted. Indexing to indicate different modulation orders and coding rate R and determining a TBS index, and determining a different transport block size according to a Resource Block number NRB and a Transport Block Size (TBS) index, the resource block size is The continuous size is 12 subcarriers in 1 time slot resource, wherein some control signals and resources remaining by the reference signal are removed. The channel type may include a data channel and a control channel. The data channel generally carries User Equipment data, control channel bearer control information, and control information such as MCS index number and channel information. The bandwidth size generally refers to the bandwidth allocated by the system to the data transmission. The LTE system is divided into 20M, 10M, 5M and other bandwidths. The data transmission direction includes uplink data and downlink data. The uplink data generally refers to a user transmitting data to a base station, and the downlink data refers to a base station transmitting data to a user.

In IEEE802.11ac, IEEE802.11ad, IEEE802.11aj, IEEE802.16e, IEEE802.11n, microwave communication, and optical fiber communication, etc., LDPC codes are widely used. In the parity check matrix of the LDPC code, each row is a parity code, and if the value of an element of an index position is equal to 1 in each row, the bit participates in the parity code, and if it is equal to 0, the The location bit does not participate in the parity code. The parity check matrix H of the quasi-cyclic LDPC code is a matrix of M×Z rows and N×Z columns, which is composed of M×N sub-matrices, each of which is a difference of a basic permutation matrix of size Z×Z. A power sub-matrix can also be considered as a sub-matrix obtained by a cyclic shift of a size of a Z×Z unit array. The quasi-cyclic LDPC code may also be referred to as a structured LDPC code. At this time, as long as the cyclic shift size and the sub-matrix size are known, a quasi-cyclic LDPC code can be determined, and all shift sizes constitute an M×N matrix, which can be called a basic check matrix or a base matrix or a prototype map (base protograph). The sub-matrix size may be referred to as an expansion factor or a lifting size, and is primarily described in the present disclosure as an expansion factor, which is consistent. The parity check matrix of the quasi-cyclic LDPC code has the following form:

If hb _ij = -1, then

Is an all-zero matrix of size Z×Z; in order to mathematically describe the cyclic shift of the unit array more easily, in the basic check matrix of the quasi-cyclic LDPC code described above, a basic size Z×Z is defined here. The permutation matrix P, for the cyclic shift of the unit array, that is, the power of the corresponding size of the basic permutation matrix P, the basic permutation matrix P is as follows:

By such a power hb _ij , each block matrix can be uniquely identified. If a block matrix is an all-zero matrix, hb _{ij is} generally represented by -1 or a null value; and if a block matrix is The cyclic shift s of the unit matrix is obtained, then hb _ij is equal to s, so all hb _ij can form a basic check matrix Hb, and then the basic matrix (or basic check matrix) Hb of the LDPC code can be expressed as follows:

Therefore, the quasi-cyclic LDPC code can be uniquely determined by the base matrix Hb and the spreading factor Z. The base matrix includes a plurality of parameters: MB, NB, and KB, where MB represents the number of base matrix rows (which can be said to be the number of check columns of the base matrix), NB represents the number of base matrix columns, and KB = NB-MB represents the base matrix. The number of system columns.

For example, the base check matrix Hb (2 rows and 4 columns) is as follows and the expansion factor Z is equal to 4:

Then the parity check matrix is:

The elements in the parity check matrix have only two element values of 0 and 1, so they can be described as a binary matrix; and the transformation from the base matrix to the parity check matrix (binary matrix) can be described as: the base matrix is expanded into The parity check matrix or the base matrix is promoted to a parity check matrix. From the above-mentioned LDPC code parity check matrix, it can be known that the element index of the first row of the parity check matrix equal to 1 is [1 6 9], indicating that in the quasi-cyclic LDPC code, the first bit, The 6th bit and the 9th bit constitute a parity code; similarly, the index equal to 1 in the 2nd line is [2 7 10], and the 2nd bit, the 7th bit, and the 10th bit constitute a parity code And so on, it can be known that the LDPC code is actually a codeword in which a large number of parity codes are stacked. The advantage of the quasi-cyclic LDPC code is that as long as the basic parity check matrix Hb and the spreading factor Z are stored, the storage is very simple, and the coding/decoding algorithm can utilize its blocking characteristics, which can simplify the algorithm, such as hierarchical decoding. However, the bit node positions in each row do not conflict, and pipeline operations can be used, which can reduce decoding delay and decoding complexity, and is very simple to implement.

There are various LDPC decoding methods, such as probability domain BP decoding algorithm, log domain BP decoding algorithm and hierarchical minimum and decoding algorithm. Probability domain BP decoding algorithm has the best performance, but the disadvantage is that because it involves a large number of multiplication operations, the computational complexity is very large, so the required hardware cost is very high, and the dynamic range of the numerical value is not stable, so it is generally in practice. Not used in the app. Compared to the probability domain BP decoding algorithm, the log-domain BP decoding algorithm reduces many computational units, but still requires a lot of multiplication operations, and the hardware costs required are also quite large. The layered minimum and decoding algorithm converts the key computation (log operation and multiplication) units of the log-domain BP decoding algorithm into minimum and minimum values, and the required hardware resources are greatly reduced, and the performance will have a small loss. But you can reduce a lot of hardware resources. Therefore, the more practical applications are the layered minimum and decoding algorithms. No matter which decoding method is used, iterative decoding is needed. The decoding module is mainly divided into two parts: check node update module and variable node update module.

In LDPC encoding and decoding, in order to ensure excellent performance, high throughput, high flexibility and low complexity, the designed LDPC code parity check matrix is closely related. Conversely, if the designed LDPC parity check matrix is not good, the performance of LDPC coding will be degraded, and the complexity and flexibility of coding may also be affected. Therefore, the concept of girth is introduced in the LDPC code design process. In order to better understand the concept of girth, we introduce the case where the basic matrix of the LDPC code has a short 4 ring and a short 6 ring to form a girth. In general, the basic matrix needs to be expanded into a parity check matrix or a binary matrix. In the parity check matrix, on any two different row indices i and l, and any two different column indexes on j and k, if the row index is i and l and the column index is j and k In the four elements {h _ij , h _ik , h _lk , h _lj } of the common indication, all four elements are equal to 1, and it is considered that there is a short circle of length 4 in the parity check matrix; In the parity check matrix, on any three different row indexes i, l, and a, and any three different column indexes are j, k, and b, if the row index is i, l, and a is the same as the six elements {h _ij , h _ik , h _lk , h _lb , h _ab , h _aj } indicated by the column index j, k and b. If these 6 elements are equal to 1, we think that There is a short circle of length 6 in the parity check matrix; similarly, in the parity check matrix, any four different row indexes are i, l, a, and c, and any four different columns. The index is j, k, b, and d, if the row index is i, l, a, and c and the column index is j, k, b, and d are collectively indicated by 8 elements {h _ij , h _ik , h _lk , h _lb , h _ab , h _ad , h _cd , h _cj }, if these 8 elements are all equal to 1, we think that there is a short circle of length 8 in the parity check matrix. As in the above example, there is also a short circle with a girth of 4, such as 601 and 602 shown in FIG. In the basic matrix, it can be considered that the necessary and sufficient condition for girth=4 in the parity check matrix corresponding to it is: in the basic matrix, there are at least one short four-ring 4 elements {h _ij , h _ik , h _Lk , h _lj } satisfied

(h _ij -h _ik +h _lk -h _lj )%Z=0

Here Z is the expansion factor, and % means the remainder operator, and the elements of the four positions will cause girth=4 to appear. In this way, since the information is only exchanged between the 4 nodes (2 variable nodes + 2 check nodes), after the multiple iterations, most of the information exchanged continuously receives information from the self feedback, and the external information is less. , the final codeword performance will be worse.

In the parity check matrix corresponding to the LDPC code, a sufficient and necessary condition for girth=6 is that there is no short 4-ring of girth=4, and in the basic matrix, there are at least one element of a short 6-ring {h _Ij , h _ik , h _lk , h _lb , h _ab , h _aj } satisfy

_{_{_{(h ij -h ik + h lk}}} -h lb + h ab -h aj)% Z = 0

Here Z is the expansion factor, and % means the remainder operator, then the elements of the 6 positions will cause the occurrence of girth=6. In this way, since most of the information is exchanged between the 6 nodes (3 variable nodes + 3 check nodes), since the foreign information exchanged for the same reason as girth=4 is less, the final codeword performance may be slightly lower. difference.

In the parity check matrix corresponding to the LDPC code, the necessary and sufficient condition for girth=8 is: there is no short 4-ring of girth=4 and a short 6-ring without girth=6, and at least in the basic matrix The 8 elements of a short 8-ring {h _ij , h _ik , h _lk , h _lb , h _ab , h _ad , h _cd , h _cj } satisfy

(h _ij -h _ik +h _lk -h _lb +h _ab -h _ad +h _cd -h _cj )%Z=0

Where Z is the expansion factor and % is the remainder operator, then the elements of the 8 positions will cause girth=8 to appear.

Although the quasi-cyclic LDPC code has been applied in various communication standards, it can be found through analysis that the code rate and code length of various standards are relatively limited, that is, the flexibility is relatively poor. For example, in the IEEE 802.11ad standard, there are only one code length (672) and four code rates (1/2, 5/8, 3/4, 13/16); in the IEEE 802.11n standard, there are only three Code length (648, 1296, 1944) and 4 code rates (1/2, 2/3, 3/4, 5/6). It can be found that since the quasi-cyclic LDPC is defined by a partial basic matrix, the disadvantage of these quasi-cyclic LDPC codes in use is that the flexibility is insufficient, and the flexibility refers to the flexible change of the code rate and the code length. Therefore, if the LDPC code is required to achieve flexible code rate and code length, it is more difficult to achieve performance without exception (ie, glitch) in each code length and code rate, and the performance and flexibility are satisfied for the LDPC code. This is very difficult. Moreover, in the new RAT (new Radio Access Technology) system, the channel coding scheme is required to support flexible code rate and code length, that is, the code length change interval is at least 8 bits, and the code rate can be flexibly changed. The device in the embodiments of the present disclosure can effectively solve the above problems.

On the basis of the above-mentioned embodiments, a modified embodiment of the above embodiment is also proposed. It is to be noted that, in order to simplify the description, only the differences from the above embodiment will be described in the respective modified embodiments.

In an embodiment of the present disclosure, the row weight of the base matrix includes at least 3/4 elements of the following set: {8, 9, 9, 8, 5, 6, 5, 6, 6, 6, 5, 6,4,5,5,5,5}; and/or,

The column weight of the base matrix includes at least 3/4 elements of the following set: {17, 5, 16, 4, 4, 4, 15, 4, 4, 10, 4, 3, 1, 1, 1, 1 ,1,1,1,1,1,1,1,1,1};

Wherein the row weight refers to the number of all the elements for indicating the shift size of the unit array cyclic shift when the row index is fixed in the base matrix and the column index is 0 to (nb-1);

The column weight refers to the number of all elements for indicating the shift size of the unit array cyclic shift when the column index in the base matrix is fixed and the row index is 0 to (mb-1).

Wherein, in the basic matrix, an element for indicating an all-zero square matrix is represented by a '-1', and a shift size element for indicating a cyclic shift of the unit array adopts a value greater than or equal to 0 and smaller than the expansion factor value. Integer representation. At least 80% of the elements of the base matrix are identical to the following reference base matrix Hb:

Further, at least 80% of the positions of the elements of the base matrix for indicating the shift size of the unit array cyclic shift are at least 80% of the positions of the following reference base matrix Hb':

Specifically, the position of the element for indicating the shift size of the unit array cyclic shift in the new base matrix obtained by the row matrix after row replacement and/or column permutation has at least 80% of the element position and the reference base matrix Hb. '中'1' has the same position.

For example, the code data processing apparatus in the embodiment of the present disclosure includes a storage module, an encoding module, and a rate matching module.

The storage module is configured to: store a set of basic matrix parameters and a set of expansion factor parameters; the set of basic matrix parameters includes a basic matrix, as follows:

Wherein, the basic matrix is a basic matrix corresponding to a maximum spreading factor Zmax=1024, “-1” represents an element for indicating an all-zero square matrix, and the others are used to indicate a shift size of a unit array cyclic shift. An element whose specific value is an integer greater than or equal to 0 less than a maximum spreading factor of 1024. The set of spreading factor parameters is {4 6 8 10 12 14 16 20 24 28 32 40 48 56 64 80 96 112 128 160 192 224 256 320 384 448 512 640 768 896 1024}.

An encoding module is connected to the storage module, and the encoding module is configured to: obtain, from the storage module, a base matrix of mb=18 rows nb=26 columns and an expansion factor parameter Z=56 used for quasi-cyclic LDPC encoding. The number of system columns kb=nb-mb=8, based on the base matrix of the one mb=18 rows nb=26 columns and one spreading factor parameter pair of information sequence X to be encoded with length kb×Z=8×56=448 bits Performing a quasi-cyclic LDPC encoding to obtain an LDPC code sequence Y having a length of nb×Z=26×56=1456 bits; The basic matrix of the mb=16 rows nb=26 columns is as follows

The basic matrix of mb=18 rows nb=26 columns corresponding to the expansion factor value of 56 described above is the basic matrix corresponding to the maximum expansion factor value Zmax=1024 described above, and is obtained by the following formula:

Containing B0=371 elements for indicating the all-zero square matrix (indicated by "-1" in this embodiment) and B1=97 elements for indicating the shift size of the unit array cyclic shift, The specific value of the element indicating the all-zero square matrix is an integer greater than or equal to 0 and less than Z=56.

The rate matching module is connected to the quasi-cyclic LDPC encoding module, and the rate matching module is configured to: select a length of N=1344 bits from the LDPC mother code sequence Y of length nb×Z=26×56=1456 bits. Rate matching LDPC code sequence. The performance is shown in Figure 6. It can be seen that the performance of the new scheme is better than that of the old scheme. Therefore, it can be seen that the scheme can improve performance.

Wherein, the column having one column in the basic matrix has the heaviest weight.

In another embodiment of the present disclosure, the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and the A0 consecutive bit blocks respectively correspond to A0 column indexes of the base matrix. The A0 column index numbers constitute a set T0, and the A0 is any integer from 0 to 3; wherein the element value and the number of elements of the set T0 are determined by at least one of the following parameters:

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.

The specific value of the A0 is determined by at least one of the following parameters:

Transmission block size TBS, application scenario, user UE type, frequency band, code rate R, combination of transport block size TBS and code rate R, channel type, data transmission direction, TBS index number, and resource unit number NRB combination, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.

The transport block size TBS is an integer greater than 0; the application scenario includes: a mobile broadband enhanced eMBB, an ultra-high reliability low latency communication URLLC, and a large-scale Internet of Things mMTC; the frequency band includes: a frequency range configured by the system The code rate R is a real number greater than 0 and less than 1; the channel type includes: a control channel and a data channel; the data transmission direction includes: uplink data and downlink data; and the TBS index number is used to combine resource units The number indicates a corresponding transport block size TBS, the TBS index number is an integer greater than or equal to 0; the MCS index number is used to indicate an MCS scheme or a combination of a modulation order and a TBS index, where the MCS index number is An integer greater than or equal to 0; the number of resource units NRB is the number of resource blocks configured by the system; the bandwidth size is a real number greater than zero. The user UE type is a user type defined in the LTE system.

Optionally, if the transport block size TBS is smaller than the positive integer TBS0, the A0 value is the set G1; if the transport block size TBS is greater than or equal to the positive integer TBS0, the A0 value is the set G2; wherein, G1 The element values in G2 and G2 are integers from 0 to 3, and the intersection of G1 and G2 is an empty set.

According to different transport block sizes, the TBS adopts different A0 values, and the beneficial effects are as follows: the decoding performance of the quasi-cyclic LDPC coding can be balanced, and the performance is better at low code lengths. For example, when the information length (or transport block size TBS) is less than TBS0=1024 bits, A0 is equal to 0, that is, in the rate matching module, the performance of A0 equal to 0 is better than the performance of A0 greater than 0, but when the long code length is long, such as information When the length (or transport block size TBS) is greater than or equal to TBS0=1024 bits, A0 is an integer greater than 0, and the performance is superior. Therefore, the LDPC code can maintain good decoding performance under flexible code length and code rate. The TBS0=1024 described above is only an example. According to different basic matrix designs, TBS0 is not limited to the above values. Further, for example, in the rate matching module, the positive integer TBS0 is an integer greater than 256 and less than 4096.

Optionally, if the code rate R is greater than the positive real number R′, the specific value of A0 is the set G3; if the code rate R is less than or equal to the positive real number R′, the specific value of A0 is the set G4; R' is a real number greater than 0 and less than 1, the code rate R is the code rate of the LDPC code sequence after the rate matching, and R is a real number greater than 0 and less than 1, wherein the element value in G3 and G4 is 0. Integer to 3, G3 and G4 The intersection is an empty set.

The specific value of the A0 is set according to different code rates, and the beneficial effect is that the quasi-cyclic LDPC code can obtain equal and superior decoding performance at different code rates, that is, at different code rates under the same code length ( For example, the performance under 0.2~0.93) will be smoother, and there will be no poor performance of a certain bit rate, and partial bit rate performance is better.

Optionally, if the frequency band is greater than the positive real number FB0, the specific value of A0 is set G5; if the frequency band is less than or equal to the positive real number FB0, the specific value of A0 is set G6; wherein, G5 is neutralized in G6 The element value is an integer from 0 to 3, and the intersection of G5 and G6 is an empty set.

The specific value of the A0 is determined according to different frequency bands. The beneficial effect is that if the frequency band is in the low frequency part, the available bandwidth is relatively small, so the general data amount is small, the transport block size TBS is relatively small, and the low frequency channel multipath has a large influence. Therefore, a lower code rate is required for transmission, so it is also necessary to adjust the specific value of A0 so that the quasi-cyclic LDPC code can be in an optimal decoding state, thereby improving the robustness of the system; when the frequency band is high, Due to the large available bandwidth, the multipath impact of the signal is reduced, the larger transport block size TBS can be transmitted, and the bit rate is higher. Adjusting the specific value of A0 can still ensure that the performance of the quasi-cyclic LDPC code is still good in different frequency bands. The frequency band refers to the central frequency point of the communication bandwidth used by the system. For example, the communication bandwidth is 20 MHz and the position is between 1.5 GHz and 1.52 GHz. At this time, the communication frequency band is known to be 1.51 GHz.

Optionally, if the channel type is a control channel, the specific value of A0 is a set G7; if the channel type is a data channel, the specific value of A0 is a set G8; wherein, the element value in G7 and G8 It is an integer from 0 to 3, and the intersection of G7 and G8 is an empty set.

Determining the specific value of the A0 according to different channel types, the beneficial effect is that the data of the general control channel is relatively small and the code rate is relatively low, and the data volume of the data channel is relatively large and the code rate is relatively high, so At this time, the specific value of A0 can be determined according to whether the data is a control channel and a data channel, and the performance under different data types can be kept good. For example, in the data coding of the control channel, quasi-cyclic LDPC coding uses A0 equal to 0, and data coding under the data channel quasi-cyclic LDPC coding uses A0 equal to 1 or 2 (or 1 from {1, 2}). The specific numerical value of A0 is not limited to the method described above.

Optionally, if the data transmission direction is an uplink data transmission, the specific value of A0 is a set G9; if the data transmission direction is a downlink data transmission, a specific value of A0 is a set G10; In the G9, the element value in G10 is an integer from 0 to 3, and the intersection of G9 and G10 is an empty set.

Determining the specific value of the A0 according to different data transmission directions, the beneficial effect is: generally, the uplink data has less data flow, and the downlink data has a larger data stream, so the A0 can be determined according to different data transmission directions. The specific values can keep the performance of data encoding in different transmission directions better. The uplink data refers to that the user terminal (mobile device UE) transmits data to the base station, and the downlink data refers to the base station transmits data to the user terminal (mobile device UE).

Optionally, if the bandwidth is greater than the positive real number BW0, the specific value of A0 is the set G11; if the bandwidth is less than or equal to the positive real number BW0, the specific value of A0 is the set G12; wherein, G11 neutralizes the G12 The element value is an integer from 0 to 3, and the intersection of G11 and G12 is an empty set.

The specific value of the A0 is determined according to different bandwidths. The beneficial effect is that when the bandwidth is large, the amount of data is relatively large, that is, the transport block size TBS is correspondingly large, but when the bandwidth is small, the amount of data transmitted is Smaller, the performance of the quasi-cyclic LDPC code in different bandwidth conditions can be kept better. For example, when the bandwidth is small (the bandwidth is less than BW0=10MHz), A0 can be equal to 0, that is, G11={0}, and when the bandwidth is large (the bandwidth is greater than or equal to BW0=10MHz), A0 can be equal to 1 or 2, that is, G12={1,2}. The specific numerical value of the BW0 is not limited to the above numerical values.

Specifically, when the values of the parameters are not the same, the set T0 is different.

In still another embodiment of the present disclosure, the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, and the A2 consecutive bit blocks respectively correspond to the base matrix A2 column index numbers, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb; wherein the element value and the number of elements of the set T1 are determined by at least one of the following parameters:

Specifically, when the values of the parameters are not the same, the set T1 is different.

In another embodiment of the present disclosure, the rate matching module is further configured to: interleave the LDPC coded output sequence according to an interlace pattern InP, and then sequentially select the rate matching output sequence The interleaving pattern InP is in units of consecutive bit blocks of Z bits, and the interleaving pattern InP includes nb integers from 0 to (nb-1) which are not equal to each other; wherein the interlace pattern InP is specific The element value and the specific number of elements are determined by at least one of the following parameters:

Wherein, when the values of the parameters are different, the interlace pattern InP is different.

In still another embodiment of the present disclosure, the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and the A0 consecutive bit blocks respectively correspond to A0 column indexes of the base matrix. The A0 column index numbers constitute a set T0, and the A0 is any integer from 0 to 3.

In the basic matrix, all element values in the set T0 are used as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M0 of the mb' row A0 column, Mb' is an integer greater than 0 less than or equal to mb, and the matrix M0 has at least one of the following conditions:

The difference between the column weights of any two columns in the matrix M0 is not more than 1;

An element of any one of the columns of the matrix M0 includes at least one element for indicating an all-zero square matrix;

The matrix M0 includes at least A3 non-full lines, and the non-full line means that at least one of the lines is used to indicate an all-zero square matrix element; the A3 is equal to 2 or 3;

The matrix M0 includes at least one row having a row weight equal to 1;

The matrix M0 includes at least one row having a row weight equal to A0.

In still another embodiment of the present disclosure, the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, and the A2 consecutive bit blocks respectively correspond to the base matrix A2 column index numbers, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb.

In the basic matrix, all element values in the set T1 are taken as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M1 of the mb' row A2 column, Mb' is an integer greater than 0 less than or equal to mb, and the matrix M1 has at least one of the following conditions:

Among the two elements in the matrix M1, there are at most one element indicating the shift size of the cyclic shift of the unit array among the two elements indicated by the same row index number;

Any one of the rows of the matrix M1 includes at most 2 elements indicating the shift size of the cyclic shift of the unit array.

In the basic matrix, all element values in the set T0 are used as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M0 of the mb' row A0 column, Mb' is an integer greater than 0 and less than mb.

The rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, and the A2 consecutive bit blocks respectively correspond to A2 column index numbers of the base matrix, the A2 The column index numbers constitute a set T1, and the A2 is any integer from 0 to mb.

In the basic matrix, all element values in the set T1 are taken as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M1 of the mb' row A2 column, Mb' is an integer greater than 0 less than or equal to mb.

The matrix M0 and the matrix M1 form a matrix M2=[M0M1] of the mb' row (A0+A2) column, wherein the matrix M2 has at least one of the following conditions:

One of the rows of the matrix M2 having a row weight equal to 1 indicates that the column index number of the shift size element of the unit array cyclic shift is an integer from 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, at least one column index number of the shift size element indicating the cyclic shift of the unit array in any row is an integer of 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, the row weight of at least one row is equal to 2, wherein the column index numbers of the elements of the shift size indicating the cyclic shift of the unit array in each of the at least one row are 0 to (A0-1) An integer, A0 is an integer greater than one;

In the matrix M2, at least one row of rows is greater than or equal to A0, wherein all of the first A0 of the column index numbers of the elements of the shift size indicating the cyclic shift of the unit array in each row of the at least one row are 0. To an integer of (A0-1), A0 is an integer greater than zero.

In the rate matching process, as shown in the example of FIG. 4, the basic matrix is a matrix of mb=6 rows nb=16 columns, kb=nb-mb=16-6=10, and the sequence of information to be encoded is X, which is accurate. After cyclic LDPC coding, an LDPC mother code sequence 502, Y=[X, P], where P is a redundancy check bit obtained by quasi-cyclic LDPC coding (or LDPC code check bit), and a black square in the basic matrix is obtained. Block 503 refers to the element used to indicate the shift size of the unit array cyclic shift, and black box 504 refers to the element used to indicate the all-zero square matrix. It can be seen that the base matrix of the example includes B0= 40 elements for indicating the all-zero square matrix and B1=56 elements for indicating the shift size of the unit array cyclic shift, the dimension of the unit matrix or the all-zero square matrix is Z×Z, LDPC Each consecutive Z bit in the mother code code word 502 has a one-to-one correspondence with the base matrix. For example, the rate matching process selects the corresponding N bits from the LDPC mother code code word Y to obtain the rate matched LDPC. a sequence of code words, for example, removing A0×Z bits in the sequence of information to be encoded and A1 bits in the check sequence LDPC codeword sequence after rate matching can be obtained.

In the example of FIG. 4, M0 in the base matrix one-to-one corresponding to the A0×Z bits is a matrix composed of the first two columns. The above-mentioned characteristics of M0 bring about the beneficial effects that the quasi-cyclic LDPC code can obtain superior performance in the rate matching process.

The above-mentioned characteristics of M1 have the beneficial effects that the quasi-cyclic LDPC code can obtain superior performance in the rate matching process.

The characteristics of M2 described above, which constrain the relationship between M0 and M1, have the beneficial effects that the quasi-cyclic LDPC code can obtain superior performance in the rate matching process.

In still another embodiment of the present disclosure, the number of system columns of the base matrix of one mb row nb column used is kb; the code rate of the LDPC code sequence after the rate matching is R, wherein there are threshold values R0, R1, Kb0, kb1, kb2, kb3, kb4.

If R is less than or equal to R0, the value of kb is [kb0 kb1]; if R is greater than R0 and less than or equal to R1, the value of kb is [kb2 kb3]; if R is greater than R1, the range of kb is [kb1] Kb4];

Where mb and nb satisfy the relation kb=nb-mb, R0 is a real number greater than 0 and less than 1, R1 is a real number greater than R0 and less than 1, kb0 is an integer greater than 0 and less than kb, and kb1 is an integer greater than kb0 and less than kb. Kb2 is an integer greater than kb0 less than kb1, kb3 is greater than kb1 less than kb4, kb4 is an integer greater than kb3, and R is a real number greater than 0 and less than one.

When determining the number of system columns kb of the basic matrix of the quasi-cyclic LDPC code, since the number of system columns kb is closely related to the length of the information sequence, the length of the information sequence is generally equal to the product of the number of system columns kb and the spreading factor, so the system column The number of kb can be varied within a wide range, and can flexibly support code lengths of different lengths and different lengths at different code rates, mainly to ensure that the quasi-cyclic LDPC codes are within the corresponding code rate range and corresponding code lengths. Obtaining superior decoding performance.

Optionally, the threshold parameter is: R0=2/5, R1=2/3, kb0=8, kb1=12, kb2=10, kb3=14, kb4=16. The threshold parameter of this example is not limited to the above values.

Optionally, the code rate of the LDPC code sequence after the rate matching is R is a real number greater than or equal to 8/9 and less than 1.

In still another embodiment of the present disclosure, if the code rate of the LDPC code sequence after the rate matching is R, under the condition of being greater than R2, the LDPC code sequence Y of length nb×Z bits needs to be interleaved first. And then selecting a rate matched LDPC code sequence of length N bits; wherein R2 is a real number greater than 5/6 less than 1, and R is a real number greater than 0 and less than 1.

Optionally, the device further includes:

And a padding module, configured to fill the source information sequence with a dummy bit to obtain a sequence of information to be encoded, where the padded dummy bit is located at the front of the source information sequence.

Optionally, the position of the A0 x Z bit is located at the end of the sequence of information to be encoded.

Optionally, the rate matching module is further configured to: interleave the LDPC coded output sequence by a reordering number, and then select an N bit rate matching output sequence.

The method for determining the reordering number includes: rearranging in units of Z consecutive bit blocks, the sequence numbers of the Z consecutive bit blocks are one-to-one corresponding to column index numbers of the basic matrix, and are consecutive to the A0 The column index number of the base matrix corresponding to the bit block is located at the end of the reordering number.

The apparatus in the present disclosure obtains a rate matching output sequence in a rate matching process after quasi-cyclic LDPC encoding, wherein the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and/or does not include an LDPC coded output sequence. A2 consecutive bit blocks in the check bits, such that the rate match output sequence does not include A0 consecutive bit blocks in the sequence of information to be encoded, and/or the rate match output sequence does not include the LDPC coded output A2 consecutive bit blocks in the check bits of the sequence, and defining A0 and A2 according to different parameter conditions, and constraining A0 The position of the continuous bit block in the information sequence to be encoded and the position of the A2 consecutive bit blocks in the LDPC coded output sequence, improving the performance of the quasi-cyclic LDPC code in different environments or scenarios to adapt to various code lengths and code rates. Performance requirements to support flexible code lengths and bit rates, as well as maintaining good performance.

An apparatus in an embodiment of the present disclosure is exemplified.

Specific example 1

A quasi-cyclic LDPC code data processing apparatus is provided, including a storage module, an encoding module, and a rate matching module.

The storage module is configured to store a base matrix and a set of spreading factor values used for quasi-cyclic LDPC encoding; the basic matrix is a matrix of mb rows and nb columns, the basic matrix including elements for indicating an all-zero square matrix An element for indicating a shift size of a unit array cyclic shift, each of the set of spread factor values being used to indicate the number of rows of the all-zero square matrix or the unit matrix, each of An extension factor value is an integer greater than 0, the mb is an integer greater than 0, the nb is an integer greater than mb; the base matrix may describe a base check matrix or other exponential index matrix (the index is a permutation The order of the matrix, etc., the expansion factor value is also called lifting size or shift size or sub-block size. The term is not limited to other terms in the patent. same.

The encoding module is configured to: acquire the base matrix and an expansion factor value from the storage module, and process the information to be encoded based on the obtained basic matrix and the expansion factor value

The sequence is subjected to quasi-cyclic LDPC coding to obtain an LDPC coded output sequence.

In the storage module, the row weight of the basic matrix includes at least 3/4 elements of the following set: {8, 9, 9, 8, 5, 6, 5, 6, 6, 6, 5, 6, 4 , 5, 5, 5, 5}; and/or, the column weight of the base matrix includes at least 3/4 elements of the following set: {4, 15, 4, 4, 4, 16, 5, 17, 4 , 10, 4, 3, 1, 1, 1, 1, 1, 1}.

The row weight refers to the number of elements for indicating the shift size of the unit array cyclic shift when the row index is fixed in the base matrix and the column index is 0 to (nb-1).

The column weight refers to the number of elements for indicating the shift size of the unit array cyclic shift when the column index in the base matrix is fixed and the row index is 0 to (mb-1).

In the basic matrix, the element for indicating the all-zero square matrix is represented by '-1', and the element for indicating the shift size of the cyclic shift of the unit array adopts an integer greater than or equal to 0 and smaller than the expansion factor value. Indicates that the expansion factor value is equal to 1024 at this time, including: the basic matrix is the following basic matrix Hb:

Alternatively, at least 80% of the positions of the elements of the base matrix indicating the shift size of the unit array cyclic shift are at least 80% of the positions of the following reference base matrix Hb':

And, the position of the element for indicating the shift size of the unit array cyclic shift in the new base matrix obtained by the row matrix after the row permutation and/or the column permutation has at least 80% of the element position and the following reference base matrix Hb '中'1' has the same position. The row permutation refers to: any two rows in the basic matrix are exchanged, and multiple operations can be performed; the column permutation refers to: exchanging any two columns in the basic matrix, and performing multiple operations.

Concrete example 2

The storage module is configured to store a base matrix and a set of spreading factor values used for quasi-cyclic LDPC encoding; the basic matrix is a matrix of mb rows and nb columns, the basic matrix including elements for indicating an all-zero square matrix An element for indicating a shift size of a unit array cyclic shift, the spread factor value is used to indicate the number of rows of the all-zero square matrix or the unit matrix, and the expansion factor value is an integer greater than 0, The mb is an integer greater than 0, and the nb is an integer greater than mb.

The encoding module is configured to: obtain the basic matrix and an expansion factor value from the storage module, and perform quasi-cyclic LDPC encoding on the sequence of the information to be encoded based on the obtained basic matrix and the spreading factor value to obtain an LDPC encoded output sequence.

In an embodiment of the present disclosure, the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and the A0 consecutive bit blocks respectively correspond to column index numbers of the basic matrix to form a set. T0, the A0 is any integer from 0 to 3; wherein the element value and the number of elements of the set T0 are determined by at least one of the following parameters:

In the following examples, the basic matrix size used is exemplified as the base matrix of mb=8 rows nb=16 columns, so the value of T1 is an integer value of 8 to 15, that is, the check bit portion of the LDPC coded output sequence is The Z bit is the index number of the unit number sort.

The element value and the number of elements of T0 are determined according to the transport block size TBS parameter. When the transport block size TBS is smaller than the positive integer TBS0, the value of T0 is the set G1; when the transport block size TBS is greater than or equal to the positive integer TBS0, the T0 is the set G2; wherein, the intersection of G1 and G2 Empty set. For example, TBS0 is equal to 1024, G1 is an empty set, G2 is a set {0}; the transport block size TBS is less than TBS0=1024, A0 is equal to 0, and the LDPC coded output sequence is not punctured (deleted) systematic bits after rate matching ( Information bit); the transport block size TBS is greater than or equal to TBS0=1024, A0 is equal to 1, and the LDPC coded output sequence needs to be punctured (deleted) system bits (information bits) of A0×Z bits after rate matching.

Determining an element value and an element number of T0 according to the application scenario, where the application scenario includes: a mobile broadband enhanced eMBB, an ultra-high reliability low latency communication URLLC, and a large-scale Internet of Things mMTC. When the application scenario is ultra-high reliability low latency communication URLLC and/or large-scale Internet of Things mMTC, the value of T0 is set G1; when the application scenario is mobile broadband enhanced eMBB, T0 is a set G2. Where the intersection of G1 and G2 is an empty set. For example, the application scenario is ultra-reliable low-latency communication URLLC and/or large-scale Internet of Things mMTC, G1 is an empty set, G2 is a set {2}, that is, A0 is equal to 0, and the LDPC coded output sequence is not punctured after rate matching. (delete) system bits (information bits); the application scenario is mobile broadband enhanced eMBB, that is, the transport block size TBS is greater than or equal to TBS0=1024, A0 is equal to 2, and the LDPC coded output sequence needs to be punched after rate matching (delete ) System bits (information bits) of A0 × Z bits.

Determining an element value and an element number of T0 according to the user UE type, where the user UE type includes various mobile user types defined by LTE. The element value and the number of elements of T0 are determined according to different user types.

Determining the element value and the number of elements of T0 according to the frequency band, wherein the frequency band is greater than the positive real number FB0, then T0 is the set G5; if the frequency band is less than or equal to the positive real number FB0, then T0 is the set G6; wherein, G5 and G6 The intersection is an empty set. The T0 is determined according to different frequency bands, and the beneficial effect is that if the frequency band is in the low frequency part, the available bandwidth is relatively small, so the general data amount is small, the transport block size TBS is relatively small, and the low frequency channel multipath has a large influence, so it is required Lower bit rate for transmission, so it also needs The specific value (or T0) of A0 is adjusted so that the quasi-cyclic LDPC code can be in an optimal decoding state, thereby improving the robustness of the system; when the frequency band is high, the signal is large due to the available bandwidth. The multipath effect is reduced, the larger transport block size TBS can be transmitted, and the bit rate is higher. Adjusting the specific value of A0 can still ensure that the performance of the quasi-cyclic LDPC code is still good in different frequency bands. The frequency band refers to the central frequency point of the communication bandwidth used by the system. For example, the communication bandwidth is 20 MHz and the position is between 1.5 GHz and 1.52 GHz. At this time, the communication frequency band is known to be 1.51 GHz.

Determining T0 according to the bandwidth size, wherein the bandwidth size is greater than the positive real number BW0, then T0 is the set G11; if the bandwidth size is less than or equal to the positive real number BW0, then T0 is the set G12; wherein, the intersection of G11 and G12 is Empty set. Determining the specific value of the A0 according to different bandwidths (or T0, T0 includes different values and different numbers of values, it is considered to be different), and the beneficial effect is that when the bandwidth is large, the amount of data is relatively large. That is, the transport block size TBS is correspondingly large, but when the bandwidth is small, the amount of data transmitted is relatively small, which can make the performance of the quasi-cyclic LDPC code in different bandwidth conditions better. For example, when the bandwidth is small (the bandwidth is less than BW0=10MHz), A0 can be equal to 0, that is, G11={0}, and when the bandwidth is large (the bandwidth is greater than or equal to BW0=10MHz), A0 can be equal to 1 or 2, that is, G12={1,2}. That is, G11 is an empty set, and G12 is {1, 2}. The specific numerical value of the BW0 is not limited to the above numerical values.

Determining a specific value of A0 according to the code rate R, wherein the code rate R is greater than the positive real number R', then T0 is the set G3; the code rate R is less than or equal to the positive real number R', then T0 is the set G4; The positive real number R' is a real number greater than 0 and less than 1, the code rate R is the code rate of the rate matching output sequence, and R is a real number greater than 0 and less than 1, wherein the intersection of G3 and G4 is an empty set. The T0 is set according to different code rates, and the beneficial effect is that the quasi-cyclic LDPC code can obtain equal and superior decoding performance at different code rates, that is, different code rates under the same code length (for example, 0.2 to 0.93). Under the performance will be relatively smooth, there will be no poor performance of a certain bit rate, and partial bit rate performance is better.

Of course, the combination of the transport block size TBS and the code rate R may also be used to determine T0 to increase the robustness of system communication.

Determining T0 according to the channel type, wherein the channel type is a control channel, then T0 is a set G7; the channel type is a data channel, then T0 is a set G8; wherein, the intersection of G7 and G8 is an empty set. The T0 is determined according to different channel types, and the beneficial effect is that the data of the general control channel is relatively small and the code rate is relatively low, and the data volume of the data channel is large and the code rate is relatively high. Therefore, at this time, T0 can be determined according to whether the data is a control channel and a data channel, and the performance under different data types can be kept good. For example, in the data coding of the control channel, the quasi-cyclic LDPC coding adopts A0 equal to 0, that is, T0 is an empty set; and the data coding quasi-cyclic LDPC coding under the data channel adopts A0 equal to 1 or 2 (or selects from {1, 2} 1). The T0 is not limited to the values described above.

Determining T0 according to the data transmission direction, wherein the data transmission direction is uplink data transmission, then T0 is a set G9; and the data transmission direction is downlink data transmission, then T0 is a set G10; wherein, the intersection of G9 and G10 Empty set. Determining the specific value of the A0 according to different data transmission directions, the beneficial effect is: generally, the uplink data has less data flow, and the downlink data has a larger data stream, so the T0 can be determined according to different data transmission directions. The performance of data encoding in different transmission directions can be kept better. The uplink data refers to that the user terminal (mobile device UE) transmits data to the base station, and the downlink data refers to the base station transmits data to the user terminal (mobile device UE).

Of course, T0 may be determined according to a combination of a TBS index number and a resource unit number NRB, where the TBS index number refers to a transport block size index number used in a different system (such as LTE) for different MCS (coded modulation scheme), and The source unit number NRB combination can be used to index the resulting transport block size TBS, and the value of T0 can be determined according to a method similar to that described above.

It is of course possible to determine T0 according to the combination of the modulation coding scheme MCS index number and the resource unit number NRB. The MCS index number may indicate the TBS index number, and the T0 may be determined according to the combination of the TBS index number and the resource unit number NRB described above. The MCS index is generally indicated by system setting or signaling.

Of course, T0 can be determined according to the combination of the code rate R and the number of resource units NRB. The number of modulation units can be known by knowing the number of resource units NRB. According to the order, the size of the rate matching output sequence can be known, and then the code rate R Multiply to obtain the transport block size TBS, and then determine T0 similarly to the above.

The in-band and out-of-band indications may also be used to determine T0. If the data is transmitted within the bandwidth allocated by the system, T0 is the set G20; if the data is transmitted outside the bandwidth allocated by the system, T0 is the set G21; wherein, G20 and G21 The intersection is an empty set.

The value of T0 described above is not limited to the above method.

Specific example 3

A quasi-cyclic LDPC code data processing apparatus is provided, including: a storage module, an encoding module, and a rate matching module.

The storage module is configured to store a base matrix and a set of spreading factor values used for quasi-cyclic LDPC encoding; the basic matrix is a matrix of mb rows and nb columns, the basic matrix including elements for indicating an all-zero square matrix An element for indicating a shift size of a unit array cyclic shift, each of the set of spread factor values being used to indicate the number of rows of the all-zero square matrix or the unit matrix, each of One spreading factor value is an integer greater than 0, the mb represents an integer greater than 0, and the nb represents an integer greater than mb.

The encoding module is configured to acquire the base matrix and a spreading factor value from the storage module, perform quasi-cyclic LDPC encoding on the sequence of the information to be encoded based on the obtained basic matrix and the spreading factor value, to obtain an LDPC encoded output sequence.

In an embodiment of the present disclosure, the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the base matrix The column index number constitutes a set T1, and the A2 is any integer from 0 to mb; wherein the element value and the number of elements of the set T1 are determined by at least one of the following parameters:

In the example described below, the base matrix size used is exemplified as the base matrix of mb=8 rows nb=16 columns, so the value of T1 is an integer value of 8 to 15, that is, the check of the LDPC coded output sequence. The bit number is an index number sorted by Z bit number.

Determining an element value and an element number of T1 according to the transport block size TBS parameter, wherein when the transport block size TBS is smaller than a positive integer TBS0, the value of T1 is a set G1; the transport block size TBS is greater than or equal to positive An integer TBS0, then T1 takes a value of the set G2; wherein the TBS0 is an integer greater than 600 and less than 4096. For example, TBS0 is equal to 892, G1 is the set {8, 10, 12, 13, 14, 15}, and G2 is the set {9, 11, 12, 13, 14, 15}.

Determining an element value and an element number of T1 according to the application scenario, where the application scenario includes: a mobile broadband enhanced eMBB, an ultra-high reliability low latency communication URLLC, and a large-scale Internet of Things mMTC. When the application scenario is ultra-reliable low-latency communication URLLC and/or large-scale Internet of Things mMTC, the value of T1 is set G3, and G3 is a set {8, 10, 12, 13, 14, 15}; The application scenario is mobile broadband enhanced eMBB, and T1 takes the value G4, and G4 is the set {9, 11, 12, 13, 14, 15}.

Determining an element value and an element number of T1 according to the user UE type, where the user UE type includes various mobile user types defined by LTE. The element value and the number of elements of T1 are determined according to different user types.

The element value and the number of elements of T1 are determined according to the frequency band, wherein the frequency band is greater than the positive real number FB0, then T1 is the set G5; and the frequency band is less than or equal to the positive real number FB0, then T1 is the set G6. G5 is the set {8,10,11,13,14,15}, and G6 is the set {9,10,12,13,14,15}. The T1 is determined according to different frequency bands, and the beneficial effect is that if the frequency band is in the low frequency part, the available bandwidth is relatively small, so the general data amount is small, the transport block size TBS is relatively small, and the low frequency channel multipath has a large influence, so it is required The lower code rate is transmitted, so it is also necessary to adjust the specific value (or T1) of A2 so that the quasi-cyclic LDPC code can be in an optimal decoding state, thereby improving the robustness of the system; Because the available bandwidth is large, the multipath of the signal is reduced, the larger transport block size TBS can be transmitted, and the bit rate is higher. Adjusting the specific value of A2 can still ensure that the performance of the quasi-cyclic LDPC code is still good in different frequency bands. . The frequency band refers to the central frequency point of the communication bandwidth used by the system. For example, the communication bandwidth is 20 MHz and the position is between 1.5 GHz and 1.52 GHz. At this time, the communication frequency band is known to be 1.51 GHz.

Determining T1 according to the bandwidth size, wherein the bandwidth size is greater than the positive real number BW0, then T1 is the set G11; and the bandwidth size is less than or equal to the positive real number BW0, then T1 is the set G12. Determining the specific value of the A2 according to different bandwidths (or T1, T1 includes different values and different numbers of values, it is considered to be different), and the beneficial effect is that when the bandwidth is large, the amount of data is relatively large. That is, the transport block size TBS is correspondingly large, but when the bandwidth is small, the amount of data transmitted is relatively small, which can make the performance of the quasi-cyclic LDPC code in different bandwidth conditions better. For example, G11 is a set {8, 10, 12, 13, 14, 15}, and G12 is a set {9, 11, 12, 13, 14, 15}.

Determining a specific value of A2 according to the code rate R, wherein the code rate R is greater than the positive real number R', then T1 is the set G3; the code rate R is less than or equal to the positive real number R', then T1 is the set G4; Positive real number R' Is a real number greater than 0 and less than 1, the code rate R is the code rate of the rate matching output sequence, and R is a real number greater than 0 and less than 1, wherein the intersection of G3 and G4 is an empty set. The T1 is set according to different code rates, and the beneficial effect is that the quasi-cyclic LDPC code can obtain equal and superior decoding performance at different code rates, that is, different code rates at the same code length (for example, 0.2 to 0.93). Under the performance will be relatively smooth, there will be no poor performance of a certain bit rate, and partial bit rate performance is better. For example, G3 is a set {8, 10, 12, 13, 14, 15}, and G4 is a set {9, 11, 12, 13, 14, 15}.

Of course, the combination of the transport block size TBS and the code rate R may also be used to determine T1 to increase the robustness of system communication.

Determining T1 according to the channel type, wherein the channel type is a control channel, then T1 is a set G7; the channel type is a data channel, then T1 is a set G8; wherein, the intersection of G7 and G8 is an empty set. Determining the T1 according to different channel types has the beneficial effects that: the data of the general control channel is relatively small and the code rate is relatively low, and the data volume of the data channel is relatively large and the code rate is relatively high, so at this time, T1 can be determined based on whether the data is a control channel and a data channel, and can be made to perform well under different data types. For example, G7 is a set {8, 10, 12, 13, 14, 15}, and G8 is a set {9, 11, 12, 13, 14, 15}. The T1 is not limited to the values described above.

Determining T1 according to the data transmission direction, wherein the data transmission direction is uplink data transmission, then T1 is a set G9; and the data transmission direction is downlink data transmission, then T1 is a set G10; wherein, the intersection of G9 and G10 Empty set. Determining the specific value of the A2 according to different data transmission directions, the beneficial effect is: generally, the uplink data has less data flow, and the downlink data has a larger data stream, so the T1 can be determined according to different data transmission directions. The performance of data encoding in different transmission directions can be kept better. The uplink data refers to that the user terminal (mobile device UE) transmits data to the base station, and the downlink data refers to the base station transmits data to the user terminal (mobile device UE). For example, G9 is a set {8, 10, 12, 13, 14, 15}, and G10 is a set {9, 11, 12, 13, 14, 15}.

Certainly, T1 may be determined according to a combination of a TBS index number and a resource unit number NRB, where the TBS index number refers to a transport block size index number used in a different system (such as LTE) for different MCS (code modulation scheme), and The source unit number NRB combination can be used to index the resulting transport block size TBS, and the value of T1 can be determined according to a method similar to that described above.

Certainly, T1 may be determined according to a combination of a modulation coding scheme MCS index number and a resource unit number NRB, and the MCS index number may indicate a TBS index number, and thus may adopt the foregoing TBS index number and A combination of resource unit numbers NRB to determine T1. The MCS index is generally indicated by system settings or signaling.

Of course, T1 can be determined according to the combination of the code rate R and the number of resource units NRB. The number of modulation units can be known by knowing the number of resource units NRB. According to the order, the size of the rate matching output sequence can be known, and then the code rate R Multiply to obtain the transport block size TBS, and then determine T1 similarly to the above.

The in-band and out-of-band indications may also be used to determine T1. If the data is transmitted within the bandwidth allocated by the system, then T1 is the set G20; if the data is transmitted outside the bandwidth allocated by the system, then T1 is the set G21; wherein, G20 and G21 The intersection is an empty set. For example, G20 is a set {8, 10, 12, 13, 14}, and G21 is a set {9, 11, 12, 13, 14, 15}.

The value of T1 described above is not limited to the above method.

Concrete example 4

The storage module is configured to store a base matrix and a set of spreading factor values used for quasi-cyclic LDPC encoding; the basic matrix is a matrix of mb rows and nb columns, the basic matrix including elements for indicating an all-zero square matrix An element for indicating a shift size of a unit array cyclic shift, each of the set of spread factor values being used to indicate the number of rows of the all-zero square matrix or the unit matrix, each of An expansion factor value is an integer greater than 0, the mb is an integer greater than 0, and the nb is an integer greater than mb.

The rate matching module is further configured to: interleave the LDPC coded output sequence according to an interlace pattern InP, and sequentially select the rate matching output sequence, where the interlace pattern InP is in units of Z bits of consecutive bit blocks. The interleaving pattern InP contains nb from 0 to (nb-1) which are not equal to each other. An integer; wherein the element value and the number of elements of the interleaving pattern InP are determined by at least one of the following parameters:

In an embodiment of the invention, the interleaving pattern InP is different when the values of the parameters are not the same.

Concrete example 5

A quasi-cyclic LDPC code data processing apparatus is further provided, comprising a storage module, an encoding module and a rate matching module.

In an embodiment of the present invention, the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and the A0 consecutive bit blocks respectively correspond to column index numbers of the basic matrix to form a set. T0, the A0 is any integer from 0 to 3. In the basic matrix, all element values in the set T0 are composed of all elements indicated by the column index number and the row index number 0 to (mb'-1). Mb' row matrix M0 of row A0, said mb' is an integer greater than 0 less than mb, said matrix M0 having at least one of the following conditions:

The matrix M0 includes at least A3 non-full lines, the non-full line is at least one of the lines for indicating all zero square elements; the A3 is equal to 2 or 3;

The matrix M0 includes at least one row having a row weight equal to 1;

The matrix M0 includes at least one row having a row weight equal to A0.

The beneficial effects of the operation are: making the LDPC decoding performance better, and supporting flexible code length and code rate design.

Concrete example 6

In an embodiment of the present invention, the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, and the A2 consecutive bit blocks respectively correspond to the base matrix The column index number constitutes a set T1, and the A2 is any integer from 0 to mb; in the basic matrix, all element values in the set T0 are used as a column index number and a row index number of 0 to (mb'-1) All elements indicated constitute a matrix M1 of mb' row A2 columns, which is an integer greater than 0 and less than mb, said matrix M1 having at least one of the following conditions:

At most one of the two elements indicated by the same row index number in any two columns of the matrix M1, one element indicating the shift size of the unit array cyclic shift;

Concrete example 7

In an embodiment of the present invention, the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and the A0 consecutive bit blocks respectively correspond to column index numbers of the basic matrix to form a set. T0, the A0 is any integer from 0 to 3. In the basic matrix, all element values in the set T0 are composed of all elements indicated by the column index number and the row index number 0 to (mb'-1). Mb' is a matrix M0 of row A0, which is an integer greater than 0 and less than mb.

In another embodiment of the present invention, the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, and the A2 consecutive bit blocks respectively correspond to the base matrix Column index number constitutes a set T1, the A2 being any integer from 0 to mb; In the base matrix, all the elements in the set T0 as the column index number and all the elements indicated by the row index number 0 to (mb'-1) constitute the matrix M1 of the mb' row A2 column, the mb' is greater than 0 is an integer less than mb;

The matrix M0 and the matrix M1 form a matrix M2=[M0 M1] of the mb' row (A0+A2) column, wherein the matrix M2 has at least one of the following conditions:

One of the rows in the matrix M2 whose row weight is equal to 1 indicates the column index number of the shift size element of the unit array cyclic shift is an integer from 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, the column index number of at least one element indicating the shift size of the cyclic shift of the unit array in any one row is an integer of 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, at least one row has a row weight equal to 2, wherein each of the at least one row has 2 column index numbers indicating the shift size of the unit array cyclic shift is 0 to (A0-1 An integer, A0 is an integer greater than one;

In the matrix M2, at least one row of rows is greater than or equal to A0, wherein all of the first A0 of the column index numbers of the elements of the shift size indicating the cyclic shift of the unit array in each row of the at least one row are 0 to An integer of (A0-1), A0 is an integer greater than zero.

Based on the above embodiments, the present disclosure also proposes a quasi-cyclic LDPC code data processing method.

As shown in FIG. 5, a quasi-cyclic LDPC code data processing method in the embodiment of the present disclosure includes steps S501 to S503.

S501. Acquire the base matrix and a spreading factor value from a base matrix and a set of spreading factor values used in pre-stored quasi-cyclic LDPC encoding; the basic matrix is a matrix of mb rows and nb columns, and the basis is An element for indicating an all-zero square matrix and an element for indicating a shift size of the unit array cyclic shift are included in the matrix, each of the set of spread factor values being used to indicate the all-zero square The number of rows of the array or the unit array, each of the expansion factor values being an integer greater than 0, the mb being an integer greater than 0, and the nb being an integer greater than mb.

S502. The information to be encoded is to be based on the obtained parameters of the basic matrix and the expansion factor value. The sequence is subjected to quasi-cyclic LDPC coding to obtain an LDPC mother codeword sequence.

S503. Select a rate matching output sequence from the LDPC mother codeword sequence.

The column weight of the base matrix includes at least 3/4 elements of the following set: {17, 5, 16, 4, 4, 4, 15, 4, 4, 10, 4, 3, 1, 1, 1, 1 , 1,1,1,1,1,1,1,1,1}.

In an embodiment of the present disclosure, in the basic matrix, an element for indicating an all-zero square matrix is represented by a '-1', and an element for indicating a shift size of the unit array cyclic shift is greater than or equal to 0. And less than an integer representation of the spreading factor value; at least 80% of the elements of the base matrix are identical to the following reference base matrix Hb:

In an embodiment of the present disclosure, the shift in the base matrix is used to indicate a cyclic shift of the unit array. The position of the bit-sized element is at least 80% of the element position is the same as the position of '1' in the reference base matrix Hb' below:

In an embodiment of the present disclosure, the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and the A0 consecutive bit blocks respectively correspond to A0 column index numbers of the base matrix. The A0 column index numbers constitute a set T0, and the A0 is any integer of 0 to 3; wherein the element value and the element number of the set T0 are determined by at least one of the following parameters:

Specifically, if the transport block size TBS is less than a set positive integer TBS0, the A0 is any element value in the set G1; if the transport block size TBS is greater than or equal to a set positive integer TBS0, the A0 a value of any element in the set G2; wherein the element values in the set G1 and the set G2 are respectively integers of 0 to 3, and the intersection of the set G1 and the set G2 is an empty set; Correct The value of the integer TBS0 ranges from greater than 256 to less than 4096.

Specifically, if the code rate R is greater than a set positive real number R', the A0 is any element value in the set G3; if the code rate R is less than or equal to the set positive real number R', the A0 a value of any element in the set G4; the positive real number R' is a real number greater than 0 and less than 1, the code rate R being a real number greater than 0 and less than 1, the set G3 neutralizing elements in the set G4 The values are integers from 0 to 3, respectively, and the intersection of the set G3 and the set G4 is an empty set.

Specifically, if the frequency band is greater than a set positive real number FB0, the A0 is a value of any element in the set G5;

If the frequency band is less than or equal to the set positive real number FB0, the A0 is any element value in the set G6;

The element values in the set G5 and the set G6 are respectively integers of 0 to 3, and the intersection of the set G5 and the set G6 is an empty set.

Specifically, if the channel type is a control channel, the A0 is any element value in the set G7; if the channel type is a data channel, the A0 is any element value in the set G8; The element value in the set G7 and the set G8 is an integer of 0 to 3, and the intersection of the set G7 and the set G8 is an empty set.

Specifically, if the data transmission direction is an uplink data transmission, the A0 is any element value in the set G9; if the data transmission direction is a downlink data transmission, the A0 is any element value in the set G10. Wherein, the element value in the set G9 and the set G10 is an integer of 0 to 3, and the intersection of the set G9 and the set G10 is an empty set.

Specifically, if the bandwidth is greater than the positive real number BW0, the A0 is any element value in the set G11; if the frequency band is less than or equal to the positive real number BW0, the A0 is any element value in the set G12; The element value in the set G11 and the set G12 is an integer of 0 to 3, and the intersection of the set G11 and the set G12 is an empty set.

Optionally, when the values of the parameters are not the same, the set T0 is different.

In an embodiment of the present disclosure, the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the base matrix A2 column index numbers, the A2 column index numbers constitute a set T1, and the A2 is Any integer from 0 to mb; wherein the element value and the number of elements of the set T1 are determined by at least one of the following parameters:

Optionally, when the values of the parameters are not the same, the set T1 is different.

In an embodiment of the present disclosure, the selecting a rate matching output sequence from the LDPC mother codeword sequence includes:

Interleaving the LDPC coded output sequence according to the interleaving pattern InP, and then sequentially selecting the rate matching output sequence; the interleaving pattern InP is in units of Z bits of consecutive bit blocks, and the interleaving pattern InP includes nb pieces An integer that is unequal from 0 to (nb-1); wherein the element value and the number of elements of the interleaving pattern InP are determined by at least one of the following parameters:

In an embodiment of the present disclosure, when the values of the parameters are not the same, the interleaving pattern InP is different.

In an embodiment of the present disclosure, the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and the A0 consecutive bit blocks respectively correspond to A0 column index numbers of the base matrix. The A0 column index numbers constitute a set T0, and the A0 is any integer from 0 to 3.

The matrix M0 includes at least A3 non-full lines, and the non-full lines means at least one of the lines is used for Indicating an all zero square matrix element; the A3 is equal to 2 or 3;

The matrix M0 includes at least one row having a row weight equal to 1;

The matrix M0 includes at least one row having a row weight equal to A0.

In an embodiment of the present disclosure, the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the base matrix A2 column index numbers, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb.

In still another embodiment of the present disclosure, if the code rate R of the rate matched LDPC code sequence is less than or equal to the set threshold R0, the system column number kb of the basic matrix ranges from [set threshold kb0] Setting a threshold kb1]; if the code rate R of the rate-matched LDPC code sequence is greater than a set threshold R0 and less than or equal to a set threshold R1, the system matrix number kb of the basic matrix ranges from [Setting The threshold kb2 sets a threshold kb3]; if the rate R of the rate matched LDPC code sequence is greater than R1, the system column number kb of the basic matrix ranges from [set threshold kb1 set threshold kb4]; The set threshold R0 is a real number greater than 0 and less than 1, the set threshold R1 is a real number greater than the set threshold R0 being less than 1, and the set threshold kb0 is an integer greater than 0 and less than kb. The set threshold kb1 is an integer greater than the set threshold kb0 and less than kb, and the set threshold kb2 is an integer greater than the set threshold kb0 and less than the set threshold kb1, the set threshold kb3 Is greater than the set threshold kb1 and less than the set threshold kb4, the set threshold kb4 is large The integer of the threshold kb3 is set.

In still another embodiment of the present disclosure, the setting threshold R0=2/5, the setting threshold R1=2/3, the setting threshold kb0=8, and the setting threshold kb1=12, The set threshold kb2=10, the set threshold kb3=14, and the set threshold kb4=16.

Specifically, the code rate R of the rate matched LDPC code sequence is a real number greater than or equal to 8/9 and less than 1.

In still another embodiment of the present disclosure, if the code rate R of the rate matched LDPC code sequence is greater than R2, the LDPC coded output sequence is interleaved, and then the N bit rate matching speed is selected. The rate matches the output sequence; wherein R2 is a real number greater than 5/6 less than 1, and the code rate R of the rate matched LDPC code sequence is a real number greater than 0 and less than one.

Optionally, the method further includes: filling the source information sequence with the dummy bit to obtain a sequence of information to be encoded, where the location of the padding dummy bit is at the front of the source information sequence.

Optionally, the position of the A0×Z bit is located at the end of the sequence of information to be encoded.

Optionally, the method further includes: interleaving the LDPC coded output sequence by a reordering number, and then selecting an N bit rate matching output sequence. The method for determining the reordering number includes: rearranging in units of Z consecutive bit blocks, the sequence numbers of the Z consecutive bit blocks are one-to-one corresponding to column index numbers of the basic matrix, and are consecutive to the A0 The column index number of the base matrix corresponding to the bit block is located at the end of the reordering number.

The method in the present disclosure obtains a rate matching output sequence in a rate matching process after quasi-cyclic LDPC encoding, wherein the rate matching output sequence does not include A0 consecutive bit blocks in the information sequence to be encoded, and/or does not include an LDPC coded output sequence. A2 consecutive bit blocks in the check bits, such that the rate match output sequence does not include A0 consecutive bit blocks in the sequence of information to be encoded, and/or the rate match output sequence does not include the LDPC coded output A2 consecutive bit blocks in the check bits of the sequence, and defining A0 and A2 according to different parameter conditions, and constraining the position of A0 consecutive bit blocks in the information sequence to be encoded and A2 consecutive bit blocks in the LDPC The position in the encoded output sequence improves the performance of the quasi-cyclic LDPC code in different environments or scenarios to adapt to various code length and code rate performance requirements, thereby supporting flexible code length and code rate, and maintaining good performance.

Based on the methods in the above embodiments, the present disclosure also proposes a quasi-cyclic LDPC code data processing apparatus.

A quasi-cyclic LDPC code data processing apparatus according to an embodiment of the present disclosure includes a processor and a storage device, wherein the storage device stores a base matrix and a set of expansion factor values used for quasi-cyclic LDPC encoding, and stores multiple An instruction to implement an LDPC code data processing method, the processor executing the plurality of instructions to:

Obtaining the base matrix and an expansion factor value from the storage module, based on the obtained Base matrix and spreading factor value, quasi-cyclic LDPC encoding of the sequence of information to be encoded, to obtain an LDPC coded output sequence; the base matrix is a matrix of mb rows and nb columns, and the base matrix includes a matrix for indicating all zero squares An element and an element for indicating a shift size of the unit array cyclic shift, the spread factor value being used to indicate the number of rows of the all-zero square matrix or the unit matrix, the expansion factor value being an integer greater than 0 , the mb is an integer greater than 0, and the nb is an integer greater than mb;

In an embodiment of the present disclosure, the row weight of the base matrix includes at least 3/4 elements of the following set: {8, 9, 9, 8, 5, 6, 5, 6, 6, 6, 5, 6, 4, 5, 5, 5, 5}; and/or, the column weight of the base matrix comprises at least 3/4 elements of the following set: {17, 5, 16, 4, 4, 4, 15, 4, 4, 10, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}.

The row weight refers to the number of elements used to indicate the shift size of the unit array cyclic shift when the row index is fixed in the base matrix and the column index is 0 to (nb-1); the column weight refers to the basis The number of elements for indicating the shift size of the unit array cyclic shift when the column index is fixed in the matrix and the row index is 0 to (mb-1).

In an embodiment of the present disclosure, the position of the element in the base matrix indicating the shift size of the unit array cyclic shift has at least 80% of the element position and the position of the following reference base matrix Hb' '1' the same:

In an embodiment of the present disclosure, the rate matching module is further configured to interleave the LDPC coded output sequence according to an interlace pattern InP, and then sequentially select the rate matching output sequence; the interlace pattern InP is Z The interleave pattern InP includes nb integers ranging from 0 to (nb-1) unequal to each other; wherein the specific element value and the specific element number of the interleaving pattern InP are at least one of the following The parameters are determined:

Specifically, when the values of the parameters are not the same, the interleaving pattern InP is different.

The matrix M0 includes at least A3 non-full lines, and the non-full line means that at least one line is included to indicate an all-zero square matrix element; the A3 is equal to 2 or 3;

The matrix M0 includes at least one row having a row weight equal to 1;

The matrix M0 includes at least one row having a row weight equal to A0.

Any one of the two elements indicated by the same row index number in any two columns of the matrix M1 has at most one element indicating the shift size of the unit array cyclic shift;

The matrix M0 and the matrix M1 form a matrix M2=[M0 of the mb' row (A0+A2) column M1], wherein the matrix M2 has at least one of the following conditions:

In the matrix M2, at least one row has a row weight equal to 2, wherein each of the at least one row indicates a column index number of the shift size element of the unit array cyclic shift is 0 to (A0-1) An integer, A0 is an integer greater than one.

In the present disclosure, after quasi-cyclic LDPC encoding, a rate matching output sequence is obtained in a rate matching process, wherein the rate matching output sequence does not select A0 consecutive bit blocks in the information sequence to be encoded, and/or does not include an LDPC coded output sequence. A2 consecutive bit blocks in the check bits, such that the rate matching output sequence does not include A0 consecutive bit blocks in the sequence of information to be encoded, and/or the rate matching output sequence does not include the LDPC coded output sequence A2 consecutive bit blocks in the check bits, and defining A0 and A2 according to different parameter conditions, and constraining the position of A0 consecutive bit blocks in the information sequence to be encoded and A2 consecutive bit blocks in LDPC coding The position in the output sequence improves the performance of the quasi-cyclic LDPC code in different environments or scenarios to adapt to various code length and code rate performance requirements, thereby supporting flexible code length and code rate, and maintaining good performance.

Based on the method in the above embodiments, an embodiment of the present disclosure provides a computer readable storage medium storing computer executable instructions configured to perform the above method.

Although the present application describes specific examples of the present disclosure, those skilled in the art can devise variations of the present disclosure.

Various modifications of the present disclosure can be made by those skilled in the art in light of the technical idea of the present disclosure, which still fall within the protection scope of the present disclosure.

Industrial applicability

The apparatus and method in the present disclosure effectively solve the problem of lack of flexibility in the LDPC encoding and decoding process in the related art, support flexible code length and code rate, and maintain good performance.

Claims

A quasi-cyclic LDPC code data processing device includes:

a storage module configured to store a base matrix and a set of boost values used in quasi-cyclic LDPC coding; the base matrix is a matrix of mb rows and nb columns, the base matrix includes elements for indicating an all-zero square matrix An element for indicating a shift size of the unit array cyclic shift, each of the set of lift value values for indicating the number of rows of the all zero square matrix or the unit array, each of the The boost value is an integer greater than 0, the mb represents an integer greater than 0, and the nb represents an integer greater than mb;

The encoding module is configured to obtain the basic matrix and a lifting value from the storage module, perform quasi-cyclic LDPC encoding on the sequence of the information to be encoded based on the obtained basic matrix and the lifting value, to obtain an LDPC encoded output sequence;

A rate matching module is configured to select a rate matching output sequence from the LDPC coded output sequence.
The apparatus of claim 1, wherein the row weight of the base matrix comprises at least 3/4 elements of the following set: {8, 9, 9, 8, 5, 6, 5, 6, 6, 6, 5,6,4,5,5,5,5}; and/or,

The column weight of the base matrix includes at least 3/4 elements of the following set: {4, 15, 4, 4, 4, 16, 5, 17, 4, 10, 4, 3, 1, 1, 1, 1 ,1,1};

The row weight refers to the number of elements used to indicate the shift size of the unit array cyclic shift when the row index is fixed in the base matrix and the column index is 0 to (nb-1);

The column weight refers to the number of elements for indicating the shift size of the unit array cyclic shift when the column index in the base matrix is fixed and the row index is 0 to (mb-1).
The apparatus according to claim 1, wherein in the basic matrix, an element for indicating an all-zero square matrix is represented by a '-1', and an element for indicating a shift size of the unit array cyclic shift is greater than or An integer representation equal to 0 and less than the boost value; at least 80% of the elements of the base matrix are identical to the following reference base matrix Hb:
The apparatus according to claim 1, wherein a position of an element of the base matrix indicating a shift size of the unit array cyclic shift has at least 80% of an element position and a '1' in the following reference base matrix Hb' The same location:
The apparatus according to claim 4, wherein the base matrix is subjected to row permutation and/or column permutation, and an element of the new base matrix for indicating a shift size of the unit array cyclic shift has at least 80% of elements. The position is the same as the position of '1' in the reference base matrix Hb'.
The apparatus according to claim 1, wherein said rate matching output sequence does not include A0 consecutive bit blocks in said sequence of information to be encoded, said A0 consecutive bit blocks respectively corresponding to A0 columns of said base matrix An index number, the A0 column index numbers constitute a set T0, and the A0 is 0 to 3 An arbitrary integer; wherein the element value and the number of elements of the set T0 are determined by at least one of the following parameters:

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The apparatus of claim 6, wherein the set T0 is different when values of the parameters are not the same.
The apparatus of claim 1, wherein the rate matching output sequence does not include A2 consecutive bit blocks in parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the basis A2 column index numbers of the matrix, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb; wherein the element value and the number of elements of the set T1 are determined by at least one of the following parameters :

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The apparatus of claim 8, wherein the set T1 is different when values of the parameters are not the same.
The apparatus according to claim 1, wherein said rate matching module is further configured to interleave said LDPC coded output sequence in an interleaving pattern InP, and then sequentially select said rate matching output sequence; said interleaving pattern InP In the unit of consecutive bits of Z bits, the interleaving pattern InP includes nb integers from 0 to (nb-1) which are not equal to each other; wherein the element value and the number of elements of the interleaving pattern InP are at least one of the following The parameters are determined:

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The apparatus of claim 10, wherein the interleaving pattern InP is different when values of the parameters are not the same.
The apparatus of claim 1 wherein said rate matching output sequence does not comprise said A0 consecutive bit blocks in the information sequence to be encoded, the A0 consecutive bit blocks respectively corresponding to A0 column index numbers of the base matrix, the A0 column index numbers forming a set T0, and the A0 is 0 to 3 Any integer in it;

In the basic matrix, all element values in the set T0 are used as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M0 of the mb' row A0 column, Mb' is an integer greater than 0 less than or equal to mb, and the matrix M0 has at least one of the following conditions:

The difference between the column weights of any two columns in the matrix M0 is not more than 1;

An element of any one of the columns of the matrix M0 includes at least one element for indicating an all-zero square matrix;

The matrix M0 includes at least A3 non-full lines, and the non-full line means that the line includes at least one element for indicating an all-zero square matrix; the A3 is equal to 2 or 3;

The matrix M0 includes at least one row having a row weight equal to 1;

The matrix M0 includes at least one row having a row weight equal to A0.
The apparatus of claim 1, wherein the rate matching output sequence does not include A2 consecutive bit blocks in parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the basis A2 column index numbers of the matrix, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb;

In the basic matrix, all element values in the set T1 are taken as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M1 of the mb' row A2 column, Mb' is an integer greater than 0 less than or equal to mb, and the matrix M1 has at least one of the following conditions:

At most one of the two elements indicated by the same row index number in any two columns of the matrix M1, one element indicating the shift size of the unit array cyclic shift;

Any one of the rows of the matrix M1 includes at most 2 elements indicating the shift size of the cyclic shift of the unit array.
The apparatus according to claim 1, wherein said rate matching output sequence does not include A0 consecutive bit blocks in said sequence of information to be encoded, said A0 consecutive bit blocks respectively corresponding to A0 of said base matrix Column index number, the A0 column index number constitutes a set T0, and the A0 is any integer from 0 to 3;

In the basic matrix, all element values in the set T0 are used as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M0 of the mb' row A0 column, Mb' is an integer greater than 0 and less than mb;

The rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, and the A2 consecutive bit blocks respectively correspond to A2 column index numbers of the base matrix, the A2 The column index numbers constitute a set T1, and the A2 is any integer from 0 to mb;

In the basic matrix, all element values in the set T1 are taken as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M1 of the mb' row A2 column, Mb' is an integer greater than 0 less than or equal to mb;

The matrix M0 and the matrix M1 form a matrix M2=[M0M1] of the mb' row (A0+A2) column, wherein the matrix M2 has at least one of the following conditions:

One of the rows in the matrix M2 whose row weight is equal to 1 indicates the column index number of the shift size element of the unit array cyclic shift is an integer from 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, the column index number of at least one element indicating the shift size of the cyclic shift of the unit array in any one row is an integer of 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, the row weight of at least one row is equal to 2, wherein the column index numbers of the elements of the shift size indicating the cyclic shift of the unit array in each of the at least one row are 0 to (A0-1) An integer, A0 is an integer greater than one;

In the matrix M2, at least one row of rows is greater than or equal to A0, wherein all of the first A0 of the column index numbers of the elements of the shift size indicating the cyclic shift of the unit array in each row of the at least one row are 0 to An integer of (A0-1), A0 is an integer greater than zero.
A quasi-cyclic LDPC code data processing apparatus, wherein the apparatus comprises a processor and a storage device, wherein the storage device stores a base matrix and a set of lifting values used for quasi-cyclic LDPC encoding, and stores a plurality of instructions To implement an LDPC code data processing method, the processor executes the plurality of instructions to:

Acquiring the basic matrix and a lifting value from the storage module, performing quasi-cyclic LDPC encoding on the sequence of information to be encoded based on the obtained basic matrix and the lifting value, to obtain an LDPC encoding output sequence; a matrix of mb rows nb columns, the base matrix including elements for indicating an all-zero square matrix and elements for indicating a shift size of the unit array cyclic shift, the boost value for indicating the all zeros a square matrix or a number of rows of the unit array, the boost value is an integer greater than 0, the mb is an integer greater than 0, and the nb is an integer greater than mb;

From the LDPC coded output sequence, a rate matching output sequence is selected.
The apparatus of claim 15, wherein the row weight of the base matrix comprises the following set At least 3/4 elements: {8,9,9,8,5,6,5,6,6,6,5,6,4,5,5,5,5}; and/or,

The column weight of the base matrix includes at least 3/4 elements of the following set: {17, 5, 16, 4, 4, 4, 15, 4, 4, 10, 4, 3, 1, 1, 1, 1 ,1,1,1,1,1,1,1,1,1};

The row weight refers to the number of elements used to indicate the shift size of the unit array cyclic shift when the row index is fixed in the base matrix and the column index is 0 to (nb-1);

The column weight refers to the number of elements for indicating the shift size of the unit array cyclic shift when the column index in the base matrix is fixed and the row index is 0 to (mb-1).
The apparatus according to claim 15, wherein in the base matrix, an element for indicating an all-zero square matrix is represented by a '-1', and an element for indicating a shift size of the unit array cyclic shift is greater than or An integer representation equal to 0 and less than the boost value; at least 80% of the elements of the base matrix are identical to the following reference base matrix Hb:
The apparatus according to claim 15, wherein a position of an element for indicating a shift size of the unit array cyclic shift in the base matrix has at least 80% of an element position and a '1' in the following reference base matrix Hb' The same location:
The apparatus according to claim 18, wherein said base matrix is subjected to row permutation and/or column permutation, and an element of said new base matrix for indicating a shift size of said unit array cyclic shift has at least 80% of elements The position is the same as the position of '1' in the reference base matrix Hb'.
The apparatus according to claim 15, wherein said rate matching output sequence does not include A0 consecutive bit blocks in said sequence of information to be encoded, said A0 consecutive bit blocks respectively corresponding to A0 columns of said base matrix The index number, the A0 column index number constitutes a set T0, and the A0 is any integer of 0 to 3; wherein the element value and the number of elements of the set T0 are determined by at least one of the following parameters:

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The apparatus of claim 20, wherein the set T0 is different when values of the parameters are not the same.
The apparatus of claim 15, wherein the rate matching output sequence does not include A2 consecutive bit blocks in parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the basis A2 column index numbers of the matrix, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb; wherein the element value and the number of elements of the set T1 are determined by at least one of the following parameters :

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The apparatus of claim 22, wherein the set T1 is different when values of the parameters are not the same.
The apparatus according to claim 15, wherein said rate matching module is further configured to interleave said LDPC coded output sequence in an interleaving pattern InP, and then sequentially select said rate matching output sequence; said interleaving pattern InP In the unit of consecutive bits of Z bits, the interleaving pattern InP includes nb integers from 0 to (nb-1) which are not equal to each other; wherein the element value and the number of elements of the interleaving pattern InP are at least one of the following The parameters are determined:

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The apparatus of claim 24, wherein the interleaving pattern InP is different when values of the parameters are not the same.
The apparatus according to claim 15, wherein said rate matching output sequence does not include A0 consecutive bit blocks in said sequence of information to be encoded, said A0 consecutive bit blocks respectively corresponding to A0 columns of said base matrix An index number, the A0 column index numbers constitute a set T0, and the A0 is any integer from 0 to 3;

In the basic matrix, all element values in the set T0 are used as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M0 of the mb' row A0 column, Mb' is an integer greater than 0 less than or equal to mb, and the matrix M0 has at least one of the following conditions:

The difference between the column weights of any two columns in the matrix M0 is not more than 1;

An element of any one of the columns of the matrix M0 includes at least one element for indicating an all-zero square matrix;

The matrix M0 includes at least A3 non-full lines, and the non-full line means that the line includes at least one element for indicating an all-zero square matrix; the A3 is equal to 2 or 3;

The matrix M0 includes at least one row having a row weight equal to 1;

The matrix M0 includes at least one row having a row weight equal to A0.
The apparatus of claim 15, wherein the rate matching output sequence does not include A2 consecutive bit blocks in parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the basis A2 column index numbers of the matrix, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb;

In the basic matrix, all element values in the set T1 are taken as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M1 of the mb' row A2 column, Mb' is an integer greater than 0 less than or equal to mb, and the matrix M1 has at least one of the following conditions:

At most one of the two elements indicated by the same row index number in any two columns of the matrix M1, one element indicating the shift size of the unit array cyclic shift;

Any one of the rows of the matrix M1 includes at most 2 elements indicating the shift size of the cyclic shift of the unit array.
The apparatus according to claim 15, wherein said rate matching output sequence does not include A0 consecutive bit blocks in said sequence of information to be encoded, said A0 consecutive bit blocks respectively corresponding to A0 of said base matrix Column index number, the A0 column index number constitutes a set T0, and the A0 is any integer from 0 to 3;

In the basic matrix, all element values in the set T0 are used as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M0 of the mb' row A0 column, Mb' is an integer greater than 0 and less than mb;

The rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, and the A2 consecutive bit blocks respectively correspond to A2 column index numbers of the base matrix, the A2 The column index numbers constitute a set T1, and the A2 is any integer from 0 to mb;

In the basic matrix, all element values in the set T1 are taken as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M1 of the mb' row A2 column, Mb' is an integer greater than 0 less than or equal to mb;

The matrix M0 and the matrix M1 form a matrix M2=[M0M1] of the mb' row (A0+A2) column, wherein the matrix M2 has at least one of the following conditions:

One of the rows in the matrix M2 whose row weight is equal to 1 indicates the column index number of the shift size element of the unit array cyclic shift is an integer from 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, the column index number of at least one element indicating the shift size of the cyclic shift of the unit array in any row one is an integer of 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, at least one row has a row weight equal to 2, wherein each row of the at least one row of the row indicates that the column index number of the element of the shift size of the unit array cyclic shift is 0 to (A0-1 An integer, A0 is an integer greater than one;

In the matrix M2, at least one row of rows is greater than or equal to A0, wherein all of the first A0 of the column index numbers of the elements of the shift size indicating the cyclic shift of the unit array in each row of the at least one row are 0 to An integer of (A0-1), A0 is an integer greater than zero.
A quasi-cyclic LDPC code data processing method, wherein the method comprises:

Acquiring the basic matrix and a lifting value from a base matrix and a set of lifting values used in pre-stored quasi-cyclic LDPC encoding; the basic matrix is a matrix of mb rows and nb columns, and the basic matrix includes And an element for indicating an all-zero square matrix and an element for indicating a shift size of the unit array cyclic shift, wherein the boost value is used to indicate the number of rows of the all-zero square matrix or the unit matrix, the boost value Is an integer greater than 0, the mb is an integer greater than 0, and the nb is an integer greater than mb;

Performing a quasi-cyclic LDPC encoding on the encoded information sequence based on the obtained basic matrix parameter and the lifting value, to obtain an LDPC mother codeword sequence;

From the LDPC mother codeword sequence, a rate matching output sequence is selected.
The method of claim 29, wherein the row weight of the base matrix comprises at least 3/4 elements of the following set: {8,9,9,8,5,6,5,6,6,6, 5,6,4,5,5,5,5}; and/or,

The column weight of the base matrix includes at least 3/4 elements of the following set: {17, 5, 16, 4, 4, 4, 15, 4, 4, 10, 4, 3, 1, 1, 1, 1 ,1,1,1,1,1,1,1,1,1};

The row weight refers to the number of elements used to indicate the shift size of the unit array cyclic shift when the row index is fixed in the base matrix and the column index is 0 to (nb-1);

The column weight refers to the number of elements for indicating the shift size of the unit array cyclic shift when the column index in the base matrix is fixed and the row index is 0 to (mb-1).
The method according to claim 29, wherein in the base matrix, an element for indicating an all-zero square matrix is represented by a '-1', and an element for indicating a shift size of the unit array cyclic shift is greater than or An integer representation equal to 0 and less than the boost value; at least 80% of the elements of the base matrix are identical to the following reference base matrix Hb:
The method of claim 29, wherein the position of the element in the base matrix indicating the shift size of the unit array cyclic shift has at least 80% of the element position and the following reference base matrix Hb' in the '1' The same location:
The method according to claim 32, wherein the position of the element for indicating the shift size of the unit array cyclic shift in the new base matrix obtained by the row matrix after row replacement and/or column permutation is at least 80% The position of the element is the same as the position of '1' in the reference base matrix Hb'.
The method according to claim 29, wherein said rate matching output sequence does not include A0 consecutive bit blocks in said sequence of information to be encoded, said A0 consecutive bit blocks respectively corresponding to A0 columns of said base matrix The index number, the A0 column index number constitutes a set T0, and the A0 is any integer of 0 to 3; wherein the element value and the number of elements of the set T0 are determined by at least one of the following parameters:

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The method of claim 34, wherein the set T0 is different when the values of the parameters are not the same.
The method of claim 29, wherein the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the basis A2 column index numbers of the matrix, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb; wherein the element value and the number of elements of the set T1 are determined by at least one of the following parameters :

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The method of claim 36, wherein the set T1 is different when the values of the parameters are not the same.
The method of claim 29, wherein said from said LDPC mother codeword sequence, Select the rate matching output sequence, including:

Interleaving the LDPC coded output sequence according to the interleaving pattern InP, and then sequentially selecting the rate matching output sequence; the interleaving pattern InP is in units of Z bits of consecutive bit blocks, and the interleaving pattern InP includes nb pieces An integer that is unequal from 0 to (nb-1); wherein the element value and the number of elements of the interleaving pattern InP are determined by at least one of the following parameters:

Combination of transport block size TBS, application scenario, user UE type, frequency band, code rate R, transport block size TBS and code rate R, channel type, data transmission direction, TBS index number and resource unit number NRB, modulation and coding scheme Combination of MCS index number and resource unit number NRB, combination of code rate R and resource unit number NRB, bandwidth size, in-band and out-of-band indication.
The method of claim 38, wherein the interleaving pattern InP is different when the values of the parameters are not the same.
The method according to claim 29, wherein said rate matching output sequence does not include A0 consecutive bit blocks in said sequence of information to be encoded, said A0 consecutive bit blocks respectively corresponding to A0 columns of said base matrix An index number, the A0 column index numbers constitute a set T0, and the A0 is any integer from 0 to 3;

In the basic matrix, all element values in the set T0 are used as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M0 of the mb' row A0 column, Mb' is an integer greater than 0 less than or equal to mb, and the matrix M0 has at least one of the following conditions:

The difference between the column weights of any two columns in the matrix M0 is not more than 1;

An element of any one of the columns of the matrix M0 includes at least one element for indicating an all-zero square matrix;

The matrix M0 includes at least A3 non-full lines, and the non-full line means that the line includes at least one element for indicating an all-zero square matrix; the A3 is equal to 2 or 3;

The matrix M0 includes at least one row having a row weight equal to 1;

The matrix M0 includes at least one row having a row weight equal to A0.
The method of claim 29, wherein the rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, the A2 consecutive bit blocks respectively corresponding to the basis A2 column index numbers of the matrix, the A2 column index numbers constitute a set T1, and the A2 is any integer from 0 to mb;

In the basic matrix, all element values in the set T1 are taken as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M1 of the mb' row A2 column, Mb' is an integer greater than 0 less than or equal to mb, and the matrix M1 has at least one of the following conditions:

At most one of the two elements indicated by the same row index number in any two columns of the matrix M1, one element indicating the shift size of the unit array cyclic shift;

Any one of the rows of the matrix M1 includes at most 2 elements indicating the shift size of the cyclic shift of the unit array.
The method according to claim 29, wherein said rate matching output sequence does not include A0 consecutive bit blocks in said sequence of information to be encoded, said A0 consecutive bit blocks respectively corresponding to A0 of said base matrix Column index number, the A0 column index number constitutes a set T0, and the A0 is any integer from 0 to 3;

In the basic matrix, all element values in the set T0 are used as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M0 of the mb' row A0 column, Mb' is an integer greater than 0 and less than mb;

The rate matching output sequence does not include A2 consecutive bit blocks in the parity bits of the LDPC coded output sequence, and the A2 consecutive bit blocks respectively correspond to A2 column index numbers of the base matrix, the A2 The column index numbers constitute a set T1, and the A2 is any integer from 0 to mb;

In the basic matrix, all element values in the set T1 are taken as a column index number and all elements indicated by 0 to (mb'-1) as a row index number constitute a matrix M1 of the mb' row A2 column, Mb' is an integer greater than 0 less than or equal to mb;

The matrix M0 and the matrix M1 form a matrix M2=[M0M1] of the mb' row (A0+A2) column, wherein the matrix M2 has at least one of the following conditions:

One of the rows in the matrix M2 whose row weight is equal to 1 indicates the column index number of the shift size element of the unit array cyclic shift is an integer from 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, the column index number of at least one element indicating the shift size of the unit array cyclic shift in any row is an integer from 0 to (A0-1), and A0 is an integer greater than 0;

In the matrix M2, the row weight of at least one row is equal to 2, wherein the column index numbers of the elements of the shift size indicating the cyclic shift of the unit array in each of the at least one row are 0 to (A0-1) Integer, A0 is an integer greater than one;

In the matrix M2, at least one row of rows is greater than or equal to A0, wherein all of the first A0 of the column index numbers of the elements of the shift size indicating the cyclic shift of the unit array in each row of the at least one row are 0 to An integer of (A0-1), A0 is an integer greater than zero.
A computer readable storage medium storing computer executable instructions configured to perform the method of any one of claims 29-42.