WO2018103274A1

WO2018103274A1 - Soc chip having tamper-resistant mechanism for internal data of memory, and method therefor

Info

Publication number: WO2018103274A1
Application number: PCT/CN2017/085623
Authority: WO
Inventors: 王健; 杨灿华
Original assignee: 上海新微技术研发中心有限公司
Priority date: 2016-12-09
Filing date: 2017-05-24
Publication date: 2018-06-14
Also published as: CN108229207B; CN108229207A

Abstract

Provided are an SOC chip having a tamper-resistant mechanism for internal data of a memory, and a method, the chip comprising: a first storage unit for storing sensitive system data, the maintenance thereof being the responsibility of a chip production provider; a second storage unit for storing user data and a program, the maintenance thereof being the responsibility of a user; a microprocessor for accessing the first storage unit and second storage unit; an access control unit which is connected between the microprocessor and the first storage unit and between the microprocessor and the second storage unit, and which is used for completing control over a time sequence of the microprocessor accessing the first storage unit and second storage unit; and a characteristic value unit, which is connected to the microprocessor, and is used for calculating a characteristic value of a user code in the second storage unit, and comparing same to a feature value pre-stored in the first storage unit so as to determine whether the user code has been illegally tampered with. The invention, by means of a characteristic value verification circuit which has been powered on, can detect whether an NVM memory has accidentally lost data, improving the reliability of a chip.

Description

SOC chip and method with memory internal data anti-tamper mechanism

Technical field

The invention belongs to the field of system on chip, and relates to a SOC chip and method having a memory internal data anti-tampering mechanism.

Background technique

System on Chip (SOC), in a narrow sense, is the core of information system integration, is the integration of key components of the system on a chip; in a broad sense, SOC is a micro-mini system, which will Microprocessors, analog IP cores, digital IP cores, and memory (or off-chip memory control interfaces) are integrated on a single chip and are typically custom-tailored or standard-oriented for specific applications.

The Microcontroller Unit (MCU) is internally integrated with Non-Volatile Memory (NVM) for storing user programs and data. As the use of MCUs becomes more and more popular, the requirements for data security within MCUs are becoming higher and higher. How to protect the data in NVM non-volatile memory becomes especially important.

User code stored in the MVM's internal NVM memory is often an important component of an illegal attack, and the purpose of controlling the user's system is achieved by tampering with internal user code.

Similarly, under certain conditions (such as high temperature/high voltage limit conditions), NVM memory may also suffer from internal data loss or partial data bit tampering.

Therefore, how to provide a SOC chip and method with a memory internal data anti-tampering mechanism to improve chip security has become an important technical problem to be solved by those skilled in the art.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a SOC chip and method having a memory internal data tamper-proof mechanism for solving the problem of high security risk of the SOC chip in the prior art.

To achieve the above and other related objects, the present invention provides a SOC chip having a memory internal data tamper-proof mechanism, including:

a first storage unit for storing sensitive system data maintained by a chip production provider;

a second storage unit for storing user data and programs maintained by the user;

a microprocessor for accessing the first storage unit or the second storage unit;

An access control unit is connected between the microprocessor and the first storage unit and the second storage unit for completing timing control of the microprocessor accessing the first storage unit and the second storage unit;

An eigenvalue unit, coupled to the microprocessor, for calculating a feature value of the user code in the second storage unit, and comparing with a feature value pre-stored in the first storage unit to determine a user code Whether it has been illegally tampered with.

Optionally, the feature value unit is configured to generate an interrupt of the user code being illegally tampered to the microprocessor when it is determined to be illegally tampering.

Optionally, the microprocessor is arranged to reset the chip upon receiving the interrupt.

Optionally, the feature value unit includes a feature value calculation unit, a first latch, and a comparator; wherein:

The feature value calculation unit is connected between the microprocessor and the first latch, and configured to receive a user code read by the microprocessor from the second storage unit, and calculate the user code. a feature value, and inputting the calculated feature value into the first latch;

a first input of the comparator is coupled to the microprocessor, a second input of the comparator is coupled to an output of the first latch, an output of the comparator and the micro And a processor connection, configured to compare the feature value read by the microprocessor from the first storage unit with the feature value calculated by the feature value calculation unit.

Optionally, a second lock is further connected between the input end of the feature value calculation unit and the comparator And a register for powering up the comparator.

Optionally, the feature value pre-stored in the first storage unit is 128 bits, and the feature value calculated by the feature value unit according to the user code is 128 bits.

Optionally, the user code in the second storage unit is 32 bits.

Optionally, the first storage unit and the second storage unit are both non-volatile memories.

Optionally, the sensitive system data includes one or more of a bootloader, a user key, system storage space configuration information, a calibration value, and a chip unique identification code.

The present invention also provides a method for preventing a tampering mechanism of a data internal memory, which is applied to a SOC chip having a memory internal data tamper prevention mechanism according to any one of the preceding claims, the method comprising:

After the chip is powered on and the reset operation is completed, the first storage unit and the second storage unit are all accessible through the address space of the microprocessor;

The program is executed from the first storage unit, the microprocessor reads out the user code in the second storage unit to the feature value unit, and the feature value unit calculates a corresponding feature value;

After multiple iterations, the final 128-bit eigenvalue is obtained;

The feature value unit compares the calculated feature value with a 128-bit feature value stored in the first storage unit;

If the comparison result is consistent, jump to the user program area to execute the user program; if the comparison result is inconsistent, an interrupt is generated to the microprocessor;

After the microprocessor receives an interrupt of illegal tampering, the chip is reset.

As described above, the SOC chip and method having the memory internal data tamper-proof mechanism of the present invention has the following beneficial effects: the present invention uses different NVM memories to store system information and user code data respectively, and when the system is powered on, the user is checked first. Whether the code has been tampered with, if the verification is correct, the user program is executed. If the verification fails, the chip is reset. The feature value unit may be any general or private hash algorithm, which is difficult to crack. Through the feature value verification circuit after power-on, it is possible to detect whether the NVM memory accidentally loses data and improve the reliability of the chip.

DRAWINGS

FIG. 1 is a schematic structural view of a SOC chip having a memory internal data tamper-proof mechanism according to the present invention.

Fig. 2 is a circuit diagram showing the characteristic value unit.

3 is a flow chart showing a method of the internal data tamper prevention mechanism of the memory of the present invention.

Component label description

1 first storage unit

2 second storage unit

3 access control unit

4 microprocessor

5 eigenvalue unit

501 eigenvalue calculation unit

502 first latch

503 comparator

504 second latch

S1 to S6 steps

detailed description

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

Please refer to Figure 1 to Figure 3. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, instead of the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

The present invention provides a SOC chip having a memory internal data tamper-proof mechanism. Referring to FIG. 1, a schematic structural diagram of the SOC chip is shown, including a first storage unit 1, a second storage unit 2, an access control unit 3, and a micro processing. 4 and feature value unit 5.

Specifically, the first storage unit 1 is configured to store sensitive system data that is maintained by a chip production provider. As an example, the sensitive system data includes one or more of a bootloader, a user key, system storage space configuration information, a calibration value, and a chip unique identification code. In this embodiment, the first storage unit 1 stores 128-bit feature values.

The second storage unit 2 is used to store user data and programs that are maintained by the user. In this embodiment, a 32-bit user code is stored in the second storage unit 2.

In this embodiment, the first storage unit 1 and the second storage unit 2 both use a non-volatile memory (NVM). When the power is turned off, the stored data does not disappear. The invention separates sensitive data and common data into different memories, and is physically isolated, which is beneficial to increase the security of the chip.

The microprocessor 4 is used for read/write access to the first storage unit 1 or the second storage unit 2. The access control unit 3 is connected between the microprocessor 4 and the first storage unit 1 and the second storage unit 2 for completing the access of the microprocessor 4 to the first storage unit 1. Timing control of the second storage unit 2.

Specifically, the feature value unit 5 is connected to the microprocessor 4, and is configured to calculate a feature value of the user code in the second storage unit 2, and a feature value pre-stored in the first storage unit. Compare to determine if the user code has been illegally tampered with.

Specifically, the feature value unit 5 is set to generate an interruption of the user code being illegally tampered to the microprocessor 4 when it is determined to be illegally tampering. The microprocessor 4 is arranged to reset the chip upon receiving the interrupt.

As an example, a circuit configuration diagram of the feature value unit 5 is shown in FIG. 2, including a feature value calculation unit 501, a first latch 502, and a comparator 503;

The feature value calculation unit 501 is connected between the microprocessor 4 and the first latch 502 for receiving a user code read by the microprocessor 4 from the second storage unit 2, Calculating the feature value of the user code, and inputting the calculated feature value into the first latch 502;

The first input of the comparator 503 is connected to the microprocessor 4, the second input of the comparator 503 is connected to the output of the first latch 502, and the output of the comparator 503 The terminal is connected to the microprocessor 4 for comparing the feature value read by the microprocessor 4 from the first storage unit 1 with the feature value calculated by the feature value calculation unit 501.

In this embodiment, the feature value stored in the first storage unit 1 in advance is 128 bits, and the feature value calculated by the feature value unit 5 according to the user code is also 128 bits.

Specifically, the feature value calculation unit 501 is some digital logic for receiving 32-bit data from the microprocessor 4 and calculating 128-bit feature values by combinatorial logic. The first latch 502 is a set of 128-bit wide latches for latching the feature values output by the feature value calculation unit 501.

In particular, the feature value unit 501 can adopt any general or private hash algorithm, which is difficult to crack.

Specifically, when the microprocessor transmits the last 32-bit data, the second latch 504 is set by a write operation, indicating that the result of the feature value calculation unit 501 has been calculated. The output of the second latch 504 is used to enable the comparator 503 to indicate that the output of the comparator 503 is active. In this embodiment, the second latch 504 receives a 1-bit input signal.

The comparator 503 performs an exclusive OR operation, and outputs a "0" when the comparison result is the same, without interruption. If the comparison result is different, "1" is output and the interrupt is generated.

The feature value unit 5 of the present invention uses a digital circuit architecture to calculate whether the user code is tampered by calculating the feature value of the user code and comparing it with the 128-bit feature value stored in the first storage unit 1 in advance. The secure storage of data in the second storage unit is achieved, and the reliability of the chip is improved.

3 is a flow chart showing a method for preventing tampering of an internal data of a memory according to the present invention. The method includes:

Step S1: After the chip is powered on and the reset operation is completed, both the first storage unit 1 and the second storage unit 2 can be accessed through the address space of the microprocessor 4.

Step S2: the program is executed from the first storage unit 1, and the microprocessor 4 reads out the user code in the second storage unit 2 to the feature value unit 5, and the feature value unit 5 calculates The corresponding feature value is output.

Step S3: After multiple iteration calculations, the final 128-bit eigenvalue is obtained.

Step S4: The feature value unit 5 compares the calculated feature value with a 128-bit feature value stored in the first storage unit 1.

Step S5: If the comparison result is consistent, jump to the user program area to execute the user program; if the comparison result is inconsistent, an interrupt is generated to the microprocessor 4.

Step S6: After the microprocessor 4 receives the interrupt of the illegal tampering, the chip is reset.

In summary, the SOC chip and method having the memory internal data anti-tamper mechanism of the present invention use different NVM memories to store system information and user code data respectively. When the system is powered on, first check whether the user code has been tampered with. If the test is correct, the user program is executed. If the verification fails, the chip is reset. The feature value unit may be any general or private hash algorithm, which is difficult to crack. Through the feature value verification circuit after power-on, it is possible to detect whether the NVM memory accidentally loses data and improve the reliability of the chip. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the invention will be covered by the appended claims.

Claims

A SOC chip having a memory internal data anti-tampering mechanism, comprising:

a first storage unit for storing sensitive system data maintained by a chip production provider;

a second storage unit for storing user data and programs maintained by the user;

a microprocessor for accessing the first storage unit or the second storage unit;

An access control unit is connected between the microprocessor and the first storage unit and the second storage unit for completing timing control of the microprocessor accessing the first storage unit and the second storage unit;

An eigenvalue unit, coupled to the microprocessor, for calculating a feature value of the user code in the second storage unit, and comparing with a feature value pre-stored in the first storage unit to determine a user code Whether it has been illegally tampered with.
The SOC chip with a memory internal data tamper-proof mechanism according to claim 1, wherein said feature value unit is set to generate an interruption of a user code being illegally falsified to the micro when it is determined to be illegally falsified. processor.
The SOC chip with a memory internal data tamper resistance mechanism according to claim 2, wherein said microprocessor is arranged to reset said chip after receiving said interrupt.
The SOC chip with a memory internal data tamper prevention mechanism according to claim 1, wherein said feature value unit comprises a feature value calculation unit and a first latch And comparator; where:

The feature value calculation unit is connected between the microprocessor and the first latch, and configured to receive a user code read by the microprocessor from the second storage unit, and calculate the user code. a feature value, and inputting the calculated feature value into the first latch;

a first input of the comparator is coupled to the microprocessor, a second input of the comparator is coupled to an output of the first latch, an output of the comparator and the micro And a processor connection, configured to compare the feature value read by the microprocessor from the first storage unit with the feature value calculated by the feature value calculation unit.
The SOC chip with a memory internal data tamper-proof mechanism according to claim 4, wherein a second latch is further connected between the input end of the characteristic value calculating unit and the comparator for The comparator is powered up.
The SOC chip with a memory internal data tamper-proof mechanism according to claim 1, wherein a feature value pre-stored in said first storage unit is 128 bits, and said feature value unit is calculated based on a user code. The eigenvalue is 128 bits.
The SOC chip with a memory internal data tamper-proof mechanism according to claim 1, wherein the user code in the second storage unit is 32 bits.
The SOC chip with a memory internal data tamper-proof mechanism according to claim 1, wherein the first storage unit and the second storage unit are both non-volatile memories.
The SOC chip with a memory internal data tamper-proof mechanism according to claim 1, wherein the sensitive system data comprises a bootloader, a user key, system storage space configuration information, a calibration value, and a chip unique identifier. One or more of the codes.
A method for tamper-proofing a memory internal data, which is characterized in that it is applied to a SOC chip having a memory internal data tamper-proof mechanism according to any one of claims 1-9, the method comprising:

After the chip is powered on and the reset operation is completed, the first storage unit and the second storage unit are all accessible through the address space of the microprocessor;

The program is executed from the first storage unit, the microprocessor reads out the user code in the second storage unit to the feature value unit, and the feature value unit calculates a corresponding feature value;

After multiple iterations, the final 128-bit eigenvalue is obtained;

The feature value unit compares the calculated feature value with a 128-bit feature value stored in the first storage unit;

If the comparison result is consistent, jump to the user program area to execute the user program; if the comparison result is inconsistent, an interrupt is generated to the microprocessor;

After the microprocessor receives an interrupt of illegal tampering, the chip is reset.